2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
27 #include <asm/amd_iommu_types.h>
28 #include <asm/amd_iommu.h>
30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
32 #define EXIT_LOOP_COUNT 10000000
34 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
37 * general struct to manage commands send to an IOMMU
43 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
44 struct unity_map_entry *e);
46 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
47 static int iommu_has_npcache(struct amd_iommu *iommu)
49 return iommu->cap & IOMMU_CAP_NPCACHE;
52 /****************************************************************************
54 * Interrupt handling functions
56 ****************************************************************************/
58 irqreturn_t amd_iommu_int_handler(int irq, void *data)
63 /****************************************************************************
65 * IOMMU command queuing functions
67 ****************************************************************************/
70 * Writes the command to the IOMMUs command buffer and informs the
71 * hardware about the new command. Must be called with iommu->lock held.
73 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
78 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
79 target = iommu->cmd_buf + tail;
80 memcpy_toio(target, cmd, sizeof(*cmd));
81 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
82 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
85 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
91 * General queuing function for commands. Takes iommu->lock and calls
92 * __iommu_queue_command().
94 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
99 spin_lock_irqsave(&iommu->lock, flags);
100 ret = __iommu_queue_command(iommu, cmd);
101 spin_unlock_irqrestore(&iommu->lock, flags);
107 * This function is called whenever we need to ensure that the IOMMU has
108 * completed execution of all commands we sent. It sends a
109 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
110 * us about that by writing a value to a physical address we pass with
113 static int iommu_completion_wait(struct amd_iommu *iommu)
117 struct iommu_cmd cmd;
120 memset(&cmd, 0, sizeof(cmd));
121 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
122 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
124 iommu->need_sync = 0;
126 ret = iommu_queue_command(iommu, &cmd);
131 while (!ready && (i < EXIT_LOOP_COUNT)) {
133 /* wait for the bit to become one */
134 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
135 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
138 /* set bit back to zero */
139 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
140 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
142 if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
143 printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
149 * Command send function for invalidating a device table entry
151 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
153 struct iommu_cmd cmd;
155 BUG_ON(iommu == NULL);
157 memset(&cmd, 0, sizeof(cmd));
158 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
161 iommu->need_sync = 1;
163 return iommu_queue_command(iommu, &cmd);
167 * Generic command send function for invalidaing TLB entries
169 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
170 u64 address, u16 domid, int pde, int s)
172 struct iommu_cmd cmd;
174 memset(&cmd, 0, sizeof(cmd));
175 address &= PAGE_MASK;
176 CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
177 cmd.data[1] |= domid;
178 cmd.data[2] = lower_32_bits(address);
179 cmd.data[3] = upper_32_bits(address);
180 if (s) /* size bit - we flush more than one 4kb page */
181 cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
182 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
183 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
185 iommu->need_sync = 1;
187 return iommu_queue_command(iommu, &cmd);
191 * TLB invalidation function which is called from the mapping functions.
192 * It invalidates a single PTE if the range to flush is within a single
193 * page. Otherwise it flushes the whole TLB of the IOMMU.
195 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
196 u64 address, size_t size)
199 unsigned pages = iommu_num_pages(address, size);
201 address &= PAGE_MASK;
205 * If we have to flush more than one page, flush all
206 * TLB entries for this domain
208 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
212 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
217 /* Flush the whole IO/TLB for a given protection domain */
218 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
220 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
222 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
225 /****************************************************************************
227 * The functions below are used the create the page table mappings for
228 * unity mapped regions.
230 ****************************************************************************/
233 * Generic mapping functions. It maps a physical address into a DMA
234 * address space. It allocates the page table pages if necessary.
235 * In the future it can be extended to a generic mapping function
236 * supporting all features of AMD IOMMU page tables like level skipping
237 * and full 64 bit address spaces.
239 static int iommu_map(struct protection_domain *dom,
240 unsigned long bus_addr,
241 unsigned long phys_addr,
244 u64 __pte, *pte, *page;
246 bus_addr = PAGE_ALIGN(bus_addr);
247 phys_addr = PAGE_ALIGN(bus_addr);
249 /* only support 512GB address spaces for now */
250 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
253 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
255 if (!IOMMU_PTE_PRESENT(*pte)) {
256 page = (u64 *)get_zeroed_page(GFP_KERNEL);
259 *pte = IOMMU_L2_PDE(virt_to_phys(page));
262 pte = IOMMU_PTE_PAGE(*pte);
263 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
265 if (!IOMMU_PTE_PRESENT(*pte)) {
266 page = (u64 *)get_zeroed_page(GFP_KERNEL);
269 *pte = IOMMU_L1_PDE(virt_to_phys(page));
272 pte = IOMMU_PTE_PAGE(*pte);
273 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
275 if (IOMMU_PTE_PRESENT(*pte))
278 __pte = phys_addr | IOMMU_PTE_P;
279 if (prot & IOMMU_PROT_IR)
280 __pte |= IOMMU_PTE_IR;
281 if (prot & IOMMU_PROT_IW)
282 __pte |= IOMMU_PTE_IW;
290 * This function checks if a specific unity mapping entry is needed for
291 * this specific IOMMU.
293 static int iommu_for_unity_map(struct amd_iommu *iommu,
294 struct unity_map_entry *entry)
298 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
299 bdf = amd_iommu_alias_table[i];
300 if (amd_iommu_rlookup_table[bdf] == iommu)
308 * Init the unity mappings for a specific IOMMU in the system
310 * Basically iterates over all unity mapping entries and applies them to
311 * the default domain DMA of that IOMMU if necessary.
313 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
315 struct unity_map_entry *entry;
318 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
319 if (!iommu_for_unity_map(iommu, entry))
321 ret = dma_ops_unity_map(iommu->default_dom, entry);
330 * This function actually applies the mapping to the page table of the
333 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
334 struct unity_map_entry *e)
339 for (addr = e->address_start; addr < e->address_end;
341 ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
345 * if unity mapping is in aperture range mark the page
346 * as allocated in the aperture
348 if (addr < dma_dom->aperture_size)
349 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
356 * Inits the unity mappings required for a specific device
358 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
361 struct unity_map_entry *e;
364 list_for_each_entry(e, &amd_iommu_unity_map, list) {
365 if (!(devid >= e->devid_start && devid <= e->devid_end))
367 ret = dma_ops_unity_map(dma_dom, e);
375 /****************************************************************************
377 * The next functions belong to the address allocator for the dma_ops
378 * interface functions. They work like the allocators in the other IOMMU
379 * drivers. Its basically a bitmap which marks the allocated pages in
380 * the aperture. Maybe it could be enhanced in the future to a more
381 * efficient allocator.
383 ****************************************************************************/
384 static unsigned long dma_mask_to_pages(unsigned long mask)
386 return (mask >> PAGE_SHIFT) +
387 (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT);
391 * The address allocator core function.
393 * called with domain->lock held
395 static unsigned long dma_ops_alloc_addresses(struct device *dev,
396 struct dma_ops_domain *dom,
398 unsigned long align_mask)
400 unsigned long limit = dma_mask_to_pages(*dev->dma_mask);
401 unsigned long address;
402 unsigned long size = dom->aperture_size >> PAGE_SHIFT;
403 unsigned long boundary_size;
405 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
406 PAGE_SIZE) >> PAGE_SHIFT;
407 limit = limit < size ? limit : size;
409 if (dom->next_bit >= limit) {
411 dom->need_flush = true;
414 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
415 0 , boundary_size, align_mask);
417 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
418 0, boundary_size, align_mask);
419 dom->need_flush = true;
422 if (likely(address != -1)) {
423 dom->next_bit = address + pages;
424 address <<= PAGE_SHIFT;
426 address = bad_dma_address;
428 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
434 * The address free function.
436 * called with domain->lock held
438 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
439 unsigned long address,
442 address >>= PAGE_SHIFT;
443 iommu_area_free(dom->bitmap, address, pages);
446 /****************************************************************************
448 * The next functions belong to the domain allocation. A domain is
449 * allocated for every IOMMU as the default domain. If device isolation
450 * is enabled, every device get its own domain. The most important thing
451 * about domains is the page table mapping the DMA address space they
454 ****************************************************************************/
456 static u16 domain_id_alloc(void)
461 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
462 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
464 if (id > 0 && id < MAX_DOMAIN_ID)
465 __set_bit(id, amd_iommu_pd_alloc_bitmap);
468 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
474 * Used to reserve address ranges in the aperture (e.g. for exclusion
477 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
478 unsigned long start_page,
481 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
483 if (start_page + pages > last_page)
484 pages = last_page - start_page;
486 set_bit_string(dom->bitmap, start_page, pages);
489 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
494 p1 = dma_dom->domain.pt_root;
499 for (i = 0; i < 512; ++i) {
500 if (!IOMMU_PTE_PRESENT(p1[i]))
503 p2 = IOMMU_PTE_PAGE(p1[i]);
504 for (j = 0; j < 512; ++i) {
505 if (!IOMMU_PTE_PRESENT(p2[j]))
507 p3 = IOMMU_PTE_PAGE(p2[j]);
508 free_page((unsigned long)p3);
511 free_page((unsigned long)p2);
514 free_page((unsigned long)p1);
518 * Free a domain, only used if something went wrong in the
519 * allocation path and we need to free an already allocated page table
521 static void dma_ops_domain_free(struct dma_ops_domain *dom)
526 dma_ops_free_pagetable(dom);
528 kfree(dom->pte_pages);
536 * Allocates a new protection domain usable for the dma_ops functions.
537 * It also intializes the page table and the address allocator data
538 * structures required for the dma_ops interface
540 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
543 struct dma_ops_domain *dma_dom;
544 unsigned i, num_pte_pages;
549 * Currently the DMA aperture must be between 32 MB and 1GB in size
551 if ((order < 25) || (order > 30))
554 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
558 spin_lock_init(&dma_dom->domain.lock);
560 dma_dom->domain.id = domain_id_alloc();
561 if (dma_dom->domain.id == 0)
563 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
564 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
565 dma_dom->domain.priv = dma_dom;
566 if (!dma_dom->domain.pt_root)
568 dma_dom->aperture_size = (1ULL << order);
569 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
571 if (!dma_dom->bitmap)
574 * mark the first page as allocated so we never return 0 as
575 * a valid dma-address. So we can use 0 as error value
577 dma_dom->bitmap[0] = 1;
578 dma_dom->next_bit = 0;
580 dma_dom->need_flush = false;
582 /* Intialize the exclusion range if necessary */
583 if (iommu->exclusion_start &&
584 iommu->exclusion_start < dma_dom->aperture_size) {
585 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
586 int pages = iommu_num_pages(iommu->exclusion_start,
587 iommu->exclusion_length);
588 dma_ops_reserve_addresses(dma_dom, startpage, pages);
592 * At the last step, build the page tables so we don't need to
593 * allocate page table pages in the dma_ops mapping/unmapping
596 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
597 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
599 if (!dma_dom->pte_pages)
602 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
606 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
608 for (i = 0; i < num_pte_pages; ++i) {
609 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
610 if (!dma_dom->pte_pages[i])
612 address = virt_to_phys(dma_dom->pte_pages[i]);
613 l2_pde[i] = IOMMU_L1_PDE(address);
619 dma_ops_domain_free(dma_dom);
625 * Find out the protection domain structure for a given PCI device. This
626 * will give us the pointer to the page table root for example.
628 static struct protection_domain *domain_for_device(u16 devid)
630 struct protection_domain *dom;
633 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
634 dom = amd_iommu_pd_table[devid];
635 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
641 * If a device is not yet associated with a domain, this function does
642 * assigns it visible for the hardware
644 static void set_device_domain(struct amd_iommu *iommu,
645 struct protection_domain *domain,
650 u64 pte_root = virt_to_phys(domain->pt_root);
652 pte_root |= (domain->mode & 0x07) << 9;
653 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2;
655 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
656 amd_iommu_dev_table[devid].data[0] = pte_root;
657 amd_iommu_dev_table[devid].data[1] = pte_root >> 32;
658 amd_iommu_dev_table[devid].data[2] = domain->id;
660 amd_iommu_pd_table[devid] = domain;
661 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
663 iommu_queue_inv_dev_entry(iommu, devid);
665 iommu->need_sync = 1;
668 /*****************************************************************************
670 * The next functions belong to the dma_ops mapping/unmapping code.
672 *****************************************************************************/
675 * This function checks if the driver got a valid device from the caller to
676 * avoid dereferencing invalid pointers.
678 static bool check_device(struct device *dev)
680 if (!dev || !dev->dma_mask)
687 * In the dma_ops path we only have the struct device. This function
688 * finds the corresponding IOMMU, the protection domain and the
689 * requestor id for a given device.
690 * If the device is not yet associated with a domain this is also done
693 static int get_device_resources(struct device *dev,
694 struct amd_iommu **iommu,
695 struct protection_domain **domain,
698 struct dma_ops_domain *dma_dom;
699 struct pci_dev *pcidev;
706 if (dev->bus != &pci_bus_type)
709 pcidev = to_pci_dev(dev);
710 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
712 /* device not translated by any IOMMU in the system? */
713 if (_bdf > amd_iommu_last_bdf)
716 *bdf = amd_iommu_alias_table[_bdf];
718 *iommu = amd_iommu_rlookup_table[*bdf];
721 dma_dom = (*iommu)->default_dom;
722 *domain = domain_for_device(*bdf);
723 if (*domain == NULL) {
724 *domain = &dma_dom->domain;
725 set_device_domain(*iommu, *domain, *bdf);
726 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
727 "device ", (*domain)->id);
728 print_devid(_bdf, 1);
735 * This is the generic map function. It maps one 4kb page at paddr to
736 * the given address in the DMA address space for the domain.
738 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
739 struct dma_ops_domain *dom,
740 unsigned long address,
746 WARN_ON(address > dom->aperture_size);
750 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
751 pte += IOMMU_PTE_L0_INDEX(address);
753 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
755 if (direction == DMA_TO_DEVICE)
756 __pte |= IOMMU_PTE_IR;
757 else if (direction == DMA_FROM_DEVICE)
758 __pte |= IOMMU_PTE_IW;
759 else if (direction == DMA_BIDIRECTIONAL)
760 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
766 return (dma_addr_t)address;
770 * The generic unmapping function for on page in the DMA address space.
772 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
773 struct dma_ops_domain *dom,
774 unsigned long address)
778 if (address >= dom->aperture_size)
781 WARN_ON(address & 0xfffULL || address > dom->aperture_size);
783 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
784 pte += IOMMU_PTE_L0_INDEX(address);
792 * This function contains common code for mapping of a physically
793 * contiguous memory region into DMA address space. It is uses by all
794 * mapping functions provided by this IOMMU driver.
795 * Must be called with the domain lock held.
797 static dma_addr_t __map_single(struct device *dev,
798 struct amd_iommu *iommu,
799 struct dma_ops_domain *dma_dom,
805 dma_addr_t offset = paddr & ~PAGE_MASK;
806 dma_addr_t address, start;
808 unsigned long align_mask = 0;
811 pages = iommu_num_pages(paddr, size);
815 align_mask = (1UL << get_order(size)) - 1;
817 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask);
818 if (unlikely(address == bad_dma_address))
822 for (i = 0; i < pages; ++i) {
823 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
829 if (unlikely(dma_dom->need_flush && !iommu_fullflush)) {
830 iommu_flush_tlb(iommu, dma_dom->domain.id);
831 dma_dom->need_flush = false;
832 } else if (unlikely(iommu_has_npcache(iommu)))
833 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
840 * Does the reverse of the __map_single function. Must be called with
841 * the domain lock held too
843 static void __unmap_single(struct amd_iommu *iommu,
844 struct dma_ops_domain *dma_dom,
852 if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
855 pages = iommu_num_pages(dma_addr, size);
856 dma_addr &= PAGE_MASK;
859 for (i = 0; i < pages; ++i) {
860 dma_ops_domain_unmap(iommu, dma_dom, start);
864 dma_ops_free_addresses(dma_dom, dma_addr, pages);
867 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
871 * The exported map_single function for dma_ops.
873 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
874 size_t size, int dir)
877 struct amd_iommu *iommu;
878 struct protection_domain *domain;
882 if (!check_device(dev))
883 return bad_dma_address;
885 get_device_resources(dev, &iommu, &domain, &devid);
887 if (iommu == NULL || domain == NULL)
888 /* device not handled by any AMD IOMMU */
889 return (dma_addr_t)paddr;
891 spin_lock_irqsave(&domain->lock, flags);
892 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false);
893 if (addr == bad_dma_address)
896 if (unlikely(iommu->need_sync))
897 iommu_completion_wait(iommu);
900 spin_unlock_irqrestore(&domain->lock, flags);
906 * The exported unmap_single function for dma_ops.
908 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
909 size_t size, int dir)
912 struct amd_iommu *iommu;
913 struct protection_domain *domain;
916 if (!check_device(dev) ||
917 !get_device_resources(dev, &iommu, &domain, &devid))
918 /* device not handled by any AMD IOMMU */
921 spin_lock_irqsave(&domain->lock, flags);
923 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
925 if (unlikely(iommu->need_sync))
926 iommu_completion_wait(iommu);
928 spin_unlock_irqrestore(&domain->lock, flags);
932 * This is a special map_sg function which is used if we should map a
933 * device which is not handled by an AMD IOMMU in the system.
935 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
938 struct scatterlist *s;
941 for_each_sg(sglist, s, nelems, i) {
942 s->dma_address = (dma_addr_t)sg_phys(s);
943 s->dma_length = s->length;
950 * The exported map_sg function for dma_ops (handles scatter-gather
953 static int map_sg(struct device *dev, struct scatterlist *sglist,
957 struct amd_iommu *iommu;
958 struct protection_domain *domain;
961 struct scatterlist *s;
963 int mapped_elems = 0;
965 if (!check_device(dev))
968 get_device_resources(dev, &iommu, &domain, &devid);
970 if (!iommu || !domain)
971 return map_sg_no_iommu(dev, sglist, nelems, dir);
973 spin_lock_irqsave(&domain->lock, flags);
975 for_each_sg(sglist, s, nelems, i) {
978 s->dma_address = __map_single(dev, iommu, domain->priv,
979 paddr, s->length, dir, false);
981 if (s->dma_address) {
982 s->dma_length = s->length;
988 if (unlikely(iommu->need_sync))
989 iommu_completion_wait(iommu);
992 spin_unlock_irqrestore(&domain->lock, flags);
996 for_each_sg(sglist, s, mapped_elems, i) {
998 __unmap_single(iommu, domain->priv, s->dma_address,
1000 s->dma_address = s->dma_length = 0;
1009 * The exported map_sg function for dma_ops (handles scatter-gather
1012 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1013 int nelems, int dir)
1015 unsigned long flags;
1016 struct amd_iommu *iommu;
1017 struct protection_domain *domain;
1018 struct scatterlist *s;
1022 if (!check_device(dev) ||
1023 !get_device_resources(dev, &iommu, &domain, &devid))
1026 spin_lock_irqsave(&domain->lock, flags);
1028 for_each_sg(sglist, s, nelems, i) {
1029 __unmap_single(iommu, domain->priv, s->dma_address,
1030 s->dma_length, dir);
1031 s->dma_address = s->dma_length = 0;
1034 if (unlikely(iommu->need_sync))
1035 iommu_completion_wait(iommu);
1037 spin_unlock_irqrestore(&domain->lock, flags);
1041 * The exported alloc_coherent function for dma_ops.
1043 static void *alloc_coherent(struct device *dev, size_t size,
1044 dma_addr_t *dma_addr, gfp_t flag)
1046 unsigned long flags;
1048 struct amd_iommu *iommu;
1049 struct protection_domain *domain;
1053 if (!check_device(dev))
1056 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1060 memset(virt_addr, 0, size);
1061 paddr = virt_to_phys(virt_addr);
1063 get_device_resources(dev, &iommu, &domain, &devid);
1065 if (!iommu || !domain) {
1066 *dma_addr = (dma_addr_t)paddr;
1070 spin_lock_irqsave(&domain->lock, flags);
1072 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1073 size, DMA_BIDIRECTIONAL, true);
1075 if (*dma_addr == bad_dma_address) {
1076 free_pages((unsigned long)virt_addr, get_order(size));
1081 if (unlikely(iommu->need_sync))
1082 iommu_completion_wait(iommu);
1085 spin_unlock_irqrestore(&domain->lock, flags);
1091 * The exported free_coherent function for dma_ops.
1093 static void free_coherent(struct device *dev, size_t size,
1094 void *virt_addr, dma_addr_t dma_addr)
1096 unsigned long flags;
1097 struct amd_iommu *iommu;
1098 struct protection_domain *domain;
1101 if (!check_device(dev))
1104 get_device_resources(dev, &iommu, &domain, &devid);
1106 if (!iommu || !domain)
1109 spin_lock_irqsave(&domain->lock, flags);
1111 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1113 if (unlikely(iommu->need_sync))
1114 iommu_completion_wait(iommu);
1116 spin_unlock_irqrestore(&domain->lock, flags);
1119 free_pages((unsigned long)virt_addr, get_order(size));
1123 * The function for pre-allocating protection domains.
1125 * If the driver core informs the DMA layer if a driver grabs a device
1126 * we don't need to preallocate the protection domains anymore.
1127 * For now we have to.
1129 void prealloc_protection_domains(void)
1131 struct pci_dev *dev = NULL;
1132 struct dma_ops_domain *dma_dom;
1133 struct amd_iommu *iommu;
1134 int order = amd_iommu_aperture_order;
1137 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1138 devid = (dev->bus->number << 8) | dev->devfn;
1139 if (devid > amd_iommu_last_bdf)
1141 devid = amd_iommu_alias_table[devid];
1142 if (domain_for_device(devid))
1144 iommu = amd_iommu_rlookup_table[devid];
1147 dma_dom = dma_ops_domain_alloc(iommu, order);
1150 init_unity_mappings_for_device(dma_dom, devid);
1151 set_device_domain(iommu, &dma_dom->domain, devid);
1152 printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ",
1153 dma_dom->domain.id);
1154 print_devid(devid, 1);
1158 static struct dma_mapping_ops amd_iommu_dma_ops = {
1159 .alloc_coherent = alloc_coherent,
1160 .free_coherent = free_coherent,
1161 .map_single = map_single,
1162 .unmap_single = unmap_single,
1164 .unmap_sg = unmap_sg,
1168 * The function which clues the AMD IOMMU driver into dma_ops.
1170 int __init amd_iommu_init_dma_ops(void)
1172 struct amd_iommu *iommu;
1173 int order = amd_iommu_aperture_order;
1177 * first allocate a default protection domain for every IOMMU we
1178 * found in the system. Devices not assigned to any other
1179 * protection domain will be assigned to the default one.
1181 list_for_each_entry(iommu, &amd_iommu_list, list) {
1182 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1183 if (iommu->default_dom == NULL)
1185 ret = iommu_init_unity_mappings(iommu);
1191 * If device isolation is enabled, pre-allocate the protection
1192 * domains for each device.
1194 if (amd_iommu_isolate)
1195 prealloc_protection_domains();
1199 bad_dma_address = 0;
1200 #ifdef CONFIG_GART_IOMMU
1201 gart_iommu_aperture_disabled = 1;
1202 gart_iommu_aperture = 0;
1205 /* Make the driver finally visible to the drivers */
1206 dma_ops = &amd_iommu_dma_ops;
1212 list_for_each_entry(iommu, &amd_iommu_list, list) {
1213 if (iommu->default_dom)
1214 dma_ops_domain_free(iommu->default_dom);