2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
49 static struct protection_domain *pt_domain;
51 static struct iommu_ops amd_iommu_ops;
54 * general struct to manage commands send to an IOMMU
60 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
61 static void update_domain(struct protection_domain *domain);
63 /****************************************************************************
67 ****************************************************************************/
69 static inline u16 get_device_id(struct device *dev)
71 struct pci_dev *pdev = to_pci_dev(dev);
73 return calc_devid(pdev->bus->number, pdev->devfn);
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
78 return dev->archdata.iommu;
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
87 struct dma_ops_domain *entry, *ret = NULL;
89 u16 alias = amd_iommu_alias_table[devid];
91 if (list_empty(&iommu_pd_list))
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
113 static bool check_device(struct device *dev)
117 if (!dev || !dev->dma_mask)
120 /* No device or no PCI device */
121 if (!dev || dev->bus != &pci_bus_type)
124 devid = get_device_id(dev);
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
130 if (amd_iommu_rlookup_table[devid] == NULL)
136 static int iommu_init_device(struct device *dev)
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
142 if (dev->archdata.iommu)
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
151 devid = get_device_id(dev);
152 alias = amd_iommu_alias_table[devid];
153 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
155 dev_data->alias = &pdev->dev;
157 atomic_set(&dev_data->bind, 0);
159 dev->archdata.iommu = dev_data;
165 static void iommu_uninit_device(struct device *dev)
167 kfree(dev->archdata.iommu);
169 #ifdef CONFIG_AMD_IOMMU_STATS
172 * Initialization code for statistics collection
175 DECLARE_STATS_COUNTER(compl_wait);
176 DECLARE_STATS_COUNTER(cnt_map_single);
177 DECLARE_STATS_COUNTER(cnt_unmap_single);
178 DECLARE_STATS_COUNTER(cnt_map_sg);
179 DECLARE_STATS_COUNTER(cnt_unmap_sg);
180 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
181 DECLARE_STATS_COUNTER(cnt_free_coherent);
182 DECLARE_STATS_COUNTER(cross_page);
183 DECLARE_STATS_COUNTER(domain_flush_single);
184 DECLARE_STATS_COUNTER(domain_flush_all);
185 DECLARE_STATS_COUNTER(alloced_io_mem);
186 DECLARE_STATS_COUNTER(total_map_requests);
188 static struct dentry *stats_dir;
189 static struct dentry *de_fflush;
191 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
193 if (stats_dir == NULL)
196 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
200 static void amd_iommu_stats_init(void)
202 stats_dir = debugfs_create_dir("amd-iommu", NULL);
203 if (stats_dir == NULL)
206 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
207 (u32 *)&amd_iommu_unmap_flush);
209 amd_iommu_stats_add(&compl_wait);
210 amd_iommu_stats_add(&cnt_map_single);
211 amd_iommu_stats_add(&cnt_unmap_single);
212 amd_iommu_stats_add(&cnt_map_sg);
213 amd_iommu_stats_add(&cnt_unmap_sg);
214 amd_iommu_stats_add(&cnt_alloc_coherent);
215 amd_iommu_stats_add(&cnt_free_coherent);
216 amd_iommu_stats_add(&cross_page);
217 amd_iommu_stats_add(&domain_flush_single);
218 amd_iommu_stats_add(&domain_flush_all);
219 amd_iommu_stats_add(&alloced_io_mem);
220 amd_iommu_stats_add(&total_map_requests);
225 /****************************************************************************
227 * Interrupt handling functions
229 ****************************************************************************/
231 static void dump_dte_entry(u16 devid)
235 for (i = 0; i < 8; ++i)
236 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
237 amd_iommu_dev_table[devid].data[i]);
240 static void dump_command(unsigned long phys_addr)
242 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
245 for (i = 0; i < 4; ++i)
246 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
249 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
252 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
253 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
254 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
255 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
256 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
258 printk(KERN_ERR "AMD-Vi: Event logged [");
261 case EVENT_TYPE_ILL_DEV:
262 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
263 "address=0x%016llx flags=0x%04x]\n",
264 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
266 dump_dte_entry(devid);
268 case EVENT_TYPE_IO_FAULT:
269 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
270 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
271 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
272 domid, address, flags);
274 case EVENT_TYPE_DEV_TAB_ERR:
275 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
276 "address=0x%016llx flags=0x%04x]\n",
277 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
280 case EVENT_TYPE_PAGE_TAB_ERR:
281 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
282 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
283 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
284 domid, address, flags);
286 case EVENT_TYPE_ILL_CMD:
287 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
288 reset_iommu_command_buffer(iommu);
289 dump_command(address);
291 case EVENT_TYPE_CMD_HARD_ERR:
292 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
293 "flags=0x%04x]\n", address, flags);
295 case EVENT_TYPE_IOTLB_INV_TO:
296 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
297 "address=0x%016llx]\n",
298 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
301 case EVENT_TYPE_INV_DEV_REQ:
302 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
303 "address=0x%016llx flags=0x%04x]\n",
304 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
308 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
312 static void iommu_poll_events(struct amd_iommu *iommu)
317 spin_lock_irqsave(&iommu->lock, flags);
319 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
320 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
322 while (head != tail) {
323 iommu_print_event(iommu, iommu->evt_buf + head);
324 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
327 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
329 spin_unlock_irqrestore(&iommu->lock, flags);
332 irqreturn_t amd_iommu_int_handler(int irq, void *data)
334 struct amd_iommu *iommu;
336 for_each_iommu(iommu)
337 iommu_poll_events(iommu);
342 /****************************************************************************
344 * IOMMU command queuing functions
346 ****************************************************************************/
349 * Writes the command to the IOMMUs command buffer and informs the
350 * hardware about the new command. Must be called with iommu->lock held.
352 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
357 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
358 target = iommu->cmd_buf + tail;
359 memcpy_toio(target, cmd, sizeof(*cmd));
360 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
361 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
364 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
370 * General queuing function for commands. Takes iommu->lock and calls
371 * __iommu_queue_command().
373 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
378 spin_lock_irqsave(&iommu->lock, flags);
379 ret = __iommu_queue_command(iommu, cmd);
381 iommu->need_sync = true;
382 spin_unlock_irqrestore(&iommu->lock, flags);
388 * This function waits until an IOMMU has completed a completion
391 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
397 INC_STATS_COUNTER(compl_wait);
399 while (!ready && (i < EXIT_LOOP_COUNT)) {
401 /* wait for the bit to become one */
402 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
403 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
406 /* set bit back to zero */
407 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
408 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
410 if (unlikely(i == EXIT_LOOP_COUNT)) {
411 spin_unlock(&iommu->lock);
412 reset_iommu_command_buffer(iommu);
413 spin_lock(&iommu->lock);
418 * This function queues a completion wait command into the command
421 static int __iommu_completion_wait(struct amd_iommu *iommu)
423 struct iommu_cmd cmd;
425 memset(&cmd, 0, sizeof(cmd));
426 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
427 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
429 return __iommu_queue_command(iommu, &cmd);
433 * This function is called whenever we need to ensure that the IOMMU has
434 * completed execution of all commands we sent. It sends a
435 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
436 * us about that by writing a value to a physical address we pass with
439 static int iommu_completion_wait(struct amd_iommu *iommu)
444 spin_lock_irqsave(&iommu->lock, flags);
446 if (!iommu->need_sync)
449 ret = __iommu_completion_wait(iommu);
451 iommu->need_sync = false;
456 __iommu_wait_for_completion(iommu);
459 spin_unlock_irqrestore(&iommu->lock, flags);
464 static void iommu_flush_complete(struct protection_domain *domain)
468 for (i = 0; i < amd_iommus_present; ++i) {
469 if (!domain->dev_iommu[i])
473 * Devices of this domain are behind this IOMMU
474 * We need to wait for completion of all commands.
476 iommu_completion_wait(amd_iommus[i]);
481 * Command send function for invalidating a device table entry
483 static int iommu_flush_device(struct device *dev)
485 struct amd_iommu *iommu;
486 struct iommu_cmd cmd;
489 devid = get_device_id(dev);
490 iommu = amd_iommu_rlookup_table[devid];
493 memset(&cmd, 0, sizeof(cmd));
494 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
497 return iommu_queue_command(iommu, &cmd);
500 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
501 u16 domid, int pde, int s)
503 memset(cmd, 0, sizeof(*cmd));
504 address &= PAGE_MASK;
505 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
506 cmd->data[1] |= domid;
507 cmd->data[2] = lower_32_bits(address);
508 cmd->data[3] = upper_32_bits(address);
509 if (s) /* size bit - we flush more than one 4kb page */
510 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
511 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
512 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
516 * Generic command send function for invalidaing TLB entries
518 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
519 u64 address, u16 domid, int pde, int s)
521 struct iommu_cmd cmd;
524 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
526 ret = iommu_queue_command(iommu, &cmd);
532 * TLB invalidation function which is called from the mapping functions.
533 * It invalidates a single PTE if the range to flush is within a single
534 * page. Otherwise it flushes the whole TLB of the IOMMU.
536 static void __iommu_flush_pages(struct protection_domain *domain,
537 u64 address, size_t size, int pde)
540 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
542 address &= PAGE_MASK;
546 * If we have to flush more than one page, flush all
547 * TLB entries for this domain
549 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
554 for (i = 0; i < amd_iommus_present; ++i) {
555 if (!domain->dev_iommu[i])
559 * Devices of this domain are behind this IOMMU
560 * We need a TLB flush
562 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
569 static void iommu_flush_pages(struct protection_domain *domain,
570 u64 address, size_t size)
572 __iommu_flush_pages(domain, address, size, 0);
575 /* Flush the whole IO/TLB for a given protection domain */
576 static void iommu_flush_tlb(struct protection_domain *domain)
578 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
581 /* Flush the whole IO/TLB for a given protection domain - including PDE */
582 static void iommu_flush_tlb_pde(struct protection_domain *domain)
584 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
589 * This function flushes the DTEs for all devices in domain
591 static void iommu_flush_domain_devices(struct protection_domain *domain)
593 struct iommu_dev_data *dev_data;
596 spin_lock_irqsave(&domain->lock, flags);
598 list_for_each_entry(dev_data, &domain->dev_list, list)
599 iommu_flush_device(dev_data->dev);
601 spin_unlock_irqrestore(&domain->lock, flags);
604 static void iommu_flush_all_domain_devices(void)
606 struct protection_domain *domain;
609 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
611 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
612 iommu_flush_domain_devices(domain);
613 iommu_flush_complete(domain);
616 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
619 void amd_iommu_flush_all_devices(void)
621 iommu_flush_all_domain_devices();
625 * This function uses heavy locking and may disable irqs for some time. But
626 * this is no issue because it is only called during resume.
628 void amd_iommu_flush_all_domains(void)
630 struct protection_domain *domain;
633 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
635 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
636 spin_lock(&domain->lock);
637 iommu_flush_tlb_pde(domain);
638 iommu_flush_complete(domain);
639 spin_unlock(&domain->lock);
642 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
645 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
647 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
649 if (iommu->reset_in_progress)
650 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
652 iommu->reset_in_progress = true;
654 amd_iommu_reset_cmd_buffer(iommu);
655 amd_iommu_flush_all_devices();
656 amd_iommu_flush_all_domains();
658 iommu->reset_in_progress = false;
661 /****************************************************************************
663 * The functions below are used the create the page table mappings for
664 * unity mapped regions.
666 ****************************************************************************/
669 * This function is used to add another level to an IO page table. Adding
670 * another level increases the size of the address space by 9 bits to a size up
673 static bool increase_address_space(struct protection_domain *domain,
678 if (domain->mode == PAGE_MODE_6_LEVEL)
679 /* address space already 64 bit large */
682 pte = (void *)get_zeroed_page(gfp);
686 *pte = PM_LEVEL_PDE(domain->mode,
687 virt_to_phys(domain->pt_root));
688 domain->pt_root = pte;
690 domain->updated = true;
695 static u64 *alloc_pte(struct protection_domain *domain,
696 unsigned long address,
704 while (address > PM_LEVEL_SIZE(domain->mode))
705 increase_address_space(domain, gfp);
707 level = domain->mode - 1;
708 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
710 while (level > end_lvl) {
711 if (!IOMMU_PTE_PRESENT(*pte)) {
712 page = (u64 *)get_zeroed_page(gfp);
715 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
720 pte = IOMMU_PTE_PAGE(*pte);
722 if (pte_page && level == end_lvl)
725 pte = &pte[PM_LEVEL_INDEX(level, address)];
732 * This function checks if there is a PTE for a given dma address. If
733 * there is one, it returns the pointer to it.
735 static u64 *fetch_pte(struct protection_domain *domain,
736 unsigned long address, int map_size)
741 level = domain->mode - 1;
742 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
744 while (level > map_size) {
745 if (!IOMMU_PTE_PRESENT(*pte))
750 pte = IOMMU_PTE_PAGE(*pte);
751 pte = &pte[PM_LEVEL_INDEX(level, address)];
753 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
763 * Generic mapping functions. It maps a physical address into a DMA
764 * address space. It allocates the page table pages if necessary.
765 * In the future it can be extended to a generic mapping function
766 * supporting all features of AMD IOMMU page tables like level skipping
767 * and full 64 bit address spaces.
769 static int iommu_map_page(struct protection_domain *dom,
770 unsigned long bus_addr,
771 unsigned long phys_addr,
777 bus_addr = PAGE_ALIGN(bus_addr);
778 phys_addr = PAGE_ALIGN(phys_addr);
780 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
781 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
783 if (!(prot & IOMMU_PROT_MASK))
786 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
788 if (IOMMU_PTE_PRESENT(*pte))
791 __pte = phys_addr | IOMMU_PTE_P;
792 if (prot & IOMMU_PROT_IR)
793 __pte |= IOMMU_PTE_IR;
794 if (prot & IOMMU_PROT_IW)
795 __pte |= IOMMU_PTE_IW;
804 static void iommu_unmap_page(struct protection_domain *dom,
805 unsigned long bus_addr, int map_size)
807 u64 *pte = fetch_pte(dom, bus_addr, map_size);
814 * This function checks if a specific unity mapping entry is needed for
815 * this specific IOMMU.
817 static int iommu_for_unity_map(struct amd_iommu *iommu,
818 struct unity_map_entry *entry)
822 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
823 bdf = amd_iommu_alias_table[i];
824 if (amd_iommu_rlookup_table[bdf] == iommu)
832 * This function actually applies the mapping to the page table of the
835 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
836 struct unity_map_entry *e)
841 for (addr = e->address_start; addr < e->address_end;
843 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
848 * if unity mapping is in aperture range mark the page
849 * as allocated in the aperture
851 if (addr < dma_dom->aperture_size)
852 __set_bit(addr >> PAGE_SHIFT,
853 dma_dom->aperture[0]->bitmap);
860 * Init the unity mappings for a specific IOMMU in the system
862 * Basically iterates over all unity mapping entries and applies them to
863 * the default domain DMA of that IOMMU if necessary.
865 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
867 struct unity_map_entry *entry;
870 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
871 if (!iommu_for_unity_map(iommu, entry))
873 ret = dma_ops_unity_map(iommu->default_dom, entry);
882 * Inits the unity mappings required for a specific device
884 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
887 struct unity_map_entry *e;
890 list_for_each_entry(e, &amd_iommu_unity_map, list) {
891 if (!(devid >= e->devid_start && devid <= e->devid_end))
893 ret = dma_ops_unity_map(dma_dom, e);
901 /****************************************************************************
903 * The next functions belong to the address allocator for the dma_ops
904 * interface functions. They work like the allocators in the other IOMMU
905 * drivers. Its basically a bitmap which marks the allocated pages in
906 * the aperture. Maybe it could be enhanced in the future to a more
907 * efficient allocator.
909 ****************************************************************************/
912 * The address allocator core functions.
914 * called with domain->lock held
918 * Used to reserve address ranges in the aperture (e.g. for exclusion
921 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
922 unsigned long start_page,
925 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
927 if (start_page + pages > last_page)
928 pages = last_page - start_page;
930 for (i = start_page; i < start_page + pages; ++i) {
931 int index = i / APERTURE_RANGE_PAGES;
932 int page = i % APERTURE_RANGE_PAGES;
933 __set_bit(page, dom->aperture[index]->bitmap);
938 * This function is used to add a new aperture range to an existing
939 * aperture in case of dma_ops domain allocation or address allocation
942 static int alloc_new_range(struct dma_ops_domain *dma_dom,
943 bool populate, gfp_t gfp)
945 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
946 struct amd_iommu *iommu;
949 #ifdef CONFIG_IOMMU_STRESS
953 if (index >= APERTURE_MAX_RANGES)
956 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
957 if (!dma_dom->aperture[index])
960 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
961 if (!dma_dom->aperture[index]->bitmap)
964 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
967 unsigned long address = dma_dom->aperture_size;
968 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
971 for (i = 0; i < num_ptes; ++i) {
972 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
977 dma_dom->aperture[index]->pte_pages[i] = pte_page;
979 address += APERTURE_RANGE_SIZE / 64;
983 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
985 /* Intialize the exclusion range if necessary */
986 for_each_iommu(iommu) {
987 if (iommu->exclusion_start &&
988 iommu->exclusion_start >= dma_dom->aperture[index]->offset
989 && iommu->exclusion_start < dma_dom->aperture_size) {
990 unsigned long startpage;
991 int pages = iommu_num_pages(iommu->exclusion_start,
992 iommu->exclusion_length,
994 startpage = iommu->exclusion_start >> PAGE_SHIFT;
995 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1000 * Check for areas already mapped as present in the new aperture
1001 * range and mark those pages as reserved in the allocator. Such
1002 * mappings may already exist as a result of requested unity
1003 * mappings for devices.
1005 for (i = dma_dom->aperture[index]->offset;
1006 i < dma_dom->aperture_size;
1008 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
1009 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1012 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1015 update_domain(&dma_dom->domain);
1020 update_domain(&dma_dom->domain);
1022 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1024 kfree(dma_dom->aperture[index]);
1025 dma_dom->aperture[index] = NULL;
1030 static unsigned long dma_ops_area_alloc(struct device *dev,
1031 struct dma_ops_domain *dom,
1033 unsigned long align_mask,
1035 unsigned long start)
1037 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1038 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1039 int i = start >> APERTURE_RANGE_SHIFT;
1040 unsigned long boundary_size;
1041 unsigned long address = -1;
1042 unsigned long limit;
1044 next_bit >>= PAGE_SHIFT;
1046 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1047 PAGE_SIZE) >> PAGE_SHIFT;
1049 for (;i < max_index; ++i) {
1050 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1052 if (dom->aperture[i]->offset >= dma_mask)
1055 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1056 dma_mask >> PAGE_SHIFT);
1058 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1059 limit, next_bit, pages, 0,
1060 boundary_size, align_mask);
1061 if (address != -1) {
1062 address = dom->aperture[i]->offset +
1063 (address << PAGE_SHIFT);
1064 dom->next_address = address + (pages << PAGE_SHIFT);
1074 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1075 struct dma_ops_domain *dom,
1077 unsigned long align_mask,
1080 unsigned long address;
1082 #ifdef CONFIG_IOMMU_STRESS
1083 dom->next_address = 0;
1084 dom->need_flush = true;
1087 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1088 dma_mask, dom->next_address);
1090 if (address == -1) {
1091 dom->next_address = 0;
1092 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1094 dom->need_flush = true;
1097 if (unlikely(address == -1))
1098 address = DMA_ERROR_CODE;
1100 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1106 * The address free function.
1108 * called with domain->lock held
1110 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1111 unsigned long address,
1114 unsigned i = address >> APERTURE_RANGE_SHIFT;
1115 struct aperture_range *range = dom->aperture[i];
1117 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1119 #ifdef CONFIG_IOMMU_STRESS
1124 if (address >= dom->next_address)
1125 dom->need_flush = true;
1127 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1129 iommu_area_free(range->bitmap, address, pages);
1133 /****************************************************************************
1135 * The next functions belong to the domain allocation. A domain is
1136 * allocated for every IOMMU as the default domain. If device isolation
1137 * is enabled, every device get its own domain. The most important thing
1138 * about domains is the page table mapping the DMA address space they
1141 ****************************************************************************/
1144 * This function adds a protection domain to the global protection domain list
1146 static void add_domain_to_list(struct protection_domain *domain)
1148 unsigned long flags;
1150 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1151 list_add(&domain->list, &amd_iommu_pd_list);
1152 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1156 * This function removes a protection domain to the global
1157 * protection domain list
1159 static void del_domain_from_list(struct protection_domain *domain)
1161 unsigned long flags;
1163 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1164 list_del(&domain->list);
1165 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1168 static u16 domain_id_alloc(void)
1170 unsigned long flags;
1173 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1174 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1176 if (id > 0 && id < MAX_DOMAIN_ID)
1177 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1180 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1185 static void domain_id_free(int id)
1187 unsigned long flags;
1189 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1190 if (id > 0 && id < MAX_DOMAIN_ID)
1191 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1192 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1195 static void free_pagetable(struct protection_domain *domain)
1200 p1 = domain->pt_root;
1205 for (i = 0; i < 512; ++i) {
1206 if (!IOMMU_PTE_PRESENT(p1[i]))
1209 p2 = IOMMU_PTE_PAGE(p1[i]);
1210 for (j = 0; j < 512; ++j) {
1211 if (!IOMMU_PTE_PRESENT(p2[j]))
1213 p3 = IOMMU_PTE_PAGE(p2[j]);
1214 free_page((unsigned long)p3);
1217 free_page((unsigned long)p2);
1220 free_page((unsigned long)p1);
1222 domain->pt_root = NULL;
1226 * Free a domain, only used if something went wrong in the
1227 * allocation path and we need to free an already allocated page table
1229 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1236 del_domain_from_list(&dom->domain);
1238 free_pagetable(&dom->domain);
1240 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1241 if (!dom->aperture[i])
1243 free_page((unsigned long)dom->aperture[i]->bitmap);
1244 kfree(dom->aperture[i]);
1251 * Allocates a new protection domain usable for the dma_ops functions.
1252 * It also intializes the page table and the address allocator data
1253 * structures required for the dma_ops interface
1255 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1257 struct dma_ops_domain *dma_dom;
1259 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1263 spin_lock_init(&dma_dom->domain.lock);
1265 dma_dom->domain.id = domain_id_alloc();
1266 if (dma_dom->domain.id == 0)
1268 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1269 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1270 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1271 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1272 dma_dom->domain.priv = dma_dom;
1273 if (!dma_dom->domain.pt_root)
1276 dma_dom->need_flush = false;
1277 dma_dom->target_dev = 0xffff;
1279 add_domain_to_list(&dma_dom->domain);
1281 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1285 * mark the first page as allocated so we never return 0 as
1286 * a valid dma-address. So we can use 0 as error value
1288 dma_dom->aperture[0]->bitmap[0] = 1;
1289 dma_dom->next_address = 0;
1295 dma_ops_domain_free(dma_dom);
1301 * little helper function to check whether a given protection domain is a
1304 static bool dma_ops_domain(struct protection_domain *domain)
1306 return domain->flags & PD_DMA_OPS_MASK;
1309 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1311 u64 pte_root = virt_to_phys(domain->pt_root);
1313 BUG_ON(amd_iommu_pd_table[devid] != NULL);
1315 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1316 << DEV_ENTRY_MODE_SHIFT;
1317 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1319 amd_iommu_dev_table[devid].data[2] = domain->id;
1320 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1321 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1323 amd_iommu_pd_table[devid] = domain;
1327 static void clear_dte_entry(u16 devid)
1329 struct protection_domain *domain = amd_iommu_pd_table[devid];
1331 BUG_ON(domain == NULL);
1333 /* remove domain from the lookup table */
1334 amd_iommu_pd_table[devid] = NULL;
1336 /* remove entry from the device table seen by the hardware */
1337 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1338 amd_iommu_dev_table[devid].data[1] = 0;
1339 amd_iommu_dev_table[devid].data[2] = 0;
1341 amd_iommu_apply_erratum_63(devid);
1344 static void do_attach(struct device *dev, struct protection_domain *domain)
1346 struct iommu_dev_data *dev_data;
1347 struct amd_iommu *iommu;
1350 devid = get_device_id(dev);
1351 iommu = amd_iommu_rlookup_table[devid];
1352 dev_data = get_dev_data(dev);
1354 /* Update data structures */
1355 dev_data->domain = domain;
1356 list_add(&dev_data->list, &domain->dev_list);
1357 set_dte_entry(devid, domain);
1359 /* Do reference counting */
1360 domain->dev_iommu[iommu->index] += 1;
1361 domain->dev_cnt += 1;
1363 /* Flush the DTE entry */
1364 iommu_flush_device(dev);
1367 static void do_detach(struct device *dev)
1369 struct iommu_dev_data *dev_data;
1370 struct amd_iommu *iommu;
1373 devid = get_device_id(dev);
1374 iommu = amd_iommu_rlookup_table[devid];
1375 dev_data = get_dev_data(dev);
1377 /* decrease reference counters */
1378 dev_data->domain->dev_iommu[iommu->index] -= 1;
1379 dev_data->domain->dev_cnt -= 1;
1381 /* Update data structures */
1382 dev_data->domain = NULL;
1383 list_del(&dev_data->list);
1384 clear_dte_entry(devid);
1386 /* Flush the DTE entry */
1387 iommu_flush_device(dev);
1391 * If a device is not yet associated with a domain, this function does
1392 * assigns it visible for the hardware
1394 static int __attach_device(struct device *dev,
1395 struct protection_domain *domain)
1397 struct iommu_dev_data *dev_data, *alias_data;
1399 dev_data = get_dev_data(dev);
1400 alias_data = get_dev_data(dev_data->alias);
1406 spin_lock(&domain->lock);
1408 /* Some sanity checks */
1409 if (alias_data->domain != NULL &&
1410 alias_data->domain != domain)
1413 if (dev_data->domain != NULL &&
1414 dev_data->domain != domain)
1417 /* Do real assignment */
1418 if (dev_data->alias != dev) {
1419 alias_data = get_dev_data(dev_data->alias);
1420 if (alias_data->domain == NULL)
1421 do_attach(dev_data->alias, domain);
1423 atomic_inc(&alias_data->bind);
1426 if (dev_data->domain == NULL)
1427 do_attach(dev, domain);
1429 atomic_inc(&dev_data->bind);
1432 spin_unlock(&domain->lock);
1438 * If a device is not yet associated with a domain, this function does
1439 * assigns it visible for the hardware
1441 static int attach_device(struct device *dev,
1442 struct protection_domain *domain)
1444 unsigned long flags;
1447 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1448 ret = __attach_device(dev, domain);
1449 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1452 * We might boot into a crash-kernel here. The crashed kernel
1453 * left the caches in the IOMMU dirty. So we have to flush
1454 * here to evict all dirty stuff.
1456 iommu_flush_tlb_pde(domain);
1462 * Removes a device from a protection domain (unlocked)
1464 static void __detach_device(struct device *dev)
1466 struct iommu_dev_data *dev_data = get_dev_data(dev);
1467 struct iommu_dev_data *alias_data;
1468 unsigned long flags;
1470 BUG_ON(!dev_data->domain);
1472 spin_lock_irqsave(&dev_data->domain->lock, flags);
1474 if (dev_data->alias != dev) {
1475 alias_data = get_dev_data(dev_data->alias);
1476 if (atomic_dec_and_test(&alias_data->bind))
1477 do_detach(dev_data->alias);
1480 if (atomic_dec_and_test(&dev_data->bind))
1483 spin_unlock_irqrestore(&dev_data->domain->lock, flags);
1486 * If we run in passthrough mode the device must be assigned to the
1487 * passthrough domain if it is detached from any other domain
1489 if (iommu_pass_through && dev_data->domain == NULL)
1490 __attach_device(dev, pt_domain);
1494 * Removes a device from a protection domain (with devtable_lock held)
1496 static void detach_device(struct device *dev)
1498 unsigned long flags;
1500 /* lock device table */
1501 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1502 __detach_device(dev);
1503 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1507 * Find out the protection domain structure for a given PCI device. This
1508 * will give us the pointer to the page table root for example.
1510 static struct protection_domain *domain_for_device(struct device *dev)
1512 struct protection_domain *dom;
1513 struct iommu_dev_data *dev_data, *alias_data;
1514 unsigned long flags;
1517 devid = get_device_id(dev);
1518 alias = amd_iommu_alias_table[devid];
1519 dev_data = get_dev_data(dev);
1520 alias_data = get_dev_data(dev_data->alias);
1524 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1525 dom = dev_data->domain;
1527 alias_data->domain != NULL) {
1528 __attach_device(dev, alias_data->domain);
1529 dom = alias_data->domain;
1532 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1537 static int device_change_notifier(struct notifier_block *nb,
1538 unsigned long action, void *data)
1540 struct device *dev = data;
1542 struct protection_domain *domain;
1543 struct dma_ops_domain *dma_domain;
1544 struct amd_iommu *iommu;
1545 unsigned long flags;
1547 if (!check_device(dev))
1550 devid = get_device_id(dev);
1551 iommu = amd_iommu_rlookup_table[devid];
1554 case BUS_NOTIFY_UNBOUND_DRIVER:
1556 domain = domain_for_device(dev);
1560 if (iommu_pass_through)
1564 case BUS_NOTIFY_ADD_DEVICE:
1566 iommu_init_device(dev);
1568 domain = domain_for_device(dev);
1570 /* allocate a protection domain if a device is added */
1571 dma_domain = find_protection_domain(devid);
1574 dma_domain = dma_ops_domain_alloc();
1577 dma_domain->target_dev = devid;
1579 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1580 list_add_tail(&dma_domain->list, &iommu_pd_list);
1581 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1584 case BUS_NOTIFY_DEL_DEVICE:
1586 iommu_uninit_device(dev);
1592 iommu_flush_device(dev);
1593 iommu_completion_wait(iommu);
1599 static struct notifier_block device_nb = {
1600 .notifier_call = device_change_notifier,
1603 /*****************************************************************************
1605 * The next functions belong to the dma_ops mapping/unmapping code.
1607 *****************************************************************************/
1610 * In the dma_ops path we only have the struct device. This function
1611 * finds the corresponding IOMMU, the protection domain and the
1612 * requestor id for a given device.
1613 * If the device is not yet associated with a domain this is also done
1616 static struct protection_domain *get_domain(struct device *dev)
1618 struct protection_domain *domain;
1619 struct dma_ops_domain *dma_dom;
1620 u16 devid = get_device_id(dev);
1622 if (!check_device(dev))
1623 return ERR_PTR(-EINVAL);
1625 domain = domain_for_device(dev);
1626 if (domain != NULL && !dma_ops_domain(domain))
1627 return ERR_PTR(-EBUSY);
1632 /* Device not bount yet - bind it */
1633 dma_dom = find_protection_domain(devid);
1635 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1636 attach_device(dev, &dma_dom->domain);
1637 DUMP_printk("Using protection domain %d for device %s\n",
1638 dma_dom->domain.id, dev_name(dev));
1640 return &dma_dom->domain;
1643 static void update_device_table(struct protection_domain *domain)
1645 unsigned long flags;
1648 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
1649 if (amd_iommu_pd_table[i] != domain)
1651 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1652 set_dte_entry(i, domain);
1653 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1657 static void update_domain(struct protection_domain *domain)
1659 if (!domain->updated)
1662 update_device_table(domain);
1663 iommu_flush_domain_devices(domain);
1664 iommu_flush_tlb_pde(domain);
1666 domain->updated = false;
1670 * This function fetches the PTE for a given address in the aperture
1672 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1673 unsigned long address)
1675 struct aperture_range *aperture;
1676 u64 *pte, *pte_page;
1678 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1682 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1684 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1686 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1688 pte += PM_LEVEL_INDEX(0, address);
1690 update_domain(&dom->domain);
1696 * This is the generic map function. It maps one 4kb page at paddr to
1697 * the given address in the DMA address space for the domain.
1699 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1700 unsigned long address,
1706 WARN_ON(address > dom->aperture_size);
1710 pte = dma_ops_get_pte(dom, address);
1712 return DMA_ERROR_CODE;
1714 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1716 if (direction == DMA_TO_DEVICE)
1717 __pte |= IOMMU_PTE_IR;
1718 else if (direction == DMA_FROM_DEVICE)
1719 __pte |= IOMMU_PTE_IW;
1720 else if (direction == DMA_BIDIRECTIONAL)
1721 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1727 return (dma_addr_t)address;
1731 * The generic unmapping function for on page in the DMA address space.
1733 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1734 unsigned long address)
1736 struct aperture_range *aperture;
1739 if (address >= dom->aperture_size)
1742 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1746 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1750 pte += PM_LEVEL_INDEX(0, address);
1758 * This function contains common code for mapping of a physically
1759 * contiguous memory region into DMA address space. It is used by all
1760 * mapping functions provided with this IOMMU driver.
1761 * Must be called with the domain lock held.
1763 static dma_addr_t __map_single(struct device *dev,
1764 struct dma_ops_domain *dma_dom,
1771 dma_addr_t offset = paddr & ~PAGE_MASK;
1772 dma_addr_t address, start, ret;
1774 unsigned long align_mask = 0;
1777 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1780 INC_STATS_COUNTER(total_map_requests);
1783 INC_STATS_COUNTER(cross_page);
1786 align_mask = (1UL << get_order(size)) - 1;
1789 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1791 if (unlikely(address == DMA_ERROR_CODE)) {
1793 * setting next_address here will let the address
1794 * allocator only scan the new allocated range in the
1795 * first run. This is a small optimization.
1797 dma_dom->next_address = dma_dom->aperture_size;
1799 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1803 * aperture was sucessfully enlarged by 128 MB, try
1810 for (i = 0; i < pages; ++i) {
1811 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1812 if (ret == DMA_ERROR_CODE)
1820 ADD_STATS_COUNTER(alloced_io_mem, size);
1822 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1823 iommu_flush_tlb(&dma_dom->domain);
1824 dma_dom->need_flush = false;
1825 } else if (unlikely(amd_iommu_np_cache))
1826 iommu_flush_pages(&dma_dom->domain, address, size);
1833 for (--i; i >= 0; --i) {
1835 dma_ops_domain_unmap(dma_dom, start);
1838 dma_ops_free_addresses(dma_dom, address, pages);
1840 return DMA_ERROR_CODE;
1844 * Does the reverse of the __map_single function. Must be called with
1845 * the domain lock held too
1847 static void __unmap_single(struct dma_ops_domain *dma_dom,
1848 dma_addr_t dma_addr,
1852 dma_addr_t i, start;
1855 if ((dma_addr == DMA_ERROR_CODE) ||
1856 (dma_addr + size > dma_dom->aperture_size))
1859 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1860 dma_addr &= PAGE_MASK;
1863 for (i = 0; i < pages; ++i) {
1864 dma_ops_domain_unmap(dma_dom, start);
1868 SUB_STATS_COUNTER(alloced_io_mem, size);
1870 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1872 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1873 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1874 dma_dom->need_flush = false;
1879 * The exported map_single function for dma_ops.
1881 static dma_addr_t map_page(struct device *dev, struct page *page,
1882 unsigned long offset, size_t size,
1883 enum dma_data_direction dir,
1884 struct dma_attrs *attrs)
1886 unsigned long flags;
1887 struct protection_domain *domain;
1890 phys_addr_t paddr = page_to_phys(page) + offset;
1892 INC_STATS_COUNTER(cnt_map_single);
1894 domain = get_domain(dev);
1895 if (PTR_ERR(domain) == -EINVAL)
1896 return (dma_addr_t)paddr;
1897 else if (IS_ERR(domain))
1898 return DMA_ERROR_CODE;
1900 dma_mask = *dev->dma_mask;
1902 spin_lock_irqsave(&domain->lock, flags);
1904 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1906 if (addr == DMA_ERROR_CODE)
1909 iommu_flush_complete(domain);
1912 spin_unlock_irqrestore(&domain->lock, flags);
1918 * The exported unmap_single function for dma_ops.
1920 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1921 enum dma_data_direction dir, struct dma_attrs *attrs)
1923 unsigned long flags;
1924 struct protection_domain *domain;
1926 INC_STATS_COUNTER(cnt_unmap_single);
1928 domain = get_domain(dev);
1932 spin_lock_irqsave(&domain->lock, flags);
1934 __unmap_single(domain->priv, dma_addr, size, dir);
1936 iommu_flush_complete(domain);
1938 spin_unlock_irqrestore(&domain->lock, flags);
1942 * This is a special map_sg function which is used if we should map a
1943 * device which is not handled by an AMD IOMMU in the system.
1945 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1946 int nelems, int dir)
1948 struct scatterlist *s;
1951 for_each_sg(sglist, s, nelems, i) {
1952 s->dma_address = (dma_addr_t)sg_phys(s);
1953 s->dma_length = s->length;
1960 * The exported map_sg function for dma_ops (handles scatter-gather
1963 static int map_sg(struct device *dev, struct scatterlist *sglist,
1964 int nelems, enum dma_data_direction dir,
1965 struct dma_attrs *attrs)
1967 unsigned long flags;
1968 struct protection_domain *domain;
1970 struct scatterlist *s;
1972 int mapped_elems = 0;
1975 INC_STATS_COUNTER(cnt_map_sg);
1977 domain = get_domain(dev);
1978 if (PTR_ERR(domain) == -EINVAL)
1979 return map_sg_no_iommu(dev, sglist, nelems, dir);
1980 else if (IS_ERR(domain))
1983 dma_mask = *dev->dma_mask;
1985 spin_lock_irqsave(&domain->lock, flags);
1987 for_each_sg(sglist, s, nelems, i) {
1990 s->dma_address = __map_single(dev, domain->priv,
1991 paddr, s->length, dir, false,
1994 if (s->dma_address) {
1995 s->dma_length = s->length;
2001 iommu_flush_complete(domain);
2004 spin_unlock_irqrestore(&domain->lock, flags);
2006 return mapped_elems;
2008 for_each_sg(sglist, s, mapped_elems, i) {
2010 __unmap_single(domain->priv, s->dma_address,
2011 s->dma_length, dir);
2012 s->dma_address = s->dma_length = 0;
2021 * The exported map_sg function for dma_ops (handles scatter-gather
2024 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2025 int nelems, enum dma_data_direction dir,
2026 struct dma_attrs *attrs)
2028 unsigned long flags;
2029 struct protection_domain *domain;
2030 struct scatterlist *s;
2033 INC_STATS_COUNTER(cnt_unmap_sg);
2035 domain = get_domain(dev);
2039 spin_lock_irqsave(&domain->lock, flags);
2041 for_each_sg(sglist, s, nelems, i) {
2042 __unmap_single(domain->priv, s->dma_address,
2043 s->dma_length, dir);
2044 s->dma_address = s->dma_length = 0;
2047 iommu_flush_complete(domain);
2049 spin_unlock_irqrestore(&domain->lock, flags);
2053 * The exported alloc_coherent function for dma_ops.
2055 static void *alloc_coherent(struct device *dev, size_t size,
2056 dma_addr_t *dma_addr, gfp_t flag)
2058 unsigned long flags;
2060 struct protection_domain *domain;
2062 u64 dma_mask = dev->coherent_dma_mask;
2064 INC_STATS_COUNTER(cnt_alloc_coherent);
2066 domain = get_domain(dev);
2067 if (PTR_ERR(domain) == -EINVAL) {
2068 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2069 *dma_addr = __pa(virt_addr);
2071 } else if (IS_ERR(domain))
2074 dma_mask = dev->coherent_dma_mask;
2075 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2078 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2082 paddr = virt_to_phys(virt_addr);
2085 dma_mask = *dev->dma_mask;
2087 spin_lock_irqsave(&domain->lock, flags);
2089 *dma_addr = __map_single(dev, domain->priv, paddr,
2090 size, DMA_BIDIRECTIONAL, true, dma_mask);
2092 if (*dma_addr == DMA_ERROR_CODE) {
2093 spin_unlock_irqrestore(&domain->lock, flags);
2097 iommu_flush_complete(domain);
2099 spin_unlock_irqrestore(&domain->lock, flags);
2105 free_pages((unsigned long)virt_addr, get_order(size));
2111 * The exported free_coherent function for dma_ops.
2113 static void free_coherent(struct device *dev, size_t size,
2114 void *virt_addr, dma_addr_t dma_addr)
2116 unsigned long flags;
2117 struct protection_domain *domain;
2119 INC_STATS_COUNTER(cnt_free_coherent);
2121 domain = get_domain(dev);
2125 spin_lock_irqsave(&domain->lock, flags);
2127 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2129 iommu_flush_complete(domain);
2131 spin_unlock_irqrestore(&domain->lock, flags);
2134 free_pages((unsigned long)virt_addr, get_order(size));
2138 * This function is called by the DMA layer to find out if we can handle a
2139 * particular device. It is part of the dma_ops.
2141 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2143 return check_device(dev);
2147 * The function for pre-allocating protection domains.
2149 * If the driver core informs the DMA layer if a driver grabs a device
2150 * we don't need to preallocate the protection domains anymore.
2151 * For now we have to.
2153 static void prealloc_protection_domains(void)
2155 struct pci_dev *dev = NULL;
2156 struct dma_ops_domain *dma_dom;
2159 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2161 /* Do we handle this device? */
2162 if (!check_device(&dev->dev))
2165 iommu_init_device(&dev->dev);
2167 /* Is there already any domain for it? */
2168 if (domain_for_device(&dev->dev))
2171 devid = get_device_id(&dev->dev);
2173 dma_dom = dma_ops_domain_alloc();
2176 init_unity_mappings_for_device(dma_dom, devid);
2177 dma_dom->target_dev = devid;
2179 attach_device(&dev->dev, &dma_dom->domain);
2181 list_add_tail(&dma_dom->list, &iommu_pd_list);
2185 static struct dma_map_ops amd_iommu_dma_ops = {
2186 .alloc_coherent = alloc_coherent,
2187 .free_coherent = free_coherent,
2188 .map_page = map_page,
2189 .unmap_page = unmap_page,
2191 .unmap_sg = unmap_sg,
2192 .dma_supported = amd_iommu_dma_supported,
2196 * The function which clues the AMD IOMMU driver into dma_ops.
2198 int __init amd_iommu_init_dma_ops(void)
2200 struct amd_iommu *iommu;
2204 * first allocate a default protection domain for every IOMMU we
2205 * found in the system. Devices not assigned to any other
2206 * protection domain will be assigned to the default one.
2208 for_each_iommu(iommu) {
2209 iommu->default_dom = dma_ops_domain_alloc();
2210 if (iommu->default_dom == NULL)
2212 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2213 ret = iommu_init_unity_mappings(iommu);
2219 * Pre-allocate the protection domains for each device.
2221 prealloc_protection_domains();
2225 #ifdef CONFIG_GART_IOMMU
2226 gart_iommu_aperture_disabled = 1;
2227 gart_iommu_aperture = 0;
2230 /* Make the driver finally visible to the drivers */
2231 dma_ops = &amd_iommu_dma_ops;
2233 register_iommu(&amd_iommu_ops);
2235 bus_register_notifier(&pci_bus_type, &device_nb);
2237 amd_iommu_stats_init();
2243 for_each_iommu(iommu) {
2244 if (iommu->default_dom)
2245 dma_ops_domain_free(iommu->default_dom);
2251 /*****************************************************************************
2253 * The following functions belong to the exported interface of AMD IOMMU
2255 * This interface allows access to lower level functions of the IOMMU
2256 * like protection domain handling and assignement of devices to domains
2257 * which is not possible with the dma_ops interface.
2259 *****************************************************************************/
2261 static void cleanup_domain(struct protection_domain *domain)
2263 unsigned long flags;
2266 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2268 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2269 if (amd_iommu_pd_table[devid] == domain)
2270 clear_dte_entry(devid);
2272 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2275 static void protection_domain_free(struct protection_domain *domain)
2280 del_domain_from_list(domain);
2283 domain_id_free(domain->id);
2288 static struct protection_domain *protection_domain_alloc(void)
2290 struct protection_domain *domain;
2292 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2296 spin_lock_init(&domain->lock);
2297 domain->id = domain_id_alloc();
2300 INIT_LIST_HEAD(&domain->dev_list);
2302 add_domain_to_list(domain);
2312 static int amd_iommu_domain_init(struct iommu_domain *dom)
2314 struct protection_domain *domain;
2316 domain = protection_domain_alloc();
2320 domain->mode = PAGE_MODE_3_LEVEL;
2321 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2322 if (!domain->pt_root)
2330 protection_domain_free(domain);
2335 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2337 struct protection_domain *domain = dom->priv;
2342 if (domain->dev_cnt > 0)
2343 cleanup_domain(domain);
2345 BUG_ON(domain->dev_cnt != 0);
2347 free_pagetable(domain);
2349 domain_id_free(domain->id);
2356 static void amd_iommu_detach_device(struct iommu_domain *dom,
2359 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2360 struct amd_iommu *iommu;
2363 if (!check_device(dev))
2366 devid = get_device_id(dev);
2368 if (dev_data->domain != NULL)
2371 iommu = amd_iommu_rlookup_table[devid];
2375 iommu_flush_device(dev);
2376 iommu_completion_wait(iommu);
2379 static int amd_iommu_attach_device(struct iommu_domain *dom,
2382 struct protection_domain *domain = dom->priv;
2383 struct iommu_dev_data *dev_data;
2384 struct amd_iommu *iommu;
2388 if (!check_device(dev))
2391 dev_data = dev->archdata.iommu;
2393 devid = get_device_id(dev);
2395 iommu = amd_iommu_rlookup_table[devid];
2399 if (dev_data->domain)
2402 ret = attach_device(dev, domain);
2404 iommu_completion_wait(iommu);
2409 static int amd_iommu_map_range(struct iommu_domain *dom,
2410 unsigned long iova, phys_addr_t paddr,
2411 size_t size, int iommu_prot)
2413 struct protection_domain *domain = dom->priv;
2414 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2418 if (iommu_prot & IOMMU_READ)
2419 prot |= IOMMU_PROT_IR;
2420 if (iommu_prot & IOMMU_WRITE)
2421 prot |= IOMMU_PROT_IW;
2426 for (i = 0; i < npages; ++i) {
2427 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2438 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2439 unsigned long iova, size_t size)
2442 struct protection_domain *domain = dom->priv;
2443 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2447 for (i = 0; i < npages; ++i) {
2448 iommu_unmap_page(domain, iova, PM_MAP_4k);
2452 iommu_flush_tlb_pde(domain);
2455 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2458 struct protection_domain *domain = dom->priv;
2459 unsigned long offset = iova & ~PAGE_MASK;
2463 pte = fetch_pte(domain, iova, PM_MAP_4k);
2465 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2468 paddr = *pte & IOMMU_PAGE_MASK;
2474 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2480 static struct iommu_ops amd_iommu_ops = {
2481 .domain_init = amd_iommu_domain_init,
2482 .domain_destroy = amd_iommu_domain_destroy,
2483 .attach_dev = amd_iommu_attach_device,
2484 .detach_dev = amd_iommu_detach_device,
2485 .map = amd_iommu_map_range,
2486 .unmap = amd_iommu_unmap_range,
2487 .iova_to_phys = amd_iommu_iova_to_phys,
2488 .domain_has_cap = amd_iommu_domain_has_cap,
2491 /*****************************************************************************
2493 * The next functions do a basic initialization of IOMMU for pass through
2496 * In passthrough mode the IOMMU is initialized and enabled but not used for
2497 * DMA-API translation.
2499 *****************************************************************************/
2501 int __init amd_iommu_init_passthrough(void)
2503 struct amd_iommu *iommu;
2504 struct pci_dev *dev = NULL;
2507 /* allocate passthroug domain */
2508 pt_domain = protection_domain_alloc();
2512 pt_domain->mode |= PAGE_MODE_NONE;
2514 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2516 if (!check_device(&dev->dev))
2519 devid = get_device_id(&dev->dev);
2521 iommu = amd_iommu_rlookup_table[devid];
2525 attach_device(&dev->dev, pt_domain);
2528 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");