2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
27 #include <asm/amd_iommu_types.h>
28 #include <asm/amd_iommu.h>
30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
32 #define EXIT_LOOP_COUNT 10000000
34 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
37 * general struct to manage commands send to an IOMMU
43 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
44 struct unity_map_entry *e);
46 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
47 static int iommu_has_npcache(struct amd_iommu *iommu)
49 return iommu->cap & IOMMU_CAP_NPCACHE;
52 /****************************************************************************
54 * Interrupt handling functions
56 ****************************************************************************/
58 static void iommu_print_event(void *__evt)
61 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
62 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
63 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
64 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
65 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
67 printk(KERN_ERR "AMD IOMMU: Event logged [");
70 case EVENT_TYPE_ILL_DEV:
71 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
72 "address=0x%016llx flags=0x%04x]\n",
73 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
76 case EVENT_TYPE_IO_FAULT:
77 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
78 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
79 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
80 domid, address, flags);
82 case EVENT_TYPE_DEV_TAB_ERR:
83 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
84 "address=0x%016llx flags=0x%04x]\n",
85 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
88 case EVENT_TYPE_PAGE_TAB_ERR:
89 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
90 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
91 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
92 domid, address, flags);
94 case EVENT_TYPE_ILL_CMD:
95 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
97 case EVENT_TYPE_CMD_HARD_ERR:
98 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
99 "flags=0x%04x]\n", address, flags);
101 case EVENT_TYPE_IOTLB_INV_TO:
102 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
103 "address=0x%016llx]\n",
104 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
107 case EVENT_TYPE_INV_DEV_REQ:
108 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
109 "address=0x%016llx flags=0x%04x]\n",
110 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
114 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
118 static void iommu_poll_events(struct amd_iommu *iommu)
123 spin_lock_irqsave(&iommu->lock, flags);
125 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
126 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
128 while (head != tail) {
129 iommu_print_event(iommu->evt_buf + head);
130 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
133 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
135 spin_unlock_irqrestore(&iommu->lock, flags);
138 irqreturn_t amd_iommu_int_handler(int irq, void *data)
140 struct amd_iommu *iommu;
142 list_for_each_entry(iommu, &amd_iommu_list, list)
143 iommu_poll_events(iommu);
148 /****************************************************************************
150 * IOMMU command queuing functions
152 ****************************************************************************/
155 * Writes the command to the IOMMUs command buffer and informs the
156 * hardware about the new command. Must be called with iommu->lock held.
158 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
163 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
164 target = iommu->cmd_buf + tail;
165 memcpy_toio(target, cmd, sizeof(*cmd));
166 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
167 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
170 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
176 * General queuing function for commands. Takes iommu->lock and calls
177 * __iommu_queue_command().
179 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
184 spin_lock_irqsave(&iommu->lock, flags);
185 ret = __iommu_queue_command(iommu, cmd);
186 spin_unlock_irqrestore(&iommu->lock, flags);
192 * This function is called whenever we need to ensure that the IOMMU has
193 * completed execution of all commands we sent. It sends a
194 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
195 * us about that by writing a value to a physical address we pass with
198 static int iommu_completion_wait(struct amd_iommu *iommu)
202 struct iommu_cmd cmd;
205 memset(&cmd, 0, sizeof(cmd));
206 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
207 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
209 iommu->need_sync = 0;
211 ret = iommu_queue_command(iommu, &cmd);
216 while (!ready && (i < EXIT_LOOP_COUNT)) {
218 /* wait for the bit to become one */
219 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
220 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
223 /* set bit back to zero */
224 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
225 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
227 if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
228 printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
234 * Command send function for invalidating a device table entry
236 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
238 struct iommu_cmd cmd;
240 BUG_ON(iommu == NULL);
242 memset(&cmd, 0, sizeof(cmd));
243 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
246 iommu->need_sync = 1;
248 return iommu_queue_command(iommu, &cmd);
252 * Generic command send function for invalidaing TLB entries
254 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
255 u64 address, u16 domid, int pde, int s)
257 struct iommu_cmd cmd;
259 memset(&cmd, 0, sizeof(cmd));
260 address &= PAGE_MASK;
261 CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
262 cmd.data[1] |= domid;
263 cmd.data[2] = lower_32_bits(address);
264 cmd.data[3] = upper_32_bits(address);
265 if (s) /* size bit - we flush more than one 4kb page */
266 cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
267 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
268 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
270 iommu->need_sync = 1;
272 return iommu_queue_command(iommu, &cmd);
276 * TLB invalidation function which is called from the mapping functions.
277 * It invalidates a single PTE if the range to flush is within a single
278 * page. Otherwise it flushes the whole TLB of the IOMMU.
280 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
281 u64 address, size_t size)
284 unsigned pages = iommu_num_pages(address, size);
286 address &= PAGE_MASK;
290 * If we have to flush more than one page, flush all
291 * TLB entries for this domain
293 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
297 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
302 /* Flush the whole IO/TLB for a given protection domain */
303 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
305 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
307 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
310 /****************************************************************************
312 * The functions below are used the create the page table mappings for
313 * unity mapped regions.
315 ****************************************************************************/
318 * Generic mapping functions. It maps a physical address into a DMA
319 * address space. It allocates the page table pages if necessary.
320 * In the future it can be extended to a generic mapping function
321 * supporting all features of AMD IOMMU page tables like level skipping
322 * and full 64 bit address spaces.
324 static int iommu_map(struct protection_domain *dom,
325 unsigned long bus_addr,
326 unsigned long phys_addr,
329 u64 __pte, *pte, *page;
331 bus_addr = PAGE_ALIGN(bus_addr);
332 phys_addr = PAGE_ALIGN(bus_addr);
334 /* only support 512GB address spaces for now */
335 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
338 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
340 if (!IOMMU_PTE_PRESENT(*pte)) {
341 page = (u64 *)get_zeroed_page(GFP_KERNEL);
344 *pte = IOMMU_L2_PDE(virt_to_phys(page));
347 pte = IOMMU_PTE_PAGE(*pte);
348 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
350 if (!IOMMU_PTE_PRESENT(*pte)) {
351 page = (u64 *)get_zeroed_page(GFP_KERNEL);
354 *pte = IOMMU_L1_PDE(virt_to_phys(page));
357 pte = IOMMU_PTE_PAGE(*pte);
358 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
360 if (IOMMU_PTE_PRESENT(*pte))
363 __pte = phys_addr | IOMMU_PTE_P;
364 if (prot & IOMMU_PROT_IR)
365 __pte |= IOMMU_PTE_IR;
366 if (prot & IOMMU_PROT_IW)
367 __pte |= IOMMU_PTE_IW;
375 * This function checks if a specific unity mapping entry is needed for
376 * this specific IOMMU.
378 static int iommu_for_unity_map(struct amd_iommu *iommu,
379 struct unity_map_entry *entry)
383 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
384 bdf = amd_iommu_alias_table[i];
385 if (amd_iommu_rlookup_table[bdf] == iommu)
393 * Init the unity mappings for a specific IOMMU in the system
395 * Basically iterates over all unity mapping entries and applies them to
396 * the default domain DMA of that IOMMU if necessary.
398 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
400 struct unity_map_entry *entry;
403 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
404 if (!iommu_for_unity_map(iommu, entry))
406 ret = dma_ops_unity_map(iommu->default_dom, entry);
415 * This function actually applies the mapping to the page table of the
418 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
419 struct unity_map_entry *e)
424 for (addr = e->address_start; addr < e->address_end;
426 ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
430 * if unity mapping is in aperture range mark the page
431 * as allocated in the aperture
433 if (addr < dma_dom->aperture_size)
434 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
441 * Inits the unity mappings required for a specific device
443 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
446 struct unity_map_entry *e;
449 list_for_each_entry(e, &amd_iommu_unity_map, list) {
450 if (!(devid >= e->devid_start && devid <= e->devid_end))
452 ret = dma_ops_unity_map(dma_dom, e);
460 /****************************************************************************
462 * The next functions belong to the address allocator for the dma_ops
463 * interface functions. They work like the allocators in the other IOMMU
464 * drivers. Its basically a bitmap which marks the allocated pages in
465 * the aperture. Maybe it could be enhanced in the future to a more
466 * efficient allocator.
468 ****************************************************************************/
469 static unsigned long dma_mask_to_pages(unsigned long mask)
471 return (mask >> PAGE_SHIFT) +
472 (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT);
476 * The address allocator core function.
478 * called with domain->lock held
480 static unsigned long dma_ops_alloc_addresses(struct device *dev,
481 struct dma_ops_domain *dom,
483 unsigned long align_mask)
485 unsigned long limit = dma_mask_to_pages(*dev->dma_mask);
486 unsigned long address;
487 unsigned long size = dom->aperture_size >> PAGE_SHIFT;
488 unsigned long boundary_size;
490 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
491 PAGE_SIZE) >> PAGE_SHIFT;
492 limit = limit < size ? limit : size;
494 if (dom->next_bit >= limit) {
496 dom->need_flush = true;
499 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
500 0 , boundary_size, align_mask);
502 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
503 0, boundary_size, align_mask);
504 dom->need_flush = true;
507 if (likely(address != -1)) {
508 dom->next_bit = address + pages;
509 address <<= PAGE_SHIFT;
511 address = bad_dma_address;
513 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
519 * The address free function.
521 * called with domain->lock held
523 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
524 unsigned long address,
527 address >>= PAGE_SHIFT;
528 iommu_area_free(dom->bitmap, address, pages);
531 /****************************************************************************
533 * The next functions belong to the domain allocation. A domain is
534 * allocated for every IOMMU as the default domain. If device isolation
535 * is enabled, every device get its own domain. The most important thing
536 * about domains is the page table mapping the DMA address space they
539 ****************************************************************************/
541 static u16 domain_id_alloc(void)
546 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
547 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
549 if (id > 0 && id < MAX_DOMAIN_ID)
550 __set_bit(id, amd_iommu_pd_alloc_bitmap);
553 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
559 * Used to reserve address ranges in the aperture (e.g. for exclusion
562 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
563 unsigned long start_page,
566 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
568 if (start_page + pages > last_page)
569 pages = last_page - start_page;
571 set_bit_string(dom->bitmap, start_page, pages);
574 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
579 p1 = dma_dom->domain.pt_root;
584 for (i = 0; i < 512; ++i) {
585 if (!IOMMU_PTE_PRESENT(p1[i]))
588 p2 = IOMMU_PTE_PAGE(p1[i]);
589 for (j = 0; j < 512; ++i) {
590 if (!IOMMU_PTE_PRESENT(p2[j]))
592 p3 = IOMMU_PTE_PAGE(p2[j]);
593 free_page((unsigned long)p3);
596 free_page((unsigned long)p2);
599 free_page((unsigned long)p1);
603 * Free a domain, only used if something went wrong in the
604 * allocation path and we need to free an already allocated page table
606 static void dma_ops_domain_free(struct dma_ops_domain *dom)
611 dma_ops_free_pagetable(dom);
613 kfree(dom->pte_pages);
621 * Allocates a new protection domain usable for the dma_ops functions.
622 * It also intializes the page table and the address allocator data
623 * structures required for the dma_ops interface
625 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
628 struct dma_ops_domain *dma_dom;
629 unsigned i, num_pte_pages;
634 * Currently the DMA aperture must be between 32 MB and 1GB in size
636 if ((order < 25) || (order > 30))
639 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
643 spin_lock_init(&dma_dom->domain.lock);
645 dma_dom->domain.id = domain_id_alloc();
646 if (dma_dom->domain.id == 0)
648 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
649 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
650 dma_dom->domain.priv = dma_dom;
651 if (!dma_dom->domain.pt_root)
653 dma_dom->aperture_size = (1ULL << order);
654 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
656 if (!dma_dom->bitmap)
659 * mark the first page as allocated so we never return 0 as
660 * a valid dma-address. So we can use 0 as error value
662 dma_dom->bitmap[0] = 1;
663 dma_dom->next_bit = 0;
665 dma_dom->need_flush = false;
667 /* Intialize the exclusion range if necessary */
668 if (iommu->exclusion_start &&
669 iommu->exclusion_start < dma_dom->aperture_size) {
670 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
671 int pages = iommu_num_pages(iommu->exclusion_start,
672 iommu->exclusion_length);
673 dma_ops_reserve_addresses(dma_dom, startpage, pages);
677 * At the last step, build the page tables so we don't need to
678 * allocate page table pages in the dma_ops mapping/unmapping
681 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
682 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
684 if (!dma_dom->pte_pages)
687 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
691 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
693 for (i = 0; i < num_pte_pages; ++i) {
694 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
695 if (!dma_dom->pte_pages[i])
697 address = virt_to_phys(dma_dom->pte_pages[i]);
698 l2_pde[i] = IOMMU_L1_PDE(address);
704 dma_ops_domain_free(dma_dom);
710 * Find out the protection domain structure for a given PCI device. This
711 * will give us the pointer to the page table root for example.
713 static struct protection_domain *domain_for_device(u16 devid)
715 struct protection_domain *dom;
718 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
719 dom = amd_iommu_pd_table[devid];
720 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
726 * If a device is not yet associated with a domain, this function does
727 * assigns it visible for the hardware
729 static void set_device_domain(struct amd_iommu *iommu,
730 struct protection_domain *domain,
735 u64 pte_root = virt_to_phys(domain->pt_root);
737 pte_root |= (domain->mode & 0x07) << 9;
738 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2;
740 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
741 amd_iommu_dev_table[devid].data[0] = pte_root;
742 amd_iommu_dev_table[devid].data[1] = pte_root >> 32;
743 amd_iommu_dev_table[devid].data[2] = domain->id;
745 amd_iommu_pd_table[devid] = domain;
746 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
748 iommu_queue_inv_dev_entry(iommu, devid);
750 iommu->need_sync = 1;
753 /*****************************************************************************
755 * The next functions belong to the dma_ops mapping/unmapping code.
757 *****************************************************************************/
760 * This function checks if the driver got a valid device from the caller to
761 * avoid dereferencing invalid pointers.
763 static bool check_device(struct device *dev)
765 if (!dev || !dev->dma_mask)
772 * In the dma_ops path we only have the struct device. This function
773 * finds the corresponding IOMMU, the protection domain and the
774 * requestor id for a given device.
775 * If the device is not yet associated with a domain this is also done
778 static int get_device_resources(struct device *dev,
779 struct amd_iommu **iommu,
780 struct protection_domain **domain,
783 struct dma_ops_domain *dma_dom;
784 struct pci_dev *pcidev;
791 if (dev->bus != &pci_bus_type)
794 pcidev = to_pci_dev(dev);
795 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
797 /* device not translated by any IOMMU in the system? */
798 if (_bdf > amd_iommu_last_bdf)
801 *bdf = amd_iommu_alias_table[_bdf];
803 *iommu = amd_iommu_rlookup_table[*bdf];
806 dma_dom = (*iommu)->default_dom;
807 *domain = domain_for_device(*bdf);
808 if (*domain == NULL) {
809 *domain = &dma_dom->domain;
810 set_device_domain(*iommu, *domain, *bdf);
811 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
812 "device ", (*domain)->id);
813 print_devid(_bdf, 1);
820 * This is the generic map function. It maps one 4kb page at paddr to
821 * the given address in the DMA address space for the domain.
823 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
824 struct dma_ops_domain *dom,
825 unsigned long address,
831 WARN_ON(address > dom->aperture_size);
835 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
836 pte += IOMMU_PTE_L0_INDEX(address);
838 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
840 if (direction == DMA_TO_DEVICE)
841 __pte |= IOMMU_PTE_IR;
842 else if (direction == DMA_FROM_DEVICE)
843 __pte |= IOMMU_PTE_IW;
844 else if (direction == DMA_BIDIRECTIONAL)
845 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
851 return (dma_addr_t)address;
855 * The generic unmapping function for on page in the DMA address space.
857 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
858 struct dma_ops_domain *dom,
859 unsigned long address)
863 if (address >= dom->aperture_size)
866 WARN_ON(address & 0xfffULL || address > dom->aperture_size);
868 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
869 pte += IOMMU_PTE_L0_INDEX(address);
877 * This function contains common code for mapping of a physically
878 * contiguous memory region into DMA address space. It is uses by all
879 * mapping functions provided by this IOMMU driver.
880 * Must be called with the domain lock held.
882 static dma_addr_t __map_single(struct device *dev,
883 struct amd_iommu *iommu,
884 struct dma_ops_domain *dma_dom,
890 dma_addr_t offset = paddr & ~PAGE_MASK;
891 dma_addr_t address, start;
893 unsigned long align_mask = 0;
896 pages = iommu_num_pages(paddr, size);
900 align_mask = (1UL << get_order(size)) - 1;
902 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask);
903 if (unlikely(address == bad_dma_address))
907 for (i = 0; i < pages; ++i) {
908 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
914 if (unlikely(dma_dom->need_flush && !iommu_fullflush)) {
915 iommu_flush_tlb(iommu, dma_dom->domain.id);
916 dma_dom->need_flush = false;
917 } else if (unlikely(iommu_has_npcache(iommu)))
918 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
925 * Does the reverse of the __map_single function. Must be called with
926 * the domain lock held too
928 static void __unmap_single(struct amd_iommu *iommu,
929 struct dma_ops_domain *dma_dom,
937 if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
940 pages = iommu_num_pages(dma_addr, size);
941 dma_addr &= PAGE_MASK;
944 for (i = 0; i < pages; ++i) {
945 dma_ops_domain_unmap(iommu, dma_dom, start);
949 dma_ops_free_addresses(dma_dom, dma_addr, pages);
952 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
956 * The exported map_single function for dma_ops.
958 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
959 size_t size, int dir)
962 struct amd_iommu *iommu;
963 struct protection_domain *domain;
967 if (!check_device(dev))
968 return bad_dma_address;
970 get_device_resources(dev, &iommu, &domain, &devid);
972 if (iommu == NULL || domain == NULL)
973 /* device not handled by any AMD IOMMU */
974 return (dma_addr_t)paddr;
976 spin_lock_irqsave(&domain->lock, flags);
977 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false);
978 if (addr == bad_dma_address)
981 if (unlikely(iommu->need_sync))
982 iommu_completion_wait(iommu);
985 spin_unlock_irqrestore(&domain->lock, flags);
991 * The exported unmap_single function for dma_ops.
993 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
994 size_t size, int dir)
997 struct amd_iommu *iommu;
998 struct protection_domain *domain;
1001 if (!check_device(dev) ||
1002 !get_device_resources(dev, &iommu, &domain, &devid))
1003 /* device not handled by any AMD IOMMU */
1006 spin_lock_irqsave(&domain->lock, flags);
1008 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1010 if (unlikely(iommu->need_sync))
1011 iommu_completion_wait(iommu);
1013 spin_unlock_irqrestore(&domain->lock, flags);
1017 * This is a special map_sg function which is used if we should map a
1018 * device which is not handled by an AMD IOMMU in the system.
1020 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1021 int nelems, int dir)
1023 struct scatterlist *s;
1026 for_each_sg(sglist, s, nelems, i) {
1027 s->dma_address = (dma_addr_t)sg_phys(s);
1028 s->dma_length = s->length;
1035 * The exported map_sg function for dma_ops (handles scatter-gather
1038 static int map_sg(struct device *dev, struct scatterlist *sglist,
1039 int nelems, int dir)
1041 unsigned long flags;
1042 struct amd_iommu *iommu;
1043 struct protection_domain *domain;
1046 struct scatterlist *s;
1048 int mapped_elems = 0;
1050 if (!check_device(dev))
1053 get_device_resources(dev, &iommu, &domain, &devid);
1055 if (!iommu || !domain)
1056 return map_sg_no_iommu(dev, sglist, nelems, dir);
1058 spin_lock_irqsave(&domain->lock, flags);
1060 for_each_sg(sglist, s, nelems, i) {
1063 s->dma_address = __map_single(dev, iommu, domain->priv,
1064 paddr, s->length, dir, false);
1066 if (s->dma_address) {
1067 s->dma_length = s->length;
1073 if (unlikely(iommu->need_sync))
1074 iommu_completion_wait(iommu);
1077 spin_unlock_irqrestore(&domain->lock, flags);
1079 return mapped_elems;
1081 for_each_sg(sglist, s, mapped_elems, i) {
1083 __unmap_single(iommu, domain->priv, s->dma_address,
1084 s->dma_length, dir);
1085 s->dma_address = s->dma_length = 0;
1094 * The exported map_sg function for dma_ops (handles scatter-gather
1097 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1098 int nelems, int dir)
1100 unsigned long flags;
1101 struct amd_iommu *iommu;
1102 struct protection_domain *domain;
1103 struct scatterlist *s;
1107 if (!check_device(dev) ||
1108 !get_device_resources(dev, &iommu, &domain, &devid))
1111 spin_lock_irqsave(&domain->lock, flags);
1113 for_each_sg(sglist, s, nelems, i) {
1114 __unmap_single(iommu, domain->priv, s->dma_address,
1115 s->dma_length, dir);
1116 s->dma_address = s->dma_length = 0;
1119 if (unlikely(iommu->need_sync))
1120 iommu_completion_wait(iommu);
1122 spin_unlock_irqrestore(&domain->lock, flags);
1126 * The exported alloc_coherent function for dma_ops.
1128 static void *alloc_coherent(struct device *dev, size_t size,
1129 dma_addr_t *dma_addr, gfp_t flag)
1131 unsigned long flags;
1133 struct amd_iommu *iommu;
1134 struct protection_domain *domain;
1138 if (!check_device(dev))
1141 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1145 memset(virt_addr, 0, size);
1146 paddr = virt_to_phys(virt_addr);
1148 get_device_resources(dev, &iommu, &domain, &devid);
1150 if (!iommu || !domain) {
1151 *dma_addr = (dma_addr_t)paddr;
1155 spin_lock_irqsave(&domain->lock, flags);
1157 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1158 size, DMA_BIDIRECTIONAL, true);
1160 if (*dma_addr == bad_dma_address) {
1161 free_pages((unsigned long)virt_addr, get_order(size));
1166 if (unlikely(iommu->need_sync))
1167 iommu_completion_wait(iommu);
1170 spin_unlock_irqrestore(&domain->lock, flags);
1176 * The exported free_coherent function for dma_ops.
1178 static void free_coherent(struct device *dev, size_t size,
1179 void *virt_addr, dma_addr_t dma_addr)
1181 unsigned long flags;
1182 struct amd_iommu *iommu;
1183 struct protection_domain *domain;
1186 if (!check_device(dev))
1189 get_device_resources(dev, &iommu, &domain, &devid);
1191 if (!iommu || !domain)
1194 spin_lock_irqsave(&domain->lock, flags);
1196 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1198 if (unlikely(iommu->need_sync))
1199 iommu_completion_wait(iommu);
1201 spin_unlock_irqrestore(&domain->lock, flags);
1204 free_pages((unsigned long)virt_addr, get_order(size));
1208 * This function is called by the DMA layer to find out if we can handle a
1209 * particular device. It is part of the dma_ops.
1211 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1214 struct pci_dev *pcidev;
1216 /* No device or no PCI device */
1217 if (!dev || dev->bus != &pci_bus_type)
1220 pcidev = to_pci_dev(dev);
1222 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1224 /* Out of our scope? */
1225 if (bdf > amd_iommu_last_bdf)
1232 * The function for pre-allocating protection domains.
1234 * If the driver core informs the DMA layer if a driver grabs a device
1235 * we don't need to preallocate the protection domains anymore.
1236 * For now we have to.
1238 void prealloc_protection_domains(void)
1240 struct pci_dev *dev = NULL;
1241 struct dma_ops_domain *dma_dom;
1242 struct amd_iommu *iommu;
1243 int order = amd_iommu_aperture_order;
1246 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1247 devid = (dev->bus->number << 8) | dev->devfn;
1248 if (devid > amd_iommu_last_bdf)
1250 devid = amd_iommu_alias_table[devid];
1251 if (domain_for_device(devid))
1253 iommu = amd_iommu_rlookup_table[devid];
1256 dma_dom = dma_ops_domain_alloc(iommu, order);
1259 init_unity_mappings_for_device(dma_dom, devid);
1260 set_device_domain(iommu, &dma_dom->domain, devid);
1261 printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ",
1262 dma_dom->domain.id);
1263 print_devid(devid, 1);
1267 static struct dma_mapping_ops amd_iommu_dma_ops = {
1268 .alloc_coherent = alloc_coherent,
1269 .free_coherent = free_coherent,
1270 .map_single = map_single,
1271 .unmap_single = unmap_single,
1273 .unmap_sg = unmap_sg,
1274 .dma_supported = amd_iommu_dma_supported,
1278 * The function which clues the AMD IOMMU driver into dma_ops.
1280 int __init amd_iommu_init_dma_ops(void)
1282 struct amd_iommu *iommu;
1283 int order = amd_iommu_aperture_order;
1287 * first allocate a default protection domain for every IOMMU we
1288 * found in the system. Devices not assigned to any other
1289 * protection domain will be assigned to the default one.
1291 list_for_each_entry(iommu, &amd_iommu_list, list) {
1292 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1293 if (iommu->default_dom == NULL)
1295 ret = iommu_init_unity_mappings(iommu);
1301 * If device isolation is enabled, pre-allocate the protection
1302 * domains for each device.
1304 if (amd_iommu_isolate)
1305 prealloc_protection_domains();
1309 bad_dma_address = 0;
1310 #ifdef CONFIG_GART_IOMMU
1311 gart_iommu_aperture_disabled = 1;
1312 gart_iommu_aperture = 0;
1315 /* Make the driver finally visible to the drivers */
1316 dma_ops = &amd_iommu_dma_ops;
1322 list_for_each_entry(iommu, &amd_iommu_list, list) {
1323 if (iommu->default_dom)
1324 dma_ops_domain_free(iommu->default_dom);