2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/bitmap.h>
22 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <linux/delay.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_proto.h>
33 #include <asm/amd_iommu_types.h>
34 #include <asm/amd_iommu.h>
36 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
38 #define LOOP_TIMEOUT 100000
40 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
42 /* A list of preallocated protection domains */
43 static LIST_HEAD(iommu_pd_list);
44 static DEFINE_SPINLOCK(iommu_pd_list_lock);
47 * Domain for untranslated devices - only allocated
48 * if iommu=pt passed on kernel cmd line.
50 static struct protection_domain *pt_domain;
52 static struct iommu_ops amd_iommu_ops;
55 * general struct to manage commands send to an IOMMU
61 static void update_domain(struct protection_domain *domain);
63 /****************************************************************************
67 ****************************************************************************/
69 static inline u16 get_device_id(struct device *dev)
71 struct pci_dev *pdev = to_pci_dev(dev);
73 return calc_devid(pdev->bus->number, pdev->devfn);
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
78 return dev->archdata.iommu;
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
87 struct dma_ops_domain *entry, *ret = NULL;
89 u16 alias = amd_iommu_alias_table[devid];
91 if (list_empty(&iommu_pd_list))
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
113 static bool check_device(struct device *dev)
117 if (!dev || !dev->dma_mask)
120 /* No device or no PCI device */
121 if (dev->bus != &pci_bus_type)
124 devid = get_device_id(dev);
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
130 if (amd_iommu_rlookup_table[devid] == NULL)
136 static int iommu_init_device(struct device *dev)
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
142 if (dev->archdata.iommu)
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
151 devid = get_device_id(dev);
152 alias = amd_iommu_alias_table[devid];
153 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
155 dev_data->alias = &pdev->dev;
157 atomic_set(&dev_data->bind, 0);
159 dev->archdata.iommu = dev_data;
165 static void iommu_uninit_device(struct device *dev)
167 kfree(dev->archdata.iommu);
170 void __init amd_iommu_uninit_devices(void)
172 struct pci_dev *pdev = NULL;
174 for_each_pci_dev(pdev) {
176 if (!check_device(&pdev->dev))
179 iommu_uninit_device(&pdev->dev);
183 int __init amd_iommu_init_devices(void)
185 struct pci_dev *pdev = NULL;
188 for_each_pci_dev(pdev) {
190 if (!check_device(&pdev->dev))
193 ret = iommu_init_device(&pdev->dev);
202 amd_iommu_uninit_devices();
206 #ifdef CONFIG_AMD_IOMMU_STATS
209 * Initialization code for statistics collection
212 DECLARE_STATS_COUNTER(compl_wait);
213 DECLARE_STATS_COUNTER(cnt_map_single);
214 DECLARE_STATS_COUNTER(cnt_unmap_single);
215 DECLARE_STATS_COUNTER(cnt_map_sg);
216 DECLARE_STATS_COUNTER(cnt_unmap_sg);
217 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
218 DECLARE_STATS_COUNTER(cnt_free_coherent);
219 DECLARE_STATS_COUNTER(cross_page);
220 DECLARE_STATS_COUNTER(domain_flush_single);
221 DECLARE_STATS_COUNTER(domain_flush_all);
222 DECLARE_STATS_COUNTER(alloced_io_mem);
223 DECLARE_STATS_COUNTER(total_map_requests);
225 static struct dentry *stats_dir;
226 static struct dentry *de_fflush;
228 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
230 if (stats_dir == NULL)
233 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
237 static void amd_iommu_stats_init(void)
239 stats_dir = debugfs_create_dir("amd-iommu", NULL);
240 if (stats_dir == NULL)
243 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
244 (u32 *)&amd_iommu_unmap_flush);
246 amd_iommu_stats_add(&compl_wait);
247 amd_iommu_stats_add(&cnt_map_single);
248 amd_iommu_stats_add(&cnt_unmap_single);
249 amd_iommu_stats_add(&cnt_map_sg);
250 amd_iommu_stats_add(&cnt_unmap_sg);
251 amd_iommu_stats_add(&cnt_alloc_coherent);
252 amd_iommu_stats_add(&cnt_free_coherent);
253 amd_iommu_stats_add(&cross_page);
254 amd_iommu_stats_add(&domain_flush_single);
255 amd_iommu_stats_add(&domain_flush_all);
256 amd_iommu_stats_add(&alloced_io_mem);
257 amd_iommu_stats_add(&total_map_requests);
262 /****************************************************************************
264 * Interrupt handling functions
266 ****************************************************************************/
268 static void dump_dte_entry(u16 devid)
272 for (i = 0; i < 8; ++i)
273 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
274 amd_iommu_dev_table[devid].data[i]);
277 static void dump_command(unsigned long phys_addr)
279 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
282 for (i = 0; i < 4; ++i)
283 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
286 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
289 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
290 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
291 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
292 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
293 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
295 printk(KERN_ERR "AMD-Vi: Event logged [");
298 case EVENT_TYPE_ILL_DEV:
299 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
300 "address=0x%016llx flags=0x%04x]\n",
301 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
303 dump_dte_entry(devid);
305 case EVENT_TYPE_IO_FAULT:
306 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
307 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
308 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
309 domid, address, flags);
311 case EVENT_TYPE_DEV_TAB_ERR:
312 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
313 "address=0x%016llx flags=0x%04x]\n",
314 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
317 case EVENT_TYPE_PAGE_TAB_ERR:
318 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
319 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
320 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
321 domid, address, flags);
323 case EVENT_TYPE_ILL_CMD:
324 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
325 dump_command(address);
327 case EVENT_TYPE_CMD_HARD_ERR:
328 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
329 "flags=0x%04x]\n", address, flags);
331 case EVENT_TYPE_IOTLB_INV_TO:
332 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
333 "address=0x%016llx]\n",
334 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
337 case EVENT_TYPE_INV_DEV_REQ:
338 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
339 "address=0x%016llx flags=0x%04x]\n",
340 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
344 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
348 static void iommu_poll_events(struct amd_iommu *iommu)
353 spin_lock_irqsave(&iommu->lock, flags);
355 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
356 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
358 while (head != tail) {
359 iommu_print_event(iommu, iommu->evt_buf + head);
360 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
363 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
365 spin_unlock_irqrestore(&iommu->lock, flags);
368 irqreturn_t amd_iommu_int_handler(int irq, void *data)
370 struct amd_iommu *iommu;
372 for_each_iommu(iommu)
373 iommu_poll_events(iommu);
378 /****************************************************************************
380 * IOMMU command queuing functions
382 ****************************************************************************/
384 static int wait_on_sem(volatile u64 *sem)
388 while (*sem == 0 && i < LOOP_TIMEOUT) {
393 if (i == LOOP_TIMEOUT) {
394 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
401 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
402 struct iommu_cmd *cmd,
407 target = iommu->cmd_buf + tail;
408 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
410 /* Copy command to buffer */
411 memcpy(target, cmd, sizeof(*cmd));
413 /* Tell the IOMMU about it */
414 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
417 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
419 WARN_ON(address & 0x7ULL);
421 memset(cmd, 0, sizeof(*cmd));
422 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
423 cmd->data[1] = upper_32_bits(__pa(address));
425 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
428 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
430 memset(cmd, 0, sizeof(*cmd));
431 cmd->data[0] = devid;
432 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
435 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
436 size_t size, u16 domid, int pde)
441 pages = iommu_num_pages(address, size, PAGE_SIZE);
446 * If we have to flush more than one page, flush all
447 * TLB entries for this domain
449 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
453 address &= PAGE_MASK;
455 memset(cmd, 0, sizeof(*cmd));
456 cmd->data[1] |= domid;
457 cmd->data[2] = lower_32_bits(address);
458 cmd->data[3] = upper_32_bits(address);
459 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
460 if (s) /* size bit - we flush more than one 4kb page */
461 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
462 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
463 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
467 * Writes the command to the IOMMUs command buffer and informs the
468 * hardware about the new command.
470 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
472 u32 left, tail, head, next_tail;
475 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
478 spin_lock_irqsave(&iommu->lock, flags);
480 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
481 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
482 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
483 left = (head - next_tail) % iommu->cmd_buf_size;
486 struct iommu_cmd sync_cmd;
487 volatile u64 sem = 0;
490 build_completion_wait(&sync_cmd, (u64)&sem);
491 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
493 spin_unlock_irqrestore(&iommu->lock, flags);
495 if ((ret = wait_on_sem(&sem)) != 0)
501 copy_cmd_to_buffer(iommu, cmd, tail);
503 /* We need to sync now to make sure all commands are processed */
504 iommu->need_sync = true;
506 spin_unlock_irqrestore(&iommu->lock, flags);
512 * This function queues a completion wait command into the command
515 static int iommu_completion_wait(struct amd_iommu *iommu)
517 struct iommu_cmd cmd;
518 volatile u64 sem = 0;
521 if (!iommu->need_sync)
524 build_completion_wait(&cmd, (u64)&sem);
526 ret = iommu_queue_command(iommu, &cmd);
530 return wait_on_sem(&sem);
533 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
535 struct iommu_cmd cmd;
537 build_inv_dte(&cmd, devid);
539 return iommu_queue_command(iommu, &cmd);
543 * Command send function for invalidating a device table entry
545 static int device_flush_dte(struct device *dev)
547 struct amd_iommu *iommu;
550 devid = get_device_id(dev);
551 iommu = amd_iommu_rlookup_table[devid];
553 return iommu_flush_dte(iommu, devid);
557 * TLB invalidation function which is called from the mapping functions.
558 * It invalidates a single PTE if the range to flush is within a single
559 * page. Otherwise it flushes the whole TLB of the IOMMU.
561 static void __domain_flush_pages(struct protection_domain *domain,
562 u64 address, size_t size, int pde)
564 struct iommu_cmd cmd;
567 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
569 for (i = 0; i < amd_iommus_present; ++i) {
570 if (!domain->dev_iommu[i])
574 * Devices of this domain are behind this IOMMU
575 * We need a TLB flush
577 ret |= iommu_queue_command(amd_iommus[i], &cmd);
583 static void domain_flush_pages(struct protection_domain *domain,
584 u64 address, size_t size)
586 __domain_flush_pages(domain, address, size, 0);
589 /* Flush the whole IO/TLB for a given protection domain */
590 static void domain_flush_tlb(struct protection_domain *domain)
592 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
595 /* Flush the whole IO/TLB for a given protection domain - including PDE */
596 static void domain_flush_tlb_pde(struct protection_domain *domain)
598 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
601 static void domain_flush_complete(struct protection_domain *domain)
605 for (i = 0; i < amd_iommus_present; ++i) {
606 if (!domain->dev_iommu[i])
610 * Devices of this domain are behind this IOMMU
611 * We need to wait for completion of all commands.
613 iommu_completion_wait(amd_iommus[i]);
619 * This function flushes the DTEs for all devices in domain
621 static void domain_flush_devices(struct protection_domain *domain)
623 struct iommu_dev_data *dev_data;
626 spin_lock_irqsave(&domain->lock, flags);
628 list_for_each_entry(dev_data, &domain->dev_list, list)
629 device_flush_dte(dev_data->dev);
631 spin_unlock_irqrestore(&domain->lock, flags);
634 static void iommu_flush_all_domain_devices(void)
636 struct protection_domain *domain;
639 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
641 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
642 domain_flush_devices(domain);
643 domain_flush_complete(domain);
646 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
649 void amd_iommu_flush_all_devices(void)
651 iommu_flush_all_domain_devices();
655 * This function uses heavy locking and may disable irqs for some time. But
656 * this is no issue because it is only called during resume.
658 void amd_iommu_flush_all_domains(void)
660 struct protection_domain *domain;
663 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
665 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
666 spin_lock(&domain->lock);
667 domain_flush_tlb_pde(domain);
668 domain_flush_complete(domain);
669 spin_unlock(&domain->lock);
672 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
675 /****************************************************************************
677 * The functions below are used the create the page table mappings for
678 * unity mapped regions.
680 ****************************************************************************/
683 * This function is used to add another level to an IO page table. Adding
684 * another level increases the size of the address space by 9 bits to a size up
687 static bool increase_address_space(struct protection_domain *domain,
692 if (domain->mode == PAGE_MODE_6_LEVEL)
693 /* address space already 64 bit large */
696 pte = (void *)get_zeroed_page(gfp);
700 *pte = PM_LEVEL_PDE(domain->mode,
701 virt_to_phys(domain->pt_root));
702 domain->pt_root = pte;
704 domain->updated = true;
709 static u64 *alloc_pte(struct protection_domain *domain,
710 unsigned long address,
711 unsigned long page_size,
718 BUG_ON(!is_power_of_2(page_size));
720 while (address > PM_LEVEL_SIZE(domain->mode))
721 increase_address_space(domain, gfp);
723 level = domain->mode - 1;
724 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
725 address = PAGE_SIZE_ALIGN(address, page_size);
726 end_lvl = PAGE_SIZE_LEVEL(page_size);
728 while (level > end_lvl) {
729 if (!IOMMU_PTE_PRESENT(*pte)) {
730 page = (u64 *)get_zeroed_page(gfp);
733 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
736 /* No level skipping support yet */
737 if (PM_PTE_LEVEL(*pte) != level)
742 pte = IOMMU_PTE_PAGE(*pte);
744 if (pte_page && level == end_lvl)
747 pte = &pte[PM_LEVEL_INDEX(level, address)];
754 * This function checks if there is a PTE for a given dma address. If
755 * there is one, it returns the pointer to it.
757 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
762 if (address > PM_LEVEL_SIZE(domain->mode))
765 level = domain->mode - 1;
766 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
771 if (!IOMMU_PTE_PRESENT(*pte))
775 if (PM_PTE_LEVEL(*pte) == 0x07) {
776 unsigned long pte_mask, __pte;
779 * If we have a series of large PTEs, make
780 * sure to return a pointer to the first one.
782 pte_mask = PTE_PAGE_SIZE(*pte);
783 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
784 __pte = ((unsigned long)pte) & pte_mask;
789 /* No level skipping support yet */
790 if (PM_PTE_LEVEL(*pte) != level)
795 /* Walk to the next level */
796 pte = IOMMU_PTE_PAGE(*pte);
797 pte = &pte[PM_LEVEL_INDEX(level, address)];
804 * Generic mapping functions. It maps a physical address into a DMA
805 * address space. It allocates the page table pages if necessary.
806 * In the future it can be extended to a generic mapping function
807 * supporting all features of AMD IOMMU page tables like level skipping
808 * and full 64 bit address spaces.
810 static int iommu_map_page(struct protection_domain *dom,
811 unsigned long bus_addr,
812 unsigned long phys_addr,
814 unsigned long page_size)
819 if (!(prot & IOMMU_PROT_MASK))
822 bus_addr = PAGE_ALIGN(bus_addr);
823 phys_addr = PAGE_ALIGN(phys_addr);
824 count = PAGE_SIZE_PTE_COUNT(page_size);
825 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
827 for (i = 0; i < count; ++i)
828 if (IOMMU_PTE_PRESENT(pte[i]))
831 if (page_size > PAGE_SIZE) {
832 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
833 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
835 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
837 if (prot & IOMMU_PROT_IR)
838 __pte |= IOMMU_PTE_IR;
839 if (prot & IOMMU_PROT_IW)
840 __pte |= IOMMU_PTE_IW;
842 for (i = 0; i < count; ++i)
850 static unsigned long iommu_unmap_page(struct protection_domain *dom,
851 unsigned long bus_addr,
852 unsigned long page_size)
854 unsigned long long unmap_size, unmapped;
857 BUG_ON(!is_power_of_2(page_size));
861 while (unmapped < page_size) {
863 pte = fetch_pte(dom, bus_addr);
867 * No PTE for this address
868 * move forward in 4kb steps
870 unmap_size = PAGE_SIZE;
871 } else if (PM_PTE_LEVEL(*pte) == 0) {
872 /* 4kb PTE found for this address */
873 unmap_size = PAGE_SIZE;
878 /* Large PTE found which maps this address */
879 unmap_size = PTE_PAGE_SIZE(*pte);
880 count = PAGE_SIZE_PTE_COUNT(unmap_size);
881 for (i = 0; i < count; i++)
885 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
886 unmapped += unmap_size;
889 BUG_ON(!is_power_of_2(unmapped));
895 * This function checks if a specific unity mapping entry is needed for
896 * this specific IOMMU.
898 static int iommu_for_unity_map(struct amd_iommu *iommu,
899 struct unity_map_entry *entry)
903 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
904 bdf = amd_iommu_alias_table[i];
905 if (amd_iommu_rlookup_table[bdf] == iommu)
913 * This function actually applies the mapping to the page table of the
916 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
917 struct unity_map_entry *e)
922 for (addr = e->address_start; addr < e->address_end;
924 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
929 * if unity mapping is in aperture range mark the page
930 * as allocated in the aperture
932 if (addr < dma_dom->aperture_size)
933 __set_bit(addr >> PAGE_SHIFT,
934 dma_dom->aperture[0]->bitmap);
941 * Init the unity mappings for a specific IOMMU in the system
943 * Basically iterates over all unity mapping entries and applies them to
944 * the default domain DMA of that IOMMU if necessary.
946 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
948 struct unity_map_entry *entry;
951 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
952 if (!iommu_for_unity_map(iommu, entry))
954 ret = dma_ops_unity_map(iommu->default_dom, entry);
963 * Inits the unity mappings required for a specific device
965 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
968 struct unity_map_entry *e;
971 list_for_each_entry(e, &amd_iommu_unity_map, list) {
972 if (!(devid >= e->devid_start && devid <= e->devid_end))
974 ret = dma_ops_unity_map(dma_dom, e);
982 /****************************************************************************
984 * The next functions belong to the address allocator for the dma_ops
985 * interface functions. They work like the allocators in the other IOMMU
986 * drivers. Its basically a bitmap which marks the allocated pages in
987 * the aperture. Maybe it could be enhanced in the future to a more
988 * efficient allocator.
990 ****************************************************************************/
993 * The address allocator core functions.
995 * called with domain->lock held
999 * Used to reserve address ranges in the aperture (e.g. for exclusion
1002 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1003 unsigned long start_page,
1006 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1008 if (start_page + pages > last_page)
1009 pages = last_page - start_page;
1011 for (i = start_page; i < start_page + pages; ++i) {
1012 int index = i / APERTURE_RANGE_PAGES;
1013 int page = i % APERTURE_RANGE_PAGES;
1014 __set_bit(page, dom->aperture[index]->bitmap);
1019 * This function is used to add a new aperture range to an existing
1020 * aperture in case of dma_ops domain allocation or address allocation
1023 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1024 bool populate, gfp_t gfp)
1026 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1027 struct amd_iommu *iommu;
1030 #ifdef CONFIG_IOMMU_STRESS
1034 if (index >= APERTURE_MAX_RANGES)
1037 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1038 if (!dma_dom->aperture[index])
1041 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1042 if (!dma_dom->aperture[index]->bitmap)
1045 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1048 unsigned long address = dma_dom->aperture_size;
1049 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1050 u64 *pte, *pte_page;
1052 for (i = 0; i < num_ptes; ++i) {
1053 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1058 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1060 address += APERTURE_RANGE_SIZE / 64;
1064 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1066 /* Initialize the exclusion range if necessary */
1067 for_each_iommu(iommu) {
1068 if (iommu->exclusion_start &&
1069 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1070 && iommu->exclusion_start < dma_dom->aperture_size) {
1071 unsigned long startpage;
1072 int pages = iommu_num_pages(iommu->exclusion_start,
1073 iommu->exclusion_length,
1075 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1076 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1081 * Check for areas already mapped as present in the new aperture
1082 * range and mark those pages as reserved in the allocator. Such
1083 * mappings may already exist as a result of requested unity
1084 * mappings for devices.
1086 for (i = dma_dom->aperture[index]->offset;
1087 i < dma_dom->aperture_size;
1089 u64 *pte = fetch_pte(&dma_dom->domain, i);
1090 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1093 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1096 update_domain(&dma_dom->domain);
1101 update_domain(&dma_dom->domain);
1103 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1105 kfree(dma_dom->aperture[index]);
1106 dma_dom->aperture[index] = NULL;
1111 static unsigned long dma_ops_area_alloc(struct device *dev,
1112 struct dma_ops_domain *dom,
1114 unsigned long align_mask,
1116 unsigned long start)
1118 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1119 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1120 int i = start >> APERTURE_RANGE_SHIFT;
1121 unsigned long boundary_size;
1122 unsigned long address = -1;
1123 unsigned long limit;
1125 next_bit >>= PAGE_SHIFT;
1127 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1128 PAGE_SIZE) >> PAGE_SHIFT;
1130 for (;i < max_index; ++i) {
1131 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1133 if (dom->aperture[i]->offset >= dma_mask)
1136 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1137 dma_mask >> PAGE_SHIFT);
1139 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1140 limit, next_bit, pages, 0,
1141 boundary_size, align_mask);
1142 if (address != -1) {
1143 address = dom->aperture[i]->offset +
1144 (address << PAGE_SHIFT);
1145 dom->next_address = address + (pages << PAGE_SHIFT);
1155 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1156 struct dma_ops_domain *dom,
1158 unsigned long align_mask,
1161 unsigned long address;
1163 #ifdef CONFIG_IOMMU_STRESS
1164 dom->next_address = 0;
1165 dom->need_flush = true;
1168 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1169 dma_mask, dom->next_address);
1171 if (address == -1) {
1172 dom->next_address = 0;
1173 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1175 dom->need_flush = true;
1178 if (unlikely(address == -1))
1179 address = DMA_ERROR_CODE;
1181 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1187 * The address free function.
1189 * called with domain->lock held
1191 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1192 unsigned long address,
1195 unsigned i = address >> APERTURE_RANGE_SHIFT;
1196 struct aperture_range *range = dom->aperture[i];
1198 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1200 #ifdef CONFIG_IOMMU_STRESS
1205 if (address >= dom->next_address)
1206 dom->need_flush = true;
1208 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1210 bitmap_clear(range->bitmap, address, pages);
1214 /****************************************************************************
1216 * The next functions belong to the domain allocation. A domain is
1217 * allocated for every IOMMU as the default domain. If device isolation
1218 * is enabled, every device get its own domain. The most important thing
1219 * about domains is the page table mapping the DMA address space they
1222 ****************************************************************************/
1225 * This function adds a protection domain to the global protection domain list
1227 static void add_domain_to_list(struct protection_domain *domain)
1229 unsigned long flags;
1231 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1232 list_add(&domain->list, &amd_iommu_pd_list);
1233 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1237 * This function removes a protection domain to the global
1238 * protection domain list
1240 static void del_domain_from_list(struct protection_domain *domain)
1242 unsigned long flags;
1244 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1245 list_del(&domain->list);
1246 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1249 static u16 domain_id_alloc(void)
1251 unsigned long flags;
1254 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1255 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1257 if (id > 0 && id < MAX_DOMAIN_ID)
1258 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1261 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1266 static void domain_id_free(int id)
1268 unsigned long flags;
1270 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1271 if (id > 0 && id < MAX_DOMAIN_ID)
1272 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1273 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1276 static void free_pagetable(struct protection_domain *domain)
1281 p1 = domain->pt_root;
1286 for (i = 0; i < 512; ++i) {
1287 if (!IOMMU_PTE_PRESENT(p1[i]))
1290 p2 = IOMMU_PTE_PAGE(p1[i]);
1291 for (j = 0; j < 512; ++j) {
1292 if (!IOMMU_PTE_PRESENT(p2[j]))
1294 p3 = IOMMU_PTE_PAGE(p2[j]);
1295 free_page((unsigned long)p3);
1298 free_page((unsigned long)p2);
1301 free_page((unsigned long)p1);
1303 domain->pt_root = NULL;
1307 * Free a domain, only used if something went wrong in the
1308 * allocation path and we need to free an already allocated page table
1310 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1317 del_domain_from_list(&dom->domain);
1319 free_pagetable(&dom->domain);
1321 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1322 if (!dom->aperture[i])
1324 free_page((unsigned long)dom->aperture[i]->bitmap);
1325 kfree(dom->aperture[i]);
1332 * Allocates a new protection domain usable for the dma_ops functions.
1333 * It also initializes the page table and the address allocator data
1334 * structures required for the dma_ops interface
1336 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1338 struct dma_ops_domain *dma_dom;
1340 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1344 spin_lock_init(&dma_dom->domain.lock);
1346 dma_dom->domain.id = domain_id_alloc();
1347 if (dma_dom->domain.id == 0)
1349 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1350 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1351 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1352 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1353 dma_dom->domain.priv = dma_dom;
1354 if (!dma_dom->domain.pt_root)
1357 dma_dom->need_flush = false;
1358 dma_dom->target_dev = 0xffff;
1360 add_domain_to_list(&dma_dom->domain);
1362 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1366 * mark the first page as allocated so we never return 0 as
1367 * a valid dma-address. So we can use 0 as error value
1369 dma_dom->aperture[0]->bitmap[0] = 1;
1370 dma_dom->next_address = 0;
1376 dma_ops_domain_free(dma_dom);
1382 * little helper function to check whether a given protection domain is a
1385 static bool dma_ops_domain(struct protection_domain *domain)
1387 return domain->flags & PD_DMA_OPS_MASK;
1390 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1392 u64 pte_root = virt_to_phys(domain->pt_root);
1394 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1395 << DEV_ENTRY_MODE_SHIFT;
1396 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1398 amd_iommu_dev_table[devid].data[2] = domain->id;
1399 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1400 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1403 static void clear_dte_entry(u16 devid)
1405 /* remove entry from the device table seen by the hardware */
1406 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1407 amd_iommu_dev_table[devid].data[1] = 0;
1408 amd_iommu_dev_table[devid].data[2] = 0;
1410 amd_iommu_apply_erratum_63(devid);
1413 static void do_attach(struct device *dev, struct protection_domain *domain)
1415 struct iommu_dev_data *dev_data;
1416 struct amd_iommu *iommu;
1419 devid = get_device_id(dev);
1420 iommu = amd_iommu_rlookup_table[devid];
1421 dev_data = get_dev_data(dev);
1423 /* Update data structures */
1424 dev_data->domain = domain;
1425 list_add(&dev_data->list, &domain->dev_list);
1426 set_dte_entry(devid, domain);
1428 /* Do reference counting */
1429 domain->dev_iommu[iommu->index] += 1;
1430 domain->dev_cnt += 1;
1432 /* Flush the DTE entry */
1433 device_flush_dte(dev);
1436 static void do_detach(struct device *dev)
1438 struct iommu_dev_data *dev_data;
1439 struct amd_iommu *iommu;
1442 devid = get_device_id(dev);
1443 iommu = amd_iommu_rlookup_table[devid];
1444 dev_data = get_dev_data(dev);
1446 /* decrease reference counters */
1447 dev_data->domain->dev_iommu[iommu->index] -= 1;
1448 dev_data->domain->dev_cnt -= 1;
1450 /* Update data structures */
1451 dev_data->domain = NULL;
1452 list_del(&dev_data->list);
1453 clear_dte_entry(devid);
1455 /* Flush the DTE entry */
1456 device_flush_dte(dev);
1460 * If a device is not yet associated with a domain, this function does
1461 * assigns it visible for the hardware
1463 static int __attach_device(struct device *dev,
1464 struct protection_domain *domain)
1466 struct iommu_dev_data *dev_data, *alias_data;
1469 dev_data = get_dev_data(dev);
1470 alias_data = get_dev_data(dev_data->alias);
1476 spin_lock(&domain->lock);
1478 /* Some sanity checks */
1480 if (alias_data->domain != NULL &&
1481 alias_data->domain != domain)
1484 if (dev_data->domain != NULL &&
1485 dev_data->domain != domain)
1488 /* Do real assignment */
1489 if (dev_data->alias != dev) {
1490 alias_data = get_dev_data(dev_data->alias);
1491 if (alias_data->domain == NULL)
1492 do_attach(dev_data->alias, domain);
1494 atomic_inc(&alias_data->bind);
1497 if (dev_data->domain == NULL)
1498 do_attach(dev, domain);
1500 atomic_inc(&dev_data->bind);
1507 spin_unlock(&domain->lock);
1513 * If a device is not yet associated with a domain, this function does
1514 * assigns it visible for the hardware
1516 static int attach_device(struct device *dev,
1517 struct protection_domain *domain)
1519 unsigned long flags;
1522 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1523 ret = __attach_device(dev, domain);
1524 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1527 * We might boot into a crash-kernel here. The crashed kernel
1528 * left the caches in the IOMMU dirty. So we have to flush
1529 * here to evict all dirty stuff.
1531 domain_flush_tlb_pde(domain);
1537 * Removes a device from a protection domain (unlocked)
1539 static void __detach_device(struct device *dev)
1541 struct iommu_dev_data *dev_data = get_dev_data(dev);
1542 struct iommu_dev_data *alias_data;
1543 struct protection_domain *domain;
1544 unsigned long flags;
1546 BUG_ON(!dev_data->domain);
1548 domain = dev_data->domain;
1550 spin_lock_irqsave(&domain->lock, flags);
1552 if (dev_data->alias != dev) {
1553 alias_data = get_dev_data(dev_data->alias);
1554 if (atomic_dec_and_test(&alias_data->bind))
1555 do_detach(dev_data->alias);
1558 if (atomic_dec_and_test(&dev_data->bind))
1561 spin_unlock_irqrestore(&domain->lock, flags);
1564 * If we run in passthrough mode the device must be assigned to the
1565 * passthrough domain if it is detached from any other domain.
1566 * Make sure we can deassign from the pt_domain itself.
1568 if (iommu_pass_through &&
1569 (dev_data->domain == NULL && domain != pt_domain))
1570 __attach_device(dev, pt_domain);
1574 * Removes a device from a protection domain (with devtable_lock held)
1576 static void detach_device(struct device *dev)
1578 unsigned long flags;
1580 /* lock device table */
1581 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1582 __detach_device(dev);
1583 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1587 * Find out the protection domain structure for a given PCI device. This
1588 * will give us the pointer to the page table root for example.
1590 static struct protection_domain *domain_for_device(struct device *dev)
1592 struct protection_domain *dom;
1593 struct iommu_dev_data *dev_data, *alias_data;
1594 unsigned long flags;
1597 devid = get_device_id(dev);
1598 alias = amd_iommu_alias_table[devid];
1599 dev_data = get_dev_data(dev);
1600 alias_data = get_dev_data(dev_data->alias);
1604 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1605 dom = dev_data->domain;
1607 alias_data->domain != NULL) {
1608 __attach_device(dev, alias_data->domain);
1609 dom = alias_data->domain;
1612 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1617 static int device_change_notifier(struct notifier_block *nb,
1618 unsigned long action, void *data)
1620 struct device *dev = data;
1622 struct protection_domain *domain;
1623 struct dma_ops_domain *dma_domain;
1624 struct amd_iommu *iommu;
1625 unsigned long flags;
1627 if (!check_device(dev))
1630 devid = get_device_id(dev);
1631 iommu = amd_iommu_rlookup_table[devid];
1634 case BUS_NOTIFY_UNBOUND_DRIVER:
1636 domain = domain_for_device(dev);
1640 if (iommu_pass_through)
1644 case BUS_NOTIFY_ADD_DEVICE:
1646 iommu_init_device(dev);
1648 domain = domain_for_device(dev);
1650 /* allocate a protection domain if a device is added */
1651 dma_domain = find_protection_domain(devid);
1654 dma_domain = dma_ops_domain_alloc();
1657 dma_domain->target_dev = devid;
1659 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1660 list_add_tail(&dma_domain->list, &iommu_pd_list);
1661 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1664 case BUS_NOTIFY_DEL_DEVICE:
1666 iommu_uninit_device(dev);
1672 device_flush_dte(dev);
1673 iommu_completion_wait(iommu);
1679 static struct notifier_block device_nb = {
1680 .notifier_call = device_change_notifier,
1683 void amd_iommu_init_notifier(void)
1685 bus_register_notifier(&pci_bus_type, &device_nb);
1688 /*****************************************************************************
1690 * The next functions belong to the dma_ops mapping/unmapping code.
1692 *****************************************************************************/
1695 * In the dma_ops path we only have the struct device. This function
1696 * finds the corresponding IOMMU, the protection domain and the
1697 * requestor id for a given device.
1698 * If the device is not yet associated with a domain this is also done
1701 static struct protection_domain *get_domain(struct device *dev)
1703 struct protection_domain *domain;
1704 struct dma_ops_domain *dma_dom;
1705 u16 devid = get_device_id(dev);
1707 if (!check_device(dev))
1708 return ERR_PTR(-EINVAL);
1710 domain = domain_for_device(dev);
1711 if (domain != NULL && !dma_ops_domain(domain))
1712 return ERR_PTR(-EBUSY);
1717 /* Device not bount yet - bind it */
1718 dma_dom = find_protection_domain(devid);
1720 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1721 attach_device(dev, &dma_dom->domain);
1722 DUMP_printk("Using protection domain %d for device %s\n",
1723 dma_dom->domain.id, dev_name(dev));
1725 return &dma_dom->domain;
1728 static void update_device_table(struct protection_domain *domain)
1730 struct iommu_dev_data *dev_data;
1732 list_for_each_entry(dev_data, &domain->dev_list, list) {
1733 u16 devid = get_device_id(dev_data->dev);
1734 set_dte_entry(devid, domain);
1738 static void update_domain(struct protection_domain *domain)
1740 if (!domain->updated)
1743 update_device_table(domain);
1745 domain_flush_devices(domain);
1746 domain_flush_tlb_pde(domain);
1748 domain->updated = false;
1752 * This function fetches the PTE for a given address in the aperture
1754 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1755 unsigned long address)
1757 struct aperture_range *aperture;
1758 u64 *pte, *pte_page;
1760 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1764 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1766 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1768 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1770 pte += PM_LEVEL_INDEX(0, address);
1772 update_domain(&dom->domain);
1778 * This is the generic map function. It maps one 4kb page at paddr to
1779 * the given address in the DMA address space for the domain.
1781 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1782 unsigned long address,
1788 WARN_ON(address > dom->aperture_size);
1792 pte = dma_ops_get_pte(dom, address);
1794 return DMA_ERROR_CODE;
1796 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1798 if (direction == DMA_TO_DEVICE)
1799 __pte |= IOMMU_PTE_IR;
1800 else if (direction == DMA_FROM_DEVICE)
1801 __pte |= IOMMU_PTE_IW;
1802 else if (direction == DMA_BIDIRECTIONAL)
1803 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1809 return (dma_addr_t)address;
1813 * The generic unmapping function for on page in the DMA address space.
1815 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1816 unsigned long address)
1818 struct aperture_range *aperture;
1821 if (address >= dom->aperture_size)
1824 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1828 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1832 pte += PM_LEVEL_INDEX(0, address);
1840 * This function contains common code for mapping of a physically
1841 * contiguous memory region into DMA address space. It is used by all
1842 * mapping functions provided with this IOMMU driver.
1843 * Must be called with the domain lock held.
1845 static dma_addr_t __map_single(struct device *dev,
1846 struct dma_ops_domain *dma_dom,
1853 dma_addr_t offset = paddr & ~PAGE_MASK;
1854 dma_addr_t address, start, ret;
1856 unsigned long align_mask = 0;
1859 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1862 INC_STATS_COUNTER(total_map_requests);
1865 INC_STATS_COUNTER(cross_page);
1868 align_mask = (1UL << get_order(size)) - 1;
1871 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1873 if (unlikely(address == DMA_ERROR_CODE)) {
1875 * setting next_address here will let the address
1876 * allocator only scan the new allocated range in the
1877 * first run. This is a small optimization.
1879 dma_dom->next_address = dma_dom->aperture_size;
1881 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1885 * aperture was successfully enlarged by 128 MB, try
1892 for (i = 0; i < pages; ++i) {
1893 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1894 if (ret == DMA_ERROR_CODE)
1902 ADD_STATS_COUNTER(alloced_io_mem, size);
1904 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1905 domain_flush_tlb(&dma_dom->domain);
1906 dma_dom->need_flush = false;
1907 } else if (unlikely(amd_iommu_np_cache))
1908 domain_flush_pages(&dma_dom->domain, address, size);
1915 for (--i; i >= 0; --i) {
1917 dma_ops_domain_unmap(dma_dom, start);
1920 dma_ops_free_addresses(dma_dom, address, pages);
1922 return DMA_ERROR_CODE;
1926 * Does the reverse of the __map_single function. Must be called with
1927 * the domain lock held too
1929 static void __unmap_single(struct dma_ops_domain *dma_dom,
1930 dma_addr_t dma_addr,
1934 dma_addr_t flush_addr;
1935 dma_addr_t i, start;
1938 if ((dma_addr == DMA_ERROR_CODE) ||
1939 (dma_addr + size > dma_dom->aperture_size))
1942 flush_addr = dma_addr;
1943 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1944 dma_addr &= PAGE_MASK;
1947 for (i = 0; i < pages; ++i) {
1948 dma_ops_domain_unmap(dma_dom, start);
1952 SUB_STATS_COUNTER(alloced_io_mem, size);
1954 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1956 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1957 domain_flush_pages(&dma_dom->domain, flush_addr, size);
1958 dma_dom->need_flush = false;
1963 * The exported map_single function for dma_ops.
1965 static dma_addr_t map_page(struct device *dev, struct page *page,
1966 unsigned long offset, size_t size,
1967 enum dma_data_direction dir,
1968 struct dma_attrs *attrs)
1970 unsigned long flags;
1971 struct protection_domain *domain;
1974 phys_addr_t paddr = page_to_phys(page) + offset;
1976 INC_STATS_COUNTER(cnt_map_single);
1978 domain = get_domain(dev);
1979 if (PTR_ERR(domain) == -EINVAL)
1980 return (dma_addr_t)paddr;
1981 else if (IS_ERR(domain))
1982 return DMA_ERROR_CODE;
1984 dma_mask = *dev->dma_mask;
1986 spin_lock_irqsave(&domain->lock, flags);
1988 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1990 if (addr == DMA_ERROR_CODE)
1993 domain_flush_complete(domain);
1996 spin_unlock_irqrestore(&domain->lock, flags);
2002 * The exported unmap_single function for dma_ops.
2004 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2005 enum dma_data_direction dir, struct dma_attrs *attrs)
2007 unsigned long flags;
2008 struct protection_domain *domain;
2010 INC_STATS_COUNTER(cnt_unmap_single);
2012 domain = get_domain(dev);
2016 spin_lock_irqsave(&domain->lock, flags);
2018 __unmap_single(domain->priv, dma_addr, size, dir);
2020 domain_flush_complete(domain);
2022 spin_unlock_irqrestore(&domain->lock, flags);
2026 * This is a special map_sg function which is used if we should map a
2027 * device which is not handled by an AMD IOMMU in the system.
2029 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2030 int nelems, int dir)
2032 struct scatterlist *s;
2035 for_each_sg(sglist, s, nelems, i) {
2036 s->dma_address = (dma_addr_t)sg_phys(s);
2037 s->dma_length = s->length;
2044 * The exported map_sg function for dma_ops (handles scatter-gather
2047 static int map_sg(struct device *dev, struct scatterlist *sglist,
2048 int nelems, enum dma_data_direction dir,
2049 struct dma_attrs *attrs)
2051 unsigned long flags;
2052 struct protection_domain *domain;
2054 struct scatterlist *s;
2056 int mapped_elems = 0;
2059 INC_STATS_COUNTER(cnt_map_sg);
2061 domain = get_domain(dev);
2062 if (PTR_ERR(domain) == -EINVAL)
2063 return map_sg_no_iommu(dev, sglist, nelems, dir);
2064 else if (IS_ERR(domain))
2067 dma_mask = *dev->dma_mask;
2069 spin_lock_irqsave(&domain->lock, flags);
2071 for_each_sg(sglist, s, nelems, i) {
2074 s->dma_address = __map_single(dev, domain->priv,
2075 paddr, s->length, dir, false,
2078 if (s->dma_address) {
2079 s->dma_length = s->length;
2085 domain_flush_complete(domain);
2088 spin_unlock_irqrestore(&domain->lock, flags);
2090 return mapped_elems;
2092 for_each_sg(sglist, s, mapped_elems, i) {
2094 __unmap_single(domain->priv, s->dma_address,
2095 s->dma_length, dir);
2096 s->dma_address = s->dma_length = 0;
2105 * The exported map_sg function for dma_ops (handles scatter-gather
2108 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2109 int nelems, enum dma_data_direction dir,
2110 struct dma_attrs *attrs)
2112 unsigned long flags;
2113 struct protection_domain *domain;
2114 struct scatterlist *s;
2117 INC_STATS_COUNTER(cnt_unmap_sg);
2119 domain = get_domain(dev);
2123 spin_lock_irqsave(&domain->lock, flags);
2125 for_each_sg(sglist, s, nelems, i) {
2126 __unmap_single(domain->priv, s->dma_address,
2127 s->dma_length, dir);
2128 s->dma_address = s->dma_length = 0;
2131 domain_flush_complete(domain);
2133 spin_unlock_irqrestore(&domain->lock, flags);
2137 * The exported alloc_coherent function for dma_ops.
2139 static void *alloc_coherent(struct device *dev, size_t size,
2140 dma_addr_t *dma_addr, gfp_t flag)
2142 unsigned long flags;
2144 struct protection_domain *domain;
2146 u64 dma_mask = dev->coherent_dma_mask;
2148 INC_STATS_COUNTER(cnt_alloc_coherent);
2150 domain = get_domain(dev);
2151 if (PTR_ERR(domain) == -EINVAL) {
2152 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2153 *dma_addr = __pa(virt_addr);
2155 } else if (IS_ERR(domain))
2158 dma_mask = dev->coherent_dma_mask;
2159 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2162 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2166 paddr = virt_to_phys(virt_addr);
2169 dma_mask = *dev->dma_mask;
2171 spin_lock_irqsave(&domain->lock, flags);
2173 *dma_addr = __map_single(dev, domain->priv, paddr,
2174 size, DMA_BIDIRECTIONAL, true, dma_mask);
2176 if (*dma_addr == DMA_ERROR_CODE) {
2177 spin_unlock_irqrestore(&domain->lock, flags);
2181 domain_flush_complete(domain);
2183 spin_unlock_irqrestore(&domain->lock, flags);
2189 free_pages((unsigned long)virt_addr, get_order(size));
2195 * The exported free_coherent function for dma_ops.
2197 static void free_coherent(struct device *dev, size_t size,
2198 void *virt_addr, dma_addr_t dma_addr)
2200 unsigned long flags;
2201 struct protection_domain *domain;
2203 INC_STATS_COUNTER(cnt_free_coherent);
2205 domain = get_domain(dev);
2209 spin_lock_irqsave(&domain->lock, flags);
2211 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2213 domain_flush_complete(domain);
2215 spin_unlock_irqrestore(&domain->lock, flags);
2218 free_pages((unsigned long)virt_addr, get_order(size));
2222 * This function is called by the DMA layer to find out if we can handle a
2223 * particular device. It is part of the dma_ops.
2225 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2227 return check_device(dev);
2231 * The function for pre-allocating protection domains.
2233 * If the driver core informs the DMA layer if a driver grabs a device
2234 * we don't need to preallocate the protection domains anymore.
2235 * For now we have to.
2237 static void prealloc_protection_domains(void)
2239 struct pci_dev *dev = NULL;
2240 struct dma_ops_domain *dma_dom;
2243 for_each_pci_dev(dev) {
2245 /* Do we handle this device? */
2246 if (!check_device(&dev->dev))
2249 /* Is there already any domain for it? */
2250 if (domain_for_device(&dev->dev))
2253 devid = get_device_id(&dev->dev);
2255 dma_dom = dma_ops_domain_alloc();
2258 init_unity_mappings_for_device(dma_dom, devid);
2259 dma_dom->target_dev = devid;
2261 attach_device(&dev->dev, &dma_dom->domain);
2263 list_add_tail(&dma_dom->list, &iommu_pd_list);
2267 static struct dma_map_ops amd_iommu_dma_ops = {
2268 .alloc_coherent = alloc_coherent,
2269 .free_coherent = free_coherent,
2270 .map_page = map_page,
2271 .unmap_page = unmap_page,
2273 .unmap_sg = unmap_sg,
2274 .dma_supported = amd_iommu_dma_supported,
2278 * The function which clues the AMD IOMMU driver into dma_ops.
2281 void __init amd_iommu_init_api(void)
2283 register_iommu(&amd_iommu_ops);
2286 int __init amd_iommu_init_dma_ops(void)
2288 struct amd_iommu *iommu;
2292 * first allocate a default protection domain for every IOMMU we
2293 * found in the system. Devices not assigned to any other
2294 * protection domain will be assigned to the default one.
2296 for_each_iommu(iommu) {
2297 iommu->default_dom = dma_ops_domain_alloc();
2298 if (iommu->default_dom == NULL)
2300 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2301 ret = iommu_init_unity_mappings(iommu);
2307 * Pre-allocate the protection domains for each device.
2309 prealloc_protection_domains();
2314 /* Make the driver finally visible to the drivers */
2315 dma_ops = &amd_iommu_dma_ops;
2317 amd_iommu_stats_init();
2323 for_each_iommu(iommu) {
2324 if (iommu->default_dom)
2325 dma_ops_domain_free(iommu->default_dom);
2331 /*****************************************************************************
2333 * The following functions belong to the exported interface of AMD IOMMU
2335 * This interface allows access to lower level functions of the IOMMU
2336 * like protection domain handling and assignement of devices to domains
2337 * which is not possible with the dma_ops interface.
2339 *****************************************************************************/
2341 static void cleanup_domain(struct protection_domain *domain)
2343 struct iommu_dev_data *dev_data, *next;
2344 unsigned long flags;
2346 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2348 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2349 struct device *dev = dev_data->dev;
2351 __detach_device(dev);
2352 atomic_set(&dev_data->bind, 0);
2355 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2358 static void protection_domain_free(struct protection_domain *domain)
2363 del_domain_from_list(domain);
2366 domain_id_free(domain->id);
2371 static struct protection_domain *protection_domain_alloc(void)
2373 struct protection_domain *domain;
2375 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2379 spin_lock_init(&domain->lock);
2380 mutex_init(&domain->api_lock);
2381 domain->id = domain_id_alloc();
2384 INIT_LIST_HEAD(&domain->dev_list);
2386 add_domain_to_list(domain);
2396 static int amd_iommu_domain_init(struct iommu_domain *dom)
2398 struct protection_domain *domain;
2400 domain = protection_domain_alloc();
2404 domain->mode = PAGE_MODE_3_LEVEL;
2405 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2406 if (!domain->pt_root)
2414 protection_domain_free(domain);
2419 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2421 struct protection_domain *domain = dom->priv;
2426 if (domain->dev_cnt > 0)
2427 cleanup_domain(domain);
2429 BUG_ON(domain->dev_cnt != 0);
2431 free_pagetable(domain);
2433 protection_domain_free(domain);
2438 static void amd_iommu_detach_device(struct iommu_domain *dom,
2441 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2442 struct amd_iommu *iommu;
2445 if (!check_device(dev))
2448 devid = get_device_id(dev);
2450 if (dev_data->domain != NULL)
2453 iommu = amd_iommu_rlookup_table[devid];
2457 device_flush_dte(dev);
2458 iommu_completion_wait(iommu);
2461 static int amd_iommu_attach_device(struct iommu_domain *dom,
2464 struct protection_domain *domain = dom->priv;
2465 struct iommu_dev_data *dev_data;
2466 struct amd_iommu *iommu;
2470 if (!check_device(dev))
2473 dev_data = dev->archdata.iommu;
2475 devid = get_device_id(dev);
2477 iommu = amd_iommu_rlookup_table[devid];
2481 if (dev_data->domain)
2484 ret = attach_device(dev, domain);
2486 iommu_completion_wait(iommu);
2491 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2492 phys_addr_t paddr, int gfp_order, int iommu_prot)
2494 unsigned long page_size = 0x1000UL << gfp_order;
2495 struct protection_domain *domain = dom->priv;
2499 if (iommu_prot & IOMMU_READ)
2500 prot |= IOMMU_PROT_IR;
2501 if (iommu_prot & IOMMU_WRITE)
2502 prot |= IOMMU_PROT_IW;
2504 mutex_lock(&domain->api_lock);
2505 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2506 mutex_unlock(&domain->api_lock);
2511 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2514 struct protection_domain *domain = dom->priv;
2515 unsigned long page_size, unmap_size;
2517 page_size = 0x1000UL << gfp_order;
2519 mutex_lock(&domain->api_lock);
2520 unmap_size = iommu_unmap_page(domain, iova, page_size);
2521 mutex_unlock(&domain->api_lock);
2523 domain_flush_tlb_pde(domain);
2525 return get_order(unmap_size);
2528 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2531 struct protection_domain *domain = dom->priv;
2532 unsigned long offset_mask;
2536 pte = fetch_pte(domain, iova);
2538 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2541 if (PM_PTE_LEVEL(*pte) == 0)
2542 offset_mask = PAGE_SIZE - 1;
2544 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2546 __pte = *pte & PM_ADDR_MASK;
2547 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2552 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2556 case IOMMU_CAP_CACHE_COHERENCY:
2563 static struct iommu_ops amd_iommu_ops = {
2564 .domain_init = amd_iommu_domain_init,
2565 .domain_destroy = amd_iommu_domain_destroy,
2566 .attach_dev = amd_iommu_attach_device,
2567 .detach_dev = amd_iommu_detach_device,
2568 .map = amd_iommu_map,
2569 .unmap = amd_iommu_unmap,
2570 .iova_to_phys = amd_iommu_iova_to_phys,
2571 .domain_has_cap = amd_iommu_domain_has_cap,
2574 /*****************************************************************************
2576 * The next functions do a basic initialization of IOMMU for pass through
2579 * In passthrough mode the IOMMU is initialized and enabled but not used for
2580 * DMA-API translation.
2582 *****************************************************************************/
2584 int __init amd_iommu_init_passthrough(void)
2586 struct amd_iommu *iommu;
2587 struct pci_dev *dev = NULL;
2590 /* allocate passthrough domain */
2591 pt_domain = protection_domain_alloc();
2595 pt_domain->mode |= PAGE_MODE_NONE;
2597 for_each_pci_dev(dev) {
2598 if (!check_device(&dev->dev))
2601 devid = get_device_id(&dev->dev);
2603 iommu = amd_iommu_rlookup_table[devid];
2607 attach_device(&dev->dev, pt_domain);
2610 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");