2 * Shared support code for AMD K8 northbridges and derivates.
3 * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
5 #include <linux/types.h>
6 #include <linux/slab.h>
7 #include <linux/init.h>
8 #include <linux/errno.h>
9 #include <linux/module.h>
10 #include <linux/spinlock.h>
11 #include <asm/amd_nb.h>
13 static u32 *flush_words;
15 struct pci_device_id k8_nb_ids[] = {
16 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
17 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
18 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
21 EXPORT_SYMBOL(k8_nb_ids);
23 struct k8_northbridge_info k8_northbridges;
24 EXPORT_SYMBOL(k8_northbridges);
26 static struct pci_dev *next_k8_northbridge(struct pci_dev *dev)
29 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
32 } while (!pci_match_id(&k8_nb_ids[0], dev));
36 int cache_k8_northbridges(void)
41 if (k8_northbridges.num)
45 while ((dev = next_k8_northbridge(dev)) != NULL)
46 k8_northbridges.num++;
48 /* some CPU families (e.g. family 0x11) do not support GART */
49 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
50 boot_cpu_data.x86 == 0x15)
51 k8_northbridges.gart_supported = 1;
53 k8_northbridges.nb_misc = kmalloc((k8_northbridges.num + 1) *
54 sizeof(void *), GFP_KERNEL);
55 if (!k8_northbridges.nb_misc)
58 if (!k8_northbridges.num) {
59 k8_northbridges.nb_misc[0] = NULL;
63 if (k8_northbridges.gart_supported) {
64 flush_words = kmalloc(k8_northbridges.num * sizeof(u32),
67 kfree(k8_northbridges.nb_misc);
74 while ((dev = next_k8_northbridge(dev)) != NULL) {
75 k8_northbridges.nb_misc[i] = dev;
76 if (k8_northbridges.gart_supported)
77 pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
79 k8_northbridges.nb_misc[i] = NULL;
82 EXPORT_SYMBOL_GPL(cache_k8_northbridges);
84 /* Ignores subdevice/subvendor but as far as I can figure out
85 they're useless anyways */
86 int __init early_is_k8_nb(u32 device)
88 struct pci_device_id *id;
89 u32 vendor = device & 0xffff;
91 for (id = k8_nb_ids; id->vendor; id++)
92 if (vendor == id->vendor && device == id->device)
97 void k8_flush_garts(void)
101 static DEFINE_SPINLOCK(gart_lock);
103 if (!k8_northbridges.gart_supported)
106 /* Avoid races between AGP and IOMMU. In theory it's not needed
107 but I'm not sure if the hardware won't lose flush requests
108 when another is pending. This whole thing is so expensive anyways
109 that it doesn't matter to serialize more. -AK */
110 spin_lock_irqsave(&gart_lock, flags);
112 for (i = 0; i < k8_northbridges.num; i++) {
113 pci_write_config_dword(k8_northbridges.nb_misc[i], 0x9c,
117 for (i = 0; i < k8_northbridges.num; i++) {
119 /* Make sure the hardware actually executed the flush*/
121 pci_read_config_dword(k8_northbridges.nb_misc[i],
128 spin_unlock_irqrestore(&gart_lock, flags);
130 printk("nothing to flush?\n");
132 EXPORT_SYMBOL_GPL(k8_flush_garts);
134 static __init int init_k8_nbs(void)
138 err = cache_k8_northbridges();
141 printk(KERN_NOTICE "K8 NB: Cannot enumerate AMD northbridges.\n");
146 /* This has to go after the PCI subsystem */
147 fs_initcall(init_k8_nbs);