2 * Firmware replacement code.
4 * Work around broken BIOSes that don't set an aperture, only set the
5 * aperture in the AGP bridge, or set too small aperture.
7 * If all fails map the aperture over some low memory. This is cheaper than
8 * doing bounce buffering. The memory is lost. This is done at early boot
9 * because only the bootmem allocator can allocate 32+MB.
11 * Copyright 2002 Andi Kleen, SuSE Labs.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/init.h>
16 #include <linux/memblock.h>
17 #include <linux/mmzone.h>
18 #include <linux/pci_ids.h>
19 #include <linux/pci.h>
20 #include <linux/bitops.h>
21 #include <linux/ioport.h>
22 #include <linux/suspend.h>
23 #include <linux/kmemleak.h>
26 #include <asm/iommu.h>
28 #include <asm/pci-direct.h>
30 #include <asm/amd_nb.h>
31 #include <asm/x86_init.h>
33 int gart_iommu_aperture;
34 int gart_iommu_aperture_disabled __initdata;
35 int gart_iommu_aperture_allowed __initdata;
37 int fallback_aper_order __initdata = 1; /* 64MB */
38 int fallback_aper_force __initdata;
40 int fix_aperture __initdata = 1;
42 struct bus_dev_range {
48 static struct bus_dev_range bus_dev_ranges[] __initdata = {
54 static struct resource gart_resource = {
56 .flags = IORESOURCE_MEM,
59 static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
61 gart_resource.start = aper_base;
62 gart_resource.end = aper_base + aper_size - 1;
63 insert_resource(&iomem_resource, &gart_resource);
66 /* This code runs before the PCI subsystem is initialized, so just
67 access the northbridge directly. */
69 static u32 __init allocate_aperture(void)
74 /* aper_size should <= 1G */
75 if (fallback_aper_order > 5)
76 fallback_aper_order = 5;
77 aper_size = (32 * 1024 * 1024) << fallback_aper_order;
80 * Aperture has to be naturally aligned. This means a 2GB aperture
81 * won't have much chance of finding a place in the lower 4GB of
82 * memory. Unfortunately we cannot move it up because that would
83 * make the IOMMU useless.
86 * using 512M as goal, in case kexec will load kernel_big
87 * that will do the on position decompress, and could overlap with
88 * that positon with gart that is used.
91 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
92 * ==> kernel_small(gart area become e820_reserved)
93 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
94 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
95 * so don't use 512M below as gart iommu, leave the space for kernel
98 addr = memblock_find_in_range(0, 1ULL<<32, aper_size, 512ULL<<20);
99 if (addr == MEMBLOCK_ERROR || addr + aper_size > 0xffffffff) {
101 "Cannot allocate aperture memory hole (%lx,%uK)\n",
102 addr, aper_size>>10);
105 memblock_x86_reserve_range(addr, addr + aper_size, "aperture64");
107 * Kmemleak should not scan this block as it may not be mapped via the
108 * kernel direct mapping.
110 kmemleak_ignore(phys_to_virt(addr));
111 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
112 aper_size >> 10, addr);
113 insert_aperture_resource((u32)addr, aper_size);
114 register_nosave_region(addr >> PAGE_SHIFT,
115 (addr+aper_size) >> PAGE_SHIFT);
121 /* Find a PCI capability */
122 static u32 __init find_cap(int bus, int slot, int func, int cap)
127 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
128 PCI_STATUS_CAP_LIST))
131 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
132 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
136 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
141 pos = read_pci_config_byte(bus, slot, func,
142 pos+PCI_CAP_LIST_NEXT);
147 /* Read a standard AGPv3 bridge header */
148 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
153 u32 aper_low, aper_hi;
157 printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
158 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
159 if (apsizereg == 0xffffffff) {
160 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
164 /* old_order could be the value from NB gart setting */
167 apsize = apsizereg & 0xfff;
168 /* Some BIOS use weird encodings not in the AGPv3 table. */
171 nbits = hweight16(apsize);
173 if ((int)*order < 0) /* < 32MB */
176 aper_low = read_pci_config(bus, slot, func, 0x10);
177 aper_hi = read_pci_config(bus, slot, func, 0x14);
178 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
181 * On some sick chips, APSIZE is 0. It means it wants 4G
182 * so let double check that order, and lets trust AMD NB settings:
184 printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n",
185 aper, 32 << old_order);
186 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
187 printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
188 32 << *order, apsizereg);
192 printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
193 aper, 32 << *order, apsizereg);
195 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
201 * Look for an AGP bridge. Windows only expects the aperture in the
202 * AGP bridge and some BIOS forget to initialize the Northbridge too.
203 * Work around this here.
205 * Do an PCI bus scan by hand because we're running before the PCI
208 * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
209 * generically. It's probably overkill to always scan all slots because
210 * the AGP bridges should be always an own bus on the HT hierarchy,
211 * but do it here for future safety.
213 static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
217 /* Poor man's PCI discovery */
218 for (bus = 0; bus < 256; bus++) {
219 for (slot = 0; slot < 32; slot++) {
220 for (func = 0; func < 8; func++) {
223 class = read_pci_config(bus, slot, func,
225 if (class == 0xffffffff)
228 switch (class >> 16) {
229 case PCI_CLASS_BRIDGE_HOST:
230 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
232 cap = find_cap(bus, slot, func,
237 return read_agp(bus, slot, func, cap,
241 /* No multi-function device? */
242 type = read_pci_config_byte(bus, slot, func,
249 printk(KERN_INFO "No AGP bridge found\n");
254 static int gart_fix_e820 __initdata = 1;
256 static int __init parse_gart_mem(char *p)
261 if (!strncmp(p, "off", 3))
263 else if (!strncmp(p, "on", 2))
268 early_param("gart_fix_e820", parse_gart_mem);
270 void __init early_gart_iommu_check(void)
273 * in case it is enabled before, esp for kexec/kdump,
274 * previous kernel already enable that. memset called
275 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
276 * or second kernel have different position for GART hole. and new
277 * kernel could use hole as RAM that is still used by GART set by
279 * or BIOS forget to put that in reserved.
280 * try to update e820 to make that region as reserved.
282 u32 agp_aper_order = 0;
283 int i, fix, slot, valid_agp = 0;
285 u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
286 u64 aper_base = 0, last_aper_base = 0;
287 int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
289 if (!early_pci_allowed())
292 /* This is mostly duplicate of iommu_hole_init */
293 search_agp_bridge(&agp_aper_order, &valid_agp);
296 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
298 int dev_base, dev_limit;
300 bus = bus_dev_ranges[i].bus;
301 dev_base = bus_dev_ranges[i].dev_base;
302 dev_limit = bus_dev_ranges[i].dev_limit;
304 for (slot = dev_base; slot < dev_limit; slot++) {
305 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
308 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
309 aper_enabled = ctl & GARTEN;
310 aper_order = (ctl >> 1) & 7;
311 aper_size = (32 * 1024 * 1024) << aper_order;
312 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
316 if ((aper_order != last_aper_order) ||
317 (aper_base != last_aper_base) ||
318 (aper_enabled != last_aper_enabled)) {
324 last_aper_order = aper_order;
325 last_aper_base = aper_base;
326 last_aper_enabled = aper_enabled;
331 if (!fix && !aper_enabled)
334 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
337 if (gart_fix_e820 && !fix && aper_enabled) {
338 if (e820_any_mapped(aper_base, aper_base + aper_size,
340 /* reserve it, so we can reuse it in second kernel */
341 printk(KERN_INFO "update e820 for GART\n");
342 e820_add_region(aper_base, aper_size, E820_RESERVED);
350 /* disable them all at first */
351 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
353 int dev_base, dev_limit;
355 bus = bus_dev_ranges[i].bus;
356 dev_base = bus_dev_ranges[i].dev_base;
357 dev_limit = bus_dev_ranges[i].dev_limit;
359 for (slot = dev_base; slot < dev_limit; slot++) {
360 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
363 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
365 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
371 static int __initdata printed_gart_size_msg;
373 int __init gart_iommu_hole_init(void)
375 u32 agp_aper_base = 0, agp_aper_order = 0;
376 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
377 u64 aper_base, last_aper_base = 0;
378 int fix, slot, valid_agp = 0;
381 if (gart_iommu_aperture_disabled || !fix_aperture ||
382 !early_pci_allowed())
385 printk(KERN_INFO "Checking aperture...\n");
387 if (!fallback_aper_force)
388 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
392 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
394 int dev_base, dev_limit;
397 bus = bus_dev_ranges[i].bus;
398 dev_base = bus_dev_ranges[i].dev_base;
399 dev_limit = bus_dev_ranges[i].dev_limit;
401 for (slot = dev_base; slot < dev_limit; slot++) {
402 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
406 gart_iommu_aperture = 1;
407 x86_init.iommu.iommu_init = gart_iommu_init;
409 ctl = read_pci_config(bus, slot, 3,
410 AMD64_GARTAPERTURECTL);
413 * Before we do anything else disable the GART. It may
414 * still be enabled if we boot into a crash-kernel here.
415 * Reconfiguring the GART while it is enabled could have
416 * unknown side-effects.
419 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
421 aper_order = (ctl >> 1) & 7;
422 aper_size = (32 * 1024 * 1024) << aper_order;
423 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
426 printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
427 node, aper_base, aper_size >> 20);
430 if (!aperture_valid(aper_base, aper_size, 64<<20)) {
431 if (valid_agp && agp_aper_base &&
432 agp_aper_base == aper_base &&
433 agp_aper_order == aper_order) {
434 /* the same between two setting from NB and agp */
436 max_pfn > MAX_DMA32_PFN &&
437 !printed_gart_size_msg) {
438 printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
439 printk(KERN_ERR "please increase GART size in your BIOS setup\n");
440 printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
441 printed_gart_size_msg = 1;
449 if ((last_aper_order && aper_order != last_aper_order) ||
450 (last_aper_base && aper_base != last_aper_base)) {
454 last_aper_order = aper_order;
455 last_aper_base = aper_base;
460 if (!fix && !fallback_aper_force) {
461 if (last_aper_base) {
462 unsigned long n = (32 * 1024 * 1024) << last_aper_order;
464 insert_aperture_resource((u32)last_aper_base, n);
470 if (!fallback_aper_force) {
471 aper_alloc = agp_aper_base;
472 aper_order = agp_aper_order;
476 /* Got the aperture from the AGP bridge */
477 } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
480 fallback_aper_force) {
482 "Your BIOS doesn't leave a aperture memory hole\n");
484 "Please enable the IOMMU option in the BIOS setup\n");
486 "This costs you %d MB of RAM\n",
487 32 << fallback_aper_order);
489 aper_order = fallback_aper_order;
490 aper_alloc = allocate_aperture();
493 * Could disable AGP and IOMMU here, but it's
494 * probably not worth it. But the later users
495 * cannot deal with bad apertures and turning
496 * on the aperture over memory causes very
497 * strange problems, so it's better to panic
500 panic("Not enough memory for aperture");
506 /* Fix up the north bridges */
507 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
508 int bus, dev_base, dev_limit;
511 * Don't enable translation yet but enable GART IO and CPU
512 * accesses and set DISTLBWALKPRB since GART table memory is UC.
514 u32 ctl = DISTLBWALKPRB | aper_order << 1;
516 bus = bus_dev_ranges[i].bus;
517 dev_base = bus_dev_ranges[i].dev_base;
518 dev_limit = bus_dev_ranges[i].dev_limit;
519 for (slot = dev_base; slot < dev_limit; slot++) {
520 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
523 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
524 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
528 set_up_gart_resume(aper_order, aper_alloc);