2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_event.h>
39 #include <asm/x86_init.h>
40 #include <asm/pgalloc.h>
41 #include <linux/atomic.h>
42 #include <asm/mpspec.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
46 #include <asm/io_apic.h>
55 #include <asm/hypervisor.h>
57 unsigned int num_processors;
59 unsigned disabled_cpus __cpuinitdata;
61 /* Processor that is doing the boot up */
62 unsigned int boot_cpu_physical_apicid = -1U;
65 * The highest APIC ID seen during enumeration.
67 unsigned int max_physical_apicid;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
78 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
85 * On x86_32, the mapping between cpu and logical apicid may vary
86 * depending on apic in use. The following early percpu variable is
87 * used for the mapping. This is where the behaviors of x86_64 and 32
88 * actually diverge. Let's keep it ugly for now.
90 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);
93 * Knob to control our willingness to enable the local APIC.
97 static int force_enable_local_apic __initdata;
99 * APIC command line parameters
101 static int __init parse_lapic(char *arg)
103 force_enable_local_apic = 1;
106 early_param("lapic", parse_lapic);
107 /* Local APIC was disabled by the BIOS and enabled by the kernel */
108 static int enabled_via_apicbase;
111 * Handle interrupt mode configuration register (IMCR).
112 * This register controls whether the interrupt signals
113 * that reach the BSP come from the master PIC or from the
114 * local APIC. Before entering Symmetric I/O Mode, either
115 * the BIOS or the operating system must switch out of
116 * PIC Mode by changing the IMCR.
118 static inline void imcr_pic_to_apic(void)
120 /* select IMCR register */
122 /* NMI and 8259 INTR go through APIC */
126 static inline void imcr_apic_to_pic(void)
128 /* select IMCR register */
130 /* NMI and 8259 INTR go directly to BSP */
136 static int apic_calibrate_pmtmr __initdata;
137 static __init int setup_apicpmtimer(char *s)
139 apic_calibrate_pmtmr = 1;
143 __setup("apicpmtimer", setup_apicpmtimer);
147 #ifdef CONFIG_X86_X2APIC
148 /* x2apic enabled before OS handover */
149 static int x2apic_preenabled;
150 static __init int setup_nox2apic(char *str)
152 if (x2apic_enabled()) {
153 pr_warning("Bios already enabled x2apic, "
154 "can't enforce nox2apic");
158 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
161 early_param("nox2apic", setup_nox2apic);
164 unsigned long mp_lapic_addr;
166 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
167 static int disable_apic_timer __initdata;
168 /* Local APIC timer works in C2 */
169 int local_apic_timer_c2_ok;
170 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
172 int first_system_vector = 0xfe;
175 * Debug level, exported for io_apic.c
177 unsigned int apic_verbosity;
181 /* Have we found an MP table */
182 int smp_found_config;
184 static struct resource lapic_resource = {
185 .name = "Local APIC",
186 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
189 unsigned int lapic_timer_frequency = 0;
191 static void apic_pm_activate(void);
193 static unsigned long apic_phys;
196 * Get the LAPIC version
198 static inline int lapic_get_version(void)
200 return GET_APIC_VERSION(apic_read(APIC_LVR));
204 * Check, if the APIC is integrated or a separate chip
206 static inline int lapic_is_integrated(void)
211 return APIC_INTEGRATED(lapic_get_version());
216 * Check, whether this is a modern or a first generation APIC
218 static int modern_apic(void)
220 /* AMD systems use old APIC versions, so check the CPU */
221 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
222 boot_cpu_data.x86 >= 0xf)
224 return lapic_get_version() >= 0x14;
228 * right after this call apic become NOOP driven
229 * so apic->write/read doesn't do anything
231 static void __init apic_disable(void)
233 pr_info("APIC: switched to apic NOOP\n");
237 void native_apic_wait_icr_idle(void)
239 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
243 u32 native_safe_apic_wait_icr_idle(void)
250 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
253 inc_irq_stat(icr_read_retry_count);
255 } while (timeout++ < 1000);
260 void native_apic_icr_write(u32 low, u32 id)
262 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
263 apic_write(APIC_ICR, low);
266 u64 native_apic_icr_read(void)
270 icr2 = apic_read(APIC_ICR2);
271 icr1 = apic_read(APIC_ICR);
273 return icr1 | ((u64)icr2 << 32);
278 * get_physical_broadcast - Get number of physical broadcast IDs
280 int get_physical_broadcast(void)
282 return modern_apic() ? 0xff : 0xf;
287 * lapic_get_maxlvt - get the maximum number of local vector table entries
289 int lapic_get_maxlvt(void)
293 v = apic_read(APIC_LVR);
295 * - we always have APIC integrated on 64bit mode
296 * - 82489DXs do not report # of LVT entries
298 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
306 #define APIC_DIVISOR 16
309 * This function sets up the local APIC timer, with a timeout of
310 * 'clocks' APIC bus clock. During calibration we actually call
311 * this function twice on the boot CPU, once with a bogus timeout
312 * value, second time for real. The other (noncalibrating) CPUs
313 * call this function only once, with the real, calibrated value.
315 * We do reads before writes even if unnecessary, to get around the
316 * P5 APIC double write bug.
318 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
320 unsigned int lvtt_value, tmp_value;
322 lvtt_value = LOCAL_TIMER_VECTOR;
324 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
325 if (!lapic_is_integrated())
326 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
329 lvtt_value |= APIC_LVT_MASKED;
331 apic_write(APIC_LVTT, lvtt_value);
336 tmp_value = apic_read(APIC_TDCR);
337 apic_write(APIC_TDCR,
338 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
342 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
346 * Setup extended LVT, AMD specific
348 * Software should use the LVT offsets the BIOS provides. The offsets
349 * are determined by the subsystems using it like those for MCE
350 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
351 * are supported. Beginning with family 10h at least 4 offsets are
354 * Since the offsets must be consistent for all cores, we keep track
355 * of the LVT offsets in software and reserve the offset for the same
356 * vector also to be used on other cores. An offset is freed by
357 * setting the entry to APIC_EILVT_MASKED.
359 * If the BIOS is right, there should be no conflicts. Otherwise a
360 * "[Firmware Bug]: ..." error message is generated. However, if
361 * software does not properly determines the offsets, it is not
362 * necessarily a BIOS bug.
365 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
367 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
369 return (old & APIC_EILVT_MASKED)
370 || (new == APIC_EILVT_MASKED)
371 || ((new & ~APIC_EILVT_MASKED) == old);
374 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
376 unsigned int rsvd; /* 0: uninitialized */
378 if (offset >= APIC_EILVT_NR_MAX)
381 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED;
384 !eilvt_entry_is_changeable(rsvd, new))
385 /* may not change if vectors are different */
387 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
388 } while (rsvd != new);
394 * If mask=1, the LVT entry does not generate interrupts while mask=0
395 * enables the vector. See also the BKDGs. Must be called with
396 * preemption disabled.
399 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
401 unsigned long reg = APIC_EILVTn(offset);
402 unsigned int new, old, reserved;
404 new = (mask << 16) | (msg_type << 8) | vector;
405 old = apic_read(reg);
406 reserved = reserve_eilvt_offset(offset, new);
408 if (reserved != new) {
409 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
410 "vector 0x%x, but the register is already in use for "
411 "vector 0x%x on another cpu\n",
412 smp_processor_id(), reg, offset, new, reserved);
416 if (!eilvt_entry_is_changeable(old, new)) {
417 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
418 "vector 0x%x, but the register is already in use for "
419 "vector 0x%x on this cpu\n",
420 smp_processor_id(), reg, offset, new, old);
424 apic_write(reg, new);
428 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
431 * Program the next event, relative to now
433 static int lapic_next_event(unsigned long delta,
434 struct clock_event_device *evt)
436 apic_write(APIC_TMICT, delta);
441 * Setup the lapic timer in periodic or oneshot mode
443 static void lapic_timer_setup(enum clock_event_mode mode,
444 struct clock_event_device *evt)
449 /* Lapic used as dummy for broadcast ? */
450 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
453 local_irq_save(flags);
456 case CLOCK_EVT_MODE_PERIODIC:
457 case CLOCK_EVT_MODE_ONESHOT:
458 __setup_APIC_LVTT(lapic_timer_frequency,
459 mode != CLOCK_EVT_MODE_PERIODIC, 1);
461 case CLOCK_EVT_MODE_UNUSED:
462 case CLOCK_EVT_MODE_SHUTDOWN:
463 v = apic_read(APIC_LVTT);
464 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
465 apic_write(APIC_LVTT, v);
466 apic_write(APIC_TMICT, 0);
468 case CLOCK_EVT_MODE_RESUME:
469 /* Nothing to do here */
473 local_irq_restore(flags);
477 * Local APIC timer broadcast function
479 static void lapic_timer_broadcast(const struct cpumask *mask)
482 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
488 * The local apic timer can be used for any function which is CPU local.
490 static struct clock_event_device lapic_clockevent = {
492 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
493 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
495 .set_mode = lapic_timer_setup,
496 .set_next_event = lapic_next_event,
497 .broadcast = lapic_timer_broadcast,
501 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
504 * Setup the local APIC timer for this CPU. Copy the initialized values
505 * of the boot CPU and register the clock event in the framework.
507 static void __cpuinit setup_APIC_timer(void)
509 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
511 if (this_cpu_has(X86_FEATURE_ARAT)) {
512 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
513 /* Make LAPIC timer preferrable over percpu HPET */
514 lapic_clockevent.rating = 150;
517 memcpy(levt, &lapic_clockevent, sizeof(*levt));
518 levt->cpumask = cpumask_of(smp_processor_id());
520 clockevents_register_device(levt);
524 * In this functions we calibrate APIC bus clocks to the external timer.
526 * We want to do the calibration only once since we want to have local timer
527 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
530 * This was previously done by reading the PIT/HPET and waiting for a wrap
531 * around to find out, that a tick has elapsed. I have a box, where the PIT
532 * readout is broken, so it never gets out of the wait loop again. This was
533 * also reported by others.
535 * Monitoring the jiffies value is inaccurate and the clockevents
536 * infrastructure allows us to do a simple substitution of the interrupt
539 * The calibration routine also uses the pm_timer when possible, as the PIT
540 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
541 * back to normal later in the boot process).
544 #define LAPIC_CAL_LOOPS (HZ/10)
546 static __initdata int lapic_cal_loops = -1;
547 static __initdata long lapic_cal_t1, lapic_cal_t2;
548 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
549 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
550 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
553 * Temporary interrupt handler.
555 static void __init lapic_cal_handler(struct clock_event_device *dev)
557 unsigned long long tsc = 0;
558 long tapic = apic_read(APIC_TMCCT);
559 unsigned long pm = acpi_pm_read_early();
564 switch (lapic_cal_loops++) {
566 lapic_cal_t1 = tapic;
567 lapic_cal_tsc1 = tsc;
569 lapic_cal_j1 = jiffies;
572 case LAPIC_CAL_LOOPS:
573 lapic_cal_t2 = tapic;
574 lapic_cal_tsc2 = tsc;
575 if (pm < lapic_cal_pm1)
576 pm += ACPI_PM_OVRRUN;
578 lapic_cal_j2 = jiffies;
584 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
586 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
587 const long pm_thresh = pm_100ms / 100;
591 #ifndef CONFIG_X86_PM_TIMER
595 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
597 /* Check, if the PM timer is available */
601 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
603 if (deltapm > (pm_100ms - pm_thresh) &&
604 deltapm < (pm_100ms + pm_thresh)) {
605 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
609 res = (((u64)deltapm) * mult) >> 22;
610 do_div(res, 1000000);
611 pr_warning("APIC calibration not consistent "
612 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
614 /* Correct the lapic counter value */
615 res = (((u64)(*delta)) * pm_100ms);
616 do_div(res, deltapm);
617 pr_info("APIC delta adjusted to PM-Timer: "
618 "%lu (%ld)\n", (unsigned long)res, *delta);
621 /* Correct the tsc counter value */
623 res = (((u64)(*deltatsc)) * pm_100ms);
624 do_div(res, deltapm);
625 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
626 "PM-Timer: %lu (%ld)\n",
627 (unsigned long)res, *deltatsc);
628 *deltatsc = (long)res;
634 static int __init calibrate_APIC_clock(void)
636 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
637 void (*real_handler)(struct clock_event_device *dev);
638 unsigned long deltaj;
639 long delta, deltatsc;
640 int pm_referenced = 0;
643 * check if lapic timer has already been calibrated by platform
644 * specific routine, such as tsc calibration code. if so, we just fill
645 * in the clockevent structure and return.
648 if (lapic_timer_frequency) {
649 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
650 lapic_timer_frequency);
651 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
652 TICK_NSEC, lapic_clockevent.shift);
653 lapic_clockevent.max_delta_ns =
654 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
655 lapic_clockevent.min_delta_ns =
656 clockevent_delta2ns(0xF, &lapic_clockevent);
657 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
663 /* Replace the global interrupt handler */
664 real_handler = global_clock_event->event_handler;
665 global_clock_event->event_handler = lapic_cal_handler;
668 * Setup the APIC counter to maximum. There is no way the lapic
669 * can underflow in the 100ms detection time frame
671 __setup_APIC_LVTT(0xffffffff, 0, 0);
673 /* Let the interrupts run */
676 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
681 /* Restore the real event handler */
682 global_clock_event->event_handler = real_handler;
684 /* Build delta t1-t2 as apic timer counts down */
685 delta = lapic_cal_t1 - lapic_cal_t2;
686 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
688 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
690 /* we trust the PM based calibration if possible */
691 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
694 /* Calculate the scaled math multiplication factor */
695 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
696 lapic_clockevent.shift);
697 lapic_clockevent.max_delta_ns =
698 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
699 lapic_clockevent.min_delta_ns =
700 clockevent_delta2ns(0xF, &lapic_clockevent);
702 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
704 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
705 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
706 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
707 lapic_timer_frequency);
710 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
712 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
713 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
716 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
718 lapic_timer_frequency / (1000000 / HZ),
719 lapic_timer_frequency % (1000000 / HZ));
722 * Do a sanity check on the APIC calibration result
724 if (lapic_timer_frequency < (1000000 / HZ)) {
726 pr_warning("APIC frequency too slow, disabling apic timer\n");
730 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
733 * PM timer calibration failed or not turned on
734 * so lets try APIC timer based calibration
736 if (!pm_referenced) {
737 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
740 * Setup the apic timer manually
742 levt->event_handler = lapic_cal_handler;
743 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
744 lapic_cal_loops = -1;
746 /* Let the interrupts run */
749 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
752 /* Stop the lapic timer */
753 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
756 deltaj = lapic_cal_j2 - lapic_cal_j1;
757 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
759 /* Check, if the jiffies result is consistent */
760 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
761 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
763 levt->features |= CLOCK_EVT_FEAT_DUMMY;
767 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
768 pr_warning("APIC timer disabled due to verification failure\n");
776 * Setup the boot APIC
778 * Calibrate and verify the result.
780 void __init setup_boot_APIC_clock(void)
783 * The local apic timer can be disabled via the kernel
784 * commandline or from the CPU detection code. Register the lapic
785 * timer as a dummy clock event source on SMP systems, so the
786 * broadcast mechanism is used. On UP systems simply ignore it.
788 if (disable_apic_timer) {
789 pr_info("Disabling APIC timer\n");
790 /* No broadcast on UP ! */
791 if (num_possible_cpus() > 1) {
792 lapic_clockevent.mult = 1;
798 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
799 "calibrating APIC timer ...\n");
801 if (calibrate_APIC_clock()) {
802 /* No broadcast on UP ! */
803 if (num_possible_cpus() > 1)
809 * If nmi_watchdog is set to IO_APIC, we need the
810 * PIT/HPET going. Otherwise register lapic as a dummy
813 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
815 /* Setup the lapic or request the broadcast */
819 void __cpuinit setup_secondary_APIC_clock(void)
825 * The guts of the apic timer interrupt
827 static void local_apic_timer_interrupt(void)
829 int cpu = smp_processor_id();
830 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
833 * Normally we should not be here till LAPIC has been initialized but
834 * in some cases like kdump, its possible that there is a pending LAPIC
835 * timer interrupt from previous kernel's context and is delivered in
836 * new kernel the moment interrupts are enabled.
838 * Interrupts are enabled early and LAPIC is setup much later, hence
839 * its possible that when we get here evt->event_handler is NULL.
840 * Check for event_handler being NULL and discard the interrupt as
843 if (!evt->event_handler) {
844 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
846 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
851 * the NMI deadlock-detector uses this.
853 inc_irq_stat(apic_timer_irqs);
855 evt->event_handler(evt);
859 * Local APIC timer interrupt. This is the most natural way for doing
860 * local interrupts, but local timer interrupts can be emulated by
861 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
863 * [ if a single-CPU system runs an SMP kernel then we call the local
864 * interrupt as well. Thus we cannot inline the local irq ... ]
866 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
868 struct pt_regs *old_regs = set_irq_regs(regs);
871 * NOTE! We'd better ACK the irq immediately,
872 * because timer handling can be slow.
876 * update_process_times() expects us to have done irq_enter().
877 * Besides, if we don't timer interrupts ignore the global
878 * interrupt lock, which is the WrongThing (tm) to do.
882 local_apic_timer_interrupt();
885 set_irq_regs(old_regs);
888 int setup_profiling_timer(unsigned int multiplier)
894 * Local APIC start and shutdown
898 * clear_local_APIC - shutdown the local APIC
900 * This is called, when a CPU is disabled and before rebooting, so the state of
901 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
902 * leftovers during boot.
904 void clear_local_APIC(void)
909 /* APIC hasn't been mapped yet */
910 if (!x2apic_mode && !apic_phys)
913 maxlvt = lapic_get_maxlvt();
915 * Masking an LVT entry can trigger a local APIC error
916 * if the vector is zero. Mask LVTERR first to prevent this.
919 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
920 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
923 * Careful: we have to set masks only first to deassert
924 * any level-triggered sources.
926 v = apic_read(APIC_LVTT);
927 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
928 v = apic_read(APIC_LVT0);
929 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
930 v = apic_read(APIC_LVT1);
931 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
933 v = apic_read(APIC_LVTPC);
934 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
937 /* lets not touch this if we didn't frob it */
938 #ifdef CONFIG_X86_THERMAL_VECTOR
940 v = apic_read(APIC_LVTTHMR);
941 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
944 #ifdef CONFIG_X86_MCE_INTEL
946 v = apic_read(APIC_LVTCMCI);
947 if (!(v & APIC_LVT_MASKED))
948 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
953 * Clean APIC state for other OSs:
955 apic_write(APIC_LVTT, APIC_LVT_MASKED);
956 apic_write(APIC_LVT0, APIC_LVT_MASKED);
957 apic_write(APIC_LVT1, APIC_LVT_MASKED);
959 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
961 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
963 /* Integrated APIC (!82489DX) ? */
964 if (lapic_is_integrated()) {
966 /* Clear ESR due to Pentium errata 3AP and 11AP */
967 apic_write(APIC_ESR, 0);
973 * disable_local_APIC - clear and disable the local APIC
975 void disable_local_APIC(void)
979 /* APIC hasn't been mapped yet */
980 if (!x2apic_mode && !apic_phys)
986 * Disable APIC (implies clearing of registers
989 value = apic_read(APIC_SPIV);
990 value &= ~APIC_SPIV_APIC_ENABLED;
991 apic_write(APIC_SPIV, value);
995 * When LAPIC was disabled by the BIOS and enabled by the kernel,
996 * restore the disabled state.
998 if (enabled_via_apicbase) {
1001 rdmsr(MSR_IA32_APICBASE, l, h);
1002 l &= ~MSR_IA32_APICBASE_ENABLE;
1003 wrmsr(MSR_IA32_APICBASE, l, h);
1009 * If Linux enabled the LAPIC against the BIOS default disable it down before
1010 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1011 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1012 * for the case where Linux didn't enable the LAPIC.
1014 void lapic_shutdown(void)
1016 unsigned long flags;
1018 if (!cpu_has_apic && !apic_from_smp_config())
1021 local_irq_save(flags);
1023 #ifdef CONFIG_X86_32
1024 if (!enabled_via_apicbase)
1028 disable_local_APIC();
1031 local_irq_restore(flags);
1035 * This is to verify that we're looking at a real local APIC.
1036 * Check these against your board if the CPUs aren't getting
1037 * started for no apparent reason.
1039 int __init verify_local_APIC(void)
1041 unsigned int reg0, reg1;
1044 * The version register is read-only in a real APIC.
1046 reg0 = apic_read(APIC_LVR);
1047 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1048 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1049 reg1 = apic_read(APIC_LVR);
1050 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1053 * The two version reads above should print the same
1054 * numbers. If the second one is different, then we
1055 * poke at a non-APIC.
1061 * Check if the version looks reasonably.
1063 reg1 = GET_APIC_VERSION(reg0);
1064 if (reg1 == 0x00 || reg1 == 0xff)
1066 reg1 = lapic_get_maxlvt();
1067 if (reg1 < 0x02 || reg1 == 0xff)
1071 * The ID register is read/write in a real APIC.
1073 reg0 = apic_read(APIC_ID);
1074 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1075 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1076 reg1 = apic_read(APIC_ID);
1077 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1078 apic_write(APIC_ID, reg0);
1079 if (reg1 != (reg0 ^ apic->apic_id_mask))
1083 * The next two are just to see if we have sane values.
1084 * They're only really relevant if we're in Virtual Wire
1085 * compatibility mode, but most boxes are anymore.
1087 reg0 = apic_read(APIC_LVT0);
1088 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1089 reg1 = apic_read(APIC_LVT1);
1090 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1096 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1098 void __init sync_Arb_IDs(void)
1101 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1104 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1110 apic_wait_icr_idle();
1112 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1113 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1114 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1118 * An initial setup of the virtual wire mode.
1120 void __init init_bsp_APIC(void)
1125 * Don't do the setup now if we have a SMP BIOS as the
1126 * through-I/O-APIC virtual wire mode might be active.
1128 if (smp_found_config || !cpu_has_apic)
1132 * Do not trust the local APIC being empty at bootup.
1139 value = apic_read(APIC_SPIV);
1140 value &= ~APIC_VECTOR_MASK;
1141 value |= APIC_SPIV_APIC_ENABLED;
1143 #ifdef CONFIG_X86_32
1144 /* This bit is reserved on P4/Xeon and should be cleared */
1145 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1146 (boot_cpu_data.x86 == 15))
1147 value &= ~APIC_SPIV_FOCUS_DISABLED;
1150 value |= APIC_SPIV_FOCUS_DISABLED;
1151 value |= SPURIOUS_APIC_VECTOR;
1152 apic_write(APIC_SPIV, value);
1155 * Set up the virtual wire mode.
1157 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1158 value = APIC_DM_NMI;
1159 if (!lapic_is_integrated()) /* 82489DX */
1160 value |= APIC_LVT_LEVEL_TRIGGER;
1161 apic_write(APIC_LVT1, value);
1164 static void __cpuinit lapic_setup_esr(void)
1166 unsigned int oldvalue, value, maxlvt;
1168 if (!lapic_is_integrated()) {
1169 pr_info("No ESR for 82489DX.\n");
1173 if (apic->disable_esr) {
1175 * Something untraceable is creating bad interrupts on
1176 * secondary quads ... for the moment, just leave the
1177 * ESR disabled - we can't do anything useful with the
1178 * errors anyway - mbligh
1180 pr_info("Leaving ESR disabled.\n");
1184 maxlvt = lapic_get_maxlvt();
1185 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1186 apic_write(APIC_ESR, 0);
1187 oldvalue = apic_read(APIC_ESR);
1189 /* enables sending errors */
1190 value = ERROR_APIC_VECTOR;
1191 apic_write(APIC_LVTERR, value);
1194 * spec says clear errors after enabling vector.
1197 apic_write(APIC_ESR, 0);
1198 value = apic_read(APIC_ESR);
1199 if (value != oldvalue)
1200 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1201 "vector: 0x%08x after: 0x%08x\n",
1206 * setup_local_APIC - setup the local APIC
1208 * Used to setup local APIC while initializing BSP or bringin up APs.
1209 * Always called with preemption disabled.
1211 void __cpuinit setup_local_APIC(void)
1213 int cpu = smp_processor_id();
1214 unsigned int value, queued;
1215 int i, j, acked = 0;
1216 unsigned long long tsc = 0, ntsc;
1217 long long max_loops = cpu_khz;
1223 disable_ioapic_support();
1227 #ifdef CONFIG_X86_32
1228 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1229 if (lapic_is_integrated() && apic->disable_esr) {
1230 apic_write(APIC_ESR, 0);
1231 apic_write(APIC_ESR, 0);
1232 apic_write(APIC_ESR, 0);
1233 apic_write(APIC_ESR, 0);
1236 perf_events_lapic_init();
1239 * Double-check whether this APIC is really registered.
1240 * This is meaningless in clustered apic mode, so we skip it.
1242 BUG_ON(!apic->apic_id_registered());
1245 * Intel recommends to set DFR, LDR and TPR before enabling
1246 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1247 * document number 292116). So here it goes...
1249 apic->init_apic_ldr();
1251 #ifdef CONFIG_X86_32
1253 * APIC LDR is initialized. If logical_apicid mapping was
1254 * initialized during get_smp_config(), make sure it matches the
1257 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1258 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1259 /* always use the value from LDR */
1260 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1261 logical_smp_processor_id();
1264 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1265 * node mapping during NUMA init. Now that logical apicid is
1266 * guaranteed to be known, give it another chance. This is already
1267 * a bit too late - percpu allocation has already happened without
1268 * proper NUMA affinity.
1270 if (apic->x86_32_numa_cpu_node)
1271 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1272 apic->x86_32_numa_cpu_node(cpu));
1276 * Set Task Priority to 'accept all'. We never change this
1279 value = apic_read(APIC_TASKPRI);
1280 value &= ~APIC_TPRI_MASK;
1281 apic_write(APIC_TASKPRI, value);
1284 * After a crash, we no longer service the interrupts and a pending
1285 * interrupt from previous kernel might still have ISR bit set.
1287 * Most probably by now CPU has serviced that pending interrupt and
1288 * it might not have done the ack_APIC_irq() because it thought,
1289 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1290 * does not clear the ISR bit and cpu thinks it has already serivced
1291 * the interrupt. Hence a vector might get locked. It was noticed
1292 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1296 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1297 queued |= apic_read(APIC_IRR + i*0x10);
1299 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1300 value = apic_read(APIC_ISR + i*0x10);
1301 for (j = 31; j >= 0; j--) {
1302 if (value & (1<<j)) {
1309 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1315 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1318 } while (queued && max_loops > 0);
1319 WARN_ON(max_loops <= 0);
1322 * Now that we are all set up, enable the APIC
1324 value = apic_read(APIC_SPIV);
1325 value &= ~APIC_VECTOR_MASK;
1329 value |= APIC_SPIV_APIC_ENABLED;
1331 #ifdef CONFIG_X86_32
1333 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1334 * certain networking cards. If high frequency interrupts are
1335 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1336 * entry is masked/unmasked at a high rate as well then sooner or
1337 * later IOAPIC line gets 'stuck', no more interrupts are received
1338 * from the device. If focus CPU is disabled then the hang goes
1341 * [ This bug can be reproduced easily with a level-triggered
1342 * PCI Ne2000 networking cards and PII/PIII processors, dual
1346 * Actually disabling the focus CPU check just makes the hang less
1347 * frequent as it makes the interrupt distributon model be more
1348 * like LRU than MRU (the short-term load is more even across CPUs).
1349 * See also the comment in end_level_ioapic_irq(). --macro
1353 * - enable focus processor (bit==0)
1354 * - 64bit mode always use processor focus
1355 * so no need to set it
1357 value &= ~APIC_SPIV_FOCUS_DISABLED;
1361 * Set spurious IRQ vector
1363 value |= SPURIOUS_APIC_VECTOR;
1364 apic_write(APIC_SPIV, value);
1367 * Set up LVT0, LVT1:
1369 * set up through-local-APIC on the BP's LINT0. This is not
1370 * strictly necessary in pure symmetric-IO mode, but sometimes
1371 * we delegate interrupts to the 8259A.
1374 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1376 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1377 if (!cpu && (pic_mode || !value)) {
1378 value = APIC_DM_EXTINT;
1379 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1381 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1382 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1384 apic_write(APIC_LVT0, value);
1387 * only the BP should see the LINT1 NMI signal, obviously.
1390 value = APIC_DM_NMI;
1392 value = APIC_DM_NMI | APIC_LVT_MASKED;
1393 if (!lapic_is_integrated()) /* 82489DX */
1394 value |= APIC_LVT_LEVEL_TRIGGER;
1395 apic_write(APIC_LVT1, value);
1397 #ifdef CONFIG_X86_MCE_INTEL
1398 /* Recheck CMCI information after local APIC is up on CPU #0 */
1404 void __cpuinit end_local_APIC_setup(void)
1408 #ifdef CONFIG_X86_32
1411 /* Disable the local apic timer */
1412 value = apic_read(APIC_LVTT);
1413 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1414 apic_write(APIC_LVTT, value);
1421 void __init bsp_end_local_APIC_setup(void)
1423 end_local_APIC_setup();
1426 * Now that local APIC setup is completed for BP, configure the fault
1427 * handling for interrupt remapping.
1429 if (intr_remapping_enabled)
1430 enable_drhd_fault_handling();
1434 #ifdef CONFIG_X86_X2APIC
1435 void check_x2apic(void)
1437 if (x2apic_enabled()) {
1438 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1439 x2apic_preenabled = x2apic_mode = 1;
1443 void enable_x2apic(void)
1450 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1451 if (!(msr & X2APIC_ENABLE)) {
1452 printk_once(KERN_INFO "Enabling x2apic\n");
1453 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
1456 #endif /* CONFIG_X86_X2APIC */
1458 int __init enable_IR(void)
1460 #ifdef CONFIG_IRQ_REMAP
1461 if (!intr_remapping_supported()) {
1462 pr_debug("intr-remapping not supported\n");
1466 if (!x2apic_preenabled && skip_ioapic_setup) {
1467 pr_info("Skipped enabling intr-remap because of skipping "
1472 return enable_intr_remapping();
1477 void __init enable_IR_x2apic(void)
1479 unsigned long flags;
1480 int ret, x2apic_enabled = 0;
1481 int dmar_table_init_ret;
1483 dmar_table_init_ret = dmar_table_init();
1484 if (dmar_table_init_ret && !x2apic_supported())
1487 ret = save_ioapic_entries();
1489 pr_info("Saving IO-APIC state failed: %d\n", ret);
1493 local_irq_save(flags);
1494 legacy_pic->mask_all();
1495 mask_ioapic_entries();
1497 if (dmar_table_init_ret)
1503 /* IR is required if there is APIC ID > 255 even when running
1506 if (max_physical_apicid > 255 ||
1507 !hypervisor_x2apic_available())
1510 * without IR all CPUs can be addressed by IOAPIC/MSI
1511 * only in physical mode
1513 x2apic_force_phys();
1516 if (ret == IRQ_REMAP_XAPIC_MODE)
1521 if (x2apic_supported() && !x2apic_mode) {
1524 pr_info("Enabled x2apic\n");
1528 if (ret < 0) /* IR enabling failed */
1529 restore_ioapic_entries();
1530 legacy_pic->restore_mask();
1531 local_irq_restore(flags);
1534 if (x2apic_enabled || !x2apic_supported())
1537 if (x2apic_preenabled)
1538 panic("x2apic: enabled by BIOS but kernel init failed.");
1539 else if (ret == IRQ_REMAP_XAPIC_MODE)
1540 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1542 pr_info("x2apic not enabled, IRQ remapping init failed\n");
1545 #ifdef CONFIG_X86_64
1547 * Detect and enable local APICs on non-SMP boards.
1548 * Original code written by Keir Fraser.
1549 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1550 * not correctly set up (usually the APIC timer won't work etc.)
1552 static int __init detect_init_APIC(void)
1554 if (!cpu_has_apic) {
1555 pr_info("No local APIC present\n");
1559 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1564 static int __init apic_verify(void)
1569 * The APIC feature bit should now be enabled
1572 features = cpuid_edx(1);
1573 if (!(features & (1 << X86_FEATURE_APIC))) {
1574 pr_warning("Could not enable APIC!\n");
1577 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1578 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1580 /* The BIOS may have set up the APIC at some other address */
1581 rdmsr(MSR_IA32_APICBASE, l, h);
1582 if (l & MSR_IA32_APICBASE_ENABLE)
1583 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1585 pr_info("Found and enabled local APIC!\n");
1589 int __init apic_force_enable(unsigned long addr)
1597 * Some BIOSes disable the local APIC in the APIC_BASE
1598 * MSR. This can only be done in software for Intel P6 or later
1599 * and AMD K7 (Model > 1) or later.
1601 rdmsr(MSR_IA32_APICBASE, l, h);
1602 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1603 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1604 l &= ~MSR_IA32_APICBASE_BASE;
1605 l |= MSR_IA32_APICBASE_ENABLE | addr;
1606 wrmsr(MSR_IA32_APICBASE, l, h);
1607 enabled_via_apicbase = 1;
1609 return apic_verify();
1613 * Detect and initialize APIC
1615 static int __init detect_init_APIC(void)
1617 /* Disabled by kernel option? */
1621 switch (boot_cpu_data.x86_vendor) {
1622 case X86_VENDOR_AMD:
1623 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1624 (boot_cpu_data.x86 >= 15))
1627 case X86_VENDOR_INTEL:
1628 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1629 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1636 if (!cpu_has_apic) {
1638 * Over-ride BIOS and try to enable the local APIC only if
1639 * "lapic" specified.
1641 if (!force_enable_local_apic) {
1642 pr_info("Local APIC disabled by BIOS -- "
1643 "you can enable it with \"lapic\"\n");
1646 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1658 pr_info("No local APIC present or hardware disabled\n");
1664 * init_apic_mappings - initialize APIC mappings
1666 void __init init_apic_mappings(void)
1668 unsigned int new_apicid;
1671 boot_cpu_physical_apicid = read_apic_id();
1675 /* If no local APIC can be found return early */
1676 if (!smp_found_config && detect_init_APIC()) {
1677 /* lets NOP'ify apic operations */
1678 pr_info("APIC: disable apic facility\n");
1681 apic_phys = mp_lapic_addr;
1684 * acpi lapic path already maps that address in
1685 * acpi_register_lapic_address()
1687 if (!acpi_lapic && !smp_found_config)
1688 register_lapic_address(apic_phys);
1692 * Fetch the APIC ID of the BSP in case we have a
1693 * default configuration (or the MP table is broken).
1695 new_apicid = read_apic_id();
1696 if (boot_cpu_physical_apicid != new_apicid) {
1697 boot_cpu_physical_apicid = new_apicid;
1699 * yeah -- we lie about apic_version
1700 * in case if apic was disabled via boot option
1701 * but it's not a problem for SMP compiled kernel
1702 * since smp_sanity_check is prepared for such a case
1703 * and disable smp mode
1705 apic_version[new_apicid] =
1706 GET_APIC_VERSION(apic_read(APIC_LVR));
1710 void __init register_lapic_address(unsigned long address)
1712 mp_lapic_addr = address;
1715 set_fixmap_nocache(FIX_APIC_BASE, address);
1716 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1717 APIC_BASE, mp_lapic_addr);
1719 if (boot_cpu_physical_apicid == -1U) {
1720 boot_cpu_physical_apicid = read_apic_id();
1721 apic_version[boot_cpu_physical_apicid] =
1722 GET_APIC_VERSION(apic_read(APIC_LVR));
1727 * This initializes the IO-APIC and APIC hardware if this is
1730 int apic_version[MAX_LOCAL_APIC];
1732 int __init APIC_init_uniprocessor(void)
1735 pr_info("Apic disabled\n");
1738 #ifdef CONFIG_X86_64
1739 if (!cpu_has_apic) {
1741 pr_info("Apic disabled by BIOS\n");
1745 if (!smp_found_config && !cpu_has_apic)
1749 * Complain if the BIOS pretends there is one.
1751 if (!cpu_has_apic &&
1752 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1753 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1754 boot_cpu_physical_apicid);
1759 default_setup_apic_routing();
1761 verify_local_APIC();
1764 #ifdef CONFIG_X86_64
1765 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1768 * Hack: In case of kdump, after a crash, kernel might be booting
1769 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1770 * might be zero if read from MP tables. Get it from LAPIC.
1772 # ifdef CONFIG_CRASH_DUMP
1773 boot_cpu_physical_apicid = read_apic_id();
1776 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1779 #ifdef CONFIG_X86_IO_APIC
1781 * Now enable IO-APICs, actually call clear_IO_APIC
1782 * We need clear_IO_APIC before enabling error vector
1784 if (!skip_ioapic_setup && nr_ioapics)
1788 bsp_end_local_APIC_setup();
1790 #ifdef CONFIG_X86_IO_APIC
1791 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1798 x86_init.timers.setup_percpu_clockev();
1803 * Local APIC interrupts
1807 * This interrupt should _never_ happen with our APIC/SMP architecture
1809 void smp_spurious_interrupt(struct pt_regs *regs)
1816 * Check if this really is a spurious interrupt and ACK it
1817 * if it is a vectored one. Just in case...
1818 * Spurious interrupts should not be ACKed.
1820 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1821 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1824 inc_irq_stat(irq_spurious_count);
1826 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1827 pr_info("spurious APIC interrupt on CPU#%d, "
1828 "should never happen.\n", smp_processor_id());
1833 * This interrupt should never happen with our APIC/SMP architecture
1835 void smp_error_interrupt(struct pt_regs *regs)
1839 static const char * const error_interrupt_reason[] = {
1840 "Send CS error", /* APIC Error Bit 0 */
1841 "Receive CS error", /* APIC Error Bit 1 */
1842 "Send accept error", /* APIC Error Bit 2 */
1843 "Receive accept error", /* APIC Error Bit 3 */
1844 "Redirectable IPI", /* APIC Error Bit 4 */
1845 "Send illegal vector", /* APIC Error Bit 5 */
1846 "Received illegal vector", /* APIC Error Bit 6 */
1847 "Illegal register address", /* APIC Error Bit 7 */
1852 /* First tickle the hardware, only then report what went on. -- REW */
1853 v0 = apic_read(APIC_ESR);
1854 apic_write(APIC_ESR, 0);
1855 v1 = apic_read(APIC_ESR);
1857 atomic_inc(&irq_err_count);
1859 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1860 smp_processor_id(), v0 , v1);
1865 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1870 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1876 * connect_bsp_APIC - attach the APIC to the interrupt system
1878 void __init connect_bsp_APIC(void)
1880 #ifdef CONFIG_X86_32
1883 * Do not trust the local APIC being empty at bootup.
1887 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1888 * local APIC to INT and NMI lines.
1890 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1891 "enabling APIC mode.\n");
1895 if (apic->enable_apic_mode)
1896 apic->enable_apic_mode();
1900 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1901 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1903 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1906 void disconnect_bsp_APIC(int virt_wire_setup)
1910 #ifdef CONFIG_X86_32
1913 * Put the board back into PIC mode (has an effect only on
1914 * certain older boards). Note that APIC interrupts, including
1915 * IPIs, won't work beyond this point! The only exception are
1918 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1919 "entering PIC mode.\n");
1925 /* Go back to Virtual Wire compatibility mode */
1927 /* For the spurious interrupt use vector F, and enable it */
1928 value = apic_read(APIC_SPIV);
1929 value &= ~APIC_VECTOR_MASK;
1930 value |= APIC_SPIV_APIC_ENABLED;
1932 apic_write(APIC_SPIV, value);
1934 if (!virt_wire_setup) {
1936 * For LVT0 make it edge triggered, active high,
1937 * external and enabled
1939 value = apic_read(APIC_LVT0);
1940 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1941 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1942 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1943 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1944 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1945 apic_write(APIC_LVT0, value);
1948 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1952 * For LVT1 make it edge triggered, active high,
1955 value = apic_read(APIC_LVT1);
1956 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1957 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1958 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1959 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1960 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1961 apic_write(APIC_LVT1, value);
1964 void __cpuinit generic_processor_info(int apicid, int version)
1966 int cpu, max = nr_cpu_ids;
1967 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
1968 phys_cpu_present_map);
1971 * If boot cpu has not been detected yet, then only allow upto
1972 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
1974 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
1975 apicid != boot_cpu_physical_apicid) {
1976 int thiscpu = max + disabled_cpus - 1;
1979 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
1980 " reached. Keeping one slot for boot cpu."
1981 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1987 if (num_processors >= nr_cpu_ids) {
1988 int thiscpu = max + disabled_cpus;
1991 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1992 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1999 if (apicid == boot_cpu_physical_apicid) {
2001 * x86_bios_cpu_apicid is required to have processors listed
2002 * in same order as logical cpu numbers. Hence the first
2003 * entry is BSP, and so on.
2004 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2009 cpu = cpumask_next_zero(-1, cpu_present_mask);
2014 if (version == 0x0) {
2015 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2019 apic_version[apicid] = version;
2021 if (version != apic_version[boot_cpu_physical_apicid]) {
2022 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2023 apic_version[boot_cpu_physical_apicid], cpu, version);
2026 physid_set(apicid, phys_cpu_present_map);
2027 if (apicid > max_physical_apicid)
2028 max_physical_apicid = apicid;
2030 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2031 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2032 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2034 #ifdef CONFIG_X86_32
2035 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2036 apic->x86_32_early_logical_apicid(cpu);
2038 set_cpu_possible(cpu, true);
2039 set_cpu_present(cpu, true);
2042 int hard_smp_processor_id(void)
2044 return read_apic_id();
2047 void default_init_apic_ldr(void)
2051 apic_write(APIC_DFR, APIC_DFR_VALUE);
2052 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2053 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2054 apic_write(APIC_LDR, val);
2064 * 'active' is true if the local APIC was enabled by us and
2065 * not the BIOS; this signifies that we are also responsible
2066 * for disabling it before entering apm/acpi suspend
2069 /* r/w apic fields */
2070 unsigned int apic_id;
2071 unsigned int apic_taskpri;
2072 unsigned int apic_ldr;
2073 unsigned int apic_dfr;
2074 unsigned int apic_spiv;
2075 unsigned int apic_lvtt;
2076 unsigned int apic_lvtpc;
2077 unsigned int apic_lvt0;
2078 unsigned int apic_lvt1;
2079 unsigned int apic_lvterr;
2080 unsigned int apic_tmict;
2081 unsigned int apic_tdcr;
2082 unsigned int apic_thmr;
2085 static int lapic_suspend(void)
2087 unsigned long flags;
2090 if (!apic_pm_state.active)
2093 maxlvt = lapic_get_maxlvt();
2095 apic_pm_state.apic_id = apic_read(APIC_ID);
2096 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2097 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2098 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2099 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2100 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2102 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2103 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2104 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2105 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2106 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2107 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2108 #ifdef CONFIG_X86_THERMAL_VECTOR
2110 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2113 local_irq_save(flags);
2114 disable_local_APIC();
2116 if (intr_remapping_enabled)
2117 disable_intr_remapping();
2119 local_irq_restore(flags);
2123 static void lapic_resume(void)
2126 unsigned long flags;
2129 if (!apic_pm_state.active)
2132 local_irq_save(flags);
2133 if (intr_remapping_enabled) {
2135 * IO-APIC and PIC have their own resume routines.
2136 * We just mask them here to make sure the interrupt
2137 * subsystem is completely quiet while we enable x2apic
2138 * and interrupt-remapping.
2140 mask_ioapic_entries();
2141 legacy_pic->mask_all();
2148 * Make sure the APICBASE points to the right address
2150 * FIXME! This will be wrong if we ever support suspend on
2151 * SMP! We'll need to do this as part of the CPU restore!
2153 rdmsr(MSR_IA32_APICBASE, l, h);
2154 l &= ~MSR_IA32_APICBASE_BASE;
2155 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2156 wrmsr(MSR_IA32_APICBASE, l, h);
2159 maxlvt = lapic_get_maxlvt();
2160 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2161 apic_write(APIC_ID, apic_pm_state.apic_id);
2162 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2163 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2164 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2165 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2166 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2167 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2168 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2170 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2173 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2174 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2175 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2176 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2177 apic_write(APIC_ESR, 0);
2178 apic_read(APIC_ESR);
2179 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2180 apic_write(APIC_ESR, 0);
2181 apic_read(APIC_ESR);
2183 if (intr_remapping_enabled)
2184 reenable_intr_remapping(x2apic_mode);
2186 local_irq_restore(flags);
2190 * This device has no shutdown method - fully functioning local APICs
2191 * are needed on every CPU up until machine_halt/restart/poweroff.
2194 static struct syscore_ops lapic_syscore_ops = {
2195 .resume = lapic_resume,
2196 .suspend = lapic_suspend,
2199 static void __cpuinit apic_pm_activate(void)
2201 apic_pm_state.active = 1;
2204 static int __init init_lapic_sysfs(void)
2206 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2208 register_syscore_ops(&lapic_syscore_ops);
2213 /* local apic needs to resume before other devices access its registers. */
2214 core_initcall(init_lapic_sysfs);
2216 #else /* CONFIG_PM */
2218 static void apic_pm_activate(void) { }
2220 #endif /* CONFIG_PM */
2222 #ifdef CONFIG_X86_64
2224 static int __cpuinit apic_cluster_num(void)
2226 int i, clusters, zeros;
2228 u16 *bios_cpu_apicid;
2229 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2231 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2232 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2234 for (i = 0; i < nr_cpu_ids; i++) {
2235 /* are we being called early in kernel startup? */
2236 if (bios_cpu_apicid) {
2237 id = bios_cpu_apicid[i];
2238 } else if (i < nr_cpu_ids) {
2240 id = per_cpu(x86_bios_cpu_apicid, i);
2246 if (id != BAD_APICID)
2247 __set_bit(APIC_CLUSTERID(id), clustermap);
2250 /* Problem: Partially populated chassis may not have CPUs in some of
2251 * the APIC clusters they have been allocated. Only present CPUs have
2252 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2253 * Since clusters are allocated sequentially, count zeros only if
2254 * they are bounded by ones.
2258 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2259 if (test_bit(i, clustermap)) {
2260 clusters += 1 + zeros;
2269 static int __cpuinitdata multi_checked;
2270 static int __cpuinitdata multi;
2272 static int __cpuinit set_multi(const struct dmi_system_id *d)
2276 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2281 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2283 .callback = set_multi,
2284 .ident = "IBM System Summit2",
2286 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2287 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2293 static void __cpuinit dmi_check_multi(void)
2298 dmi_check_system(multi_dmi_table);
2303 * apic_is_clustered_box() -- Check if we can expect good TSC
2305 * Thus far, the major user of this is IBM's Summit2 series:
2306 * Clustered boxes may have unsynced TSC problems if they are
2308 * Use DMI to check them
2310 __cpuinit int apic_is_clustered_box(void)
2320 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2321 * not guaranteed to be synced between boards
2323 if (apic_cluster_num() > 1)
2331 * APIC command line parameters
2333 static int __init setup_disableapic(char *arg)
2336 setup_clear_cpu_cap(X86_FEATURE_APIC);
2339 early_param("disableapic", setup_disableapic);
2341 /* same as disableapic, for compatibility */
2342 static int __init setup_nolapic(char *arg)
2344 return setup_disableapic(arg);
2346 early_param("nolapic", setup_nolapic);
2348 static int __init parse_lapic_timer_c2_ok(char *arg)
2350 local_apic_timer_c2_ok = 1;
2353 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2355 static int __init parse_disable_apic_timer(char *arg)
2357 disable_apic_timer = 1;
2360 early_param("noapictimer", parse_disable_apic_timer);
2362 static int __init parse_nolapic_timer(char *arg)
2364 disable_apic_timer = 1;
2367 early_param("nolapic_timer", parse_nolapic_timer);
2369 static int __init apic_set_verbosity(char *arg)
2372 #ifdef CONFIG_X86_64
2373 skip_ioapic_setup = 0;
2379 if (strcmp("debug", arg) == 0)
2380 apic_verbosity = APIC_DEBUG;
2381 else if (strcmp("verbose", arg) == 0)
2382 apic_verbosity = APIC_VERBOSE;
2384 pr_warning("APIC Verbosity level %s not recognised"
2385 " use apic=verbose or apic=debug\n", arg);
2391 early_param("apic", apic_set_verbosity);
2393 static int __init lapic_insert_resource(void)
2398 /* Put local APIC into the resource map. */
2399 lapic_resource.start = apic_phys;
2400 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2401 insert_resource(&iomem_resource, &lapic_resource);
2407 * need call insert after e820_reserve_resources()
2408 * that is using request_resource
2410 late_initcall(lapic_insert_resource);