2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
57 #include <asm/hypervisor.h>
59 unsigned int num_processors;
61 unsigned disabled_cpus;
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_physical_apicid = -1U;
67 * The highest APIC ID seen during enumeration.
69 unsigned int max_physical_apicid;
72 * Bitmask of physically existing CPUs:
74 physid_mask_t phys_cpu_present_map;
77 * Map cpu index to physical APIC ID
79 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
80 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
82 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
87 * On x86_32, the mapping between cpu and logical apicid may vary
88 * depending on apic in use. The following early percpu variable is
89 * used for the mapping. This is where the behaviors of x86_64 and 32
90 * actually diverge. Let's keep it ugly for now.
92 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
94 /* Local APIC was disabled by the BIOS and enabled by the kernel */
95 static int enabled_via_apicbase;
98 * Handle interrupt mode configuration register (IMCR).
99 * This register controls whether the interrupt signals
100 * that reach the BSP come from the master PIC or from the
101 * local APIC. Before entering Symmetric I/O Mode, either
102 * the BIOS or the operating system must switch out of
103 * PIC Mode by changing the IMCR.
105 static inline void imcr_pic_to_apic(void)
107 /* select IMCR register */
109 /* NMI and 8259 INTR go through APIC */
113 static inline void imcr_apic_to_pic(void)
115 /* select IMCR register */
117 /* NMI and 8259 INTR go directly to BSP */
123 * Knob to control our willingness to enable the local APIC.
127 static int force_enable_local_apic __initdata;
129 * APIC command line parameters
131 static int __init parse_lapic(char *arg)
133 if (config_enabled(CONFIG_X86_32) && !arg)
134 force_enable_local_apic = 1;
135 else if (arg && !strncmp(arg, "notscdeadline", 13))
136 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
139 early_param("lapic", parse_lapic);
142 static int apic_calibrate_pmtmr __initdata;
143 static __init int setup_apicpmtimer(char *s)
145 apic_calibrate_pmtmr = 1;
149 __setup("apicpmtimer", setup_apicpmtimer);
153 #ifdef CONFIG_X86_X2APIC
154 /* x2apic enabled before OS handover */
155 int x2apic_preenabled;
156 static int x2apic_disabled;
158 static __init int setup_nox2apic(char *str)
160 if (x2apic_enabled()) {
161 int apicid = native_apic_msr_read(APIC_ID);
164 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
169 pr_warning("x2apic already enabled. will disable it\n");
171 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
177 early_param("nox2apic", setup_nox2apic);
180 unsigned long mp_lapic_addr;
182 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
183 static int disable_apic_timer __initdata;
184 /* Local APIC timer works in C2 */
185 int local_apic_timer_c2_ok;
186 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
188 int first_system_vector = 0xfe;
191 * Debug level, exported for io_apic.c
193 unsigned int apic_verbosity;
197 /* Have we found an MP table */
198 int smp_found_config;
200 static struct resource lapic_resource = {
201 .name = "Local APIC",
202 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
205 unsigned int lapic_timer_frequency = 0;
207 static void apic_pm_activate(void);
209 static unsigned long apic_phys;
212 * Get the LAPIC version
214 static inline int lapic_get_version(void)
216 return GET_APIC_VERSION(apic_read(APIC_LVR));
220 * Check, if the APIC is integrated or a separate chip
222 static inline int lapic_is_integrated(void)
227 return APIC_INTEGRATED(lapic_get_version());
232 * Check, whether this is a modern or a first generation APIC
234 static int modern_apic(void)
236 /* AMD systems use old APIC versions, so check the CPU */
237 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
238 boot_cpu_data.x86 >= 0xf)
240 return lapic_get_version() >= 0x14;
244 * right after this call apic become NOOP driven
245 * so apic->write/read doesn't do anything
247 static void __init apic_disable(void)
249 pr_info("APIC: switched to apic NOOP\n");
253 void native_apic_wait_icr_idle(void)
255 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
259 u32 native_safe_apic_wait_icr_idle(void)
266 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
269 inc_irq_stat(icr_read_retry_count);
271 } while (timeout++ < 1000);
276 void native_apic_icr_write(u32 low, u32 id)
278 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
279 apic_write(APIC_ICR, low);
282 u64 native_apic_icr_read(void)
286 icr2 = apic_read(APIC_ICR2);
287 icr1 = apic_read(APIC_ICR);
289 return icr1 | ((u64)icr2 << 32);
294 * get_physical_broadcast - Get number of physical broadcast IDs
296 int get_physical_broadcast(void)
298 return modern_apic() ? 0xff : 0xf;
303 * lapic_get_maxlvt - get the maximum number of local vector table entries
305 int lapic_get_maxlvt(void)
309 v = apic_read(APIC_LVR);
311 * - we always have APIC integrated on 64bit mode
312 * - 82489DXs do not report # of LVT entries
314 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
322 #define APIC_DIVISOR 16
323 #define TSC_DIVISOR 32
326 * This function sets up the local APIC timer, with a timeout of
327 * 'clocks' APIC bus clock. During calibration we actually call
328 * this function twice on the boot CPU, once with a bogus timeout
329 * value, second time for real. The other (noncalibrating) CPUs
330 * call this function only once, with the real, calibrated value.
332 * We do reads before writes even if unnecessary, to get around the
333 * P5 APIC double write bug.
335 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
337 unsigned int lvtt_value, tmp_value;
339 lvtt_value = LOCAL_TIMER_VECTOR;
341 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
342 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
343 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
345 if (!lapic_is_integrated())
346 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
349 lvtt_value |= APIC_LVT_MASKED;
351 apic_write(APIC_LVTT, lvtt_value);
353 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
354 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
361 tmp_value = apic_read(APIC_TDCR);
362 apic_write(APIC_TDCR,
363 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
367 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
371 * Setup extended LVT, AMD specific
373 * Software should use the LVT offsets the BIOS provides. The offsets
374 * are determined by the subsystems using it like those for MCE
375 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
376 * are supported. Beginning with family 10h at least 4 offsets are
379 * Since the offsets must be consistent for all cores, we keep track
380 * of the LVT offsets in software and reserve the offset for the same
381 * vector also to be used on other cores. An offset is freed by
382 * setting the entry to APIC_EILVT_MASKED.
384 * If the BIOS is right, there should be no conflicts. Otherwise a
385 * "[Firmware Bug]: ..." error message is generated. However, if
386 * software does not properly determines the offsets, it is not
387 * necessarily a BIOS bug.
390 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
392 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
394 return (old & APIC_EILVT_MASKED)
395 || (new == APIC_EILVT_MASKED)
396 || ((new & ~APIC_EILVT_MASKED) == old);
399 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
401 unsigned int rsvd, vector;
403 if (offset >= APIC_EILVT_NR_MAX)
406 rsvd = atomic_read(&eilvt_offsets[offset]);
408 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
409 if (vector && !eilvt_entry_is_changeable(vector, new))
410 /* may not change if vectors are different */
412 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
413 } while (rsvd != new);
415 rsvd &= ~APIC_EILVT_MASKED;
416 if (rsvd && rsvd != vector)
417 pr_info("LVT offset %d assigned for vector 0x%02x\n",
424 * If mask=1, the LVT entry does not generate interrupts while mask=0
425 * enables the vector. See also the BKDGs. Must be called with
426 * preemption disabled.
429 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
431 unsigned long reg = APIC_EILVTn(offset);
432 unsigned int new, old, reserved;
434 new = (mask << 16) | (msg_type << 8) | vector;
435 old = apic_read(reg);
436 reserved = reserve_eilvt_offset(offset, new);
438 if (reserved != new) {
439 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
440 "vector 0x%x, but the register is already in use for "
441 "vector 0x%x on another cpu\n",
442 smp_processor_id(), reg, offset, new, reserved);
446 if (!eilvt_entry_is_changeable(old, new)) {
447 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
448 "vector 0x%x, but the register is already in use for "
449 "vector 0x%x on this cpu\n",
450 smp_processor_id(), reg, offset, new, old);
454 apic_write(reg, new);
458 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
461 * Program the next event, relative to now
463 static int lapic_next_event(unsigned long delta,
464 struct clock_event_device *evt)
466 apic_write(APIC_TMICT, delta);
470 static int lapic_next_deadline(unsigned long delta,
471 struct clock_event_device *evt)
476 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
481 * Setup the lapic timer in periodic or oneshot mode
483 static void lapic_timer_setup(enum clock_event_mode mode,
484 struct clock_event_device *evt)
489 /* Lapic used as dummy for broadcast ? */
490 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
493 local_irq_save(flags);
496 case CLOCK_EVT_MODE_PERIODIC:
497 case CLOCK_EVT_MODE_ONESHOT:
498 __setup_APIC_LVTT(lapic_timer_frequency,
499 mode != CLOCK_EVT_MODE_PERIODIC, 1);
501 case CLOCK_EVT_MODE_UNUSED:
502 case CLOCK_EVT_MODE_SHUTDOWN:
503 v = apic_read(APIC_LVTT);
504 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
505 apic_write(APIC_LVTT, v);
506 apic_write(APIC_TMICT, 0);
508 case CLOCK_EVT_MODE_RESUME:
509 /* Nothing to do here */
513 local_irq_restore(flags);
517 * Local APIC timer broadcast function
519 static void lapic_timer_broadcast(const struct cpumask *mask)
522 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
528 * The local apic timer can be used for any function which is CPU local.
530 static struct clock_event_device lapic_clockevent = {
532 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
533 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
535 .set_mode = lapic_timer_setup,
536 .set_next_event = lapic_next_event,
537 .broadcast = lapic_timer_broadcast,
541 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
544 * Setup the local APIC timer for this CPU. Copy the initialized values
545 * of the boot CPU and register the clock event in the framework.
547 static void setup_APIC_timer(void)
549 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
551 if (this_cpu_has(X86_FEATURE_ARAT)) {
552 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
553 /* Make LAPIC timer preferrable over percpu HPET */
554 lapic_clockevent.rating = 150;
557 memcpy(levt, &lapic_clockevent, sizeof(*levt));
558 levt->cpumask = cpumask_of(smp_processor_id());
560 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
561 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
562 CLOCK_EVT_FEAT_DUMMY);
563 levt->set_next_event = lapic_next_deadline;
564 clockevents_config_and_register(levt,
565 (tsc_khz / TSC_DIVISOR) * 1000,
568 clockevents_register_device(levt);
572 * In this functions we calibrate APIC bus clocks to the external timer.
574 * We want to do the calibration only once since we want to have local timer
575 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
578 * This was previously done by reading the PIT/HPET and waiting for a wrap
579 * around to find out, that a tick has elapsed. I have a box, where the PIT
580 * readout is broken, so it never gets out of the wait loop again. This was
581 * also reported by others.
583 * Monitoring the jiffies value is inaccurate and the clockevents
584 * infrastructure allows us to do a simple substitution of the interrupt
587 * The calibration routine also uses the pm_timer when possible, as the PIT
588 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
589 * back to normal later in the boot process).
592 #define LAPIC_CAL_LOOPS (HZ/10)
594 static __initdata int lapic_cal_loops = -1;
595 static __initdata long lapic_cal_t1, lapic_cal_t2;
596 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
597 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
598 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
601 * Temporary interrupt handler.
603 static void __init lapic_cal_handler(struct clock_event_device *dev)
605 unsigned long long tsc = 0;
606 long tapic = apic_read(APIC_TMCCT);
607 unsigned long pm = acpi_pm_read_early();
612 switch (lapic_cal_loops++) {
614 lapic_cal_t1 = tapic;
615 lapic_cal_tsc1 = tsc;
617 lapic_cal_j1 = jiffies;
620 case LAPIC_CAL_LOOPS:
621 lapic_cal_t2 = tapic;
622 lapic_cal_tsc2 = tsc;
623 if (pm < lapic_cal_pm1)
624 pm += ACPI_PM_OVRRUN;
626 lapic_cal_j2 = jiffies;
632 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
634 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
635 const long pm_thresh = pm_100ms / 100;
639 #ifndef CONFIG_X86_PM_TIMER
643 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
645 /* Check, if the PM timer is available */
649 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
651 if (deltapm > (pm_100ms - pm_thresh) &&
652 deltapm < (pm_100ms + pm_thresh)) {
653 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
657 res = (((u64)deltapm) * mult) >> 22;
658 do_div(res, 1000000);
659 pr_warning("APIC calibration not consistent "
660 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
662 /* Correct the lapic counter value */
663 res = (((u64)(*delta)) * pm_100ms);
664 do_div(res, deltapm);
665 pr_info("APIC delta adjusted to PM-Timer: "
666 "%lu (%ld)\n", (unsigned long)res, *delta);
669 /* Correct the tsc counter value */
671 res = (((u64)(*deltatsc)) * pm_100ms);
672 do_div(res, deltapm);
673 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
674 "PM-Timer: %lu (%ld)\n",
675 (unsigned long)res, *deltatsc);
676 *deltatsc = (long)res;
682 static int __init calibrate_APIC_clock(void)
684 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
685 void (*real_handler)(struct clock_event_device *dev);
686 unsigned long deltaj;
687 long delta, deltatsc;
688 int pm_referenced = 0;
691 * check if lapic timer has already been calibrated by platform
692 * specific routine, such as tsc calibration code. if so, we just fill
693 * in the clockevent structure and return.
696 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
698 } else if (lapic_timer_frequency) {
699 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
700 lapic_timer_frequency);
701 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
702 TICK_NSEC, lapic_clockevent.shift);
703 lapic_clockevent.max_delta_ns =
704 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
705 lapic_clockevent.min_delta_ns =
706 clockevent_delta2ns(0xF, &lapic_clockevent);
707 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
711 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
712 "calibrating APIC timer ...\n");
716 /* Replace the global interrupt handler */
717 real_handler = global_clock_event->event_handler;
718 global_clock_event->event_handler = lapic_cal_handler;
721 * Setup the APIC counter to maximum. There is no way the lapic
722 * can underflow in the 100ms detection time frame
724 __setup_APIC_LVTT(0xffffffff, 0, 0);
726 /* Let the interrupts run */
729 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
734 /* Restore the real event handler */
735 global_clock_event->event_handler = real_handler;
737 /* Build delta t1-t2 as apic timer counts down */
738 delta = lapic_cal_t1 - lapic_cal_t2;
739 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
741 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
743 /* we trust the PM based calibration if possible */
744 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
747 /* Calculate the scaled math multiplication factor */
748 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
749 lapic_clockevent.shift);
750 lapic_clockevent.max_delta_ns =
751 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
752 lapic_clockevent.min_delta_ns =
753 clockevent_delta2ns(0xF, &lapic_clockevent);
755 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
757 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
758 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
759 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
760 lapic_timer_frequency);
763 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
765 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
766 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
769 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
771 lapic_timer_frequency / (1000000 / HZ),
772 lapic_timer_frequency % (1000000 / HZ));
775 * Do a sanity check on the APIC calibration result
777 if (lapic_timer_frequency < (1000000 / HZ)) {
779 pr_warning("APIC frequency too slow, disabling apic timer\n");
783 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
786 * PM timer calibration failed or not turned on
787 * so lets try APIC timer based calibration
789 if (!pm_referenced) {
790 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
793 * Setup the apic timer manually
795 levt->event_handler = lapic_cal_handler;
796 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
797 lapic_cal_loops = -1;
799 /* Let the interrupts run */
802 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
805 /* Stop the lapic timer */
806 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
809 deltaj = lapic_cal_j2 - lapic_cal_j1;
810 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
812 /* Check, if the jiffies result is consistent */
813 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
814 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
816 levt->features |= CLOCK_EVT_FEAT_DUMMY;
820 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
821 pr_warning("APIC timer disabled due to verification failure\n");
829 * Setup the boot APIC
831 * Calibrate and verify the result.
833 void __init setup_boot_APIC_clock(void)
836 * The local apic timer can be disabled via the kernel
837 * commandline or from the CPU detection code. Register the lapic
838 * timer as a dummy clock event source on SMP systems, so the
839 * broadcast mechanism is used. On UP systems simply ignore it.
841 if (disable_apic_timer) {
842 pr_info("Disabling APIC timer\n");
843 /* No broadcast on UP ! */
844 if (num_possible_cpus() > 1) {
845 lapic_clockevent.mult = 1;
851 if (calibrate_APIC_clock()) {
852 /* No broadcast on UP ! */
853 if (num_possible_cpus() > 1)
859 * If nmi_watchdog is set to IO_APIC, we need the
860 * PIT/HPET going. Otherwise register lapic as a dummy
863 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
865 /* Setup the lapic or request the broadcast */
869 void setup_secondary_APIC_clock(void)
875 * The guts of the apic timer interrupt
877 static void local_apic_timer_interrupt(void)
879 int cpu = smp_processor_id();
880 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
883 * Normally we should not be here till LAPIC has been initialized but
884 * in some cases like kdump, its possible that there is a pending LAPIC
885 * timer interrupt from previous kernel's context and is delivered in
886 * new kernel the moment interrupts are enabled.
888 * Interrupts are enabled early and LAPIC is setup much later, hence
889 * its possible that when we get here evt->event_handler is NULL.
890 * Check for event_handler being NULL and discard the interrupt as
893 if (!evt->event_handler) {
894 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
896 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
901 * the NMI deadlock-detector uses this.
903 inc_irq_stat(apic_timer_irqs);
905 evt->event_handler(evt);
909 * Local APIC timer interrupt. This is the most natural way for doing
910 * local interrupts, but local timer interrupts can be emulated by
911 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
913 * [ if a single-CPU system runs an SMP kernel then we call the local
914 * interrupt as well. Thus we cannot inline the local irq ... ]
916 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
918 struct pt_regs *old_regs = set_irq_regs(regs);
921 * NOTE! We'd better ACK the irq immediately,
922 * because timer handling can be slow.
924 * update_process_times() expects us to have done irq_enter().
925 * Besides, if we don't timer interrupts ignore the global
926 * interrupt lock, which is the WrongThing (tm) to do.
929 local_apic_timer_interrupt();
932 set_irq_regs(old_regs);
935 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
937 struct pt_regs *old_regs = set_irq_regs(regs);
940 * NOTE! We'd better ACK the irq immediately,
941 * because timer handling can be slow.
943 * update_process_times() expects us to have done irq_enter().
944 * Besides, if we don't timer interrupts ignore the global
945 * interrupt lock, which is the WrongThing (tm) to do.
948 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
949 local_apic_timer_interrupt();
950 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
953 set_irq_regs(old_regs);
956 int setup_profiling_timer(unsigned int multiplier)
962 * Local APIC start and shutdown
966 * clear_local_APIC - shutdown the local APIC
968 * This is called, when a CPU is disabled and before rebooting, so the state of
969 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
970 * leftovers during boot.
972 void clear_local_APIC(void)
977 /* APIC hasn't been mapped yet */
978 if (!x2apic_mode && !apic_phys)
981 maxlvt = lapic_get_maxlvt();
983 * Masking an LVT entry can trigger a local APIC error
984 * if the vector is zero. Mask LVTERR first to prevent this.
987 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
988 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
991 * Careful: we have to set masks only first to deassert
992 * any level-triggered sources.
994 v = apic_read(APIC_LVTT);
995 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
996 v = apic_read(APIC_LVT0);
997 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
998 v = apic_read(APIC_LVT1);
999 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1001 v = apic_read(APIC_LVTPC);
1002 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1005 /* lets not touch this if we didn't frob it */
1006 #ifdef CONFIG_X86_THERMAL_VECTOR
1008 v = apic_read(APIC_LVTTHMR);
1009 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1012 #ifdef CONFIG_X86_MCE_INTEL
1014 v = apic_read(APIC_LVTCMCI);
1015 if (!(v & APIC_LVT_MASKED))
1016 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1021 * Clean APIC state for other OSs:
1023 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1024 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1025 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1027 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1029 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1031 /* Integrated APIC (!82489DX) ? */
1032 if (lapic_is_integrated()) {
1034 /* Clear ESR due to Pentium errata 3AP and 11AP */
1035 apic_write(APIC_ESR, 0);
1036 apic_read(APIC_ESR);
1041 * disable_local_APIC - clear and disable the local APIC
1043 void disable_local_APIC(void)
1047 /* APIC hasn't been mapped yet */
1048 if (!x2apic_mode && !apic_phys)
1054 * Disable APIC (implies clearing of registers
1057 value = apic_read(APIC_SPIV);
1058 value &= ~APIC_SPIV_APIC_ENABLED;
1059 apic_write(APIC_SPIV, value);
1061 #ifdef CONFIG_X86_32
1063 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1064 * restore the disabled state.
1066 if (enabled_via_apicbase) {
1069 rdmsr(MSR_IA32_APICBASE, l, h);
1070 l &= ~MSR_IA32_APICBASE_ENABLE;
1071 wrmsr(MSR_IA32_APICBASE, l, h);
1077 * If Linux enabled the LAPIC against the BIOS default disable it down before
1078 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1079 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1080 * for the case where Linux didn't enable the LAPIC.
1082 void lapic_shutdown(void)
1084 unsigned long flags;
1086 if (!cpu_has_apic && !apic_from_smp_config())
1089 local_irq_save(flags);
1091 #ifdef CONFIG_X86_32
1092 if (!enabled_via_apicbase)
1096 disable_local_APIC();
1099 local_irq_restore(flags);
1103 * This is to verify that we're looking at a real local APIC.
1104 * Check these against your board if the CPUs aren't getting
1105 * started for no apparent reason.
1107 int __init verify_local_APIC(void)
1109 unsigned int reg0, reg1;
1112 * The version register is read-only in a real APIC.
1114 reg0 = apic_read(APIC_LVR);
1115 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1116 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1117 reg1 = apic_read(APIC_LVR);
1118 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1121 * The two version reads above should print the same
1122 * numbers. If the second one is different, then we
1123 * poke at a non-APIC.
1129 * Check if the version looks reasonably.
1131 reg1 = GET_APIC_VERSION(reg0);
1132 if (reg1 == 0x00 || reg1 == 0xff)
1134 reg1 = lapic_get_maxlvt();
1135 if (reg1 < 0x02 || reg1 == 0xff)
1139 * The ID register is read/write in a real APIC.
1141 reg0 = apic_read(APIC_ID);
1142 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1143 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1144 reg1 = apic_read(APIC_ID);
1145 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1146 apic_write(APIC_ID, reg0);
1147 if (reg1 != (reg0 ^ apic->apic_id_mask))
1151 * The next two are just to see if we have sane values.
1152 * They're only really relevant if we're in Virtual Wire
1153 * compatibility mode, but most boxes are anymore.
1155 reg0 = apic_read(APIC_LVT0);
1156 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1157 reg1 = apic_read(APIC_LVT1);
1158 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1164 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1166 void __init sync_Arb_IDs(void)
1169 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1172 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1178 apic_wait_icr_idle();
1180 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1181 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1182 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1186 * An initial setup of the virtual wire mode.
1188 void __init init_bsp_APIC(void)
1193 * Don't do the setup now if we have a SMP BIOS as the
1194 * through-I/O-APIC virtual wire mode might be active.
1196 if (smp_found_config || !cpu_has_apic)
1200 * Do not trust the local APIC being empty at bootup.
1207 value = apic_read(APIC_SPIV);
1208 value &= ~APIC_VECTOR_MASK;
1209 value |= APIC_SPIV_APIC_ENABLED;
1211 #ifdef CONFIG_X86_32
1212 /* This bit is reserved on P4/Xeon and should be cleared */
1213 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1214 (boot_cpu_data.x86 == 15))
1215 value &= ~APIC_SPIV_FOCUS_DISABLED;
1218 value |= APIC_SPIV_FOCUS_DISABLED;
1219 value |= SPURIOUS_APIC_VECTOR;
1220 apic_write(APIC_SPIV, value);
1223 * Set up the virtual wire mode.
1225 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1226 value = APIC_DM_NMI;
1227 if (!lapic_is_integrated()) /* 82489DX */
1228 value |= APIC_LVT_LEVEL_TRIGGER;
1229 apic_write(APIC_LVT1, value);
1232 static void lapic_setup_esr(void)
1234 unsigned int oldvalue, value, maxlvt;
1236 if (!lapic_is_integrated()) {
1237 pr_info("No ESR for 82489DX.\n");
1241 if (apic->disable_esr) {
1243 * Something untraceable is creating bad interrupts on
1244 * secondary quads ... for the moment, just leave the
1245 * ESR disabled - we can't do anything useful with the
1246 * errors anyway - mbligh
1248 pr_info("Leaving ESR disabled.\n");
1252 maxlvt = lapic_get_maxlvt();
1253 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1254 apic_write(APIC_ESR, 0);
1255 oldvalue = apic_read(APIC_ESR);
1257 /* enables sending errors */
1258 value = ERROR_APIC_VECTOR;
1259 apic_write(APIC_LVTERR, value);
1262 * spec says clear errors after enabling vector.
1265 apic_write(APIC_ESR, 0);
1266 value = apic_read(APIC_ESR);
1267 if (value != oldvalue)
1268 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1269 "vector: 0x%08x after: 0x%08x\n",
1274 * setup_local_APIC - setup the local APIC
1276 * Used to setup local APIC while initializing BSP or bringin up APs.
1277 * Always called with preemption disabled.
1279 void setup_local_APIC(void)
1281 int cpu = smp_processor_id();
1282 unsigned int value, queued;
1283 int i, j, acked = 0;
1284 unsigned long long tsc = 0, ntsc;
1285 long long max_loops = cpu_khz;
1291 disable_ioapic_support();
1295 #ifdef CONFIG_X86_32
1296 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1297 if (lapic_is_integrated() && apic->disable_esr) {
1298 apic_write(APIC_ESR, 0);
1299 apic_write(APIC_ESR, 0);
1300 apic_write(APIC_ESR, 0);
1301 apic_write(APIC_ESR, 0);
1304 perf_events_lapic_init();
1307 * Double-check whether this APIC is really registered.
1308 * This is meaningless in clustered apic mode, so we skip it.
1310 BUG_ON(!apic->apic_id_registered());
1313 * Intel recommends to set DFR, LDR and TPR before enabling
1314 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1315 * document number 292116). So here it goes...
1317 apic->init_apic_ldr();
1319 #ifdef CONFIG_X86_32
1321 * APIC LDR is initialized. If logical_apicid mapping was
1322 * initialized during get_smp_config(), make sure it matches the
1325 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1326 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1327 /* always use the value from LDR */
1328 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1329 logical_smp_processor_id();
1332 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1333 * node mapping during NUMA init. Now that logical apicid is
1334 * guaranteed to be known, give it another chance. This is already
1335 * a bit too late - percpu allocation has already happened without
1336 * proper NUMA affinity.
1338 if (apic->x86_32_numa_cpu_node)
1339 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1340 apic->x86_32_numa_cpu_node(cpu));
1344 * Set Task Priority to 'accept all'. We never change this
1347 value = apic_read(APIC_TASKPRI);
1348 value &= ~APIC_TPRI_MASK;
1349 apic_write(APIC_TASKPRI, value);
1352 * After a crash, we no longer service the interrupts and a pending
1353 * interrupt from previous kernel might still have ISR bit set.
1355 * Most probably by now CPU has serviced that pending interrupt and
1356 * it might not have done the ack_APIC_irq() because it thought,
1357 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1358 * does not clear the ISR bit and cpu thinks it has already serivced
1359 * the interrupt. Hence a vector might get locked. It was noticed
1360 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1364 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1365 queued |= apic_read(APIC_IRR + i*0x10);
1367 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1368 value = apic_read(APIC_ISR + i*0x10);
1369 for (j = 31; j >= 0; j--) {
1370 if (value & (1<<j)) {
1377 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1384 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1388 } while (queued && max_loops > 0);
1389 WARN_ON(max_loops <= 0);
1392 * Now that we are all set up, enable the APIC
1394 value = apic_read(APIC_SPIV);
1395 value &= ~APIC_VECTOR_MASK;
1399 value |= APIC_SPIV_APIC_ENABLED;
1401 #ifdef CONFIG_X86_32
1403 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1404 * certain networking cards. If high frequency interrupts are
1405 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1406 * entry is masked/unmasked at a high rate as well then sooner or
1407 * later IOAPIC line gets 'stuck', no more interrupts are received
1408 * from the device. If focus CPU is disabled then the hang goes
1411 * [ This bug can be reproduced easily with a level-triggered
1412 * PCI Ne2000 networking cards and PII/PIII processors, dual
1416 * Actually disabling the focus CPU check just makes the hang less
1417 * frequent as it makes the interrupt distributon model be more
1418 * like LRU than MRU (the short-term load is more even across CPUs).
1419 * See also the comment in end_level_ioapic_irq(). --macro
1423 * - enable focus processor (bit==0)
1424 * - 64bit mode always use processor focus
1425 * so no need to set it
1427 value &= ~APIC_SPIV_FOCUS_DISABLED;
1431 * Set spurious IRQ vector
1433 value |= SPURIOUS_APIC_VECTOR;
1434 apic_write(APIC_SPIV, value);
1437 * Set up LVT0, LVT1:
1439 * set up through-local-APIC on the BP's LINT0. This is not
1440 * strictly necessary in pure symmetric-IO mode, but sometimes
1441 * we delegate interrupts to the 8259A.
1444 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1446 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1447 if (!cpu && (pic_mode || !value)) {
1448 value = APIC_DM_EXTINT;
1449 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1451 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1452 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1454 apic_write(APIC_LVT0, value);
1457 * only the BP should see the LINT1 NMI signal, obviously.
1460 value = APIC_DM_NMI;
1462 value = APIC_DM_NMI | APIC_LVT_MASKED;
1463 if (!lapic_is_integrated()) /* 82489DX */
1464 value |= APIC_LVT_LEVEL_TRIGGER;
1465 apic_write(APIC_LVT1, value);
1467 #ifdef CONFIG_X86_MCE_INTEL
1468 /* Recheck CMCI information after local APIC is up on CPU #0 */
1474 void end_local_APIC_setup(void)
1478 #ifdef CONFIG_X86_32
1481 /* Disable the local apic timer */
1482 value = apic_read(APIC_LVTT);
1483 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1484 apic_write(APIC_LVTT, value);
1491 void __init bsp_end_local_APIC_setup(void)
1493 end_local_APIC_setup();
1496 * Now that local APIC setup is completed for BP, configure the fault
1497 * handling for interrupt remapping.
1499 irq_remap_enable_fault_handling();
1503 #ifdef CONFIG_X86_X2APIC
1505 * Need to disable xapic and x2apic at the same time and then enable xapic mode
1507 static inline void __disable_x2apic(u64 msr)
1509 wrmsrl(MSR_IA32_APICBASE,
1510 msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1511 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1514 static __init void disable_x2apic(void)
1518 if (!cpu_has_x2apic)
1521 rdmsrl(MSR_IA32_APICBASE, msr);
1522 if (msr & X2APIC_ENABLE) {
1523 u32 x2apic_id = read_apic_id();
1525 if (x2apic_id >= 255)
1526 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1528 pr_info("Disabling x2apic\n");
1529 __disable_x2apic(msr);
1532 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC);
1533 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1536 x2apic_disabled = 1;
1539 register_lapic_address(mp_lapic_addr);
1543 void check_x2apic(void)
1545 if (x2apic_enabled()) {
1546 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1547 x2apic_preenabled = x2apic_mode = 1;
1551 void enable_x2apic(void)
1555 rdmsrl(MSR_IA32_APICBASE, msr);
1556 if (x2apic_disabled) {
1557 __disable_x2apic(msr);
1564 if (!(msr & X2APIC_ENABLE)) {
1565 printk_once(KERN_INFO "Enabling x2apic\n");
1566 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1569 #endif /* CONFIG_X86_X2APIC */
1571 int __init enable_IR(void)
1573 #ifdef CONFIG_IRQ_REMAP
1574 if (!irq_remapping_supported()) {
1575 pr_debug("intr-remapping not supported\n");
1579 if (!x2apic_preenabled && skip_ioapic_setup) {
1580 pr_info("Skipped enabling intr-remap because of skipping "
1585 return irq_remapping_enable();
1590 void __init enable_IR_x2apic(void)
1592 unsigned long flags;
1593 int ret, x2apic_enabled = 0;
1594 int hardware_init_ret;
1596 /* Make sure irq_remap_ops are initialized */
1597 setup_irq_remapping_ops();
1599 hardware_init_ret = irq_remapping_prepare();
1600 if (hardware_init_ret && !x2apic_supported())
1603 ret = save_ioapic_entries();
1605 pr_info("Saving IO-APIC state failed: %d\n", ret);
1609 local_irq_save(flags);
1610 legacy_pic->mask_all();
1611 mask_ioapic_entries();
1613 if (x2apic_preenabled && nox2apic)
1616 if (hardware_init_ret)
1621 if (!x2apic_supported())
1625 /* IR is required if there is APIC ID > 255 even when running
1628 if (max_physical_apicid > 255 ||
1629 !hypervisor_x2apic_available()) {
1630 if (x2apic_preenabled)
1635 * without IR all CPUs can be addressed by IOAPIC/MSI
1636 * only in physical mode
1638 x2apic_force_phys();
1641 if (ret == IRQ_REMAP_XAPIC_MODE) {
1642 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1648 if (x2apic_supported() && !x2apic_mode) {
1651 pr_info("Enabled x2apic\n");
1655 if (ret < 0) /* IR enabling failed */
1656 restore_ioapic_entries();
1657 legacy_pic->restore_mask();
1658 local_irq_restore(flags);
1661 #ifdef CONFIG_X86_64
1663 * Detect and enable local APICs on non-SMP boards.
1664 * Original code written by Keir Fraser.
1665 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1666 * not correctly set up (usually the APIC timer won't work etc.)
1668 static int __init detect_init_APIC(void)
1670 if (!cpu_has_apic) {
1671 pr_info("No local APIC present\n");
1675 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1680 static int __init apic_verify(void)
1685 * The APIC feature bit should now be enabled
1688 features = cpuid_edx(1);
1689 if (!(features & (1 << X86_FEATURE_APIC))) {
1690 pr_warning("Could not enable APIC!\n");
1693 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1694 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1696 /* The BIOS may have set up the APIC at some other address */
1697 if (boot_cpu_data.x86 >= 6) {
1698 rdmsr(MSR_IA32_APICBASE, l, h);
1699 if (l & MSR_IA32_APICBASE_ENABLE)
1700 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1703 pr_info("Found and enabled local APIC!\n");
1707 int __init apic_force_enable(unsigned long addr)
1715 * Some BIOSes disable the local APIC in the APIC_BASE
1716 * MSR. This can only be done in software for Intel P6 or later
1717 * and AMD K7 (Model > 1) or later.
1719 if (boot_cpu_data.x86 >= 6) {
1720 rdmsr(MSR_IA32_APICBASE, l, h);
1721 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1722 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1723 l &= ~MSR_IA32_APICBASE_BASE;
1724 l |= MSR_IA32_APICBASE_ENABLE | addr;
1725 wrmsr(MSR_IA32_APICBASE, l, h);
1726 enabled_via_apicbase = 1;
1729 return apic_verify();
1733 * Detect and initialize APIC
1735 static int __init detect_init_APIC(void)
1737 /* Disabled by kernel option? */
1741 switch (boot_cpu_data.x86_vendor) {
1742 case X86_VENDOR_AMD:
1743 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1744 (boot_cpu_data.x86 >= 15))
1747 case X86_VENDOR_INTEL:
1748 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1749 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1756 if (!cpu_has_apic) {
1758 * Over-ride BIOS and try to enable the local APIC only if
1759 * "lapic" specified.
1761 if (!force_enable_local_apic) {
1762 pr_info("Local APIC disabled by BIOS -- "
1763 "you can enable it with \"lapic\"\n");
1766 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1778 pr_info("No local APIC present or hardware disabled\n");
1784 * init_apic_mappings - initialize APIC mappings
1786 void __init init_apic_mappings(void)
1788 unsigned int new_apicid;
1791 boot_cpu_physical_apicid = read_apic_id();
1795 /* If no local APIC can be found return early */
1796 if (!smp_found_config && detect_init_APIC()) {
1797 /* lets NOP'ify apic operations */
1798 pr_info("APIC: disable apic facility\n");
1801 apic_phys = mp_lapic_addr;
1804 * acpi lapic path already maps that address in
1805 * acpi_register_lapic_address()
1807 if (!acpi_lapic && !smp_found_config)
1808 register_lapic_address(apic_phys);
1812 * Fetch the APIC ID of the BSP in case we have a
1813 * default configuration (or the MP table is broken).
1815 new_apicid = read_apic_id();
1816 if (boot_cpu_physical_apicid != new_apicid) {
1817 boot_cpu_physical_apicid = new_apicid;
1819 * yeah -- we lie about apic_version
1820 * in case if apic was disabled via boot option
1821 * but it's not a problem for SMP compiled kernel
1822 * since smp_sanity_check is prepared for such a case
1823 * and disable smp mode
1825 apic_version[new_apicid] =
1826 GET_APIC_VERSION(apic_read(APIC_LVR));
1830 void __init register_lapic_address(unsigned long address)
1832 mp_lapic_addr = address;
1835 set_fixmap_nocache(FIX_APIC_BASE, address);
1836 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1837 APIC_BASE, mp_lapic_addr);
1839 if (boot_cpu_physical_apicid == -1U) {
1840 boot_cpu_physical_apicid = read_apic_id();
1841 apic_version[boot_cpu_physical_apicid] =
1842 GET_APIC_VERSION(apic_read(APIC_LVR));
1847 * This initializes the IO-APIC and APIC hardware if this is
1850 int apic_version[MAX_LOCAL_APIC];
1852 int __init APIC_init_uniprocessor(void)
1855 pr_info("Apic disabled\n");
1858 #ifdef CONFIG_X86_64
1859 if (!cpu_has_apic) {
1861 pr_info("Apic disabled by BIOS\n");
1865 if (!smp_found_config && !cpu_has_apic)
1869 * Complain if the BIOS pretends there is one.
1871 if (!cpu_has_apic &&
1872 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1873 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1874 boot_cpu_physical_apicid);
1879 default_setup_apic_routing();
1881 verify_local_APIC();
1884 #ifdef CONFIG_X86_64
1885 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1888 * Hack: In case of kdump, after a crash, kernel might be booting
1889 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1890 * might be zero if read from MP tables. Get it from LAPIC.
1892 # ifdef CONFIG_CRASH_DUMP
1893 boot_cpu_physical_apicid = read_apic_id();
1896 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1899 #ifdef CONFIG_X86_IO_APIC
1901 * Now enable IO-APICs, actually call clear_IO_APIC
1902 * We need clear_IO_APIC before enabling error vector
1904 if (!skip_ioapic_setup && nr_ioapics)
1908 bsp_end_local_APIC_setup();
1910 #ifdef CONFIG_X86_IO_APIC
1911 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1918 x86_init.timers.setup_percpu_clockev();
1923 * Local APIC interrupts
1927 * This interrupt should _never_ happen with our APIC/SMP architecture
1929 static inline void __smp_spurious_interrupt(void)
1934 * Check if this really is a spurious interrupt and ACK it
1935 * if it is a vectored one. Just in case...
1936 * Spurious interrupts should not be ACKed.
1938 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1939 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1942 inc_irq_stat(irq_spurious_count);
1944 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1945 pr_info("spurious APIC interrupt on CPU#%d, "
1946 "should never happen.\n", smp_processor_id());
1949 __visible void smp_spurious_interrupt(struct pt_regs *regs)
1952 __smp_spurious_interrupt();
1956 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1959 trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR);
1960 __smp_spurious_interrupt();
1961 trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR);
1966 * This interrupt should never happen with our APIC/SMP architecture
1968 static inline void __smp_error_interrupt(struct pt_regs *regs)
1972 static const char * const error_interrupt_reason[] = {
1973 "Send CS error", /* APIC Error Bit 0 */
1974 "Receive CS error", /* APIC Error Bit 1 */
1975 "Send accept error", /* APIC Error Bit 2 */
1976 "Receive accept error", /* APIC Error Bit 3 */
1977 "Redirectable IPI", /* APIC Error Bit 4 */
1978 "Send illegal vector", /* APIC Error Bit 5 */
1979 "Received illegal vector", /* APIC Error Bit 6 */
1980 "Illegal register address", /* APIC Error Bit 7 */
1983 /* First tickle the hardware, only then report what went on. -- REW */
1984 v0 = apic_read(APIC_ESR);
1985 apic_write(APIC_ESR, 0);
1986 v1 = apic_read(APIC_ESR);
1988 atomic_inc(&irq_err_count);
1990 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1991 smp_processor_id(), v0 , v1);
1996 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2001 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2005 __visible void smp_error_interrupt(struct pt_regs *regs)
2008 __smp_error_interrupt(regs);
2012 __visible void smp_trace_error_interrupt(struct pt_regs *regs)
2015 trace_error_apic_entry(ERROR_APIC_VECTOR);
2016 __smp_error_interrupt(regs);
2017 trace_error_apic_exit(ERROR_APIC_VECTOR);
2022 * connect_bsp_APIC - attach the APIC to the interrupt system
2024 void __init connect_bsp_APIC(void)
2026 #ifdef CONFIG_X86_32
2029 * Do not trust the local APIC being empty at bootup.
2033 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2034 * local APIC to INT and NMI lines.
2036 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2037 "enabling APIC mode.\n");
2041 if (apic->enable_apic_mode)
2042 apic->enable_apic_mode();
2046 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2047 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2049 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2052 void disconnect_bsp_APIC(int virt_wire_setup)
2056 #ifdef CONFIG_X86_32
2059 * Put the board back into PIC mode (has an effect only on
2060 * certain older boards). Note that APIC interrupts, including
2061 * IPIs, won't work beyond this point! The only exception are
2064 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2065 "entering PIC mode.\n");
2071 /* Go back to Virtual Wire compatibility mode */
2073 /* For the spurious interrupt use vector F, and enable it */
2074 value = apic_read(APIC_SPIV);
2075 value &= ~APIC_VECTOR_MASK;
2076 value |= APIC_SPIV_APIC_ENABLED;
2078 apic_write(APIC_SPIV, value);
2080 if (!virt_wire_setup) {
2082 * For LVT0 make it edge triggered, active high,
2083 * external and enabled
2085 value = apic_read(APIC_LVT0);
2086 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2087 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2088 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2089 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2090 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2091 apic_write(APIC_LVT0, value);
2094 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2098 * For LVT1 make it edge triggered, active high,
2101 value = apic_read(APIC_LVT1);
2102 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2103 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2104 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2105 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2106 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2107 apic_write(APIC_LVT1, value);
2110 int generic_processor_info(int apicid, int version)
2112 int cpu, max = nr_cpu_ids;
2113 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2114 phys_cpu_present_map);
2117 * If boot cpu has not been detected yet, then only allow upto
2118 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2120 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2121 apicid != boot_cpu_physical_apicid) {
2122 int thiscpu = max + disabled_cpus - 1;
2125 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2126 " reached. Keeping one slot for boot cpu."
2127 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2133 if (num_processors >= nr_cpu_ids) {
2134 int thiscpu = max + disabled_cpus;
2137 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2138 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2145 if (apicid == boot_cpu_physical_apicid) {
2147 * x86_bios_cpu_apicid is required to have processors listed
2148 * in same order as logical cpu numbers. Hence the first
2149 * entry is BSP, and so on.
2150 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2155 cpu = cpumask_next_zero(-1, cpu_present_mask);
2160 if (version == 0x0) {
2161 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2165 apic_version[apicid] = version;
2167 if (version != apic_version[boot_cpu_physical_apicid]) {
2168 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2169 apic_version[boot_cpu_physical_apicid], cpu, version);
2172 physid_set(apicid, phys_cpu_present_map);
2173 if (apicid > max_physical_apicid)
2174 max_physical_apicid = apicid;
2176 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2177 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2178 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2180 #ifdef CONFIG_X86_32
2181 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2182 apic->x86_32_early_logical_apicid(cpu);
2184 set_cpu_possible(cpu, true);
2185 set_cpu_present(cpu, true);
2190 int hard_smp_processor_id(void)
2192 return read_apic_id();
2195 void default_init_apic_ldr(void)
2199 apic_write(APIC_DFR, APIC_DFR_VALUE);
2200 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2201 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2202 apic_write(APIC_LDR, val);
2205 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2206 const struct cpumask *andmask,
2207 unsigned int *apicid)
2211 for_each_cpu_and(cpu, cpumask, andmask) {
2212 if (cpumask_test_cpu(cpu, cpu_online_mask))
2216 if (likely(cpu < nr_cpu_ids)) {
2217 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2225 * Override the generic EOI implementation with an optimized version.
2226 * Only called during early boot when only one CPU is active and with
2227 * interrupts disabled, so we know this does not race with actual APIC driver
2230 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2234 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2235 /* Should happen once for each apic */
2236 WARN_ON((*drv)->eoi_write == eoi_write);
2237 (*drv)->eoi_write = eoi_write;
2248 * 'active' is true if the local APIC was enabled by us and
2249 * not the BIOS; this signifies that we are also responsible
2250 * for disabling it before entering apm/acpi suspend
2253 /* r/w apic fields */
2254 unsigned int apic_id;
2255 unsigned int apic_taskpri;
2256 unsigned int apic_ldr;
2257 unsigned int apic_dfr;
2258 unsigned int apic_spiv;
2259 unsigned int apic_lvtt;
2260 unsigned int apic_lvtpc;
2261 unsigned int apic_lvt0;
2262 unsigned int apic_lvt1;
2263 unsigned int apic_lvterr;
2264 unsigned int apic_tmict;
2265 unsigned int apic_tdcr;
2266 unsigned int apic_thmr;
2269 static int lapic_suspend(void)
2271 unsigned long flags;
2274 if (!apic_pm_state.active)
2277 maxlvt = lapic_get_maxlvt();
2279 apic_pm_state.apic_id = apic_read(APIC_ID);
2280 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2281 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2282 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2283 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2284 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2286 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2287 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2288 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2289 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2290 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2291 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2292 #ifdef CONFIG_X86_THERMAL_VECTOR
2294 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2297 local_irq_save(flags);
2298 disable_local_APIC();
2300 irq_remapping_disable();
2302 local_irq_restore(flags);
2306 static void lapic_resume(void)
2309 unsigned long flags;
2312 if (!apic_pm_state.active)
2315 local_irq_save(flags);
2318 * IO-APIC and PIC have their own resume routines.
2319 * We just mask them here to make sure the interrupt
2320 * subsystem is completely quiet while we enable x2apic
2321 * and interrupt-remapping.
2323 mask_ioapic_entries();
2324 legacy_pic->mask_all();
2330 * Make sure the APICBASE points to the right address
2332 * FIXME! This will be wrong if we ever support suspend on
2333 * SMP! We'll need to do this as part of the CPU restore!
2335 if (boot_cpu_data.x86 >= 6) {
2336 rdmsr(MSR_IA32_APICBASE, l, h);
2337 l &= ~MSR_IA32_APICBASE_BASE;
2338 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2339 wrmsr(MSR_IA32_APICBASE, l, h);
2343 maxlvt = lapic_get_maxlvt();
2344 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2345 apic_write(APIC_ID, apic_pm_state.apic_id);
2346 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2347 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2348 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2349 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2350 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2351 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2352 #if defined(CONFIG_X86_MCE_INTEL)
2354 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2357 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2358 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2359 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2360 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2361 apic_write(APIC_ESR, 0);
2362 apic_read(APIC_ESR);
2363 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2364 apic_write(APIC_ESR, 0);
2365 apic_read(APIC_ESR);
2367 irq_remapping_reenable(x2apic_mode);
2369 local_irq_restore(flags);
2373 * This device has no shutdown method - fully functioning local APICs
2374 * are needed on every CPU up until machine_halt/restart/poweroff.
2377 static struct syscore_ops lapic_syscore_ops = {
2378 .resume = lapic_resume,
2379 .suspend = lapic_suspend,
2382 static void apic_pm_activate(void)
2384 apic_pm_state.active = 1;
2387 static int __init init_lapic_sysfs(void)
2389 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2391 register_syscore_ops(&lapic_syscore_ops);
2396 /* local apic needs to resume before other devices access its registers. */
2397 core_initcall(init_lapic_sysfs);
2399 #else /* CONFIG_PM */
2401 static void apic_pm_activate(void) { }
2403 #endif /* CONFIG_PM */
2405 #ifdef CONFIG_X86_64
2407 static int apic_cluster_num(void)
2409 int i, clusters, zeros;
2411 u16 *bios_cpu_apicid;
2412 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2414 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2415 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2417 for (i = 0; i < nr_cpu_ids; i++) {
2418 /* are we being called early in kernel startup? */
2419 if (bios_cpu_apicid) {
2420 id = bios_cpu_apicid[i];
2421 } else if (i < nr_cpu_ids) {
2423 id = per_cpu(x86_bios_cpu_apicid, i);
2429 if (id != BAD_APICID)
2430 __set_bit(APIC_CLUSTERID(id), clustermap);
2433 /* Problem: Partially populated chassis may not have CPUs in some of
2434 * the APIC clusters they have been allocated. Only present CPUs have
2435 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2436 * Since clusters are allocated sequentially, count zeros only if
2437 * they are bounded by ones.
2441 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2442 if (test_bit(i, clustermap)) {
2443 clusters += 1 + zeros;
2452 static int multi_checked;
2455 static int set_multi(const struct dmi_system_id *d)
2459 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2464 static const struct dmi_system_id multi_dmi_table[] = {
2466 .callback = set_multi,
2467 .ident = "IBM System Summit2",
2469 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2470 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2476 static void dmi_check_multi(void)
2481 dmi_check_system(multi_dmi_table);
2486 * apic_is_clustered_box() -- Check if we can expect good TSC
2488 * Thus far, the major user of this is IBM's Summit2 series:
2489 * Clustered boxes may have unsynced TSC problems if they are
2491 * Use DMI to check them
2493 int apic_is_clustered_box(void)
2503 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2504 * not guaranteed to be synced between boards
2506 if (apic_cluster_num() > 1)
2514 * APIC command line parameters
2516 static int __init setup_disableapic(char *arg)
2519 setup_clear_cpu_cap(X86_FEATURE_APIC);
2522 early_param("disableapic", setup_disableapic);
2524 /* same as disableapic, for compatibility */
2525 static int __init setup_nolapic(char *arg)
2527 return setup_disableapic(arg);
2529 early_param("nolapic", setup_nolapic);
2531 static int __init parse_lapic_timer_c2_ok(char *arg)
2533 local_apic_timer_c2_ok = 1;
2536 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2538 static int __init parse_disable_apic_timer(char *arg)
2540 disable_apic_timer = 1;
2543 early_param("noapictimer", parse_disable_apic_timer);
2545 static int __init parse_nolapic_timer(char *arg)
2547 disable_apic_timer = 1;
2550 early_param("nolapic_timer", parse_nolapic_timer);
2552 static int __init apic_set_verbosity(char *arg)
2555 #ifdef CONFIG_X86_64
2556 skip_ioapic_setup = 0;
2562 if (strcmp("debug", arg) == 0)
2563 apic_verbosity = APIC_DEBUG;
2564 else if (strcmp("verbose", arg) == 0)
2565 apic_verbosity = APIC_VERBOSE;
2567 pr_warning("APIC Verbosity level %s not recognised"
2568 " use apic=verbose or apic=debug\n", arg);
2574 early_param("apic", apic_set_verbosity);
2576 static int __init lapic_insert_resource(void)
2581 /* Put local APIC into the resource map. */
2582 lapic_resource.start = apic_phys;
2583 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2584 insert_resource(&iomem_resource, &lapic_resource);
2590 * need call insert after e820_reserve_resources()
2591 * that is using request_resource
2593 late_initcall(lapic_insert_resource);