2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
57 #include <asm/hypervisor.h>
59 unsigned int num_processors;
61 unsigned disabled_cpus;
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_physical_apicid = -1U;
65 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
68 * The highest APIC ID seen during enumeration.
70 static unsigned int max_physical_apicid;
73 * Bitmask of physically existing CPUs:
75 physid_mask_t phys_cpu_present_map;
78 * Processor to be disabled specified by kernel parameter
79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
80 * avoid undefined behaviour caused by sending INIT from AP to BSP.
82 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
85 * Map cpu index to physical APIC ID
87 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
88 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
89 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
90 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
95 * On x86_32, the mapping between cpu and logical apicid may vary
96 * depending on apic in use. The following early percpu variable is
97 * used for the mapping. This is where the behaviors of x86_64 and 32
98 * actually diverge. Let's keep it ugly for now.
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
102 /* Local APIC was disabled by the BIOS and enabled by the kernel */
103 static int enabled_via_apicbase;
106 * Handle interrupt mode configuration register (IMCR).
107 * This register controls whether the interrupt signals
108 * that reach the BSP come from the master PIC or from the
109 * local APIC. Before entering Symmetric I/O Mode, either
110 * the BIOS or the operating system must switch out of
111 * PIC Mode by changing the IMCR.
113 static inline void imcr_pic_to_apic(void)
115 /* select IMCR register */
117 /* NMI and 8259 INTR go through APIC */
121 static inline void imcr_apic_to_pic(void)
123 /* select IMCR register */
125 /* NMI and 8259 INTR go directly to BSP */
131 * Knob to control our willingness to enable the local APIC.
135 static int force_enable_local_apic __initdata;
138 * APIC command line parameters
140 static int __init parse_lapic(char *arg)
142 if (config_enabled(CONFIG_X86_32) && !arg)
143 force_enable_local_apic = 1;
144 else if (arg && !strncmp(arg, "notscdeadline", 13))
145 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
148 early_param("lapic", parse_lapic);
151 static int apic_calibrate_pmtmr __initdata;
152 static __init int setup_apicpmtimer(char *s)
154 apic_calibrate_pmtmr = 1;
158 __setup("apicpmtimer", setup_apicpmtimer);
161 unsigned long mp_lapic_addr;
163 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
164 static int disable_apic_timer __initdata;
165 /* Local APIC timer works in C2 */
166 int local_apic_timer_c2_ok;
167 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
169 int first_system_vector = FIRST_SYSTEM_VECTOR;
172 * Debug level, exported for io_apic.c
174 unsigned int apic_verbosity;
178 /* Have we found an MP table */
179 int smp_found_config;
181 static struct resource lapic_resource = {
182 .name = "Local APIC",
183 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
186 unsigned int lapic_timer_frequency = 0;
188 static void apic_pm_activate(void);
190 static unsigned long apic_phys;
193 * Get the LAPIC version
195 static inline int lapic_get_version(void)
197 return GET_APIC_VERSION(apic_read(APIC_LVR));
201 * Check, if the APIC is integrated or a separate chip
203 static inline int lapic_is_integrated(void)
208 return APIC_INTEGRATED(lapic_get_version());
213 * Check, whether this is a modern or a first generation APIC
215 static int modern_apic(void)
217 /* AMD systems use old APIC versions, so check the CPU */
218 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
219 boot_cpu_data.x86 >= 0xf)
221 return lapic_get_version() >= 0x14;
225 * right after this call apic become NOOP driven
226 * so apic->write/read doesn't do anything
228 static void __init apic_disable(void)
230 pr_info("APIC: switched to apic NOOP\n");
234 void native_apic_wait_icr_idle(void)
236 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
240 u32 native_safe_apic_wait_icr_idle(void)
247 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
250 inc_irq_stat(icr_read_retry_count);
252 } while (timeout++ < 1000);
257 void native_apic_icr_write(u32 low, u32 id)
261 local_irq_save(flags);
262 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
263 apic_write(APIC_ICR, low);
264 local_irq_restore(flags);
267 u64 native_apic_icr_read(void)
271 icr2 = apic_read(APIC_ICR2);
272 icr1 = apic_read(APIC_ICR);
274 return icr1 | ((u64)icr2 << 32);
279 * get_physical_broadcast - Get number of physical broadcast IDs
281 int get_physical_broadcast(void)
283 return modern_apic() ? 0xff : 0xf;
288 * lapic_get_maxlvt - get the maximum number of local vector table entries
290 int lapic_get_maxlvt(void)
294 v = apic_read(APIC_LVR);
296 * - we always have APIC integrated on 64bit mode
297 * - 82489DXs do not report # of LVT entries
299 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
307 #define APIC_DIVISOR 16
308 #define TSC_DIVISOR 32
311 * This function sets up the local APIC timer, with a timeout of
312 * 'clocks' APIC bus clock. During calibration we actually call
313 * this function twice on the boot CPU, once with a bogus timeout
314 * value, second time for real. The other (noncalibrating) CPUs
315 * call this function only once, with the real, calibrated value.
317 * We do reads before writes even if unnecessary, to get around the
318 * P5 APIC double write bug.
320 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
322 unsigned int lvtt_value, tmp_value;
324 lvtt_value = LOCAL_TIMER_VECTOR;
326 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
327 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
328 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
330 if (!lapic_is_integrated())
331 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
334 lvtt_value |= APIC_LVT_MASKED;
336 apic_write(APIC_LVTT, lvtt_value);
338 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
339 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
346 tmp_value = apic_read(APIC_TDCR);
347 apic_write(APIC_TDCR,
348 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
352 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
356 * Setup extended LVT, AMD specific
358 * Software should use the LVT offsets the BIOS provides. The offsets
359 * are determined by the subsystems using it like those for MCE
360 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
361 * are supported. Beginning with family 10h at least 4 offsets are
364 * Since the offsets must be consistent for all cores, we keep track
365 * of the LVT offsets in software and reserve the offset for the same
366 * vector also to be used on other cores. An offset is freed by
367 * setting the entry to APIC_EILVT_MASKED.
369 * If the BIOS is right, there should be no conflicts. Otherwise a
370 * "[Firmware Bug]: ..." error message is generated. However, if
371 * software does not properly determines the offsets, it is not
372 * necessarily a BIOS bug.
375 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
377 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
379 return (old & APIC_EILVT_MASKED)
380 || (new == APIC_EILVT_MASKED)
381 || ((new & ~APIC_EILVT_MASKED) == old);
384 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
386 unsigned int rsvd, vector;
388 if (offset >= APIC_EILVT_NR_MAX)
391 rsvd = atomic_read(&eilvt_offsets[offset]);
393 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
394 if (vector && !eilvt_entry_is_changeable(vector, new))
395 /* may not change if vectors are different */
397 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
398 } while (rsvd != new);
400 rsvd &= ~APIC_EILVT_MASKED;
401 if (rsvd && rsvd != vector)
402 pr_info("LVT offset %d assigned for vector 0x%02x\n",
409 * If mask=1, the LVT entry does not generate interrupts while mask=0
410 * enables the vector. See also the BKDGs. Must be called with
411 * preemption disabled.
414 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
416 unsigned long reg = APIC_EILVTn(offset);
417 unsigned int new, old, reserved;
419 new = (mask << 16) | (msg_type << 8) | vector;
420 old = apic_read(reg);
421 reserved = reserve_eilvt_offset(offset, new);
423 if (reserved != new) {
424 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
425 "vector 0x%x, but the register is already in use for "
426 "vector 0x%x on another cpu\n",
427 smp_processor_id(), reg, offset, new, reserved);
431 if (!eilvt_entry_is_changeable(old, new)) {
432 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
433 "vector 0x%x, but the register is already in use for "
434 "vector 0x%x on this cpu\n",
435 smp_processor_id(), reg, offset, new, old);
439 apic_write(reg, new);
443 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
446 * Program the next event, relative to now
448 static int lapic_next_event(unsigned long delta,
449 struct clock_event_device *evt)
451 apic_write(APIC_TMICT, delta);
455 static int lapic_next_deadline(unsigned long delta,
456 struct clock_event_device *evt)
461 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
465 static int lapic_timer_shutdown(struct clock_event_device *evt)
469 /* Lapic used as dummy for broadcast ? */
470 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
473 v = apic_read(APIC_LVTT);
474 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
475 apic_write(APIC_LVTT, v);
476 apic_write(APIC_TMICT, 0);
481 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
483 /* Lapic used as dummy for broadcast ? */
484 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
487 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
491 static int lapic_timer_set_periodic(struct clock_event_device *evt)
493 return lapic_timer_set_periodic_oneshot(evt, false);
496 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
498 return lapic_timer_set_periodic_oneshot(evt, true);
502 * Local APIC timer broadcast function
504 static void lapic_timer_broadcast(const struct cpumask *mask)
507 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
513 * The local apic timer can be used for any function which is CPU local.
515 static struct clock_event_device lapic_clockevent = {
517 .features = CLOCK_EVT_FEAT_PERIODIC |
518 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
519 | CLOCK_EVT_FEAT_DUMMY,
521 .set_state_shutdown = lapic_timer_shutdown,
522 .set_state_periodic = lapic_timer_set_periodic,
523 .set_state_oneshot = lapic_timer_set_oneshot,
524 .set_next_event = lapic_next_event,
525 .broadcast = lapic_timer_broadcast,
529 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
532 * Setup the local APIC timer for this CPU. Copy the initialized values
533 * of the boot CPU and register the clock event in the framework.
535 static void setup_APIC_timer(void)
537 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
539 if (this_cpu_has(X86_FEATURE_ARAT)) {
540 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
541 /* Make LAPIC timer preferrable over percpu HPET */
542 lapic_clockevent.rating = 150;
545 memcpy(levt, &lapic_clockevent, sizeof(*levt));
546 levt->cpumask = cpumask_of(smp_processor_id());
548 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
549 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
550 CLOCK_EVT_FEAT_DUMMY);
551 levt->set_next_event = lapic_next_deadline;
552 clockevents_config_and_register(levt,
553 (tsc_khz / TSC_DIVISOR) * 1000,
556 clockevents_register_device(levt);
560 * In this functions we calibrate APIC bus clocks to the external timer.
562 * We want to do the calibration only once since we want to have local timer
563 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
566 * This was previously done by reading the PIT/HPET and waiting for a wrap
567 * around to find out, that a tick has elapsed. I have a box, where the PIT
568 * readout is broken, so it never gets out of the wait loop again. This was
569 * also reported by others.
571 * Monitoring the jiffies value is inaccurate and the clockevents
572 * infrastructure allows us to do a simple substitution of the interrupt
575 * The calibration routine also uses the pm_timer when possible, as the PIT
576 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
577 * back to normal later in the boot process).
580 #define LAPIC_CAL_LOOPS (HZ/10)
582 static __initdata int lapic_cal_loops = -1;
583 static __initdata long lapic_cal_t1, lapic_cal_t2;
584 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
585 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
586 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
589 * Temporary interrupt handler.
591 static void __init lapic_cal_handler(struct clock_event_device *dev)
593 unsigned long long tsc = 0;
594 long tapic = apic_read(APIC_TMCCT);
595 unsigned long pm = acpi_pm_read_early();
600 switch (lapic_cal_loops++) {
602 lapic_cal_t1 = tapic;
603 lapic_cal_tsc1 = tsc;
605 lapic_cal_j1 = jiffies;
608 case LAPIC_CAL_LOOPS:
609 lapic_cal_t2 = tapic;
610 lapic_cal_tsc2 = tsc;
611 if (pm < lapic_cal_pm1)
612 pm += ACPI_PM_OVRRUN;
614 lapic_cal_j2 = jiffies;
620 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
622 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
623 const long pm_thresh = pm_100ms / 100;
627 #ifndef CONFIG_X86_PM_TIMER
631 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
633 /* Check, if the PM timer is available */
637 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
639 if (deltapm > (pm_100ms - pm_thresh) &&
640 deltapm < (pm_100ms + pm_thresh)) {
641 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
645 res = (((u64)deltapm) * mult) >> 22;
646 do_div(res, 1000000);
647 pr_warning("APIC calibration not consistent "
648 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
650 /* Correct the lapic counter value */
651 res = (((u64)(*delta)) * pm_100ms);
652 do_div(res, deltapm);
653 pr_info("APIC delta adjusted to PM-Timer: "
654 "%lu (%ld)\n", (unsigned long)res, *delta);
657 /* Correct the tsc counter value */
659 res = (((u64)(*deltatsc)) * pm_100ms);
660 do_div(res, deltapm);
661 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
662 "PM-Timer: %lu (%ld)\n",
663 (unsigned long)res, *deltatsc);
664 *deltatsc = (long)res;
670 static int __init calibrate_APIC_clock(void)
672 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
673 void (*real_handler)(struct clock_event_device *dev);
674 unsigned long deltaj;
675 long delta, deltatsc;
676 int pm_referenced = 0;
679 * check if lapic timer has already been calibrated by platform
680 * specific routine, such as tsc calibration code. if so, we just fill
681 * in the clockevent structure and return.
684 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
686 } else if (lapic_timer_frequency) {
687 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
688 lapic_timer_frequency);
689 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
690 TICK_NSEC, lapic_clockevent.shift);
691 lapic_clockevent.max_delta_ns =
692 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
693 lapic_clockevent.min_delta_ns =
694 clockevent_delta2ns(0xF, &lapic_clockevent);
695 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
699 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
700 "calibrating APIC timer ...\n");
704 /* Replace the global interrupt handler */
705 real_handler = global_clock_event->event_handler;
706 global_clock_event->event_handler = lapic_cal_handler;
709 * Setup the APIC counter to maximum. There is no way the lapic
710 * can underflow in the 100ms detection time frame
712 __setup_APIC_LVTT(0xffffffff, 0, 0);
714 /* Let the interrupts run */
717 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
722 /* Restore the real event handler */
723 global_clock_event->event_handler = real_handler;
725 /* Build delta t1-t2 as apic timer counts down */
726 delta = lapic_cal_t1 - lapic_cal_t2;
727 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
729 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
731 /* we trust the PM based calibration if possible */
732 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
735 /* Calculate the scaled math multiplication factor */
736 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
737 lapic_clockevent.shift);
738 lapic_clockevent.max_delta_ns =
739 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
740 lapic_clockevent.min_delta_ns =
741 clockevent_delta2ns(0xF, &lapic_clockevent);
743 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
745 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
746 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
747 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
748 lapic_timer_frequency);
751 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
753 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
754 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
757 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
759 lapic_timer_frequency / (1000000 / HZ),
760 lapic_timer_frequency % (1000000 / HZ));
763 * Do a sanity check on the APIC calibration result
765 if (lapic_timer_frequency < (1000000 / HZ)) {
767 pr_warning("APIC frequency too slow, disabling apic timer\n");
771 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
774 * PM timer calibration failed or not turned on
775 * so lets try APIC timer based calibration
777 if (!pm_referenced) {
778 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
781 * Setup the apic timer manually
783 levt->event_handler = lapic_cal_handler;
784 lapic_timer_set_periodic(levt);
785 lapic_cal_loops = -1;
787 /* Let the interrupts run */
790 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
793 /* Stop the lapic timer */
795 lapic_timer_shutdown(levt);
798 deltaj = lapic_cal_j2 - lapic_cal_j1;
799 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
801 /* Check, if the jiffies result is consistent */
802 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
803 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
805 levt->features |= CLOCK_EVT_FEAT_DUMMY;
809 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
810 pr_warning("APIC timer disabled due to verification failure\n");
818 * Setup the boot APIC
820 * Calibrate and verify the result.
822 void __init setup_boot_APIC_clock(void)
825 * The local apic timer can be disabled via the kernel
826 * commandline or from the CPU detection code. Register the lapic
827 * timer as a dummy clock event source on SMP systems, so the
828 * broadcast mechanism is used. On UP systems simply ignore it.
830 if (disable_apic_timer) {
831 pr_info("Disabling APIC timer\n");
832 /* No broadcast on UP ! */
833 if (num_possible_cpus() > 1) {
834 lapic_clockevent.mult = 1;
840 if (calibrate_APIC_clock()) {
841 /* No broadcast on UP ! */
842 if (num_possible_cpus() > 1)
848 * If nmi_watchdog is set to IO_APIC, we need the
849 * PIT/HPET going. Otherwise register lapic as a dummy
852 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
854 /* Setup the lapic or request the broadcast */
858 void setup_secondary_APIC_clock(void)
864 * The guts of the apic timer interrupt
866 static void local_apic_timer_interrupt(void)
868 int cpu = smp_processor_id();
869 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
872 * Normally we should not be here till LAPIC has been initialized but
873 * in some cases like kdump, its possible that there is a pending LAPIC
874 * timer interrupt from previous kernel's context and is delivered in
875 * new kernel the moment interrupts are enabled.
877 * Interrupts are enabled early and LAPIC is setup much later, hence
878 * its possible that when we get here evt->event_handler is NULL.
879 * Check for event_handler being NULL and discard the interrupt as
882 if (!evt->event_handler) {
883 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
885 lapic_timer_shutdown(evt);
890 * the NMI deadlock-detector uses this.
892 inc_irq_stat(apic_timer_irqs);
894 evt->event_handler(evt);
898 * Local APIC timer interrupt. This is the most natural way for doing
899 * local interrupts, but local timer interrupts can be emulated by
900 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
902 * [ if a single-CPU system runs an SMP kernel then we call the local
903 * interrupt as well. Thus we cannot inline the local irq ... ]
905 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
907 struct pt_regs *old_regs = set_irq_regs(regs);
910 * NOTE! We'd better ACK the irq immediately,
911 * because timer handling can be slow.
913 * update_process_times() expects us to have done irq_enter().
914 * Besides, if we don't timer interrupts ignore the global
915 * interrupt lock, which is the WrongThing (tm) to do.
918 local_apic_timer_interrupt();
921 set_irq_regs(old_regs);
924 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
926 struct pt_regs *old_regs = set_irq_regs(regs);
929 * NOTE! We'd better ACK the irq immediately,
930 * because timer handling can be slow.
932 * update_process_times() expects us to have done irq_enter().
933 * Besides, if we don't timer interrupts ignore the global
934 * interrupt lock, which is the WrongThing (tm) to do.
937 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
938 local_apic_timer_interrupt();
939 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
942 set_irq_regs(old_regs);
945 int setup_profiling_timer(unsigned int multiplier)
951 * Local APIC start and shutdown
955 * clear_local_APIC - shutdown the local APIC
957 * This is called, when a CPU is disabled and before rebooting, so the state of
958 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
959 * leftovers during boot.
961 void clear_local_APIC(void)
966 /* APIC hasn't been mapped yet */
967 if (!x2apic_mode && !apic_phys)
970 maxlvt = lapic_get_maxlvt();
972 * Masking an LVT entry can trigger a local APIC error
973 * if the vector is zero. Mask LVTERR first to prevent this.
976 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
977 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
980 * Careful: we have to set masks only first to deassert
981 * any level-triggered sources.
983 v = apic_read(APIC_LVTT);
984 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
985 v = apic_read(APIC_LVT0);
986 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
987 v = apic_read(APIC_LVT1);
988 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
990 v = apic_read(APIC_LVTPC);
991 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
994 /* lets not touch this if we didn't frob it */
995 #ifdef CONFIG_X86_THERMAL_VECTOR
997 v = apic_read(APIC_LVTTHMR);
998 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1001 #ifdef CONFIG_X86_MCE_INTEL
1003 v = apic_read(APIC_LVTCMCI);
1004 if (!(v & APIC_LVT_MASKED))
1005 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1010 * Clean APIC state for other OSs:
1012 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1013 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1014 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1016 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1018 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1020 /* Integrated APIC (!82489DX) ? */
1021 if (lapic_is_integrated()) {
1023 /* Clear ESR due to Pentium errata 3AP and 11AP */
1024 apic_write(APIC_ESR, 0);
1025 apic_read(APIC_ESR);
1030 * disable_local_APIC - clear and disable the local APIC
1032 void disable_local_APIC(void)
1036 /* APIC hasn't been mapped yet */
1037 if (!x2apic_mode && !apic_phys)
1043 * Disable APIC (implies clearing of registers
1046 value = apic_read(APIC_SPIV);
1047 value &= ~APIC_SPIV_APIC_ENABLED;
1048 apic_write(APIC_SPIV, value);
1050 #ifdef CONFIG_X86_32
1052 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1053 * restore the disabled state.
1055 if (enabled_via_apicbase) {
1058 rdmsr(MSR_IA32_APICBASE, l, h);
1059 l &= ~MSR_IA32_APICBASE_ENABLE;
1060 wrmsr(MSR_IA32_APICBASE, l, h);
1066 * If Linux enabled the LAPIC against the BIOS default disable it down before
1067 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1068 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1069 * for the case where Linux didn't enable the LAPIC.
1071 void lapic_shutdown(void)
1073 unsigned long flags;
1075 if (!cpu_has_apic && !apic_from_smp_config())
1078 local_irq_save(flags);
1080 #ifdef CONFIG_X86_32
1081 if (!enabled_via_apicbase)
1085 disable_local_APIC();
1088 local_irq_restore(flags);
1092 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1094 void __init sync_Arb_IDs(void)
1097 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1100 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1106 apic_wait_icr_idle();
1108 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1109 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1110 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1114 * An initial setup of the virtual wire mode.
1116 void __init init_bsp_APIC(void)
1121 * Don't do the setup now if we have a SMP BIOS as the
1122 * through-I/O-APIC virtual wire mode might be active.
1124 if (smp_found_config || !cpu_has_apic)
1128 * Do not trust the local APIC being empty at bootup.
1135 value = apic_read(APIC_SPIV);
1136 value &= ~APIC_VECTOR_MASK;
1137 value |= APIC_SPIV_APIC_ENABLED;
1139 #ifdef CONFIG_X86_32
1140 /* This bit is reserved on P4/Xeon and should be cleared */
1141 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1142 (boot_cpu_data.x86 == 15))
1143 value &= ~APIC_SPIV_FOCUS_DISABLED;
1146 value |= APIC_SPIV_FOCUS_DISABLED;
1147 value |= SPURIOUS_APIC_VECTOR;
1148 apic_write(APIC_SPIV, value);
1151 * Set up the virtual wire mode.
1153 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1154 value = APIC_DM_NMI;
1155 if (!lapic_is_integrated()) /* 82489DX */
1156 value |= APIC_LVT_LEVEL_TRIGGER;
1157 apic_write(APIC_LVT1, value);
1160 static void lapic_setup_esr(void)
1162 unsigned int oldvalue, value, maxlvt;
1164 if (!lapic_is_integrated()) {
1165 pr_info("No ESR for 82489DX.\n");
1169 if (apic->disable_esr) {
1171 * Something untraceable is creating bad interrupts on
1172 * secondary quads ... for the moment, just leave the
1173 * ESR disabled - we can't do anything useful with the
1174 * errors anyway - mbligh
1176 pr_info("Leaving ESR disabled.\n");
1180 maxlvt = lapic_get_maxlvt();
1181 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1182 apic_write(APIC_ESR, 0);
1183 oldvalue = apic_read(APIC_ESR);
1185 /* enables sending errors */
1186 value = ERROR_APIC_VECTOR;
1187 apic_write(APIC_LVTERR, value);
1190 * spec says clear errors after enabling vector.
1193 apic_write(APIC_ESR, 0);
1194 value = apic_read(APIC_ESR);
1195 if (value != oldvalue)
1196 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1197 "vector: 0x%08x after: 0x%08x\n",
1202 * setup_local_APIC - setup the local APIC
1204 * Used to setup local APIC while initializing BSP or bringin up APs.
1205 * Always called with preemption disabled.
1207 void setup_local_APIC(void)
1209 int cpu = smp_processor_id();
1210 unsigned int value, queued;
1211 int i, j, acked = 0;
1212 unsigned long long tsc = 0, ntsc;
1213 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1219 disable_ioapic_support();
1223 #ifdef CONFIG_X86_32
1224 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1225 if (lapic_is_integrated() && apic->disable_esr) {
1226 apic_write(APIC_ESR, 0);
1227 apic_write(APIC_ESR, 0);
1228 apic_write(APIC_ESR, 0);
1229 apic_write(APIC_ESR, 0);
1232 perf_events_lapic_init();
1235 * Double-check whether this APIC is really registered.
1236 * This is meaningless in clustered apic mode, so we skip it.
1238 BUG_ON(!apic->apic_id_registered());
1241 * Intel recommends to set DFR, LDR and TPR before enabling
1242 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1243 * document number 292116). So here it goes...
1245 apic->init_apic_ldr();
1247 #ifdef CONFIG_X86_32
1249 * APIC LDR is initialized. If logical_apicid mapping was
1250 * initialized during get_smp_config(), make sure it matches the
1253 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1254 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1255 /* always use the value from LDR */
1256 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1257 logical_smp_processor_id();
1261 * Set Task Priority to 'accept all'. We never change this
1264 value = apic_read(APIC_TASKPRI);
1265 value &= ~APIC_TPRI_MASK;
1266 apic_write(APIC_TASKPRI, value);
1269 * After a crash, we no longer service the interrupts and a pending
1270 * interrupt from previous kernel might still have ISR bit set.
1272 * Most probably by now CPU has serviced that pending interrupt and
1273 * it might not have done the ack_APIC_irq() because it thought,
1274 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1275 * does not clear the ISR bit and cpu thinks it has already serivced
1276 * the interrupt. Hence a vector might get locked. It was noticed
1277 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1281 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1282 queued |= apic_read(APIC_IRR + i*0x10);
1284 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1285 value = apic_read(APIC_ISR + i*0x10);
1286 for (j = 31; j >= 0; j--) {
1287 if (value & (1<<j)) {
1294 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1299 if (cpu_has_tsc && cpu_khz) {
1301 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1305 } while (queued && max_loops > 0);
1306 WARN_ON(max_loops <= 0);
1309 * Now that we are all set up, enable the APIC
1311 value = apic_read(APIC_SPIV);
1312 value &= ~APIC_VECTOR_MASK;
1316 value |= APIC_SPIV_APIC_ENABLED;
1318 #ifdef CONFIG_X86_32
1320 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1321 * certain networking cards. If high frequency interrupts are
1322 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1323 * entry is masked/unmasked at a high rate as well then sooner or
1324 * later IOAPIC line gets 'stuck', no more interrupts are received
1325 * from the device. If focus CPU is disabled then the hang goes
1328 * [ This bug can be reproduced easily with a level-triggered
1329 * PCI Ne2000 networking cards and PII/PIII processors, dual
1333 * Actually disabling the focus CPU check just makes the hang less
1334 * frequent as it makes the interrupt distributon model be more
1335 * like LRU than MRU (the short-term load is more even across CPUs).
1336 * See also the comment in end_level_ioapic_irq(). --macro
1340 * - enable focus processor (bit==0)
1341 * - 64bit mode always use processor focus
1342 * so no need to set it
1344 value &= ~APIC_SPIV_FOCUS_DISABLED;
1348 * Set spurious IRQ vector
1350 value |= SPURIOUS_APIC_VECTOR;
1351 apic_write(APIC_SPIV, value);
1354 * Set up LVT0, LVT1:
1356 * set up through-local-APIC on the BP's LINT0. This is not
1357 * strictly necessary in pure symmetric-IO mode, but sometimes
1358 * we delegate interrupts to the 8259A.
1361 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1363 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1364 if (!cpu && (pic_mode || !value)) {
1365 value = APIC_DM_EXTINT;
1366 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1368 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1369 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1371 apic_write(APIC_LVT0, value);
1374 * only the BP should see the LINT1 NMI signal, obviously.
1377 value = APIC_DM_NMI;
1379 value = APIC_DM_NMI | APIC_LVT_MASKED;
1380 if (!lapic_is_integrated()) /* 82489DX */
1381 value |= APIC_LVT_LEVEL_TRIGGER;
1382 apic_write(APIC_LVT1, value);
1384 #ifdef CONFIG_X86_MCE_INTEL
1385 /* Recheck CMCI information after local APIC is up on CPU #0 */
1391 static void end_local_APIC_setup(void)
1395 #ifdef CONFIG_X86_32
1398 /* Disable the local apic timer */
1399 value = apic_read(APIC_LVTT);
1400 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1401 apic_write(APIC_LVTT, value);
1409 * APIC setup function for application processors. Called from smpboot.c
1411 void apic_ap_setup(void)
1414 end_local_APIC_setup();
1417 #ifdef CONFIG_X86_X2APIC
1425 static int x2apic_state;
1427 static inline void __x2apic_disable(void)
1434 rdmsrl(MSR_IA32_APICBASE, msr);
1435 if (!(msr & X2APIC_ENABLE))
1437 /* Disable xapic and x2apic first and then reenable xapic mode */
1438 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1439 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1440 printk_once(KERN_INFO "x2apic disabled\n");
1443 static inline void __x2apic_enable(void)
1447 rdmsrl(MSR_IA32_APICBASE, msr);
1448 if (msr & X2APIC_ENABLE)
1450 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1451 printk_once(KERN_INFO "x2apic enabled\n");
1454 static int __init setup_nox2apic(char *str)
1456 if (x2apic_enabled()) {
1457 int apicid = native_apic_msr_read(APIC_ID);
1459 if (apicid >= 255) {
1460 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1464 pr_warning("x2apic already enabled.\n");
1467 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1468 x2apic_state = X2APIC_DISABLED;
1472 early_param("nox2apic", setup_nox2apic);
1474 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1475 void x2apic_setup(void)
1478 * If x2apic is not in ON state, disable it if already enabled
1481 if (x2apic_state != X2APIC_ON) {
1488 static __init void x2apic_disable(void)
1490 u32 x2apic_id, state = x2apic_state;
1493 x2apic_state = X2APIC_DISABLED;
1495 if (state != X2APIC_ON)
1498 x2apic_id = read_apic_id();
1499 if (x2apic_id >= 255)
1500 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1503 register_lapic_address(mp_lapic_addr);
1506 static __init void x2apic_enable(void)
1508 if (x2apic_state != X2APIC_OFF)
1512 x2apic_state = X2APIC_ON;
1516 static __init void try_to_enable_x2apic(int remap_mode)
1518 if (x2apic_state == X2APIC_DISABLED)
1521 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1522 /* IR is required if there is APIC ID > 255 even when running
1525 if (max_physical_apicid > 255 ||
1526 !hypervisor_x2apic_available()) {
1527 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1533 * without IR all CPUs can be addressed by IOAPIC/MSI
1534 * only in physical mode
1541 void __init check_x2apic(void)
1543 if (x2apic_enabled()) {
1544 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1546 x2apic_state = X2APIC_ON;
1547 } else if (!cpu_has_x2apic) {
1548 x2apic_state = X2APIC_DISABLED;
1551 #else /* CONFIG_X86_X2APIC */
1552 static int __init validate_x2apic(void)
1554 if (!apic_is_x2apic_enabled())
1557 * Checkme: Can we simply turn off x2apic here instead of panic?
1559 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1561 early_initcall(validate_x2apic);
1563 static inline void try_to_enable_x2apic(int remap_mode) { }
1564 static inline void __x2apic_enable(void) { }
1565 #endif /* !CONFIG_X86_X2APIC */
1567 static int __init try_to_enable_IR(void)
1569 #ifdef CONFIG_X86_IO_APIC
1570 if (!x2apic_enabled() && skip_ioapic_setup) {
1571 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1575 return irq_remapping_enable();
1578 void __init enable_IR_x2apic(void)
1580 unsigned long flags;
1583 ir_stat = irq_remapping_prepare();
1584 if (ir_stat < 0 && !x2apic_supported())
1587 ret = save_ioapic_entries();
1589 pr_info("Saving IO-APIC state failed: %d\n", ret);
1593 local_irq_save(flags);
1594 legacy_pic->mask_all();
1595 mask_ioapic_entries();
1597 /* If irq_remapping_prepare() succeded, try to enable it */
1599 ir_stat = try_to_enable_IR();
1600 /* ir_stat contains the remap mode or an error code */
1601 try_to_enable_x2apic(ir_stat);
1604 restore_ioapic_entries();
1605 legacy_pic->restore_mask();
1606 local_irq_restore(flags);
1609 #ifdef CONFIG_X86_64
1611 * Detect and enable local APICs on non-SMP boards.
1612 * Original code written by Keir Fraser.
1613 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1614 * not correctly set up (usually the APIC timer won't work etc.)
1616 static int __init detect_init_APIC(void)
1618 if (!cpu_has_apic) {
1619 pr_info("No local APIC present\n");
1623 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1628 static int __init apic_verify(void)
1633 * The APIC feature bit should now be enabled
1636 features = cpuid_edx(1);
1637 if (!(features & (1 << X86_FEATURE_APIC))) {
1638 pr_warning("Could not enable APIC!\n");
1641 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1642 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1644 /* The BIOS may have set up the APIC at some other address */
1645 if (boot_cpu_data.x86 >= 6) {
1646 rdmsr(MSR_IA32_APICBASE, l, h);
1647 if (l & MSR_IA32_APICBASE_ENABLE)
1648 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1651 pr_info("Found and enabled local APIC!\n");
1655 int __init apic_force_enable(unsigned long addr)
1663 * Some BIOSes disable the local APIC in the APIC_BASE
1664 * MSR. This can only be done in software for Intel P6 or later
1665 * and AMD K7 (Model > 1) or later.
1667 if (boot_cpu_data.x86 >= 6) {
1668 rdmsr(MSR_IA32_APICBASE, l, h);
1669 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1670 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1671 l &= ~MSR_IA32_APICBASE_BASE;
1672 l |= MSR_IA32_APICBASE_ENABLE | addr;
1673 wrmsr(MSR_IA32_APICBASE, l, h);
1674 enabled_via_apicbase = 1;
1677 return apic_verify();
1681 * Detect and initialize APIC
1683 static int __init detect_init_APIC(void)
1685 /* Disabled by kernel option? */
1689 switch (boot_cpu_data.x86_vendor) {
1690 case X86_VENDOR_AMD:
1691 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1692 (boot_cpu_data.x86 >= 15))
1695 case X86_VENDOR_INTEL:
1696 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1697 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1704 if (!cpu_has_apic) {
1706 * Over-ride BIOS and try to enable the local APIC only if
1707 * "lapic" specified.
1709 if (!force_enable_local_apic) {
1710 pr_info("Local APIC disabled by BIOS -- "
1711 "you can enable it with \"lapic\"\n");
1714 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1726 pr_info("No local APIC present or hardware disabled\n");
1732 * init_apic_mappings - initialize APIC mappings
1734 void __init init_apic_mappings(void)
1736 unsigned int new_apicid;
1739 boot_cpu_physical_apicid = read_apic_id();
1743 /* If no local APIC can be found return early */
1744 if (!smp_found_config && detect_init_APIC()) {
1745 /* lets NOP'ify apic operations */
1746 pr_info("APIC: disable apic facility\n");
1749 apic_phys = mp_lapic_addr;
1752 * acpi lapic path already maps that address in
1753 * acpi_register_lapic_address()
1755 if (!acpi_lapic && !smp_found_config)
1756 register_lapic_address(apic_phys);
1760 * Fetch the APIC ID of the BSP in case we have a
1761 * default configuration (or the MP table is broken).
1763 new_apicid = read_apic_id();
1764 if (boot_cpu_physical_apicid != new_apicid) {
1765 boot_cpu_physical_apicid = new_apicid;
1767 * yeah -- we lie about apic_version
1768 * in case if apic was disabled via boot option
1769 * but it's not a problem for SMP compiled kernel
1770 * since smp_sanity_check is prepared for such a case
1771 * and disable smp mode
1773 apic_version[new_apicid] =
1774 GET_APIC_VERSION(apic_read(APIC_LVR));
1778 void __init register_lapic_address(unsigned long address)
1780 mp_lapic_addr = address;
1783 set_fixmap_nocache(FIX_APIC_BASE, address);
1784 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1785 APIC_BASE, mp_lapic_addr);
1787 if (boot_cpu_physical_apicid == -1U) {
1788 boot_cpu_physical_apicid = read_apic_id();
1789 apic_version[boot_cpu_physical_apicid] =
1790 GET_APIC_VERSION(apic_read(APIC_LVR));
1794 int apic_version[MAX_LOCAL_APIC];
1797 * Local APIC interrupts
1801 * This interrupt should _never_ happen with our APIC/SMP architecture
1803 static inline void __smp_spurious_interrupt(u8 vector)
1808 * Check if this really is a spurious interrupt and ACK it
1809 * if it is a vectored one. Just in case...
1810 * Spurious interrupts should not be ACKed.
1812 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1813 if (v & (1 << (vector & 0x1f)))
1816 inc_irq_stat(irq_spurious_count);
1818 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1819 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1820 "should never happen.\n", vector, smp_processor_id());
1823 __visible void smp_spurious_interrupt(struct pt_regs *regs)
1826 __smp_spurious_interrupt(~regs->orig_ax);
1830 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1832 u8 vector = ~regs->orig_ax;
1835 trace_spurious_apic_entry(vector);
1836 __smp_spurious_interrupt(vector);
1837 trace_spurious_apic_exit(vector);
1842 * This interrupt should never happen with our APIC/SMP architecture
1844 static inline void __smp_error_interrupt(struct pt_regs *regs)
1848 static const char * const error_interrupt_reason[] = {
1849 "Send CS error", /* APIC Error Bit 0 */
1850 "Receive CS error", /* APIC Error Bit 1 */
1851 "Send accept error", /* APIC Error Bit 2 */
1852 "Receive accept error", /* APIC Error Bit 3 */
1853 "Redirectable IPI", /* APIC Error Bit 4 */
1854 "Send illegal vector", /* APIC Error Bit 5 */
1855 "Received illegal vector", /* APIC Error Bit 6 */
1856 "Illegal register address", /* APIC Error Bit 7 */
1859 /* First tickle the hardware, only then report what went on. -- REW */
1860 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1861 apic_write(APIC_ESR, 0);
1862 v = apic_read(APIC_ESR);
1864 atomic_inc(&irq_err_count);
1866 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1867 smp_processor_id(), v);
1872 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1877 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1881 __visible void smp_error_interrupt(struct pt_regs *regs)
1884 __smp_error_interrupt(regs);
1888 __visible void smp_trace_error_interrupt(struct pt_regs *regs)
1891 trace_error_apic_entry(ERROR_APIC_VECTOR);
1892 __smp_error_interrupt(regs);
1893 trace_error_apic_exit(ERROR_APIC_VECTOR);
1898 * connect_bsp_APIC - attach the APIC to the interrupt system
1900 static void __init connect_bsp_APIC(void)
1902 #ifdef CONFIG_X86_32
1905 * Do not trust the local APIC being empty at bootup.
1909 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1910 * local APIC to INT and NMI lines.
1912 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1913 "enabling APIC mode.\n");
1920 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1921 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1923 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1926 void disconnect_bsp_APIC(int virt_wire_setup)
1930 #ifdef CONFIG_X86_32
1933 * Put the board back into PIC mode (has an effect only on
1934 * certain older boards). Note that APIC interrupts, including
1935 * IPIs, won't work beyond this point! The only exception are
1938 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1939 "entering PIC mode.\n");
1945 /* Go back to Virtual Wire compatibility mode */
1947 /* For the spurious interrupt use vector F, and enable it */
1948 value = apic_read(APIC_SPIV);
1949 value &= ~APIC_VECTOR_MASK;
1950 value |= APIC_SPIV_APIC_ENABLED;
1952 apic_write(APIC_SPIV, value);
1954 if (!virt_wire_setup) {
1956 * For LVT0 make it edge triggered, active high,
1957 * external and enabled
1959 value = apic_read(APIC_LVT0);
1960 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1961 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1962 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1963 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1964 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1965 apic_write(APIC_LVT0, value);
1968 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1972 * For LVT1 make it edge triggered, active high,
1975 value = apic_read(APIC_LVT1);
1976 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1977 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1978 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1979 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1980 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1981 apic_write(APIC_LVT1, value);
1984 int generic_processor_info(int apicid, int version)
1986 int cpu, max = nr_cpu_ids;
1987 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
1988 phys_cpu_present_map);
1991 * boot_cpu_physical_apicid is designed to have the apicid
1992 * returned by read_apic_id(), i.e, the apicid of the
1993 * currently booting-up processor. However, on some platforms,
1994 * it is temporarily modified by the apicid reported as BSP
1995 * through MP table. Concretely:
1997 * - arch/x86/kernel/mpparse.c: MP_processor_info()
1998 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2000 * This function is executed with the modified
2001 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2002 * parameter doesn't work to disable APs on kdump 2nd kernel.
2004 * Since fixing handling of boot_cpu_physical_apicid requires
2005 * another discussion and tests on each platform, we leave it
2006 * for now and here we use read_apic_id() directly in this
2007 * function, generic_processor_info().
2009 if (disabled_cpu_apicid != BAD_APICID &&
2010 disabled_cpu_apicid != read_apic_id() &&
2011 disabled_cpu_apicid == apicid) {
2012 int thiscpu = num_processors + disabled_cpus;
2014 pr_warning("APIC: Disabling requested cpu."
2015 " Processor %d/0x%x ignored.\n",
2023 * If boot cpu has not been detected yet, then only allow upto
2024 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2026 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2027 apicid != boot_cpu_physical_apicid) {
2028 int thiscpu = max + disabled_cpus - 1;
2031 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2032 " reached. Keeping one slot for boot cpu."
2033 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2039 if (num_processors >= nr_cpu_ids) {
2040 int thiscpu = max + disabled_cpus;
2043 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2044 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2051 if (apicid == boot_cpu_physical_apicid) {
2053 * x86_bios_cpu_apicid is required to have processors listed
2054 * in same order as logical cpu numbers. Hence the first
2055 * entry is BSP, and so on.
2056 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2061 cpu = cpumask_next_zero(-1, cpu_present_mask);
2066 if (version == 0x0) {
2067 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2071 apic_version[apicid] = version;
2073 if (version != apic_version[boot_cpu_physical_apicid]) {
2074 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2075 apic_version[boot_cpu_physical_apicid], cpu, version);
2078 physid_set(apicid, phys_cpu_present_map);
2079 if (apicid > max_physical_apicid)
2080 max_physical_apicid = apicid;
2082 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2083 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2084 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2086 #ifdef CONFIG_X86_32
2087 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2088 apic->x86_32_early_logical_apicid(cpu);
2090 set_cpu_possible(cpu, true);
2091 set_cpu_present(cpu, true);
2096 int hard_smp_processor_id(void)
2098 return read_apic_id();
2101 void default_init_apic_ldr(void)
2105 apic_write(APIC_DFR, APIC_DFR_VALUE);
2106 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2107 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2108 apic_write(APIC_LDR, val);
2111 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2112 const struct cpumask *andmask,
2113 unsigned int *apicid)
2117 for_each_cpu_and(cpu, cpumask, andmask) {
2118 if (cpumask_test_cpu(cpu, cpu_online_mask))
2122 if (likely(cpu < nr_cpu_ids)) {
2123 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2131 * Override the generic EOI implementation with an optimized version.
2132 * Only called during early boot when only one CPU is active and with
2133 * interrupts disabled, so we know this does not race with actual APIC driver
2136 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2140 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2141 /* Should happen once for each apic */
2142 WARN_ON((*drv)->eoi_write == eoi_write);
2143 (*drv)->eoi_write = eoi_write;
2147 static void __init apic_bsp_up_setup(void)
2149 #ifdef CONFIG_X86_64
2150 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
2153 * Hack: In case of kdump, after a crash, kernel might be booting
2154 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2155 * might be zero if read from MP tables. Get it from LAPIC.
2157 # ifdef CONFIG_CRASH_DUMP
2158 boot_cpu_physical_apicid = read_apic_id();
2161 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2165 * apic_bsp_setup - Setup function for local apic and io-apic
2166 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2169 * apic_id of BSP APIC
2171 int __init apic_bsp_setup(bool upmode)
2177 apic_bsp_up_setup();
2181 id = apic_read(APIC_LDR);
2183 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2186 end_local_APIC_setup();
2187 irq_remap_enable_fault_handling();
2189 /* Setup local timer */
2190 x86_init.timers.setup_percpu_clockev();
2195 * This initializes the IO-APIC and APIC hardware if this is
2198 int __init APIC_init_uniprocessor(void)
2201 pr_info("Apic disabled\n");
2204 #ifdef CONFIG_X86_64
2205 if (!cpu_has_apic) {
2207 pr_info("Apic disabled by BIOS\n");
2211 if (!smp_found_config && !cpu_has_apic)
2215 * Complain if the BIOS pretends there is one.
2217 if (!cpu_has_apic &&
2218 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
2219 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2220 boot_cpu_physical_apicid);
2225 if (!smp_found_config)
2226 disable_ioapic_support();
2228 default_setup_apic_routing();
2229 apic_bsp_setup(true);
2233 #ifdef CONFIG_UP_LATE_INIT
2234 void __init up_late_init(void)
2236 APIC_init_uniprocessor();
2247 * 'active' is true if the local APIC was enabled by us and
2248 * not the BIOS; this signifies that we are also responsible
2249 * for disabling it before entering apm/acpi suspend
2252 /* r/w apic fields */
2253 unsigned int apic_id;
2254 unsigned int apic_taskpri;
2255 unsigned int apic_ldr;
2256 unsigned int apic_dfr;
2257 unsigned int apic_spiv;
2258 unsigned int apic_lvtt;
2259 unsigned int apic_lvtpc;
2260 unsigned int apic_lvt0;
2261 unsigned int apic_lvt1;
2262 unsigned int apic_lvterr;
2263 unsigned int apic_tmict;
2264 unsigned int apic_tdcr;
2265 unsigned int apic_thmr;
2268 static int lapic_suspend(void)
2270 unsigned long flags;
2273 if (!apic_pm_state.active)
2276 maxlvt = lapic_get_maxlvt();
2278 apic_pm_state.apic_id = apic_read(APIC_ID);
2279 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2280 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2281 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2282 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2283 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2285 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2286 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2287 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2288 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2289 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2290 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2291 #ifdef CONFIG_X86_THERMAL_VECTOR
2293 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2296 local_irq_save(flags);
2297 disable_local_APIC();
2299 irq_remapping_disable();
2301 local_irq_restore(flags);
2305 static void lapic_resume(void)
2308 unsigned long flags;
2311 if (!apic_pm_state.active)
2314 local_irq_save(flags);
2317 * IO-APIC and PIC have their own resume routines.
2318 * We just mask them here to make sure the interrupt
2319 * subsystem is completely quiet while we enable x2apic
2320 * and interrupt-remapping.
2322 mask_ioapic_entries();
2323 legacy_pic->mask_all();
2329 * Make sure the APICBASE points to the right address
2331 * FIXME! This will be wrong if we ever support suspend on
2332 * SMP! We'll need to do this as part of the CPU restore!
2334 if (boot_cpu_data.x86 >= 6) {
2335 rdmsr(MSR_IA32_APICBASE, l, h);
2336 l &= ~MSR_IA32_APICBASE_BASE;
2337 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2338 wrmsr(MSR_IA32_APICBASE, l, h);
2342 maxlvt = lapic_get_maxlvt();
2343 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2344 apic_write(APIC_ID, apic_pm_state.apic_id);
2345 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2346 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2347 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2348 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2349 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2350 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2351 #if defined(CONFIG_X86_MCE_INTEL)
2353 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2356 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2357 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2358 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2359 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2360 apic_write(APIC_ESR, 0);
2361 apic_read(APIC_ESR);
2362 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2363 apic_write(APIC_ESR, 0);
2364 apic_read(APIC_ESR);
2366 irq_remapping_reenable(x2apic_mode);
2368 local_irq_restore(flags);
2372 * This device has no shutdown method - fully functioning local APICs
2373 * are needed on every CPU up until machine_halt/restart/poweroff.
2376 static struct syscore_ops lapic_syscore_ops = {
2377 .resume = lapic_resume,
2378 .suspend = lapic_suspend,
2381 static void apic_pm_activate(void)
2383 apic_pm_state.active = 1;
2386 static int __init init_lapic_sysfs(void)
2388 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2390 register_syscore_ops(&lapic_syscore_ops);
2395 /* local apic needs to resume before other devices access its registers. */
2396 core_initcall(init_lapic_sysfs);
2398 #else /* CONFIG_PM */
2400 static void apic_pm_activate(void) { }
2402 #endif /* CONFIG_PM */
2404 #ifdef CONFIG_X86_64
2406 static int multi_checked;
2409 static int set_multi(const struct dmi_system_id *d)
2413 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2418 static const struct dmi_system_id multi_dmi_table[] = {
2420 .callback = set_multi,
2421 .ident = "IBM System Summit2",
2423 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2424 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2430 static void dmi_check_multi(void)
2435 dmi_check_system(multi_dmi_table);
2440 * apic_is_clustered_box() -- Check if we can expect good TSC
2442 * Thus far, the major user of this is IBM's Summit2 series:
2443 * Clustered boxes may have unsynced TSC problems if they are
2445 * Use DMI to check them
2447 int apic_is_clustered_box(void)
2455 * APIC command line parameters
2457 static int __init setup_disableapic(char *arg)
2460 setup_clear_cpu_cap(X86_FEATURE_APIC);
2463 early_param("disableapic", setup_disableapic);
2465 /* same as disableapic, for compatibility */
2466 static int __init setup_nolapic(char *arg)
2468 return setup_disableapic(arg);
2470 early_param("nolapic", setup_nolapic);
2472 static int __init parse_lapic_timer_c2_ok(char *arg)
2474 local_apic_timer_c2_ok = 1;
2477 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2479 static int __init parse_disable_apic_timer(char *arg)
2481 disable_apic_timer = 1;
2484 early_param("noapictimer", parse_disable_apic_timer);
2486 static int __init parse_nolapic_timer(char *arg)
2488 disable_apic_timer = 1;
2491 early_param("nolapic_timer", parse_nolapic_timer);
2493 static int __init apic_set_verbosity(char *arg)
2496 #ifdef CONFIG_X86_64
2497 skip_ioapic_setup = 0;
2503 if (strcmp("debug", arg) == 0)
2504 apic_verbosity = APIC_DEBUG;
2505 else if (strcmp("verbose", arg) == 0)
2506 apic_verbosity = APIC_VERBOSE;
2508 pr_warning("APIC Verbosity level %s not recognised"
2509 " use apic=verbose or apic=debug\n", arg);
2515 early_param("apic", apic_set_verbosity);
2517 static int __init lapic_insert_resource(void)
2522 /* Put local APIC into the resource map. */
2523 lapic_resource.start = apic_phys;
2524 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2525 insert_resource(&iomem_resource, &lapic_resource);
2531 * need call insert after e820_reserve_resources()
2532 * that is using request_resource
2534 late_initcall(lapic_insert_resource);
2536 static int __init apic_set_disabled_cpu_apicid(char *arg)
2538 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2543 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);