2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 void arch_disable_smp_support(void)
106 noioapicreroute = -1;
108 skip_ioapic_setup = 1;
111 static int __init parse_noapic(char *str)
113 /* disable IO-APIC */
114 arch_disable_smp_support();
117 early_param("noapic", parse_noapic);
119 struct irq_pin_list {
121 struct irq_pin_list *next;
124 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
126 struct irq_pin_list *pin;
128 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
134 * This is performance-critical, we want to do it O(1)
136 * Most irqs are mapped 1:1 with pins.
139 struct irq_pin_list *irq_2_pin;
140 cpumask_var_t domain;
141 cpumask_var_t old_domain;
142 unsigned move_cleanup_count;
144 u8 move_in_progress : 1;
147 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
148 #ifdef CONFIG_SPARSE_IRQ
149 static struct irq_cfg irq_cfgx[] = {
151 static struct irq_cfg irq_cfgx[NR_IRQS] = {
153 [0] = { .vector = IRQ0_VECTOR, },
154 [1] = { .vector = IRQ1_VECTOR, },
155 [2] = { .vector = IRQ2_VECTOR, },
156 [3] = { .vector = IRQ3_VECTOR, },
157 [4] = { .vector = IRQ4_VECTOR, },
158 [5] = { .vector = IRQ5_VECTOR, },
159 [6] = { .vector = IRQ6_VECTOR, },
160 [7] = { .vector = IRQ7_VECTOR, },
161 [8] = { .vector = IRQ8_VECTOR, },
162 [9] = { .vector = IRQ9_VECTOR, },
163 [10] = { .vector = IRQ10_VECTOR, },
164 [11] = { .vector = IRQ11_VECTOR, },
165 [12] = { .vector = IRQ12_VECTOR, },
166 [13] = { .vector = IRQ13_VECTOR, },
167 [14] = { .vector = IRQ14_VECTOR, },
168 [15] = { .vector = IRQ15_VECTOR, },
171 int __init arch_early_irq_init(void)
174 struct irq_desc *desc;
180 count = ARRAY_SIZE(irq_cfgx);
181 node= cpu_to_node(boot_cpu_id);
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
186 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
187 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
188 if (i < NR_IRQS_LEGACY)
189 cpumask_setall(cfg[i].domain);
195 #ifdef CONFIG_SPARSE_IRQ
196 static struct irq_cfg *irq_cfg(unsigned int irq)
198 struct irq_cfg *cfg = NULL;
199 struct irq_desc *desc;
201 desc = irq_to_desc(irq);
203 cfg = desc->chip_data;
208 static struct irq_cfg *get_one_free_irq_cfg(int node)
212 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
214 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
217 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
219 free_cpumask_var(cfg->domain);
223 cpumask_clear(cfg->domain);
224 cpumask_clear(cfg->old_domain);
231 int arch_init_chip_data(struct irq_desc *desc, int node)
235 cfg = desc->chip_data;
237 desc->chip_data = get_one_free_irq_cfg(node);
238 if (!desc->chip_data) {
239 printk(KERN_ERR "can not alloc irq_cfg\n");
247 /* for move_irq_desc */
249 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
251 struct irq_pin_list *old_entry, *head, *tail, *entry;
253 cfg->irq_2_pin = NULL;
254 old_entry = old_cfg->irq_2_pin;
258 entry = get_one_free_irq_2_pin(node);
262 entry->apic = old_entry->apic;
263 entry->pin = old_entry->pin;
266 old_entry = old_entry->next;
268 entry = get_one_free_irq_2_pin(node);
276 /* still use the old one */
279 entry->apic = old_entry->apic;
280 entry->pin = old_entry->pin;
283 old_entry = old_entry->next;
287 cfg->irq_2_pin = head;
290 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
292 struct irq_pin_list *entry, *next;
294 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
297 entry = old_cfg->irq_2_pin;
304 old_cfg->irq_2_pin = NULL;
307 void arch_init_copy_chip_data(struct irq_desc *old_desc,
308 struct irq_desc *desc, int node)
311 struct irq_cfg *old_cfg;
313 cfg = get_one_free_irq_cfg(node);
318 desc->chip_data = cfg;
320 old_cfg = old_desc->chip_data;
322 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
324 init_copy_irq_2_pin(old_cfg, cfg, node);
327 static void free_irq_cfg(struct irq_cfg *old_cfg)
332 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
334 struct irq_cfg *old_cfg, *cfg;
336 old_cfg = old_desc->chip_data;
337 cfg = desc->chip_data;
343 free_irq_2_pin(old_cfg, cfg);
344 free_irq_cfg(old_cfg);
345 old_desc->chip_data = NULL;
348 /* end for move_irq_desc */
351 static struct irq_cfg *irq_cfg(unsigned int irq)
353 return irq < nr_irqs ? irq_cfgx + irq : NULL;
360 unsigned int unused[3];
362 unsigned int unused2[11];
366 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
368 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
369 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
372 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
374 struct io_apic __iomem *io_apic = io_apic_base(apic);
375 writel(vector, &io_apic->eoi);
378 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
380 struct io_apic __iomem *io_apic = io_apic_base(apic);
381 writel(reg, &io_apic->index);
382 return readl(&io_apic->data);
385 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
387 struct io_apic __iomem *io_apic = io_apic_base(apic);
388 writel(reg, &io_apic->index);
389 writel(value, &io_apic->data);
393 * Re-write a value: to be used for read-modify-write
394 * cycles where the read already set up the index register.
396 * Older SiS APIC requires we rewrite the index register
398 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
400 struct io_apic __iomem *io_apic = io_apic_base(apic);
403 writel(reg, &io_apic->index);
404 writel(value, &io_apic->data);
407 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
409 struct irq_pin_list *entry;
412 spin_lock_irqsave(&ioapic_lock, flags);
413 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
418 reg = io_apic_read(entry->apic, 0x10 + pin*2);
419 /* Is the remote IRR bit set? */
420 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
421 spin_unlock_irqrestore(&ioapic_lock, flags);
425 spin_unlock_irqrestore(&ioapic_lock, flags);
431 struct { u32 w1, w2; };
432 struct IO_APIC_route_entry entry;
435 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
437 union entry_union eu;
439 spin_lock_irqsave(&ioapic_lock, flags);
440 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
441 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
442 spin_unlock_irqrestore(&ioapic_lock, flags);
447 * When we write a new IO APIC routing entry, we need to write the high
448 * word first! If the mask bit in the low word is clear, we will enable
449 * the interrupt, and we need to make sure the entry is fully populated
450 * before that happens.
453 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
455 union entry_union eu = {{0, 0}};
458 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
459 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
462 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
465 spin_lock_irqsave(&ioapic_lock, flags);
466 __ioapic_write_entry(apic, pin, e);
467 spin_unlock_irqrestore(&ioapic_lock, flags);
471 * When we mask an IO APIC routing entry, we need to write the low
472 * word first, in order to set the mask bit before we change the
475 static void ioapic_mask_entry(int apic, int pin)
478 union entry_union eu = { .entry.mask = 1 };
480 spin_lock_irqsave(&ioapic_lock, flags);
481 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
482 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
483 spin_unlock_irqrestore(&ioapic_lock, flags);
487 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
488 * shared ISA-space IRQs, so we have to support them. We are super
489 * fast in the common case, and fast for shared ISA-space IRQs.
491 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
493 struct irq_pin_list *entry;
495 entry = cfg->irq_2_pin;
497 entry = get_one_free_irq_2_pin(node);
499 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
503 cfg->irq_2_pin = entry;
509 while (entry->next) {
510 /* not again, please */
511 if (entry->apic == apic && entry->pin == pin)
517 entry->next = get_one_free_irq_2_pin(node);
524 * Reroute an IRQ to a different pin.
526 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
527 int oldapic, int oldpin,
528 int newapic, int newpin)
530 struct irq_pin_list *entry = cfg->irq_2_pin;
534 if (entry->apic == oldapic && entry->pin == oldpin) {
535 entry->apic = newapic;
538 /* every one is different, right? */
544 /* why? call replace before add? */
546 add_pin_to_irq_node(cfg, node, newapic, newpin);
549 static void io_apic_modify_irq(struct irq_cfg *cfg,
550 int mask_and, int mask_or,
551 void (*final)(struct irq_pin_list *entry))
554 struct irq_pin_list *entry;
556 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
559 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
562 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
568 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
570 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
573 static void io_apic_sync(struct irq_pin_list *entry)
576 * Synchronize the IO-APIC and the CPU by doing
577 * a dummy read from the IO-APIC
579 struct io_apic __iomem *io_apic;
580 io_apic = io_apic_base(entry->apic);
581 readl(&io_apic->data);
584 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
586 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
589 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
591 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
592 IO_APIC_REDIR_MASKED, NULL);
595 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
597 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
598 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
601 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
603 struct irq_cfg *cfg = desc->chip_data;
608 spin_lock_irqsave(&ioapic_lock, flags);
609 __mask_IO_APIC_irq(cfg);
610 spin_unlock_irqrestore(&ioapic_lock, flags);
613 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
615 struct irq_cfg *cfg = desc->chip_data;
618 spin_lock_irqsave(&ioapic_lock, flags);
619 __unmask_IO_APIC_irq(cfg);
620 spin_unlock_irqrestore(&ioapic_lock, flags);
623 static void mask_IO_APIC_irq(unsigned int irq)
625 struct irq_desc *desc = irq_to_desc(irq);
627 mask_IO_APIC_irq_desc(desc);
629 static void unmask_IO_APIC_irq(unsigned int irq)
631 struct irq_desc *desc = irq_to_desc(irq);
633 unmask_IO_APIC_irq_desc(desc);
636 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
638 struct IO_APIC_route_entry entry;
640 /* Check delivery_mode to be sure we're not clearing an SMI pin */
641 entry = ioapic_read_entry(apic, pin);
642 if (entry.delivery_mode == dest_SMI)
645 * Disable it in the IO-APIC irq-routing table:
647 ioapic_mask_entry(apic, pin);
650 static void clear_IO_APIC (void)
654 for (apic = 0; apic < nr_ioapics; apic++)
655 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
656 clear_IO_APIC_pin(apic, pin);
661 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
662 * specific CPU-side IRQs.
666 static int pirq_entries[MAX_PIRQS] = {
667 [0 ... MAX_PIRQS - 1] = -1
670 static int __init ioapic_pirq_setup(char *str)
673 int ints[MAX_PIRQS+1];
675 get_options(str, ARRAY_SIZE(ints), ints);
677 apic_printk(APIC_VERBOSE, KERN_INFO
678 "PIRQ redirection, working around broken MP-BIOS.\n");
680 if (ints[0] < MAX_PIRQS)
683 for (i = 0; i < max; i++) {
684 apic_printk(APIC_VERBOSE, KERN_DEBUG
685 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
687 * PIRQs are mapped upside down, usually.
689 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
694 __setup("pirq=", ioapic_pirq_setup);
695 #endif /* CONFIG_X86_32 */
697 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
700 struct IO_APIC_route_entry **ioapic_entries;
702 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
707 for (apic = 0; apic < nr_ioapics; apic++) {
708 ioapic_entries[apic] =
709 kzalloc(sizeof(struct IO_APIC_route_entry) *
710 nr_ioapic_registers[apic], GFP_ATOMIC);
711 if (!ioapic_entries[apic])
715 return ioapic_entries;
719 kfree(ioapic_entries[apic]);
720 kfree(ioapic_entries);
726 * Saves all the IO-APIC RTE's
728 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
735 for (apic = 0; apic < nr_ioapics; apic++) {
736 if (!ioapic_entries[apic])
739 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
740 ioapic_entries[apic][pin] =
741 ioapic_read_entry(apic, pin);
748 * Mask all IO APIC entries.
750 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
757 for (apic = 0; apic < nr_ioapics; apic++) {
758 if (!ioapic_entries[apic])
761 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
762 struct IO_APIC_route_entry entry;
764 entry = ioapic_entries[apic][pin];
767 ioapic_write_entry(apic, pin, entry);
774 * Restore IO APIC entries which was saved in ioapic_entries.
776 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
783 for (apic = 0; apic < nr_ioapics; apic++) {
784 if (!ioapic_entries[apic])
787 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
788 ioapic_write_entry(apic, pin,
789 ioapic_entries[apic][pin]);
794 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
798 for (apic = 0; apic < nr_ioapics; apic++)
799 kfree(ioapic_entries[apic]);
801 kfree(ioapic_entries);
805 * Find the IRQ entry number of a certain pin.
807 static int find_irq_entry(int apic, int pin, int type)
811 for (i = 0; i < mp_irq_entries; i++)
812 if (mp_irqs[i].irqtype == type &&
813 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
814 mp_irqs[i].dstapic == MP_APIC_ALL) &&
815 mp_irqs[i].dstirq == pin)
822 * Find the pin to which IRQ[irq] (ISA) is connected
824 static int __init find_isa_irq_pin(int irq, int type)
828 for (i = 0; i < mp_irq_entries; i++) {
829 int lbus = mp_irqs[i].srcbus;
831 if (test_bit(lbus, mp_bus_not_pci) &&
832 (mp_irqs[i].irqtype == type) &&
833 (mp_irqs[i].srcbusirq == irq))
835 return mp_irqs[i].dstirq;
840 static int __init find_isa_irq_apic(int irq, int type)
844 for (i = 0; i < mp_irq_entries; i++) {
845 int lbus = mp_irqs[i].srcbus;
847 if (test_bit(lbus, mp_bus_not_pci) &&
848 (mp_irqs[i].irqtype == type) &&
849 (mp_irqs[i].srcbusirq == irq))
852 if (i < mp_irq_entries) {
854 for(apic = 0; apic < nr_ioapics; apic++) {
855 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
863 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
865 * EISA Edge/Level control register, ELCR
867 static int EISA_ELCR(unsigned int irq)
869 if (irq < NR_IRQS_LEGACY) {
870 unsigned int port = 0x4d0 + (irq >> 3);
871 return (inb(port) >> (irq & 7)) & 1;
873 apic_printk(APIC_VERBOSE, KERN_INFO
874 "Broken MPtable reports ISA irq %d\n", irq);
880 /* ISA interrupts are always polarity zero edge triggered,
881 * when listed as conforming in the MP table. */
883 #define default_ISA_trigger(idx) (0)
884 #define default_ISA_polarity(idx) (0)
886 /* EISA interrupts are always polarity zero and can be edge or level
887 * trigger depending on the ELCR value. If an interrupt is listed as
888 * EISA conforming in the MP table, that means its trigger type must
889 * be read in from the ELCR */
891 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
892 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
894 /* PCI interrupts are always polarity one level triggered,
895 * when listed as conforming in the MP table. */
897 #define default_PCI_trigger(idx) (1)
898 #define default_PCI_polarity(idx) (1)
900 /* MCA interrupts are always polarity zero level triggered,
901 * when listed as conforming in the MP table. */
903 #define default_MCA_trigger(idx) (1)
904 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
906 static int MPBIOS_polarity(int idx)
908 int bus = mp_irqs[idx].srcbus;
912 * Determine IRQ line polarity (high active or low active):
914 switch (mp_irqs[idx].irqflag & 3)
916 case 0: /* conforms, ie. bus-type dependent polarity */
917 if (test_bit(bus, mp_bus_not_pci))
918 polarity = default_ISA_polarity(idx);
920 polarity = default_PCI_polarity(idx);
922 case 1: /* high active */
927 case 2: /* reserved */
929 printk(KERN_WARNING "broken BIOS!!\n");
933 case 3: /* low active */
938 default: /* invalid */
940 printk(KERN_WARNING "broken BIOS!!\n");
948 static int MPBIOS_trigger(int idx)
950 int bus = mp_irqs[idx].srcbus;
954 * Determine IRQ trigger mode (edge or level sensitive):
956 switch ((mp_irqs[idx].irqflag>>2) & 3)
958 case 0: /* conforms, ie. bus-type dependent */
959 if (test_bit(bus, mp_bus_not_pci))
960 trigger = default_ISA_trigger(idx);
962 trigger = default_PCI_trigger(idx);
963 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
964 switch (mp_bus_id_to_type[bus]) {
965 case MP_BUS_ISA: /* ISA pin */
967 /* set before the switch */
970 case MP_BUS_EISA: /* EISA pin */
972 trigger = default_EISA_trigger(idx);
975 case MP_BUS_PCI: /* PCI pin */
977 /* set before the switch */
980 case MP_BUS_MCA: /* MCA pin */
982 trigger = default_MCA_trigger(idx);
987 printk(KERN_WARNING "broken BIOS!!\n");
999 case 2: /* reserved */
1001 printk(KERN_WARNING "broken BIOS!!\n");
1010 default: /* invalid */
1012 printk(KERN_WARNING "broken BIOS!!\n");
1020 static inline int irq_polarity(int idx)
1022 return MPBIOS_polarity(idx);
1025 static inline int irq_trigger(int idx)
1027 return MPBIOS_trigger(idx);
1030 int (*ioapic_renumber_irq)(int ioapic, int irq);
1031 static int pin_2_irq(int idx, int apic, int pin)
1034 int bus = mp_irqs[idx].srcbus;
1037 * Debugging check, we are in big trouble if this message pops up!
1039 if (mp_irqs[idx].dstirq != pin)
1040 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1042 if (test_bit(bus, mp_bus_not_pci)) {
1043 irq = mp_irqs[idx].srcbusirq;
1046 * PCI IRQs are mapped in order
1050 irq += nr_ioapic_registers[i++];
1053 * For MPS mode, so far only needed by ES7000 platform
1055 if (ioapic_renumber_irq)
1056 irq = ioapic_renumber_irq(apic, irq);
1059 #ifdef CONFIG_X86_32
1061 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1063 if ((pin >= 16) && (pin <= 23)) {
1064 if (pirq_entries[pin-16] != -1) {
1065 if (!pirq_entries[pin-16]) {
1066 apic_printk(APIC_VERBOSE, KERN_DEBUG
1067 "disabling PIRQ%d\n", pin-16);
1069 irq = pirq_entries[pin-16];
1070 apic_printk(APIC_VERBOSE, KERN_DEBUG
1071 "using PIRQ%d -> IRQ %d\n",
1082 * Find a specific PCI IRQ entry.
1083 * Not an __init, possibly needed by modules
1085 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1086 struct io_apic_irq_attr *irq_attr)
1088 int apic, i, best_guess = -1;
1090 apic_printk(APIC_DEBUG,
1091 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1093 if (test_bit(bus, mp_bus_not_pci)) {
1094 apic_printk(APIC_VERBOSE,
1095 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1098 for (i = 0; i < mp_irq_entries; i++) {
1099 int lbus = mp_irqs[i].srcbus;
1101 for (apic = 0; apic < nr_ioapics; apic++)
1102 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1103 mp_irqs[i].dstapic == MP_APIC_ALL)
1106 if (!test_bit(lbus, mp_bus_not_pci) &&
1107 !mp_irqs[i].irqtype &&
1109 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1110 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1112 if (!(apic || IO_APIC_IRQ(irq)))
1115 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1116 set_io_apic_irq_attr(irq_attr, apic,
1123 * Use the first all-but-pin matching entry as a
1124 * best-guess fuzzy result for broken mptables.
1126 if (best_guess < 0) {
1127 set_io_apic_irq_attr(irq_attr, apic,
1137 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1139 void lock_vector_lock(void)
1141 /* Used to the online set of cpus does not change
1142 * during assign_irq_vector.
1144 spin_lock(&vector_lock);
1147 void unlock_vector_lock(void)
1149 spin_unlock(&vector_lock);
1153 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1156 * NOTE! The local APIC isn't very good at handling
1157 * multiple interrupts at the same interrupt level.
1158 * As the interrupt level is determined by taking the
1159 * vector number and shifting that right by 4, we
1160 * want to spread these out a bit so that they don't
1161 * all fall in the same interrupt level.
1163 * Also, we've got to be careful not to trash gate
1164 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1166 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1167 unsigned int old_vector;
1169 cpumask_var_t tmp_mask;
1171 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1174 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1177 old_vector = cfg->vector;
1179 cpumask_and(tmp_mask, mask, cpu_online_mask);
1180 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1181 if (!cpumask_empty(tmp_mask)) {
1182 free_cpumask_var(tmp_mask);
1187 /* Only try and allocate irqs on cpus that are present */
1189 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1193 apic->vector_allocation_domain(cpu, tmp_mask);
1195 vector = current_vector;
1196 offset = current_offset;
1199 if (vector >= first_system_vector) {
1200 /* If out of vectors on large boxen, must share them. */
1201 offset = (offset + 1) % 8;
1202 vector = FIRST_DEVICE_VECTOR + offset;
1204 if (unlikely(current_vector == vector))
1207 if (test_bit(vector, used_vectors))
1210 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1211 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1214 current_vector = vector;
1215 current_offset = offset;
1217 cfg->move_in_progress = 1;
1218 cpumask_copy(cfg->old_domain, cfg->domain);
1220 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1221 per_cpu(vector_irq, new_cpu)[vector] = irq;
1222 cfg->vector = vector;
1223 cpumask_copy(cfg->domain, tmp_mask);
1227 free_cpumask_var(tmp_mask);
1232 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1235 unsigned long flags;
1237 spin_lock_irqsave(&vector_lock, flags);
1238 err = __assign_irq_vector(irq, cfg, mask);
1239 spin_unlock_irqrestore(&vector_lock, flags);
1243 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1247 BUG_ON(!cfg->vector);
1249 vector = cfg->vector;
1250 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1251 per_cpu(vector_irq, cpu)[vector] = -1;
1254 cpumask_clear(cfg->domain);
1256 if (likely(!cfg->move_in_progress))
1258 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1259 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1261 if (per_cpu(vector_irq, cpu)[vector] != irq)
1263 per_cpu(vector_irq, cpu)[vector] = -1;
1267 cfg->move_in_progress = 0;
1270 void __setup_vector_irq(int cpu)
1272 /* Initialize vector_irq on a new cpu */
1273 /* This function must be called with vector_lock held */
1275 struct irq_cfg *cfg;
1276 struct irq_desc *desc;
1278 /* Mark the inuse vectors */
1279 for_each_irq_desc(irq, desc) {
1280 cfg = desc->chip_data;
1281 if (!cpumask_test_cpu(cpu, cfg->domain))
1283 vector = cfg->vector;
1284 per_cpu(vector_irq, cpu)[vector] = irq;
1286 /* Mark the free vectors */
1287 for (vector = 0; vector < NR_VECTORS; ++vector) {
1288 irq = per_cpu(vector_irq, cpu)[vector];
1293 if (!cpumask_test_cpu(cpu, cfg->domain))
1294 per_cpu(vector_irq, cpu)[vector] = -1;
1298 static struct irq_chip ioapic_chip;
1299 static struct irq_chip ir_ioapic_chip;
1301 #define IOAPIC_AUTO -1
1302 #define IOAPIC_EDGE 0
1303 #define IOAPIC_LEVEL 1
1305 #ifdef CONFIG_X86_32
1306 static inline int IO_APIC_irq_trigger(int irq)
1310 for (apic = 0; apic < nr_ioapics; apic++) {
1311 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1312 idx = find_irq_entry(apic, pin, mp_INT);
1313 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1314 return irq_trigger(idx);
1318 * nonexistent IRQs are edge default
1323 static inline int IO_APIC_irq_trigger(int irq)
1329 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1332 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1333 trigger == IOAPIC_LEVEL)
1334 desc->status |= IRQ_LEVEL;
1336 desc->status &= ~IRQ_LEVEL;
1338 if (irq_remapped(irq)) {
1339 desc->status |= IRQ_MOVE_PCNTXT;
1341 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1345 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1346 handle_edge_irq, "edge");
1350 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1351 trigger == IOAPIC_LEVEL)
1352 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1356 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1357 handle_edge_irq, "edge");
1360 int setup_ioapic_entry(int apic_id, int irq,
1361 struct IO_APIC_route_entry *entry,
1362 unsigned int destination, int trigger,
1363 int polarity, int vector, int pin)
1366 * add it to the IO-APIC irq-routing table:
1368 memset(entry,0,sizeof(*entry));
1370 if (intr_remapping_enabled) {
1371 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1373 struct IR_IO_APIC_route_entry *ir_entry =
1374 (struct IR_IO_APIC_route_entry *) entry;
1378 panic("No mapping iommu for ioapic %d\n", apic_id);
1380 index = alloc_irte(iommu, irq, 1);
1382 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1384 memset(&irte, 0, sizeof(irte));
1387 irte.dst_mode = apic->irq_dest_mode;
1389 * Trigger mode in the IRTE will always be edge, and the
1390 * actual level or edge trigger will be setup in the IO-APIC
1391 * RTE. This will help simplify level triggered irq migration.
1392 * For more details, see the comments above explainig IO-APIC
1393 * irq migration in the presence of interrupt-remapping.
1395 irte.trigger_mode = 0;
1396 irte.dlvry_mode = apic->irq_delivery_mode;
1397 irte.vector = vector;
1398 irte.dest_id = IRTE_DEST(destination);
1400 /* Set source-id of interrupt request */
1401 set_ioapic_sid(&irte, apic_id);
1403 modify_irte(irq, &irte);
1405 ir_entry->index2 = (index >> 15) & 0x1;
1407 ir_entry->format = 1;
1408 ir_entry->index = (index & 0x7fff);
1410 * IO-APIC RTE will be configured with virtual vector.
1411 * irq handler will do the explicit EOI to the io-apic.
1413 ir_entry->vector = pin;
1415 entry->delivery_mode = apic->irq_delivery_mode;
1416 entry->dest_mode = apic->irq_dest_mode;
1417 entry->dest = destination;
1418 entry->vector = vector;
1421 entry->mask = 0; /* enable IRQ */
1422 entry->trigger = trigger;
1423 entry->polarity = polarity;
1425 /* Mask level triggered irqs.
1426 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1433 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1434 int trigger, int polarity)
1436 struct irq_cfg *cfg;
1437 struct IO_APIC_route_entry entry;
1440 if (!IO_APIC_IRQ(irq))
1443 cfg = desc->chip_data;
1445 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1448 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1450 apic_printk(APIC_VERBOSE,KERN_DEBUG
1451 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1452 "IRQ %d Mode:%i Active:%i)\n",
1453 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1454 irq, trigger, polarity);
1457 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1458 dest, trigger, polarity, cfg->vector, pin)) {
1459 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1460 mp_ioapics[apic_id].apicid, pin);
1461 __clear_irq_vector(irq, cfg);
1465 ioapic_register_intr(irq, desc, trigger);
1466 if (irq < NR_IRQS_LEGACY)
1467 disable_8259A_irq(irq);
1469 ioapic_write_entry(apic_id, pin, entry);
1473 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1474 } mp_ioapic_routing[MAX_IO_APICS];
1476 static void __init setup_IO_APIC_irqs(void)
1478 int apic_id = 0, pin, idx, irq;
1480 struct irq_desc *desc;
1481 struct irq_cfg *cfg;
1482 int node = cpu_to_node(boot_cpu_id);
1484 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1487 if (!acpi_disabled && acpi_ioapic) {
1488 apic_id = mp_find_ioapic(0);
1494 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1495 idx = find_irq_entry(apic_id, pin, mp_INT);
1499 apic_printk(APIC_VERBOSE,
1500 KERN_DEBUG " %d-%d",
1501 mp_ioapics[apic_id].apicid, pin);
1503 apic_printk(APIC_VERBOSE, " %d-%d",
1504 mp_ioapics[apic_id].apicid, pin);
1508 apic_printk(APIC_VERBOSE,
1509 " (apicid-pin) not connected\n");
1513 irq = pin_2_irq(idx, apic_id, pin);
1516 * Skip the timer IRQ if there's a quirk handler
1517 * installed and if it returns 1:
1519 if (apic->multi_timer_check &&
1520 apic->multi_timer_check(apic_id, irq))
1523 desc = irq_to_desc_alloc_node(irq, node);
1525 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1528 cfg = desc->chip_data;
1529 add_pin_to_irq_node(cfg, node, apic_id, pin);
1531 * don't mark it in pin_programmed, so later acpi could
1532 * set it correctly when irq < 16
1534 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1535 irq_trigger(idx), irq_polarity(idx));
1539 apic_printk(APIC_VERBOSE,
1540 " (apicid-pin) not connected\n");
1544 * Set up the timer pin, possibly with the 8259A-master behind.
1546 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1549 struct IO_APIC_route_entry entry;
1551 if (intr_remapping_enabled)
1554 memset(&entry, 0, sizeof(entry));
1557 * We use logical delivery to get the timer IRQ
1560 entry.dest_mode = apic->irq_dest_mode;
1561 entry.mask = 0; /* don't mask IRQ for edge */
1562 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1563 entry.delivery_mode = apic->irq_delivery_mode;
1566 entry.vector = vector;
1569 * The timer IRQ doesn't have to know that behind the
1570 * scene we may have a 8259A-master in AEOI mode ...
1572 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1575 * Add it to the IO-APIC irq-routing table:
1577 ioapic_write_entry(apic_id, pin, entry);
1581 __apicdebuginit(void) print_IO_APIC(void)
1584 union IO_APIC_reg_00 reg_00;
1585 union IO_APIC_reg_01 reg_01;
1586 union IO_APIC_reg_02 reg_02;
1587 union IO_APIC_reg_03 reg_03;
1588 unsigned long flags;
1589 struct irq_cfg *cfg;
1590 struct irq_desc *desc;
1593 if (apic_verbosity == APIC_QUIET)
1596 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1597 for (i = 0; i < nr_ioapics; i++)
1598 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1599 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1602 * We are a bit conservative about what we expect. We have to
1603 * know about every hardware change ASAP.
1605 printk(KERN_INFO "testing the IO APIC.......................\n");
1607 for (apic = 0; apic < nr_ioapics; apic++) {
1609 spin_lock_irqsave(&ioapic_lock, flags);
1610 reg_00.raw = io_apic_read(apic, 0);
1611 reg_01.raw = io_apic_read(apic, 1);
1612 if (reg_01.bits.version >= 0x10)
1613 reg_02.raw = io_apic_read(apic, 2);
1614 if (reg_01.bits.version >= 0x20)
1615 reg_03.raw = io_apic_read(apic, 3);
1616 spin_unlock_irqrestore(&ioapic_lock, flags);
1619 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1620 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1621 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1622 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1623 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1625 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1626 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1628 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1629 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1632 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1633 * but the value of reg_02 is read as the previous read register
1634 * value, so ignore it if reg_02 == reg_01.
1636 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1637 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1638 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1642 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1643 * or reg_03, but the value of reg_0[23] is read as the previous read
1644 * register value, so ignore it if reg_03 == reg_0[12].
1646 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1647 reg_03.raw != reg_01.raw) {
1648 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1649 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1652 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1654 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1655 " Stat Dmod Deli Vect: \n");
1657 for (i = 0; i <= reg_01.bits.entries; i++) {
1658 struct IO_APIC_route_entry entry;
1660 entry = ioapic_read_entry(apic, i);
1662 printk(KERN_DEBUG " %02x %03X ",
1667 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1672 entry.delivery_status,
1674 entry.delivery_mode,
1679 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1680 for_each_irq_desc(irq, desc) {
1681 struct irq_pin_list *entry;
1683 cfg = desc->chip_data;
1684 entry = cfg->irq_2_pin;
1687 printk(KERN_DEBUG "IRQ%d ", irq);
1689 printk("-> %d:%d", entry->apic, entry->pin);
1692 entry = entry->next;
1697 printk(KERN_INFO ".................................... done.\n");
1702 __apicdebuginit(void) print_APIC_field(int base)
1706 if (apic_verbosity == APIC_QUIET)
1711 for (i = 0; i < 8; i++)
1712 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1714 printk(KERN_CONT "\n");
1717 __apicdebuginit(void) print_local_APIC(void *dummy)
1719 unsigned int i, v, ver, maxlvt;
1722 if (apic_verbosity == APIC_QUIET)
1725 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1726 smp_processor_id(), hard_smp_processor_id());
1727 v = apic_read(APIC_ID);
1728 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1729 v = apic_read(APIC_LVR);
1730 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1731 ver = GET_APIC_VERSION(v);
1732 maxlvt = lapic_get_maxlvt();
1734 v = apic_read(APIC_TASKPRI);
1735 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1737 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1738 if (!APIC_XAPIC(ver)) {
1739 v = apic_read(APIC_ARBPRI);
1740 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1741 v & APIC_ARBPRI_MASK);
1743 v = apic_read(APIC_PROCPRI);
1744 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1748 * Remote read supported only in the 82489DX and local APIC for
1749 * Pentium processors.
1751 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1752 v = apic_read(APIC_RRR);
1753 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1756 v = apic_read(APIC_LDR);
1757 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1758 if (!x2apic_enabled()) {
1759 v = apic_read(APIC_DFR);
1760 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1762 v = apic_read(APIC_SPIV);
1763 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1765 printk(KERN_DEBUG "... APIC ISR field:\n");
1766 print_APIC_field(APIC_ISR);
1767 printk(KERN_DEBUG "... APIC TMR field:\n");
1768 print_APIC_field(APIC_TMR);
1769 printk(KERN_DEBUG "... APIC IRR field:\n");
1770 print_APIC_field(APIC_IRR);
1772 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1773 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1774 apic_write(APIC_ESR, 0);
1776 v = apic_read(APIC_ESR);
1777 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1780 icr = apic_icr_read();
1781 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1782 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1784 v = apic_read(APIC_LVTT);
1785 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1787 if (maxlvt > 3) { /* PC is LVT#4. */
1788 v = apic_read(APIC_LVTPC);
1789 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1791 v = apic_read(APIC_LVT0);
1792 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1793 v = apic_read(APIC_LVT1);
1794 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1796 if (maxlvt > 2) { /* ERR is LVT#3. */
1797 v = apic_read(APIC_LVTERR);
1798 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1801 v = apic_read(APIC_TMICT);
1802 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1803 v = apic_read(APIC_TMCCT);
1804 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1805 v = apic_read(APIC_TDCR);
1806 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1808 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1809 v = apic_read(APIC_EFEAT);
1810 maxlvt = (v >> 16) & 0xff;
1811 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1812 v = apic_read(APIC_ECTRL);
1813 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1814 for (i = 0; i < maxlvt; i++) {
1815 v = apic_read(APIC_EILVTn(i));
1816 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1822 __apicdebuginit(void) print_all_local_APICs(void)
1827 for_each_online_cpu(cpu)
1828 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1832 __apicdebuginit(void) print_PIC(void)
1835 unsigned long flags;
1837 if (apic_verbosity == APIC_QUIET)
1840 printk(KERN_DEBUG "\nprinting PIC contents\n");
1842 spin_lock_irqsave(&i8259A_lock, flags);
1844 v = inb(0xa1) << 8 | inb(0x21);
1845 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1847 v = inb(0xa0) << 8 | inb(0x20);
1848 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1852 v = inb(0xa0) << 8 | inb(0x20);
1856 spin_unlock_irqrestore(&i8259A_lock, flags);
1858 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1860 v = inb(0x4d1) << 8 | inb(0x4d0);
1861 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1864 __apicdebuginit(int) print_all_ICs(void)
1868 /* don't print out if apic is not there */
1869 if (!cpu_has_apic || disable_apic)
1872 print_all_local_APICs();
1878 fs_initcall(print_all_ICs);
1881 /* Where if anywhere is the i8259 connect in external int mode */
1882 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1884 void __init enable_IO_APIC(void)
1886 union IO_APIC_reg_01 reg_01;
1887 int i8259_apic, i8259_pin;
1889 unsigned long flags;
1892 * The number of IO-APIC IRQ registers (== #pins):
1894 for (apic = 0; apic < nr_ioapics; apic++) {
1895 spin_lock_irqsave(&ioapic_lock, flags);
1896 reg_01.raw = io_apic_read(apic, 1);
1897 spin_unlock_irqrestore(&ioapic_lock, flags);
1898 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1900 for(apic = 0; apic < nr_ioapics; apic++) {
1902 /* See if any of the pins is in ExtINT mode */
1903 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1904 struct IO_APIC_route_entry entry;
1905 entry = ioapic_read_entry(apic, pin);
1907 /* If the interrupt line is enabled and in ExtInt mode
1908 * I have found the pin where the i8259 is connected.
1910 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1911 ioapic_i8259.apic = apic;
1912 ioapic_i8259.pin = pin;
1918 /* Look to see what if the MP table has reported the ExtINT */
1919 /* If we could not find the appropriate pin by looking at the ioapic
1920 * the i8259 probably is not connected the ioapic but give the
1921 * mptable a chance anyway.
1923 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1924 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1925 /* Trust the MP table if nothing is setup in the hardware */
1926 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1927 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1928 ioapic_i8259.pin = i8259_pin;
1929 ioapic_i8259.apic = i8259_apic;
1931 /* Complain if the MP table and the hardware disagree */
1932 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1933 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1935 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1939 * Do not trust the IO-APIC being empty at bootup
1945 * Not an __init, needed by the reboot code
1947 void disable_IO_APIC(void)
1950 * Clear the IO-APIC before rebooting:
1955 * If the i8259 is routed through an IOAPIC
1956 * Put that IOAPIC in virtual wire mode
1957 * so legacy interrupts can be delivered.
1959 * With interrupt-remapping, for now we will use virtual wire A mode,
1960 * as virtual wire B is little complex (need to configure both
1961 * IOAPIC RTE aswell as interrupt-remapping table entry).
1962 * As this gets called during crash dump, keep this simple for now.
1964 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1965 struct IO_APIC_route_entry entry;
1967 memset(&entry, 0, sizeof(entry));
1968 entry.mask = 0; /* Enabled */
1969 entry.trigger = 0; /* Edge */
1971 entry.polarity = 0; /* High */
1972 entry.delivery_status = 0;
1973 entry.dest_mode = 0; /* Physical */
1974 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1976 entry.dest = read_apic_id();
1979 * Add it to the IO-APIC irq-routing table:
1981 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1985 * Use virtual wire A mode when interrupt remapping is enabled.
1988 disconnect_bsp_APIC(!intr_remapping_enabled &&
1989 ioapic_i8259.pin != -1);
1992 #ifdef CONFIG_X86_32
1994 * function to set the IO-APIC physical IDs based on the
1995 * values stored in the MPC table.
1997 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2000 static void __init setup_ioapic_ids_from_mpc(void)
2002 union IO_APIC_reg_00 reg_00;
2003 physid_mask_t phys_id_present_map;
2006 unsigned char old_id;
2007 unsigned long flags;
2009 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2013 * Don't check I/O APIC IDs for xAPIC systems. They have
2014 * no meaning without the serial APIC bus.
2016 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2017 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2020 * This is broken; anything with a real cpu count has to
2021 * circumvent this idiocy regardless.
2023 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2026 * Set the IOAPIC ID to the value stored in the MPC table.
2028 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2030 /* Read the register 0 value */
2031 spin_lock_irqsave(&ioapic_lock, flags);
2032 reg_00.raw = io_apic_read(apic_id, 0);
2033 spin_unlock_irqrestore(&ioapic_lock, flags);
2035 old_id = mp_ioapics[apic_id].apicid;
2037 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2038 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2039 apic_id, mp_ioapics[apic_id].apicid);
2040 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2042 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2046 * Sanity check, is the ID really free? Every APIC in a
2047 * system must have a unique ID or we get lots of nice
2048 * 'stuck on smp_invalidate_needed IPI wait' messages.
2050 if (apic->check_apicid_used(phys_id_present_map,
2051 mp_ioapics[apic_id].apicid)) {
2052 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2053 apic_id, mp_ioapics[apic_id].apicid);
2054 for (i = 0; i < get_physical_broadcast(); i++)
2055 if (!physid_isset(i, phys_id_present_map))
2057 if (i >= get_physical_broadcast())
2058 panic("Max APIC ID exceeded!\n");
2059 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2061 physid_set(i, phys_id_present_map);
2062 mp_ioapics[apic_id].apicid = i;
2065 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2066 apic_printk(APIC_VERBOSE, "Setting %d in the "
2067 "phys_id_present_map\n",
2068 mp_ioapics[apic_id].apicid);
2069 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2074 * We need to adjust the IRQ routing table
2075 * if the ID changed.
2077 if (old_id != mp_ioapics[apic_id].apicid)
2078 for (i = 0; i < mp_irq_entries; i++)
2079 if (mp_irqs[i].dstapic == old_id)
2081 = mp_ioapics[apic_id].apicid;
2084 * Read the right value from the MPC table and
2085 * write it into the ID register.
2087 apic_printk(APIC_VERBOSE, KERN_INFO
2088 "...changing IO-APIC physical APIC ID to %d ...",
2089 mp_ioapics[apic_id].apicid);
2091 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2092 spin_lock_irqsave(&ioapic_lock, flags);
2093 io_apic_write(apic_id, 0, reg_00.raw);
2094 spin_unlock_irqrestore(&ioapic_lock, flags);
2099 spin_lock_irqsave(&ioapic_lock, flags);
2100 reg_00.raw = io_apic_read(apic_id, 0);
2101 spin_unlock_irqrestore(&ioapic_lock, flags);
2102 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2103 printk("could not set ID!\n");
2105 apic_printk(APIC_VERBOSE, " ok.\n");
2110 int no_timer_check __initdata;
2112 static int __init notimercheck(char *s)
2117 __setup("no_timer_check", notimercheck);
2120 * There is a nasty bug in some older SMP boards, their mptable lies
2121 * about the timer IRQ. We do the following to work around the situation:
2123 * - timer IRQ defaults to IO-APIC IRQ
2124 * - if this function detects that timer IRQs are defunct, then we fall
2125 * back to ISA timer IRQs
2127 static int __init timer_irq_works(void)
2129 unsigned long t1 = jiffies;
2130 unsigned long flags;
2135 local_save_flags(flags);
2137 /* Let ten ticks pass... */
2138 mdelay((10 * 1000) / HZ);
2139 local_irq_restore(flags);
2142 * Expect a few ticks at least, to be sure some possible
2143 * glue logic does not lock up after one or two first
2144 * ticks in a non-ExtINT mode. Also the local APIC
2145 * might have cached one ExtINT interrupt. Finally, at
2146 * least one tick may be lost due to delays.
2150 if (time_after(jiffies, t1 + 4))
2156 * In the SMP+IOAPIC case it might happen that there are an unspecified
2157 * number of pending IRQ events unhandled. These cases are very rare,
2158 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2159 * better to do it this way as thus we do not have to be aware of
2160 * 'pending' interrupts in the IRQ path, except at this point.
2163 * Edge triggered needs to resend any interrupt
2164 * that was delayed but this is now handled in the device
2169 * Starting up a edge-triggered IO-APIC interrupt is
2170 * nasty - we need to make sure that we get the edge.
2171 * If it is already asserted for some reason, we need
2172 * return 1 to indicate that is was pending.
2174 * This is not complete - we should be able to fake
2175 * an edge even if it isn't on the 8259A...
2178 static unsigned int startup_ioapic_irq(unsigned int irq)
2180 int was_pending = 0;
2181 unsigned long flags;
2182 struct irq_cfg *cfg;
2184 spin_lock_irqsave(&ioapic_lock, flags);
2185 if (irq < NR_IRQS_LEGACY) {
2186 disable_8259A_irq(irq);
2187 if (i8259A_irq_pending(irq))
2191 __unmask_IO_APIC_irq(cfg);
2192 spin_unlock_irqrestore(&ioapic_lock, flags);
2197 #ifdef CONFIG_X86_64
2198 static int ioapic_retrigger_irq(unsigned int irq)
2201 struct irq_cfg *cfg = irq_cfg(irq);
2202 unsigned long flags;
2204 spin_lock_irqsave(&vector_lock, flags);
2205 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2206 spin_unlock_irqrestore(&vector_lock, flags);
2211 static int ioapic_retrigger_irq(unsigned int irq)
2213 apic->send_IPI_self(irq_cfg(irq)->vector);
2220 * Level and edge triggered IO-APIC interrupts need different handling,
2221 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2222 * handled with the level-triggered descriptor, but that one has slightly
2223 * more overhead. Level-triggered interrupts cannot be handled with the
2224 * edge-triggered handler, without risking IRQ storms and other ugly
2229 static void send_cleanup_vector(struct irq_cfg *cfg)
2231 cpumask_var_t cleanup_mask;
2233 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2235 cfg->move_cleanup_count = 0;
2236 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2237 cfg->move_cleanup_count++;
2238 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2239 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2241 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2242 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2243 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2244 free_cpumask_var(cleanup_mask);
2246 cfg->move_in_progress = 0;
2249 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2252 struct irq_pin_list *entry;
2253 u8 vector = cfg->vector;
2255 entry = cfg->irq_2_pin;
2265 * With interrupt-remapping, destination information comes
2266 * from interrupt-remapping table entry.
2268 if (!irq_remapped(irq))
2269 io_apic_write(apic, 0x11 + pin*2, dest);
2270 reg = io_apic_read(apic, 0x10 + pin*2);
2271 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2273 io_apic_modify(apic, 0x10 + pin*2, reg);
2276 entry = entry->next;
2281 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2284 * Either sets desc->affinity to a valid value, and returns
2285 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2286 * leaves desc->affinity untouched.
2289 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2291 struct irq_cfg *cfg;
2294 if (!cpumask_intersects(mask, cpu_online_mask))
2298 cfg = desc->chip_data;
2299 if (assign_irq_vector(irq, cfg, mask))
2302 cpumask_copy(desc->affinity, mask);
2304 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2308 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2310 struct irq_cfg *cfg;
2311 unsigned long flags;
2317 cfg = desc->chip_data;
2319 spin_lock_irqsave(&ioapic_lock, flags);
2320 dest = set_desc_affinity(desc, mask);
2321 if (dest != BAD_APICID) {
2322 /* Only the high 8 bits are valid. */
2323 dest = SET_APIC_LOGICAL_ID(dest);
2324 __target_IO_APIC_irq(irq, dest, cfg);
2327 spin_unlock_irqrestore(&ioapic_lock, flags);
2333 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2335 struct irq_desc *desc;
2337 desc = irq_to_desc(irq);
2339 return set_ioapic_affinity_irq_desc(desc, mask);
2342 #ifdef CONFIG_INTR_REMAP
2345 * Migrate the IO-APIC irq in the presence of intr-remapping.
2347 * For both level and edge triggered, irq migration is a simple atomic
2348 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2350 * For level triggered, we eliminate the io-apic RTE modification (with the
2351 * updated vector information), by using a virtual vector (io-apic pin number).
2352 * Real vector that is used for interrupting cpu will be coming from
2353 * the interrupt-remapping table entry.
2356 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2358 struct irq_cfg *cfg;
2364 if (!cpumask_intersects(mask, cpu_online_mask))
2368 if (get_irte(irq, &irte))
2371 cfg = desc->chip_data;
2372 if (assign_irq_vector(irq, cfg, mask))
2375 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2377 irte.vector = cfg->vector;
2378 irte.dest_id = IRTE_DEST(dest);
2381 * Modified the IRTE and flushes the Interrupt entry cache.
2383 modify_irte(irq, &irte);
2385 if (cfg->move_in_progress)
2386 send_cleanup_vector(cfg);
2388 cpumask_copy(desc->affinity, mask);
2394 * Migrates the IRQ destination in the process context.
2396 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2397 const struct cpumask *mask)
2399 return migrate_ioapic_irq_desc(desc, mask);
2401 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2402 const struct cpumask *mask)
2404 struct irq_desc *desc = irq_to_desc(irq);
2406 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2409 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2410 const struct cpumask *mask)
2416 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2418 unsigned vector, me;
2424 me = smp_processor_id();
2425 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2428 struct irq_desc *desc;
2429 struct irq_cfg *cfg;
2430 irq = __get_cpu_var(vector_irq)[vector];
2435 desc = irq_to_desc(irq);
2440 spin_lock(&desc->lock);
2441 if (!cfg->move_cleanup_count)
2444 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2447 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2449 * Check if the vector that needs to be cleanedup is
2450 * registered at the cpu's IRR. If so, then this is not
2451 * the best time to clean it up. Lets clean it up in the
2452 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2455 if (irr & (1 << (vector % 32))) {
2456 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2459 __get_cpu_var(vector_irq)[vector] = -1;
2460 cfg->move_cleanup_count--;
2462 spin_unlock(&desc->lock);
2468 static void irq_complete_move(struct irq_desc **descp)
2470 struct irq_desc *desc = *descp;
2471 struct irq_cfg *cfg = desc->chip_data;
2472 unsigned vector, me;
2474 if (likely(!cfg->move_in_progress))
2477 vector = ~get_irq_regs()->orig_ax;
2478 me = smp_processor_id();
2480 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2481 send_cleanup_vector(cfg);
2484 static inline void irq_complete_move(struct irq_desc **descp) {}
2487 static void ack_apic_edge(unsigned int irq)
2489 struct irq_desc *desc = irq_to_desc(irq);
2491 irq_complete_move(&desc);
2492 move_native_irq(irq);
2496 atomic_t irq_mis_count;
2498 static void ack_apic_level(unsigned int irq)
2500 struct irq_desc *desc = irq_to_desc(irq);
2503 struct irq_cfg *cfg;
2504 int do_unmask_irq = 0;
2506 irq_complete_move(&desc);
2507 #ifdef CONFIG_GENERIC_PENDING_IRQ
2508 /* If we are moving the irq we need to mask it */
2509 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2511 mask_IO_APIC_irq_desc(desc);
2516 * It appears there is an erratum which affects at least version 0x11
2517 * of I/O APIC (that's the 82093AA and cores integrated into various
2518 * chipsets). Under certain conditions a level-triggered interrupt is
2519 * erroneously delivered as edge-triggered one but the respective IRR
2520 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2521 * message but it will never arrive and further interrupts are blocked
2522 * from the source. The exact reason is so far unknown, but the
2523 * phenomenon was observed when two consecutive interrupt requests
2524 * from a given source get delivered to the same CPU and the source is
2525 * temporarily disabled in between.
2527 * A workaround is to simulate an EOI message manually. We achieve it
2528 * by setting the trigger mode to edge and then to level when the edge
2529 * trigger mode gets detected in the TMR of a local APIC for a
2530 * level-triggered interrupt. We mask the source for the time of the
2531 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2532 * The idea is from Manfred Spraul. --macro
2534 cfg = desc->chip_data;
2536 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2539 * We must acknowledge the irq before we move it or the acknowledge will
2540 * not propagate properly.
2544 /* Now we can move and renable the irq */
2545 if (unlikely(do_unmask_irq)) {
2546 /* Only migrate the irq if the ack has been received.
2548 * On rare occasions the broadcast level triggered ack gets
2549 * delayed going to ioapics, and if we reprogram the
2550 * vector while Remote IRR is still set the irq will never
2553 * To prevent this scenario we read the Remote IRR bit
2554 * of the ioapic. This has two effects.
2555 * - On any sane system the read of the ioapic will
2556 * flush writes (and acks) going to the ioapic from
2558 * - We get to see if the ACK has actually been delivered.
2560 * Based on failed experiments of reprogramming the
2561 * ioapic entry from outside of irq context starting
2562 * with masking the ioapic entry and then polling until
2563 * Remote IRR was clear before reprogramming the
2564 * ioapic I don't trust the Remote IRR bit to be
2565 * completey accurate.
2567 * However there appears to be no other way to plug
2568 * this race, so if the Remote IRR bit is not
2569 * accurate and is causing problems then it is a hardware bug
2570 * and you can go talk to the chipset vendor about it.
2572 cfg = desc->chip_data;
2573 if (!io_apic_level_ack_pending(cfg))
2574 move_masked_irq(irq);
2575 unmask_IO_APIC_irq_desc(desc);
2578 /* Tail end of version 0x11 I/O APIC bug workaround */
2579 if (!(v & (1 << (i & 0x1f)))) {
2580 atomic_inc(&irq_mis_count);
2581 spin_lock(&ioapic_lock);
2582 __mask_and_edge_IO_APIC_irq(cfg);
2583 __unmask_and_level_IO_APIC_irq(cfg);
2584 spin_unlock(&ioapic_lock);
2588 #ifdef CONFIG_INTR_REMAP
2589 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2592 struct irq_pin_list *entry;
2594 entry = cfg->irq_2_pin;
2602 io_apic_eoi(apic, pin);
2603 entry = entry->next;
2608 eoi_ioapic_irq(struct irq_desc *desc)
2610 struct irq_cfg *cfg;
2611 unsigned long flags;
2615 cfg = desc->chip_data;
2617 spin_lock_irqsave(&ioapic_lock, flags);
2618 __eoi_ioapic_irq(irq, cfg);
2619 spin_unlock_irqrestore(&ioapic_lock, flags);
2622 static void ir_ack_apic_edge(unsigned int irq)
2627 static void ir_ack_apic_level(unsigned int irq)
2629 struct irq_desc *desc = irq_to_desc(irq);
2632 eoi_ioapic_irq(desc);
2634 #endif /* CONFIG_INTR_REMAP */
2636 static struct irq_chip ioapic_chip __read_mostly = {
2638 .startup = startup_ioapic_irq,
2639 .mask = mask_IO_APIC_irq,
2640 .unmask = unmask_IO_APIC_irq,
2641 .ack = ack_apic_edge,
2642 .eoi = ack_apic_level,
2644 .set_affinity = set_ioapic_affinity_irq,
2646 .retrigger = ioapic_retrigger_irq,
2649 static struct irq_chip ir_ioapic_chip __read_mostly = {
2650 .name = "IR-IO-APIC",
2651 .startup = startup_ioapic_irq,
2652 .mask = mask_IO_APIC_irq,
2653 .unmask = unmask_IO_APIC_irq,
2654 #ifdef CONFIG_INTR_REMAP
2655 .ack = ir_ack_apic_edge,
2656 .eoi = ir_ack_apic_level,
2658 .set_affinity = set_ir_ioapic_affinity_irq,
2661 .retrigger = ioapic_retrigger_irq,
2664 static inline void init_IO_APIC_traps(void)
2667 struct irq_desc *desc;
2668 struct irq_cfg *cfg;
2671 * NOTE! The local APIC isn't very good at handling
2672 * multiple interrupts at the same interrupt level.
2673 * As the interrupt level is determined by taking the
2674 * vector number and shifting that right by 4, we
2675 * want to spread these out a bit so that they don't
2676 * all fall in the same interrupt level.
2678 * Also, we've got to be careful not to trash gate
2679 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2681 for_each_irq_desc(irq, desc) {
2682 cfg = desc->chip_data;
2683 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2685 * Hmm.. We don't have an entry for this,
2686 * so default to an old-fashioned 8259
2687 * interrupt if we can..
2689 if (irq < NR_IRQS_LEGACY)
2690 make_8259A_irq(irq);
2692 /* Strange. Oh, well.. */
2693 desc->chip = &no_irq_chip;
2699 * The local APIC irq-chip implementation:
2702 static void mask_lapic_irq(unsigned int irq)
2706 v = apic_read(APIC_LVT0);
2707 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2710 static void unmask_lapic_irq(unsigned int irq)
2714 v = apic_read(APIC_LVT0);
2715 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2718 static void ack_lapic_irq(unsigned int irq)
2723 static struct irq_chip lapic_chip __read_mostly = {
2724 .name = "local-APIC",
2725 .mask = mask_lapic_irq,
2726 .unmask = unmask_lapic_irq,
2727 .ack = ack_lapic_irq,
2730 static void lapic_register_intr(int irq, struct irq_desc *desc)
2732 desc->status &= ~IRQ_LEVEL;
2733 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2737 static void __init setup_nmi(void)
2740 * Dirty trick to enable the NMI watchdog ...
2741 * We put the 8259A master into AEOI mode and
2742 * unmask on all local APICs LVT0 as NMI.
2744 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2745 * is from Maciej W. Rozycki - so we do not have to EOI from
2746 * the NMI handler or the timer interrupt.
2748 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2750 enable_NMI_through_LVT0();
2752 apic_printk(APIC_VERBOSE, " done.\n");
2756 * This looks a bit hackish but it's about the only one way of sending
2757 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2758 * not support the ExtINT mode, unfortunately. We need to send these
2759 * cycles as some i82489DX-based boards have glue logic that keeps the
2760 * 8259A interrupt line asserted until INTA. --macro
2762 static inline void __init unlock_ExtINT_logic(void)
2765 struct IO_APIC_route_entry entry0, entry1;
2766 unsigned char save_control, save_freq_select;
2768 pin = find_isa_irq_pin(8, mp_INT);
2773 apic = find_isa_irq_apic(8, mp_INT);
2779 entry0 = ioapic_read_entry(apic, pin);
2780 clear_IO_APIC_pin(apic, pin);
2782 memset(&entry1, 0, sizeof(entry1));
2784 entry1.dest_mode = 0; /* physical delivery */
2785 entry1.mask = 0; /* unmask IRQ now */
2786 entry1.dest = hard_smp_processor_id();
2787 entry1.delivery_mode = dest_ExtINT;
2788 entry1.polarity = entry0.polarity;
2792 ioapic_write_entry(apic, pin, entry1);
2794 save_control = CMOS_READ(RTC_CONTROL);
2795 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2796 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2798 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2803 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2807 CMOS_WRITE(save_control, RTC_CONTROL);
2808 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2809 clear_IO_APIC_pin(apic, pin);
2811 ioapic_write_entry(apic, pin, entry0);
2814 static int disable_timer_pin_1 __initdata;
2815 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2816 static int __init disable_timer_pin_setup(char *arg)
2818 disable_timer_pin_1 = 1;
2821 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2823 int timer_through_8259 __initdata;
2826 * This code may look a bit paranoid, but it's supposed to cooperate with
2827 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2828 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2829 * fanatically on his truly buggy board.
2831 * FIXME: really need to revamp this for all platforms.
2833 static inline void __init check_timer(void)
2835 struct irq_desc *desc = irq_to_desc(0);
2836 struct irq_cfg *cfg = desc->chip_data;
2837 int node = cpu_to_node(boot_cpu_id);
2838 int apic1, pin1, apic2, pin2;
2839 unsigned long flags;
2842 local_irq_save(flags);
2845 * get/set the timer IRQ vector:
2847 disable_8259A_irq(0);
2848 assign_irq_vector(0, cfg, apic->target_cpus());
2851 * As IRQ0 is to be enabled in the 8259A, the virtual
2852 * wire has to be disabled in the local APIC. Also
2853 * timer interrupts need to be acknowledged manually in
2854 * the 8259A for the i82489DX when using the NMI
2855 * watchdog as that APIC treats NMIs as level-triggered.
2856 * The AEOI mode will finish them in the 8259A
2859 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2861 #ifdef CONFIG_X86_32
2865 ver = apic_read(APIC_LVR);
2866 ver = GET_APIC_VERSION(ver);
2867 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2871 pin1 = find_isa_irq_pin(0, mp_INT);
2872 apic1 = find_isa_irq_apic(0, mp_INT);
2873 pin2 = ioapic_i8259.pin;
2874 apic2 = ioapic_i8259.apic;
2876 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2877 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2878 cfg->vector, apic1, pin1, apic2, pin2);
2881 * Some BIOS writers are clueless and report the ExtINTA
2882 * I/O APIC input from the cascaded 8259A as the timer
2883 * interrupt input. So just in case, if only one pin
2884 * was found above, try it both directly and through the
2888 if (intr_remapping_enabled)
2889 panic("BIOS bug: timer not connected to IO-APIC");
2893 } else if (pin2 == -1) {
2900 * Ok, does IRQ0 through the IOAPIC work?
2903 add_pin_to_irq_node(cfg, node, apic1, pin1);
2904 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2906 /* for edge trigger, setup_IO_APIC_irq already
2907 * leave it unmasked.
2908 * so only need to unmask if it is level-trigger
2909 * do we really have level trigger timer?
2912 idx = find_irq_entry(apic1, pin1, mp_INT);
2913 if (idx != -1 && irq_trigger(idx))
2914 unmask_IO_APIC_irq_desc(desc);
2916 if (timer_irq_works()) {
2917 if (nmi_watchdog == NMI_IO_APIC) {
2919 enable_8259A_irq(0);
2921 if (disable_timer_pin_1 > 0)
2922 clear_IO_APIC_pin(0, pin1);
2925 if (intr_remapping_enabled)
2926 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2927 local_irq_disable();
2928 clear_IO_APIC_pin(apic1, pin1);
2930 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2931 "8254 timer not connected to IO-APIC\n");
2933 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2934 "(IRQ0) through the 8259A ...\n");
2935 apic_printk(APIC_QUIET, KERN_INFO
2936 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2938 * legacy devices should be connected to IO APIC #0
2940 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2941 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2942 enable_8259A_irq(0);
2943 if (timer_irq_works()) {
2944 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2945 timer_through_8259 = 1;
2946 if (nmi_watchdog == NMI_IO_APIC) {
2947 disable_8259A_irq(0);
2949 enable_8259A_irq(0);
2954 * Cleanup, just in case ...
2956 local_irq_disable();
2957 disable_8259A_irq(0);
2958 clear_IO_APIC_pin(apic2, pin2);
2959 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2962 if (nmi_watchdog == NMI_IO_APIC) {
2963 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2964 "through the IO-APIC - disabling NMI Watchdog!\n");
2965 nmi_watchdog = NMI_NONE;
2967 #ifdef CONFIG_X86_32
2971 apic_printk(APIC_QUIET, KERN_INFO
2972 "...trying to set up timer as Virtual Wire IRQ...\n");
2974 lapic_register_intr(0, desc);
2975 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2976 enable_8259A_irq(0);
2978 if (timer_irq_works()) {
2979 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2982 local_irq_disable();
2983 disable_8259A_irq(0);
2984 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2985 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2987 apic_printk(APIC_QUIET, KERN_INFO
2988 "...trying to set up timer as ExtINT IRQ...\n");
2992 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2994 unlock_ExtINT_logic();
2996 if (timer_irq_works()) {
2997 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3000 local_irq_disable();
3001 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3002 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3003 "report. Then try booting with the 'noapic' option.\n");
3005 local_irq_restore(flags);
3009 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3010 * to devices. However there may be an I/O APIC pin available for
3011 * this interrupt regardless. The pin may be left unconnected, but
3012 * typically it will be reused as an ExtINT cascade interrupt for
3013 * the master 8259A. In the MPS case such a pin will normally be
3014 * reported as an ExtINT interrupt in the MP table. With ACPI
3015 * there is no provision for ExtINT interrupts, and in the absence
3016 * of an override it would be treated as an ordinary ISA I/O APIC
3017 * interrupt, that is edge-triggered and unmasked by default. We
3018 * used to do this, but it caused problems on some systems because
3019 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3020 * the same ExtINT cascade interrupt to drive the local APIC of the
3021 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3022 * the I/O APIC in all cases now. No actual device should request
3023 * it anyway. --macro
3025 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3027 void __init setup_IO_APIC(void)
3031 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3034 io_apic_irqs = ~PIC_IRQS;
3036 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3038 * Set up IO-APIC IRQ routing.
3040 #ifdef CONFIG_X86_32
3042 setup_ioapic_ids_from_mpc();
3045 setup_IO_APIC_irqs();
3046 init_IO_APIC_traps();
3051 * Called after all the initialization is done. If we didnt find any
3052 * APIC bugs then we can allow the modify fast path
3055 static int __init io_apic_bug_finalize(void)
3057 if (sis_apic_bug == -1)
3062 late_initcall(io_apic_bug_finalize);
3064 struct sysfs_ioapic_data {
3065 struct sys_device dev;
3066 struct IO_APIC_route_entry entry[0];
3068 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3070 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3072 struct IO_APIC_route_entry *entry;
3073 struct sysfs_ioapic_data *data;
3076 data = container_of(dev, struct sysfs_ioapic_data, dev);
3077 entry = data->entry;
3078 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3079 *entry = ioapic_read_entry(dev->id, i);
3084 static int ioapic_resume(struct sys_device *dev)
3086 struct IO_APIC_route_entry *entry;
3087 struct sysfs_ioapic_data *data;
3088 unsigned long flags;
3089 union IO_APIC_reg_00 reg_00;
3092 data = container_of(dev, struct sysfs_ioapic_data, dev);
3093 entry = data->entry;
3095 spin_lock_irqsave(&ioapic_lock, flags);
3096 reg_00.raw = io_apic_read(dev->id, 0);
3097 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3098 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3099 io_apic_write(dev->id, 0, reg_00.raw);
3101 spin_unlock_irqrestore(&ioapic_lock, flags);
3102 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3103 ioapic_write_entry(dev->id, i, entry[i]);
3108 static struct sysdev_class ioapic_sysdev_class = {
3110 .suspend = ioapic_suspend,
3111 .resume = ioapic_resume,
3114 static int __init ioapic_init_sysfs(void)
3116 struct sys_device * dev;
3119 error = sysdev_class_register(&ioapic_sysdev_class);
3123 for (i = 0; i < nr_ioapics; i++ ) {
3124 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3125 * sizeof(struct IO_APIC_route_entry);
3126 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3127 if (!mp_ioapic_data[i]) {
3128 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3131 dev = &mp_ioapic_data[i]->dev;
3133 dev->cls = &ioapic_sysdev_class;
3134 error = sysdev_register(dev);
3136 kfree(mp_ioapic_data[i]);
3137 mp_ioapic_data[i] = NULL;
3138 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3146 device_initcall(ioapic_init_sysfs);
3148 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3150 * Dynamic irq allocate and deallocation
3152 unsigned int create_irq_nr(unsigned int irq_want, int node)
3154 /* Allocate an unused irq */
3157 unsigned long flags;
3158 struct irq_cfg *cfg_new = NULL;
3159 struct irq_desc *desc_new = NULL;
3162 if (irq_want < nr_irqs_gsi)
3163 irq_want = nr_irqs_gsi;
3165 spin_lock_irqsave(&vector_lock, flags);
3166 for (new = irq_want; new < nr_irqs; new++) {
3167 desc_new = irq_to_desc_alloc_node(new, node);
3169 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3172 cfg_new = desc_new->chip_data;
3174 if (cfg_new->vector != 0)
3177 desc_new = move_irq_desc(desc_new, node);
3179 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3183 spin_unlock_irqrestore(&vector_lock, flags);
3186 dynamic_irq_init(irq);
3187 /* restore it, in case dynamic_irq_init clear it */
3189 desc_new->chip_data = cfg_new;
3194 int create_irq(void)
3196 int node = cpu_to_node(boot_cpu_id);
3197 unsigned int irq_want;
3200 irq_want = nr_irqs_gsi;
3201 irq = create_irq_nr(irq_want, node);
3209 void destroy_irq(unsigned int irq)
3211 unsigned long flags;
3212 struct irq_cfg *cfg;
3213 struct irq_desc *desc;
3215 /* store it, in case dynamic_irq_cleanup clear it */
3216 desc = irq_to_desc(irq);
3217 cfg = desc->chip_data;
3218 dynamic_irq_cleanup(irq);
3219 /* connect back irq_cfg */
3221 desc->chip_data = cfg;
3224 spin_lock_irqsave(&vector_lock, flags);
3225 __clear_irq_vector(irq, cfg);
3226 spin_unlock_irqrestore(&vector_lock, flags);
3230 * MSI message composition
3232 #ifdef CONFIG_PCI_MSI
3233 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3235 struct irq_cfg *cfg;
3243 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3247 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3249 if (irq_remapped(irq)) {
3254 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3255 BUG_ON(ir_index == -1);
3257 memset (&irte, 0, sizeof(irte));
3260 irte.dst_mode = apic->irq_dest_mode;
3261 irte.trigger_mode = 0; /* edge */
3262 irte.dlvry_mode = apic->irq_delivery_mode;
3263 irte.vector = cfg->vector;
3264 irte.dest_id = IRTE_DEST(dest);
3266 /* Set source-id of interrupt request */
3267 set_msi_sid(&irte, pdev);
3269 modify_irte(irq, &irte);
3271 msg->address_hi = MSI_ADDR_BASE_HI;
3272 msg->data = sub_handle;
3273 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3275 MSI_ADDR_IR_INDEX1(ir_index) |
3276 MSI_ADDR_IR_INDEX2(ir_index);
3278 if (x2apic_enabled())
3279 msg->address_hi = MSI_ADDR_BASE_HI |
3280 MSI_ADDR_EXT_DEST_ID(dest);
3282 msg->address_hi = MSI_ADDR_BASE_HI;
3286 ((apic->irq_dest_mode == 0) ?
3287 MSI_ADDR_DEST_MODE_PHYSICAL:
3288 MSI_ADDR_DEST_MODE_LOGICAL) |
3289 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3290 MSI_ADDR_REDIRECTION_CPU:
3291 MSI_ADDR_REDIRECTION_LOWPRI) |
3292 MSI_ADDR_DEST_ID(dest);
3295 MSI_DATA_TRIGGER_EDGE |
3296 MSI_DATA_LEVEL_ASSERT |
3297 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3298 MSI_DATA_DELIVERY_FIXED:
3299 MSI_DATA_DELIVERY_LOWPRI) |
3300 MSI_DATA_VECTOR(cfg->vector);
3306 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3308 struct irq_desc *desc = irq_to_desc(irq);
3309 struct irq_cfg *cfg;
3313 dest = set_desc_affinity(desc, mask);
3314 if (dest == BAD_APICID)
3317 cfg = desc->chip_data;
3319 read_msi_msg_desc(desc, &msg);
3321 msg.data &= ~MSI_DATA_VECTOR_MASK;
3322 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3323 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3324 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3326 write_msi_msg_desc(desc, &msg);
3330 #ifdef CONFIG_INTR_REMAP
3332 * Migrate the MSI irq to another cpumask. This migration is
3333 * done in the process context using interrupt-remapping hardware.
3336 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3338 struct irq_desc *desc = irq_to_desc(irq);
3339 struct irq_cfg *cfg = desc->chip_data;
3343 if (get_irte(irq, &irte))
3346 dest = set_desc_affinity(desc, mask);
3347 if (dest == BAD_APICID)
3350 irte.vector = cfg->vector;
3351 irte.dest_id = IRTE_DEST(dest);
3354 * atomically update the IRTE with the new destination and vector.
3356 modify_irte(irq, &irte);
3359 * After this point, all the interrupts will start arriving
3360 * at the new destination. So, time to cleanup the previous
3361 * vector allocation.
3363 if (cfg->move_in_progress)
3364 send_cleanup_vector(cfg);
3370 #endif /* CONFIG_SMP */
3373 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3374 * which implement the MSI or MSI-X Capability Structure.
3376 static struct irq_chip msi_chip = {
3378 .unmask = unmask_msi_irq,
3379 .mask = mask_msi_irq,
3380 .ack = ack_apic_edge,
3382 .set_affinity = set_msi_irq_affinity,
3384 .retrigger = ioapic_retrigger_irq,
3387 static struct irq_chip msi_ir_chip = {
3388 .name = "IR-PCI-MSI",
3389 .unmask = unmask_msi_irq,
3390 .mask = mask_msi_irq,
3391 #ifdef CONFIG_INTR_REMAP
3392 .ack = ir_ack_apic_edge,
3394 .set_affinity = ir_set_msi_irq_affinity,
3397 .retrigger = ioapic_retrigger_irq,
3401 * Map the PCI dev to the corresponding remapping hardware unit
3402 * and allocate 'nvec' consecutive interrupt-remapping table entries
3405 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3407 struct intel_iommu *iommu;
3410 iommu = map_dev_to_ir(dev);
3413 "Unable to map PCI %s to iommu\n", pci_name(dev));
3417 index = alloc_irte(iommu, irq, nvec);
3420 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3427 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3432 ret = msi_compose_msg(dev, irq, &msg);
3436 set_irq_msi(irq, msidesc);
3437 write_msi_msg(irq, &msg);
3439 if (irq_remapped(irq)) {
3440 struct irq_desc *desc = irq_to_desc(irq);
3442 * irq migration in process context
3444 desc->status |= IRQ_MOVE_PCNTXT;
3445 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3447 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3449 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3454 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3457 int ret, sub_handle;
3458 struct msi_desc *msidesc;
3459 unsigned int irq_want;
3460 struct intel_iommu *iommu = NULL;
3464 /* x86 doesn't support multiple MSI yet */
3465 if (type == PCI_CAP_ID_MSI && nvec > 1)
3468 node = dev_to_node(&dev->dev);
3469 irq_want = nr_irqs_gsi;
3471 list_for_each_entry(msidesc, &dev->msi_list, list) {
3472 irq = create_irq_nr(irq_want, node);
3476 if (!intr_remapping_enabled)
3481 * allocate the consecutive block of IRTE's
3484 index = msi_alloc_irte(dev, irq, nvec);
3490 iommu = map_dev_to_ir(dev);
3496 * setup the mapping between the irq and the IRTE
3497 * base index, the sub_handle pointing to the
3498 * appropriate interrupt remap table entry.
3500 set_irte_irq(irq, iommu, index, sub_handle);
3503 ret = setup_msi_irq(dev, msidesc, irq);
3515 void arch_teardown_msi_irq(unsigned int irq)
3520 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3522 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3524 struct irq_desc *desc = irq_to_desc(irq);
3525 struct irq_cfg *cfg;
3529 dest = set_desc_affinity(desc, mask);
3530 if (dest == BAD_APICID)
3533 cfg = desc->chip_data;
3535 dmar_msi_read(irq, &msg);
3537 msg.data &= ~MSI_DATA_VECTOR_MASK;
3538 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3539 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3540 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3542 dmar_msi_write(irq, &msg);
3547 #endif /* CONFIG_SMP */
3549 static struct irq_chip dmar_msi_type = {
3551 .unmask = dmar_msi_unmask,
3552 .mask = dmar_msi_mask,
3553 .ack = ack_apic_edge,
3555 .set_affinity = dmar_msi_set_affinity,
3557 .retrigger = ioapic_retrigger_irq,
3560 int arch_setup_dmar_msi(unsigned int irq)
3565 ret = msi_compose_msg(NULL, irq, &msg);
3568 dmar_msi_write(irq, &msg);
3569 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3575 #ifdef CONFIG_HPET_TIMER
3578 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3580 struct irq_desc *desc = irq_to_desc(irq);
3581 struct irq_cfg *cfg;
3585 dest = set_desc_affinity(desc, mask);
3586 if (dest == BAD_APICID)
3589 cfg = desc->chip_data;
3591 hpet_msi_read(irq, &msg);
3593 msg.data &= ~MSI_DATA_VECTOR_MASK;
3594 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3595 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3596 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3598 hpet_msi_write(irq, &msg);
3603 #endif /* CONFIG_SMP */
3605 static struct irq_chip hpet_msi_type = {
3607 .unmask = hpet_msi_unmask,
3608 .mask = hpet_msi_mask,
3609 .ack = ack_apic_edge,
3611 .set_affinity = hpet_msi_set_affinity,
3613 .retrigger = ioapic_retrigger_irq,
3616 int arch_setup_hpet_msi(unsigned int irq)
3620 struct irq_desc *desc = irq_to_desc(irq);
3622 ret = msi_compose_msg(NULL, irq, &msg);
3626 hpet_msi_write(irq, &msg);
3627 desc->status |= IRQ_MOVE_PCNTXT;
3628 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3635 #endif /* CONFIG_PCI_MSI */
3637 * Hypertransport interrupt support
3639 #ifdef CONFIG_HT_IRQ
3643 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3645 struct ht_irq_msg msg;
3646 fetch_ht_irq_msg(irq, &msg);
3648 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3649 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3651 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3652 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3654 write_ht_irq_msg(irq, &msg);
3657 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3659 struct irq_desc *desc = irq_to_desc(irq);
3660 struct irq_cfg *cfg;
3663 dest = set_desc_affinity(desc, mask);
3664 if (dest == BAD_APICID)
3667 cfg = desc->chip_data;
3669 target_ht_irq(irq, dest, cfg->vector);
3676 static struct irq_chip ht_irq_chip = {
3678 .mask = mask_ht_irq,
3679 .unmask = unmask_ht_irq,
3680 .ack = ack_apic_edge,
3682 .set_affinity = set_ht_irq_affinity,
3684 .retrigger = ioapic_retrigger_irq,
3687 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3689 struct irq_cfg *cfg;
3696 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3698 struct ht_irq_msg msg;
3701 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3702 apic->target_cpus());
3704 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3708 HT_IRQ_LOW_DEST_ID(dest) |
3709 HT_IRQ_LOW_VECTOR(cfg->vector) |
3710 ((apic->irq_dest_mode == 0) ?
3711 HT_IRQ_LOW_DM_PHYSICAL :
3712 HT_IRQ_LOW_DM_LOGICAL) |
3713 HT_IRQ_LOW_RQEOI_EDGE |
3714 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3715 HT_IRQ_LOW_MT_FIXED :
3716 HT_IRQ_LOW_MT_ARBITRATED) |
3717 HT_IRQ_LOW_IRQ_MASKED;
3719 write_ht_irq_msg(irq, &msg);
3721 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3722 handle_edge_irq, "edge");
3724 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3728 #endif /* CONFIG_HT_IRQ */
3730 #ifdef CONFIG_X86_UV
3732 * Re-target the irq to the specified CPU and enable the specified MMR located
3733 * on the specified blade to allow the sending of MSIs to the specified CPU.
3735 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3736 unsigned long mmr_offset)
3738 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3739 struct irq_cfg *cfg;
3741 unsigned long mmr_value;
3742 struct uv_IO_APIC_route_entry *entry;
3743 unsigned long flags;
3746 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3750 err = assign_irq_vector(irq, cfg, eligible_cpu);
3754 spin_lock_irqsave(&vector_lock, flags);
3755 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3757 spin_unlock_irqrestore(&vector_lock, flags);
3760 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3761 entry->vector = cfg->vector;
3762 entry->delivery_mode = apic->irq_delivery_mode;
3763 entry->dest_mode = apic->irq_dest_mode;
3764 entry->polarity = 0;
3767 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3769 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3770 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3776 * Disable the specified MMR located on the specified blade so that MSIs are
3777 * longer allowed to be sent.
3779 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3781 unsigned long mmr_value;
3782 struct uv_IO_APIC_route_entry *entry;
3785 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3788 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3791 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3792 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3794 #endif /* CONFIG_X86_64 */
3796 int __init io_apic_get_redir_entries (int ioapic)
3798 union IO_APIC_reg_01 reg_01;
3799 unsigned long flags;
3801 spin_lock_irqsave(&ioapic_lock, flags);
3802 reg_01.raw = io_apic_read(ioapic, 1);
3803 spin_unlock_irqrestore(&ioapic_lock, flags);
3805 return reg_01.bits.entries;
3808 void __init probe_nr_irqs_gsi(void)
3812 nr = acpi_probe_gsi();
3813 if (nr > nr_irqs_gsi) {
3816 /* for acpi=off or acpi is not compiled in */
3820 for (idx = 0; idx < nr_ioapics; idx++)
3821 nr += io_apic_get_redir_entries(idx) + 1;
3823 if (nr > nr_irqs_gsi)
3827 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3830 #ifdef CONFIG_SPARSE_IRQ
3831 int __init arch_probe_nr_irqs(void)
3835 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3836 nr_irqs = NR_VECTORS * nr_cpu_ids;
3838 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3839 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3841 * for MSI and HT dyn irq
3843 nr += nr_irqs_gsi * 16;
3852 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3853 struct io_apic_irq_attr *irq_attr)
3855 struct irq_desc *desc;
3856 struct irq_cfg *cfg;
3859 int trigger, polarity;
3861 ioapic = irq_attr->ioapic;
3862 if (!IO_APIC_IRQ(irq)) {
3863 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3869 node = dev_to_node(dev);
3871 node = cpu_to_node(boot_cpu_id);
3873 desc = irq_to_desc_alloc_node(irq, node);
3875 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3879 pin = irq_attr->ioapic_pin;
3880 trigger = irq_attr->trigger;
3881 polarity = irq_attr->polarity;
3884 * IRQs < 16 are already in the irq_2_pin[] map
3886 if (irq >= NR_IRQS_LEGACY) {
3887 cfg = desc->chip_data;
3888 add_pin_to_irq_node(cfg, node, ioapic, pin);
3891 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3896 int io_apic_set_pci_routing(struct device *dev, int irq,
3897 struct io_apic_irq_attr *irq_attr)
3901 * Avoid pin reprogramming. PRTs typically include entries
3902 * with redundant pin->gsi mappings (but unique PCI devices);
3903 * we only program the IOAPIC on the first.
3905 ioapic = irq_attr->ioapic;
3906 pin = irq_attr->ioapic_pin;
3907 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3908 pr_debug("Pin %d-%d already programmed\n",
3909 mp_ioapics[ioapic].apicid, pin);
3912 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3914 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3917 /* --------------------------------------------------------------------------
3918 ACPI-based IOAPIC Configuration
3919 -------------------------------------------------------------------------- */
3923 #ifdef CONFIG_X86_32
3924 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3926 union IO_APIC_reg_00 reg_00;
3927 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3929 unsigned long flags;
3933 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3934 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3935 * supports up to 16 on one shared APIC bus.
3937 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3938 * advantage of new APIC bus architecture.
3941 if (physids_empty(apic_id_map))
3942 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3944 spin_lock_irqsave(&ioapic_lock, flags);
3945 reg_00.raw = io_apic_read(ioapic, 0);
3946 spin_unlock_irqrestore(&ioapic_lock, flags);
3948 if (apic_id >= get_physical_broadcast()) {
3949 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3950 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3951 apic_id = reg_00.bits.ID;
3955 * Every APIC in a system must have a unique ID or we get lots of nice
3956 * 'stuck on smp_invalidate_needed IPI wait' messages.
3958 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3960 for (i = 0; i < get_physical_broadcast(); i++) {
3961 if (!apic->check_apicid_used(apic_id_map, i))
3965 if (i == get_physical_broadcast())
3966 panic("Max apic_id exceeded!\n");
3968 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3969 "trying %d\n", ioapic, apic_id, i);
3974 tmp = apic->apicid_to_cpu_present(apic_id);
3975 physids_or(apic_id_map, apic_id_map, tmp);
3977 if (reg_00.bits.ID != apic_id) {
3978 reg_00.bits.ID = apic_id;
3980 spin_lock_irqsave(&ioapic_lock, flags);
3981 io_apic_write(ioapic, 0, reg_00.raw);
3982 reg_00.raw = io_apic_read(ioapic, 0);
3983 spin_unlock_irqrestore(&ioapic_lock, flags);
3986 if (reg_00.bits.ID != apic_id) {
3987 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3992 apic_printk(APIC_VERBOSE, KERN_INFO
3993 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3999 int __init io_apic_get_version(int ioapic)
4001 union IO_APIC_reg_01 reg_01;
4002 unsigned long flags;
4004 spin_lock_irqsave(&ioapic_lock, flags);
4005 reg_01.raw = io_apic_read(ioapic, 1);
4006 spin_unlock_irqrestore(&ioapic_lock, flags);
4008 return reg_01.bits.version;
4011 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4015 if (skip_ioapic_setup)
4018 for (i = 0; i < mp_irq_entries; i++)
4019 if (mp_irqs[i].irqtype == mp_INT &&
4020 mp_irqs[i].srcbusirq == bus_irq)
4022 if (i >= mp_irq_entries)
4025 *trigger = irq_trigger(i);
4026 *polarity = irq_polarity(i);
4030 #endif /* CONFIG_ACPI */
4033 * This function currently is only a helper for the i386 smp boot process where
4034 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4035 * so mask in all cases should simply be apic->target_cpus()
4038 void __init setup_ioapic_dest(void)
4040 int pin, ioapic = 0, irq, irq_entry;
4041 struct irq_desc *desc;
4042 const struct cpumask *mask;
4044 if (skip_ioapic_setup == 1)
4048 if (!acpi_disabled && acpi_ioapic) {
4049 ioapic = mp_find_ioapic(0);
4055 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4056 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4057 if (irq_entry == -1)
4059 irq = pin_2_irq(irq_entry, ioapic, pin);
4061 desc = irq_to_desc(irq);
4064 * Honour affinities which have been set in early boot
4067 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4068 mask = desc->affinity;
4070 mask = apic->target_cpus();
4072 if (intr_remapping_enabled)
4073 set_ir_ioapic_affinity_irq_desc(desc, mask);
4075 set_ioapic_affinity_irq_desc(desc, mask);
4081 #define IOAPIC_RESOURCE_NAME_SIZE 11
4083 static struct resource *ioapic_resources;
4085 static struct resource * __init ioapic_setup_resources(void)
4088 struct resource *res;
4092 if (nr_ioapics <= 0)
4095 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4098 mem = alloc_bootmem(n);
4102 mem += sizeof(struct resource) * nr_ioapics;
4104 for (i = 0; i < nr_ioapics; i++) {
4106 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4107 sprintf(mem, "IOAPIC %u", i);
4108 mem += IOAPIC_RESOURCE_NAME_SIZE;
4112 ioapic_resources = res;
4117 void __init ioapic_init_mappings(void)
4119 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4120 struct resource *ioapic_res;
4123 ioapic_res = ioapic_setup_resources();
4124 for (i = 0; i < nr_ioapics; i++) {
4125 if (smp_found_config) {
4126 ioapic_phys = mp_ioapics[i].apicaddr;
4127 #ifdef CONFIG_X86_32
4130 "WARNING: bogus zero IO-APIC "
4131 "address found in MPTABLE, "
4132 "disabling IO/APIC support!\n");
4133 smp_found_config = 0;
4134 skip_ioapic_setup = 1;
4135 goto fake_ioapic_page;
4139 #ifdef CONFIG_X86_32
4142 ioapic_phys = (unsigned long)
4143 alloc_bootmem_pages(PAGE_SIZE);
4144 ioapic_phys = __pa(ioapic_phys);
4146 set_fixmap_nocache(idx, ioapic_phys);
4147 apic_printk(APIC_VERBOSE,
4148 "mapped IOAPIC to %08lx (%08lx)\n",
4149 __fix_to_virt(idx), ioapic_phys);
4152 if (ioapic_res != NULL) {
4153 ioapic_res->start = ioapic_phys;
4154 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4160 static int __init ioapic_insert_resources(void)
4163 struct resource *r = ioapic_resources;
4166 if (nr_ioapics > 0) {
4168 "IO APIC resources couldn't be allocated.\n");
4174 for (i = 0; i < nr_ioapics; i++) {
4175 insert_resource(&iomem_resource, r);
4182 /* Insert the IO APIC resources after PCI initialization has occured to handle
4183 * IO APICS that are mapped in on a BAR in PCI space. */
4184 late_initcall(ioapic_insert_resources);