2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
94 /* # of MP IRQ source entries */
98 static int nr_irqs_gsi = NR_IRQS_LEGACY;
100 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
101 int mp_bus_id_to_type[MAX_MP_BUSSES];
104 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
106 int skip_ioapic_setup;
108 void arch_disable_smp_support(void)
112 noioapicreroute = -1;
114 skip_ioapic_setup = 1;
117 static int __init parse_noapic(char *str)
119 /* disable IO-APIC */
120 arch_disable_smp_support();
123 early_param("noapic", parse_noapic);
125 struct irq_pin_list {
127 struct irq_pin_list *next;
130 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
132 struct irq_pin_list *pin;
134 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
139 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
140 #ifdef CONFIG_SPARSE_IRQ
141 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
143 static struct irq_cfg irq_cfgx[NR_IRQS];
146 int __init arch_early_irq_init(void)
149 struct irq_desc *desc;
154 if (!legacy_pic->nr_legacy_irqs) {
160 count = ARRAY_SIZE(irq_cfgx);
161 node= cpu_to_node(boot_cpu_id);
163 for (i = 0; i < count; i++) {
164 desc = irq_to_desc(i);
165 desc->chip_data = &cfg[i];
166 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
167 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
169 * For legacy IRQ's, start with assigning irq0 to irq15 to
170 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
172 if (i < legacy_pic->nr_legacy_irqs) {
173 cfg[i].vector = IRQ0_VECTOR + i;
174 cpumask_set_cpu(0, cfg[i].domain);
181 #ifdef CONFIG_SPARSE_IRQ
182 struct irq_cfg *irq_cfg(unsigned int irq)
184 struct irq_cfg *cfg = NULL;
185 struct irq_desc *desc;
187 desc = irq_to_desc(irq);
189 cfg = desc->chip_data;
194 static struct irq_cfg *get_one_free_irq_cfg(int node)
198 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
200 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
203 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
205 free_cpumask_var(cfg->domain);
214 int arch_init_chip_data(struct irq_desc *desc, int node)
218 cfg = desc->chip_data;
220 desc->chip_data = get_one_free_irq_cfg(node);
221 if (!desc->chip_data) {
222 printk(KERN_ERR "can not alloc irq_cfg\n");
230 /* for move_irq_desc */
232 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
234 struct irq_pin_list *old_entry, *head, *tail, *entry;
236 cfg->irq_2_pin = NULL;
237 old_entry = old_cfg->irq_2_pin;
241 entry = get_one_free_irq_2_pin(node);
245 entry->apic = old_entry->apic;
246 entry->pin = old_entry->pin;
249 old_entry = old_entry->next;
251 entry = get_one_free_irq_2_pin(node);
259 /* still use the old one */
262 entry->apic = old_entry->apic;
263 entry->pin = old_entry->pin;
266 old_entry = old_entry->next;
270 cfg->irq_2_pin = head;
273 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
275 struct irq_pin_list *entry, *next;
277 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
280 entry = old_cfg->irq_2_pin;
287 old_cfg->irq_2_pin = NULL;
290 void arch_init_copy_chip_data(struct irq_desc *old_desc,
291 struct irq_desc *desc, int node)
294 struct irq_cfg *old_cfg;
296 cfg = get_one_free_irq_cfg(node);
301 desc->chip_data = cfg;
303 old_cfg = old_desc->chip_data;
305 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
307 init_copy_irq_2_pin(old_cfg, cfg, node);
310 static void free_irq_cfg(struct irq_cfg *old_cfg)
315 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
317 struct irq_cfg *old_cfg, *cfg;
319 old_cfg = old_desc->chip_data;
320 cfg = desc->chip_data;
326 free_irq_2_pin(old_cfg, cfg);
327 free_irq_cfg(old_cfg);
328 old_desc->chip_data = NULL;
331 /* end for move_irq_desc */
334 struct irq_cfg *irq_cfg(unsigned int irq)
336 return irq < nr_irqs ? irq_cfgx + irq : NULL;
343 unsigned int unused[3];
345 unsigned int unused2[11];
349 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
351 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
352 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
355 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
357 struct io_apic __iomem *io_apic = io_apic_base(apic);
358 writel(vector, &io_apic->eoi);
361 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
363 struct io_apic __iomem *io_apic = io_apic_base(apic);
364 writel(reg, &io_apic->index);
365 return readl(&io_apic->data);
368 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
370 struct io_apic __iomem *io_apic = io_apic_base(apic);
371 writel(reg, &io_apic->index);
372 writel(value, &io_apic->data);
376 * Re-write a value: to be used for read-modify-write
377 * cycles where the read already set up the index register.
379 * Older SiS APIC requires we rewrite the index register
381 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
383 struct io_apic __iomem *io_apic = io_apic_base(apic);
386 writel(reg, &io_apic->index);
387 writel(value, &io_apic->data);
390 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
392 struct irq_pin_list *entry;
395 raw_spin_lock_irqsave(&ioapic_lock, flags);
396 for_each_irq_pin(entry, cfg->irq_2_pin) {
401 reg = io_apic_read(entry->apic, 0x10 + pin*2);
402 /* Is the remote IRR bit set? */
403 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
404 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
408 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
414 struct { u32 w1, w2; };
415 struct IO_APIC_route_entry entry;
418 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
420 union entry_union eu;
422 raw_spin_lock_irqsave(&ioapic_lock, flags);
423 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
424 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
425 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
430 * When we write a new IO APIC routing entry, we need to write the high
431 * word first! If the mask bit in the low word is clear, we will enable
432 * the interrupt, and we need to make sure the entry is fully populated
433 * before that happens.
436 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
438 union entry_union eu = {{0, 0}};
441 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
442 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
445 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
448 raw_spin_lock_irqsave(&ioapic_lock, flags);
449 __ioapic_write_entry(apic, pin, e);
450 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
454 * When we mask an IO APIC routing entry, we need to write the low
455 * word first, in order to set the mask bit before we change the
458 static void ioapic_mask_entry(int apic, int pin)
461 union entry_union eu = { .entry.mask = 1 };
463 raw_spin_lock_irqsave(&ioapic_lock, flags);
464 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
465 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
466 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
470 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
471 * shared ISA-space IRQs, so we have to support them. We are super
472 * fast in the common case, and fast for shared ISA-space IRQs.
475 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
477 struct irq_pin_list **last, *entry;
479 /* don't allow duplicates */
480 last = &cfg->irq_2_pin;
481 for_each_irq_pin(entry, cfg->irq_2_pin) {
482 if (entry->apic == apic && entry->pin == pin)
487 entry = get_one_free_irq_2_pin(node);
489 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
500 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
502 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
503 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
507 * Reroute an IRQ to a different pin.
509 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
510 int oldapic, int oldpin,
511 int newapic, int newpin)
513 struct irq_pin_list *entry;
515 for_each_irq_pin(entry, cfg->irq_2_pin) {
516 if (entry->apic == oldapic && entry->pin == oldpin) {
517 entry->apic = newapic;
519 /* every one is different, right? */
524 /* old apic/pin didn't exist, so just add new ones */
525 add_pin_to_irq_node(cfg, node, newapic, newpin);
528 static void __io_apic_modify_irq(struct irq_pin_list *entry,
529 int mask_and, int mask_or,
530 void (*final)(struct irq_pin_list *entry))
532 unsigned int reg, pin;
535 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
538 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
543 static void io_apic_modify_irq(struct irq_cfg *cfg,
544 int mask_and, int mask_or,
545 void (*final)(struct irq_pin_list *entry))
547 struct irq_pin_list *entry;
549 for_each_irq_pin(entry, cfg->irq_2_pin)
550 __io_apic_modify_irq(entry, mask_and, mask_or, final);
553 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
555 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
556 IO_APIC_REDIR_MASKED, NULL);
559 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
561 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
562 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
565 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
567 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
570 static void io_apic_sync(struct irq_pin_list *entry)
573 * Synchronize the IO-APIC and the CPU by doing
574 * a dummy read from the IO-APIC
576 struct io_apic __iomem *io_apic;
577 io_apic = io_apic_base(entry->apic);
578 readl(&io_apic->data);
581 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
583 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
586 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
588 struct irq_cfg *cfg = desc->chip_data;
593 raw_spin_lock_irqsave(&ioapic_lock, flags);
594 __mask_IO_APIC_irq(cfg);
595 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
598 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
600 struct irq_cfg *cfg = desc->chip_data;
603 raw_spin_lock_irqsave(&ioapic_lock, flags);
604 __unmask_IO_APIC_irq(cfg);
605 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
608 static void mask_IO_APIC_irq(unsigned int irq)
610 struct irq_desc *desc = irq_to_desc(irq);
612 mask_IO_APIC_irq_desc(desc);
614 static void unmask_IO_APIC_irq(unsigned int irq)
616 struct irq_desc *desc = irq_to_desc(irq);
618 unmask_IO_APIC_irq_desc(desc);
621 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
623 struct IO_APIC_route_entry entry;
625 /* Check delivery_mode to be sure we're not clearing an SMI pin */
626 entry = ioapic_read_entry(apic, pin);
627 if (entry.delivery_mode == dest_SMI)
630 * Disable it in the IO-APIC irq-routing table:
632 ioapic_mask_entry(apic, pin);
635 static void clear_IO_APIC (void)
639 for (apic = 0; apic < nr_ioapics; apic++)
640 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
641 clear_IO_APIC_pin(apic, pin);
646 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
647 * specific CPU-side IRQs.
651 static int pirq_entries[MAX_PIRQS] = {
652 [0 ... MAX_PIRQS - 1] = -1
655 static int __init ioapic_pirq_setup(char *str)
658 int ints[MAX_PIRQS+1];
660 get_options(str, ARRAY_SIZE(ints), ints);
662 apic_printk(APIC_VERBOSE, KERN_INFO
663 "PIRQ redirection, working around broken MP-BIOS.\n");
665 if (ints[0] < MAX_PIRQS)
668 for (i = 0; i < max; i++) {
669 apic_printk(APIC_VERBOSE, KERN_DEBUG
670 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
672 * PIRQs are mapped upside down, usually.
674 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
679 __setup("pirq=", ioapic_pirq_setup);
680 #endif /* CONFIG_X86_32 */
682 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
685 struct IO_APIC_route_entry **ioapic_entries;
687 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
692 for (apic = 0; apic < nr_ioapics; apic++) {
693 ioapic_entries[apic] =
694 kzalloc(sizeof(struct IO_APIC_route_entry) *
695 nr_ioapic_registers[apic], GFP_ATOMIC);
696 if (!ioapic_entries[apic])
700 return ioapic_entries;
704 kfree(ioapic_entries[apic]);
705 kfree(ioapic_entries);
711 * Saves all the IO-APIC RTE's
713 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
720 for (apic = 0; apic < nr_ioapics; apic++) {
721 if (!ioapic_entries[apic])
724 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
725 ioapic_entries[apic][pin] =
726 ioapic_read_entry(apic, pin);
733 * Mask all IO APIC entries.
735 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
742 for (apic = 0; apic < nr_ioapics; apic++) {
743 if (!ioapic_entries[apic])
746 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
747 struct IO_APIC_route_entry entry;
749 entry = ioapic_entries[apic][pin];
752 ioapic_write_entry(apic, pin, entry);
759 * Restore IO APIC entries which was saved in ioapic_entries.
761 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
768 for (apic = 0; apic < nr_ioapics; apic++) {
769 if (!ioapic_entries[apic])
772 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
773 ioapic_write_entry(apic, pin,
774 ioapic_entries[apic][pin]);
779 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
783 for (apic = 0; apic < nr_ioapics; apic++)
784 kfree(ioapic_entries[apic]);
786 kfree(ioapic_entries);
790 * Find the IRQ entry number of a certain pin.
792 static int find_irq_entry(int apic, int pin, int type)
796 for (i = 0; i < mp_irq_entries; i++)
797 if (mp_irqs[i].irqtype == type &&
798 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
799 mp_irqs[i].dstapic == MP_APIC_ALL) &&
800 mp_irqs[i].dstirq == pin)
807 * Find the pin to which IRQ[irq] (ISA) is connected
809 static int __init find_isa_irq_pin(int irq, int type)
813 for (i = 0; i < mp_irq_entries; i++) {
814 int lbus = mp_irqs[i].srcbus;
816 if (test_bit(lbus, mp_bus_not_pci) &&
817 (mp_irqs[i].irqtype == type) &&
818 (mp_irqs[i].srcbusirq == irq))
820 return mp_irqs[i].dstirq;
825 static int __init find_isa_irq_apic(int irq, int type)
829 for (i = 0; i < mp_irq_entries; i++) {
830 int lbus = mp_irqs[i].srcbus;
832 if (test_bit(lbus, mp_bus_not_pci) &&
833 (mp_irqs[i].irqtype == type) &&
834 (mp_irqs[i].srcbusirq == irq))
837 if (i < mp_irq_entries) {
839 for(apic = 0; apic < nr_ioapics; apic++) {
840 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
848 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
850 * EISA Edge/Level control register, ELCR
852 static int EISA_ELCR(unsigned int irq)
854 if (irq < legacy_pic->nr_legacy_irqs) {
855 unsigned int port = 0x4d0 + (irq >> 3);
856 return (inb(port) >> (irq & 7)) & 1;
858 apic_printk(APIC_VERBOSE, KERN_INFO
859 "Broken MPtable reports ISA irq %d\n", irq);
865 /* ISA interrupts are always polarity zero edge triggered,
866 * when listed as conforming in the MP table. */
868 #define default_ISA_trigger(idx) (0)
869 #define default_ISA_polarity(idx) (0)
871 /* EISA interrupts are always polarity zero and can be edge or level
872 * trigger depending on the ELCR value. If an interrupt is listed as
873 * EISA conforming in the MP table, that means its trigger type must
874 * be read in from the ELCR */
876 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
877 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
879 /* PCI interrupts are always polarity one level triggered,
880 * when listed as conforming in the MP table. */
882 #define default_PCI_trigger(idx) (1)
883 #define default_PCI_polarity(idx) (1)
885 /* MCA interrupts are always polarity zero level triggered,
886 * when listed as conforming in the MP table. */
888 #define default_MCA_trigger(idx) (1)
889 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
891 static int MPBIOS_polarity(int idx)
893 int bus = mp_irqs[idx].srcbus;
897 * Determine IRQ line polarity (high active or low active):
899 switch (mp_irqs[idx].irqflag & 3)
901 case 0: /* conforms, ie. bus-type dependent polarity */
902 if (test_bit(bus, mp_bus_not_pci))
903 polarity = default_ISA_polarity(idx);
905 polarity = default_PCI_polarity(idx);
907 case 1: /* high active */
912 case 2: /* reserved */
914 printk(KERN_WARNING "broken BIOS!!\n");
918 case 3: /* low active */
923 default: /* invalid */
925 printk(KERN_WARNING "broken BIOS!!\n");
933 static int MPBIOS_trigger(int idx)
935 int bus = mp_irqs[idx].srcbus;
939 * Determine IRQ trigger mode (edge or level sensitive):
941 switch ((mp_irqs[idx].irqflag>>2) & 3)
943 case 0: /* conforms, ie. bus-type dependent */
944 if (test_bit(bus, mp_bus_not_pci))
945 trigger = default_ISA_trigger(idx);
947 trigger = default_PCI_trigger(idx);
948 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
949 switch (mp_bus_id_to_type[bus]) {
950 case MP_BUS_ISA: /* ISA pin */
952 /* set before the switch */
955 case MP_BUS_EISA: /* EISA pin */
957 trigger = default_EISA_trigger(idx);
960 case MP_BUS_PCI: /* PCI pin */
962 /* set before the switch */
965 case MP_BUS_MCA: /* MCA pin */
967 trigger = default_MCA_trigger(idx);
972 printk(KERN_WARNING "broken BIOS!!\n");
984 case 2: /* reserved */
986 printk(KERN_WARNING "broken BIOS!!\n");
995 default: /* invalid */
997 printk(KERN_WARNING "broken BIOS!!\n");
1005 static inline int irq_polarity(int idx)
1007 return MPBIOS_polarity(idx);
1010 static inline int irq_trigger(int idx)
1012 return MPBIOS_trigger(idx);
1015 int (*ioapic_renumber_irq)(int ioapic, int irq);
1016 static int pin_2_irq(int idx, int apic, int pin)
1019 int bus = mp_irqs[idx].srcbus;
1022 * Debugging check, we are in big trouble if this message pops up!
1024 if (mp_irqs[idx].dstirq != pin)
1025 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1027 if (test_bit(bus, mp_bus_not_pci)) {
1028 irq = mp_irqs[idx].srcbusirq;
1031 * PCI IRQs are mapped in order
1035 irq += nr_ioapic_registers[i++];
1038 * For MPS mode, so far only needed by ES7000 platform
1040 if (ioapic_renumber_irq)
1041 irq = ioapic_renumber_irq(apic, irq);
1044 #ifdef CONFIG_X86_32
1046 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1048 if ((pin >= 16) && (pin <= 23)) {
1049 if (pirq_entries[pin-16] != -1) {
1050 if (!pirq_entries[pin-16]) {
1051 apic_printk(APIC_VERBOSE, KERN_DEBUG
1052 "disabling PIRQ%d\n", pin-16);
1054 irq = pirq_entries[pin-16];
1055 apic_printk(APIC_VERBOSE, KERN_DEBUG
1056 "using PIRQ%d -> IRQ %d\n",
1067 * Find a specific PCI IRQ entry.
1068 * Not an __init, possibly needed by modules
1070 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1071 struct io_apic_irq_attr *irq_attr)
1073 int apic, i, best_guess = -1;
1075 apic_printk(APIC_DEBUG,
1076 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1078 if (test_bit(bus, mp_bus_not_pci)) {
1079 apic_printk(APIC_VERBOSE,
1080 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1083 for (i = 0; i < mp_irq_entries; i++) {
1084 int lbus = mp_irqs[i].srcbus;
1086 for (apic = 0; apic < nr_ioapics; apic++)
1087 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1088 mp_irqs[i].dstapic == MP_APIC_ALL)
1091 if (!test_bit(lbus, mp_bus_not_pci) &&
1092 !mp_irqs[i].irqtype &&
1094 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1095 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1097 if (!(apic || IO_APIC_IRQ(irq)))
1100 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1101 set_io_apic_irq_attr(irq_attr, apic,
1108 * Use the first all-but-pin matching entry as a
1109 * best-guess fuzzy result for broken mptables.
1111 if (best_guess < 0) {
1112 set_io_apic_irq_attr(irq_attr, apic,
1122 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1124 void lock_vector_lock(void)
1126 /* Used to the online set of cpus does not change
1127 * during assign_irq_vector.
1129 raw_spin_lock(&vector_lock);
1132 void unlock_vector_lock(void)
1134 raw_spin_unlock(&vector_lock);
1138 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1141 * NOTE! The local APIC isn't very good at handling
1142 * multiple interrupts at the same interrupt level.
1143 * As the interrupt level is determined by taking the
1144 * vector number and shifting that right by 4, we
1145 * want to spread these out a bit so that they don't
1146 * all fall in the same interrupt level.
1148 * Also, we've got to be careful not to trash gate
1149 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1151 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1152 static int current_offset = VECTOR_OFFSET_START % 8;
1153 unsigned int old_vector;
1155 cpumask_var_t tmp_mask;
1157 if (cfg->move_in_progress)
1160 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1163 old_vector = cfg->vector;
1165 cpumask_and(tmp_mask, mask, cpu_online_mask);
1166 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1167 if (!cpumask_empty(tmp_mask)) {
1168 free_cpumask_var(tmp_mask);
1173 /* Only try and allocate irqs on cpus that are present */
1175 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1179 apic->vector_allocation_domain(cpu, tmp_mask);
1181 vector = current_vector;
1182 offset = current_offset;
1185 if (vector >= first_system_vector) {
1186 /* If out of vectors on large boxen, must share them. */
1187 offset = (offset + 1) % 8;
1188 vector = FIRST_EXTERNAL_VECTOR + offset;
1190 if (unlikely(current_vector == vector))
1193 if (test_bit(vector, used_vectors))
1196 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1197 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1200 current_vector = vector;
1201 current_offset = offset;
1203 cfg->move_in_progress = 1;
1204 cpumask_copy(cfg->old_domain, cfg->domain);
1206 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1207 per_cpu(vector_irq, new_cpu)[vector] = irq;
1208 cfg->vector = vector;
1209 cpumask_copy(cfg->domain, tmp_mask);
1213 free_cpumask_var(tmp_mask);
1217 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1220 unsigned long flags;
1222 raw_spin_lock_irqsave(&vector_lock, flags);
1223 err = __assign_irq_vector(irq, cfg, mask);
1224 raw_spin_unlock_irqrestore(&vector_lock, flags);
1228 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1232 BUG_ON(!cfg->vector);
1234 vector = cfg->vector;
1235 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1236 per_cpu(vector_irq, cpu)[vector] = -1;
1239 cpumask_clear(cfg->domain);
1241 if (likely(!cfg->move_in_progress))
1243 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1244 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1246 if (per_cpu(vector_irq, cpu)[vector] != irq)
1248 per_cpu(vector_irq, cpu)[vector] = -1;
1252 cfg->move_in_progress = 0;
1255 void __setup_vector_irq(int cpu)
1257 /* Initialize vector_irq on a new cpu */
1259 struct irq_cfg *cfg;
1260 struct irq_desc *desc;
1263 * vector_lock will make sure that we don't run into irq vector
1264 * assignments that might be happening on another cpu in parallel,
1265 * while we setup our initial vector to irq mappings.
1267 raw_spin_lock(&vector_lock);
1268 /* Mark the inuse vectors */
1269 for_each_irq_desc(irq, desc) {
1270 cfg = desc->chip_data;
1273 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1274 * will be part of the irq_cfg's domain.
1276 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1277 cpumask_set_cpu(cpu, cfg->domain);
1279 if (!cpumask_test_cpu(cpu, cfg->domain))
1281 vector = cfg->vector;
1282 per_cpu(vector_irq, cpu)[vector] = irq;
1284 /* Mark the free vectors */
1285 for (vector = 0; vector < NR_VECTORS; ++vector) {
1286 irq = per_cpu(vector_irq, cpu)[vector];
1291 if (!cpumask_test_cpu(cpu, cfg->domain))
1292 per_cpu(vector_irq, cpu)[vector] = -1;
1294 raw_spin_unlock(&vector_lock);
1297 static struct irq_chip ioapic_chip;
1298 static struct irq_chip ir_ioapic_chip;
1300 #define IOAPIC_AUTO -1
1301 #define IOAPIC_EDGE 0
1302 #define IOAPIC_LEVEL 1
1304 #ifdef CONFIG_X86_32
1305 static inline int IO_APIC_irq_trigger(int irq)
1309 for (apic = 0; apic < nr_ioapics; apic++) {
1310 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1311 idx = find_irq_entry(apic, pin, mp_INT);
1312 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1313 return irq_trigger(idx);
1317 * nonexistent IRQs are edge default
1322 static inline int IO_APIC_irq_trigger(int irq)
1328 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1331 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1332 trigger == IOAPIC_LEVEL)
1333 desc->status |= IRQ_LEVEL;
1335 desc->status &= ~IRQ_LEVEL;
1337 if (irq_remapped(irq)) {
1338 desc->status |= IRQ_MOVE_PCNTXT;
1340 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1344 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1345 handle_edge_irq, "edge");
1349 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1350 trigger == IOAPIC_LEVEL)
1351 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1355 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1356 handle_edge_irq, "edge");
1359 int setup_ioapic_entry(int apic_id, int irq,
1360 struct IO_APIC_route_entry *entry,
1361 unsigned int destination, int trigger,
1362 int polarity, int vector, int pin)
1365 * add it to the IO-APIC irq-routing table:
1367 memset(entry,0,sizeof(*entry));
1369 if (intr_remapping_enabled) {
1370 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1372 struct IR_IO_APIC_route_entry *ir_entry =
1373 (struct IR_IO_APIC_route_entry *) entry;
1377 panic("No mapping iommu for ioapic %d\n", apic_id);
1379 index = alloc_irte(iommu, irq, 1);
1381 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1383 memset(&irte, 0, sizeof(irte));
1386 irte.dst_mode = apic->irq_dest_mode;
1388 * Trigger mode in the IRTE will always be edge, and the
1389 * actual level or edge trigger will be setup in the IO-APIC
1390 * RTE. This will help simplify level triggered irq migration.
1391 * For more details, see the comments above explainig IO-APIC
1392 * irq migration in the presence of interrupt-remapping.
1394 irte.trigger_mode = 0;
1395 irte.dlvry_mode = apic->irq_delivery_mode;
1396 irte.vector = vector;
1397 irte.dest_id = IRTE_DEST(destination);
1399 /* Set source-id of interrupt request */
1400 set_ioapic_sid(&irte, apic_id);
1402 modify_irte(irq, &irte);
1404 ir_entry->index2 = (index >> 15) & 0x1;
1406 ir_entry->format = 1;
1407 ir_entry->index = (index & 0x7fff);
1409 * IO-APIC RTE will be configured with virtual vector.
1410 * irq handler will do the explicit EOI to the io-apic.
1412 ir_entry->vector = pin;
1414 entry->delivery_mode = apic->irq_delivery_mode;
1415 entry->dest_mode = apic->irq_dest_mode;
1416 entry->dest = destination;
1417 entry->vector = vector;
1420 entry->mask = 0; /* enable IRQ */
1421 entry->trigger = trigger;
1422 entry->polarity = polarity;
1424 /* Mask level triggered irqs.
1425 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1432 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1433 int trigger, int polarity)
1435 struct irq_cfg *cfg;
1436 struct IO_APIC_route_entry entry;
1439 if (!IO_APIC_IRQ(irq))
1442 cfg = desc->chip_data;
1445 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1446 * controllers like 8259. Now that IO-APIC can handle this irq, update
1449 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1450 apic->vector_allocation_domain(0, cfg->domain);
1452 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1455 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1457 apic_printk(APIC_VERBOSE,KERN_DEBUG
1458 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1459 "IRQ %d Mode:%i Active:%i)\n",
1460 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1461 irq, trigger, polarity);
1464 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1465 dest, trigger, polarity, cfg->vector, pin)) {
1466 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1467 mp_ioapics[apic_id].apicid, pin);
1468 __clear_irq_vector(irq, cfg);
1472 ioapic_register_intr(irq, desc, trigger);
1473 if (irq < legacy_pic->nr_legacy_irqs)
1474 legacy_pic->chip->mask(irq);
1476 ioapic_write_entry(apic_id, pin, entry);
1480 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1481 } mp_ioapic_routing[MAX_IO_APICS];
1483 static void __init setup_IO_APIC_irqs(void)
1485 int apic_id, pin, idx, irq;
1487 struct irq_desc *desc;
1488 struct irq_cfg *cfg;
1489 int node = cpu_to_node(boot_cpu_id);
1491 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1493 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1494 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1495 idx = find_irq_entry(apic_id, pin, mp_INT);
1499 apic_printk(APIC_VERBOSE,
1500 KERN_DEBUG " %d-%d",
1501 mp_ioapics[apic_id].apicid, pin);
1503 apic_printk(APIC_VERBOSE, " %d-%d",
1504 mp_ioapics[apic_id].apicid, pin);
1508 apic_printk(APIC_VERBOSE,
1509 " (apicid-pin) not connected\n");
1513 irq = pin_2_irq(idx, apic_id, pin);
1515 if ((apic_id > 0) && (irq > 16))
1519 * Skip the timer IRQ if there's a quirk handler
1520 * installed and if it returns 1:
1522 if (apic->multi_timer_check &&
1523 apic->multi_timer_check(apic_id, irq))
1526 desc = irq_to_desc_alloc_node(irq, node);
1528 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1531 cfg = desc->chip_data;
1532 add_pin_to_irq_node(cfg, node, apic_id, pin);
1534 * don't mark it in pin_programmed, so later acpi could
1535 * set it correctly when irq < 16
1537 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1538 irq_trigger(idx), irq_polarity(idx));
1542 apic_printk(APIC_VERBOSE,
1543 " (apicid-pin) not connected\n");
1547 * for the gsit that is not in first ioapic
1548 * but could not use acpi_register_gsi()
1549 * like some special sci in IBM x3330
1551 void setup_IO_APIC_irq_extra(u32 gsi)
1553 int apic_id = 0, pin, idx, irq;
1554 int node = cpu_to_node(boot_cpu_id);
1555 struct irq_desc *desc;
1556 struct irq_cfg *cfg;
1559 * Convert 'gsi' to 'ioapic.pin'.
1561 apic_id = mp_find_ioapic(gsi);
1565 pin = mp_find_ioapic_pin(apic_id, gsi);
1566 idx = find_irq_entry(apic_id, pin, mp_INT);
1570 irq = pin_2_irq(idx, apic_id, pin);
1571 #ifdef CONFIG_SPARSE_IRQ
1572 desc = irq_to_desc(irq);
1576 desc = irq_to_desc_alloc_node(irq, node);
1578 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1582 cfg = desc->chip_data;
1583 add_pin_to_irq_node(cfg, node, apic_id, pin);
1585 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1586 pr_debug("Pin %d-%d already programmed\n",
1587 mp_ioapics[apic_id].apicid, pin);
1590 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1592 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1593 irq_trigger(idx), irq_polarity(idx));
1597 * Set up the timer pin, possibly with the 8259A-master behind.
1599 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1602 struct IO_APIC_route_entry entry;
1604 if (intr_remapping_enabled)
1607 memset(&entry, 0, sizeof(entry));
1610 * We use logical delivery to get the timer IRQ
1613 entry.dest_mode = apic->irq_dest_mode;
1614 entry.mask = 0; /* don't mask IRQ for edge */
1615 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1616 entry.delivery_mode = apic->irq_delivery_mode;
1619 entry.vector = vector;
1622 * The timer IRQ doesn't have to know that behind the
1623 * scene we may have a 8259A-master in AEOI mode ...
1625 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1628 * Add it to the IO-APIC irq-routing table:
1630 ioapic_write_entry(apic_id, pin, entry);
1634 __apicdebuginit(void) print_IO_APIC(void)
1637 union IO_APIC_reg_00 reg_00;
1638 union IO_APIC_reg_01 reg_01;
1639 union IO_APIC_reg_02 reg_02;
1640 union IO_APIC_reg_03 reg_03;
1641 unsigned long flags;
1642 struct irq_cfg *cfg;
1643 struct irq_desc *desc;
1646 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1647 for (i = 0; i < nr_ioapics; i++)
1648 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1649 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1652 * We are a bit conservative about what we expect. We have to
1653 * know about every hardware change ASAP.
1655 printk(KERN_INFO "testing the IO APIC.......................\n");
1657 for (apic = 0; apic < nr_ioapics; apic++) {
1659 raw_spin_lock_irqsave(&ioapic_lock, flags);
1660 reg_00.raw = io_apic_read(apic, 0);
1661 reg_01.raw = io_apic_read(apic, 1);
1662 if (reg_01.bits.version >= 0x10)
1663 reg_02.raw = io_apic_read(apic, 2);
1664 if (reg_01.bits.version >= 0x20)
1665 reg_03.raw = io_apic_read(apic, 3);
1666 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1669 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1670 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1671 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1672 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1673 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1675 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1676 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1678 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1679 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1682 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1683 * but the value of reg_02 is read as the previous read register
1684 * value, so ignore it if reg_02 == reg_01.
1686 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1687 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1688 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1692 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1693 * or reg_03, but the value of reg_0[23] is read as the previous read
1694 * register value, so ignore it if reg_03 == reg_0[12].
1696 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1697 reg_03.raw != reg_01.raw) {
1698 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1699 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1702 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1704 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1705 " Stat Dmod Deli Vect:\n");
1707 for (i = 0; i <= reg_01.bits.entries; i++) {
1708 struct IO_APIC_route_entry entry;
1710 entry = ioapic_read_entry(apic, i);
1712 printk(KERN_DEBUG " %02x %03X ",
1717 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1722 entry.delivery_status,
1724 entry.delivery_mode,
1729 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1730 for_each_irq_desc(irq, desc) {
1731 struct irq_pin_list *entry;
1733 cfg = desc->chip_data;
1734 entry = cfg->irq_2_pin;
1737 printk(KERN_DEBUG "IRQ%d ", irq);
1738 for_each_irq_pin(entry, cfg->irq_2_pin)
1739 printk("-> %d:%d", entry->apic, entry->pin);
1743 printk(KERN_INFO ".................................... done.\n");
1748 __apicdebuginit(void) print_APIC_field(int base)
1754 for (i = 0; i < 8; i++)
1755 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1757 printk(KERN_CONT "\n");
1760 __apicdebuginit(void) print_local_APIC(void *dummy)
1762 unsigned int i, v, ver, maxlvt;
1765 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1766 smp_processor_id(), hard_smp_processor_id());
1767 v = apic_read(APIC_ID);
1768 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1769 v = apic_read(APIC_LVR);
1770 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1771 ver = GET_APIC_VERSION(v);
1772 maxlvt = lapic_get_maxlvt();
1774 v = apic_read(APIC_TASKPRI);
1775 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1777 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1778 if (!APIC_XAPIC(ver)) {
1779 v = apic_read(APIC_ARBPRI);
1780 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1781 v & APIC_ARBPRI_MASK);
1783 v = apic_read(APIC_PROCPRI);
1784 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1788 * Remote read supported only in the 82489DX and local APIC for
1789 * Pentium processors.
1791 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1792 v = apic_read(APIC_RRR);
1793 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1796 v = apic_read(APIC_LDR);
1797 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1798 if (!x2apic_enabled()) {
1799 v = apic_read(APIC_DFR);
1800 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1802 v = apic_read(APIC_SPIV);
1803 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1805 printk(KERN_DEBUG "... APIC ISR field:\n");
1806 print_APIC_field(APIC_ISR);
1807 printk(KERN_DEBUG "... APIC TMR field:\n");
1808 print_APIC_field(APIC_TMR);
1809 printk(KERN_DEBUG "... APIC IRR field:\n");
1810 print_APIC_field(APIC_IRR);
1812 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1813 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1814 apic_write(APIC_ESR, 0);
1816 v = apic_read(APIC_ESR);
1817 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1820 icr = apic_icr_read();
1821 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1822 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1824 v = apic_read(APIC_LVTT);
1825 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1827 if (maxlvt > 3) { /* PC is LVT#4. */
1828 v = apic_read(APIC_LVTPC);
1829 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1831 v = apic_read(APIC_LVT0);
1832 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1833 v = apic_read(APIC_LVT1);
1834 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1836 if (maxlvt > 2) { /* ERR is LVT#3. */
1837 v = apic_read(APIC_LVTERR);
1838 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1841 v = apic_read(APIC_TMICT);
1842 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1843 v = apic_read(APIC_TMCCT);
1844 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1845 v = apic_read(APIC_TDCR);
1846 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1848 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1849 v = apic_read(APIC_EFEAT);
1850 maxlvt = (v >> 16) & 0xff;
1851 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1852 v = apic_read(APIC_ECTRL);
1853 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1854 for (i = 0; i < maxlvt; i++) {
1855 v = apic_read(APIC_EILVTn(i));
1856 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1862 __apicdebuginit(void) print_local_APICs(int maxcpu)
1870 for_each_online_cpu(cpu) {
1873 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1878 __apicdebuginit(void) print_PIC(void)
1881 unsigned long flags;
1883 if (!legacy_pic->nr_legacy_irqs)
1886 printk(KERN_DEBUG "\nprinting PIC contents\n");
1888 raw_spin_lock_irqsave(&i8259A_lock, flags);
1890 v = inb(0xa1) << 8 | inb(0x21);
1891 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1893 v = inb(0xa0) << 8 | inb(0x20);
1894 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1898 v = inb(0xa0) << 8 | inb(0x20);
1902 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1904 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1906 v = inb(0x4d1) << 8 | inb(0x4d0);
1907 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1910 static int __initdata show_lapic = 1;
1911 static __init int setup_show_lapic(char *arg)
1915 if (strcmp(arg, "all") == 0) {
1916 show_lapic = CONFIG_NR_CPUS;
1918 get_option(&arg, &num);
1925 __setup("show_lapic=", setup_show_lapic);
1927 __apicdebuginit(int) print_ICs(void)
1929 if (apic_verbosity == APIC_QUIET)
1934 /* don't print out if apic is not there */
1935 if (!cpu_has_apic && !apic_from_smp_config())
1938 print_local_APICs(show_lapic);
1944 fs_initcall(print_ICs);
1947 /* Where if anywhere is the i8259 connect in external int mode */
1948 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1950 void __init enable_IO_APIC(void)
1952 union IO_APIC_reg_01 reg_01;
1953 int i8259_apic, i8259_pin;
1955 unsigned long flags;
1958 * The number of IO-APIC IRQ registers (== #pins):
1960 for (apic = 0; apic < nr_ioapics; apic++) {
1961 raw_spin_lock_irqsave(&ioapic_lock, flags);
1962 reg_01.raw = io_apic_read(apic, 1);
1963 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1964 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1967 if (!legacy_pic->nr_legacy_irqs)
1970 for(apic = 0; apic < nr_ioapics; apic++) {
1972 /* See if any of the pins is in ExtINT mode */
1973 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1974 struct IO_APIC_route_entry entry;
1975 entry = ioapic_read_entry(apic, pin);
1977 /* If the interrupt line is enabled and in ExtInt mode
1978 * I have found the pin where the i8259 is connected.
1980 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1981 ioapic_i8259.apic = apic;
1982 ioapic_i8259.pin = pin;
1988 /* Look to see what if the MP table has reported the ExtINT */
1989 /* If we could not find the appropriate pin by looking at the ioapic
1990 * the i8259 probably is not connected the ioapic but give the
1991 * mptable a chance anyway.
1993 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1994 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1995 /* Trust the MP table if nothing is setup in the hardware */
1996 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1997 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1998 ioapic_i8259.pin = i8259_pin;
1999 ioapic_i8259.apic = i8259_apic;
2001 /* Complain if the MP table and the hardware disagree */
2002 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2003 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2005 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2009 * Do not trust the IO-APIC being empty at bootup
2015 * Not an __init, needed by the reboot code
2017 void disable_IO_APIC(void)
2020 * Clear the IO-APIC before rebooting:
2024 if (!legacy_pic->nr_legacy_irqs)
2028 * If the i8259 is routed through an IOAPIC
2029 * Put that IOAPIC in virtual wire mode
2030 * so legacy interrupts can be delivered.
2032 * With interrupt-remapping, for now we will use virtual wire A mode,
2033 * as virtual wire B is little complex (need to configure both
2034 * IOAPIC RTE aswell as interrupt-remapping table entry).
2035 * As this gets called during crash dump, keep this simple for now.
2037 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2038 struct IO_APIC_route_entry entry;
2040 memset(&entry, 0, sizeof(entry));
2041 entry.mask = 0; /* Enabled */
2042 entry.trigger = 0; /* Edge */
2044 entry.polarity = 0; /* High */
2045 entry.delivery_status = 0;
2046 entry.dest_mode = 0; /* Physical */
2047 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2049 entry.dest = read_apic_id();
2052 * Add it to the IO-APIC irq-routing table:
2054 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2058 * Use virtual wire A mode when interrupt remapping is enabled.
2060 if (cpu_has_apic || apic_from_smp_config())
2061 disconnect_bsp_APIC(!intr_remapping_enabled &&
2062 ioapic_i8259.pin != -1);
2065 #ifdef CONFIG_X86_32
2067 * function to set the IO-APIC physical IDs based on the
2068 * values stored in the MPC table.
2070 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2073 void __init setup_ioapic_ids_from_mpc(void)
2075 union IO_APIC_reg_00 reg_00;
2076 physid_mask_t phys_id_present_map;
2079 unsigned char old_id;
2080 unsigned long flags;
2085 * Don't check I/O APIC IDs for xAPIC systems. They have
2086 * no meaning without the serial APIC bus.
2088 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2089 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2092 * This is broken; anything with a real cpu count has to
2093 * circumvent this idiocy regardless.
2095 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2098 * Set the IOAPIC ID to the value stored in the MPC table.
2100 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2102 /* Read the register 0 value */
2103 raw_spin_lock_irqsave(&ioapic_lock, flags);
2104 reg_00.raw = io_apic_read(apic_id, 0);
2105 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2107 old_id = mp_ioapics[apic_id].apicid;
2109 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2110 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2111 apic_id, mp_ioapics[apic_id].apicid);
2112 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2114 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2118 * Sanity check, is the ID really free? Every APIC in a
2119 * system must have a unique ID or we get lots of nice
2120 * 'stuck on smp_invalidate_needed IPI wait' messages.
2122 if (apic->check_apicid_used(&phys_id_present_map,
2123 mp_ioapics[apic_id].apicid)) {
2124 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2125 apic_id, mp_ioapics[apic_id].apicid);
2126 for (i = 0; i < get_physical_broadcast(); i++)
2127 if (!physid_isset(i, phys_id_present_map))
2129 if (i >= get_physical_broadcast())
2130 panic("Max APIC ID exceeded!\n");
2131 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2133 physid_set(i, phys_id_present_map);
2134 mp_ioapics[apic_id].apicid = i;
2137 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2138 apic_printk(APIC_VERBOSE, "Setting %d in the "
2139 "phys_id_present_map\n",
2140 mp_ioapics[apic_id].apicid);
2141 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2146 * We need to adjust the IRQ routing table
2147 * if the ID changed.
2149 if (old_id != mp_ioapics[apic_id].apicid)
2150 for (i = 0; i < mp_irq_entries; i++)
2151 if (mp_irqs[i].dstapic == old_id)
2153 = mp_ioapics[apic_id].apicid;
2156 * Read the right value from the MPC table and
2157 * write it into the ID register.
2159 apic_printk(APIC_VERBOSE, KERN_INFO
2160 "...changing IO-APIC physical APIC ID to %d ...",
2161 mp_ioapics[apic_id].apicid);
2163 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2164 raw_spin_lock_irqsave(&ioapic_lock, flags);
2165 io_apic_write(apic_id, 0, reg_00.raw);
2166 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2171 raw_spin_lock_irqsave(&ioapic_lock, flags);
2172 reg_00.raw = io_apic_read(apic_id, 0);
2173 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2174 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2175 printk("could not set ID!\n");
2177 apic_printk(APIC_VERBOSE, " ok.\n");
2182 int no_timer_check __initdata;
2184 static int __init notimercheck(char *s)
2189 __setup("no_timer_check", notimercheck);
2192 * There is a nasty bug in some older SMP boards, their mptable lies
2193 * about the timer IRQ. We do the following to work around the situation:
2195 * - timer IRQ defaults to IO-APIC IRQ
2196 * - if this function detects that timer IRQs are defunct, then we fall
2197 * back to ISA timer IRQs
2199 static int __init timer_irq_works(void)
2201 unsigned long t1 = jiffies;
2202 unsigned long flags;
2207 local_save_flags(flags);
2209 /* Let ten ticks pass... */
2210 mdelay((10 * 1000) / HZ);
2211 local_irq_restore(flags);
2214 * Expect a few ticks at least, to be sure some possible
2215 * glue logic does not lock up after one or two first
2216 * ticks in a non-ExtINT mode. Also the local APIC
2217 * might have cached one ExtINT interrupt. Finally, at
2218 * least one tick may be lost due to delays.
2222 if (time_after(jiffies, t1 + 4))
2228 * In the SMP+IOAPIC case it might happen that there are an unspecified
2229 * number of pending IRQ events unhandled. These cases are very rare,
2230 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2231 * better to do it this way as thus we do not have to be aware of
2232 * 'pending' interrupts in the IRQ path, except at this point.
2235 * Edge triggered needs to resend any interrupt
2236 * that was delayed but this is now handled in the device
2241 * Starting up a edge-triggered IO-APIC interrupt is
2242 * nasty - we need to make sure that we get the edge.
2243 * If it is already asserted for some reason, we need
2244 * return 1 to indicate that is was pending.
2246 * This is not complete - we should be able to fake
2247 * an edge even if it isn't on the 8259A...
2250 static unsigned int startup_ioapic_irq(unsigned int irq)
2252 int was_pending = 0;
2253 unsigned long flags;
2254 struct irq_cfg *cfg;
2256 raw_spin_lock_irqsave(&ioapic_lock, flags);
2257 if (irq < legacy_pic->nr_legacy_irqs) {
2258 legacy_pic->chip->mask(irq);
2259 if (legacy_pic->irq_pending(irq))
2263 __unmask_IO_APIC_irq(cfg);
2264 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2269 static int ioapic_retrigger_irq(unsigned int irq)
2272 struct irq_cfg *cfg = irq_cfg(irq);
2273 unsigned long flags;
2275 raw_spin_lock_irqsave(&vector_lock, flags);
2276 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2277 raw_spin_unlock_irqrestore(&vector_lock, flags);
2283 * Level and edge triggered IO-APIC interrupts need different handling,
2284 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2285 * handled with the level-triggered descriptor, but that one has slightly
2286 * more overhead. Level-triggered interrupts cannot be handled with the
2287 * edge-triggered handler, without risking IRQ storms and other ugly
2292 void send_cleanup_vector(struct irq_cfg *cfg)
2294 cpumask_var_t cleanup_mask;
2296 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2298 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2299 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2301 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2302 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2303 free_cpumask_var(cleanup_mask);
2305 cfg->move_in_progress = 0;
2308 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2311 struct irq_pin_list *entry;
2312 u8 vector = cfg->vector;
2314 for_each_irq_pin(entry, cfg->irq_2_pin) {
2320 * With interrupt-remapping, destination information comes
2321 * from interrupt-remapping table entry.
2323 if (!irq_remapped(irq))
2324 io_apic_write(apic, 0x11 + pin*2, dest);
2325 reg = io_apic_read(apic, 0x10 + pin*2);
2326 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2328 io_apic_modify(apic, 0x10 + pin*2, reg);
2333 * Either sets desc->affinity to a valid value, and returns
2334 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2335 * leaves desc->affinity untouched.
2338 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2339 unsigned int *dest_id)
2341 struct irq_cfg *cfg;
2344 if (!cpumask_intersects(mask, cpu_online_mask))
2348 cfg = desc->chip_data;
2349 if (assign_irq_vector(irq, cfg, mask))
2352 cpumask_copy(desc->affinity, mask);
2354 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2359 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2361 struct irq_cfg *cfg;
2362 unsigned long flags;
2368 cfg = desc->chip_data;
2370 raw_spin_lock_irqsave(&ioapic_lock, flags);
2371 ret = set_desc_affinity(desc, mask, &dest);
2373 /* Only the high 8 bits are valid. */
2374 dest = SET_APIC_LOGICAL_ID(dest);
2375 __target_IO_APIC_irq(irq, dest, cfg);
2377 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2383 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2385 struct irq_desc *desc;
2387 desc = irq_to_desc(irq);
2389 return set_ioapic_affinity_irq_desc(desc, mask);
2392 #ifdef CONFIG_INTR_REMAP
2395 * Migrate the IO-APIC irq in the presence of intr-remapping.
2397 * For both level and edge triggered, irq migration is a simple atomic
2398 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2400 * For level triggered, we eliminate the io-apic RTE modification (with the
2401 * updated vector information), by using a virtual vector (io-apic pin number).
2402 * Real vector that is used for interrupting cpu will be coming from
2403 * the interrupt-remapping table entry.
2406 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2408 struct irq_cfg *cfg;
2414 if (!cpumask_intersects(mask, cpu_online_mask))
2418 if (get_irte(irq, &irte))
2421 cfg = desc->chip_data;
2422 if (assign_irq_vector(irq, cfg, mask))
2425 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2427 irte.vector = cfg->vector;
2428 irte.dest_id = IRTE_DEST(dest);
2431 * Modified the IRTE and flushes the Interrupt entry cache.
2433 modify_irte(irq, &irte);
2435 if (cfg->move_in_progress)
2436 send_cleanup_vector(cfg);
2438 cpumask_copy(desc->affinity, mask);
2444 * Migrates the IRQ destination in the process context.
2446 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2447 const struct cpumask *mask)
2449 return migrate_ioapic_irq_desc(desc, mask);
2451 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2452 const struct cpumask *mask)
2454 struct irq_desc *desc = irq_to_desc(irq);
2456 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2459 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2460 const struct cpumask *mask)
2466 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2468 unsigned vector, me;
2474 me = smp_processor_id();
2475 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2478 struct irq_desc *desc;
2479 struct irq_cfg *cfg;
2480 irq = __get_cpu_var(vector_irq)[vector];
2485 desc = irq_to_desc(irq);
2490 raw_spin_lock(&desc->lock);
2493 * Check if the irq migration is in progress. If so, we
2494 * haven't received the cleanup request yet for this irq.
2496 if (cfg->move_in_progress)
2499 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2502 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2504 * Check if the vector that needs to be cleanedup is
2505 * registered at the cpu's IRR. If so, then this is not
2506 * the best time to clean it up. Lets clean it up in the
2507 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2510 if (irr & (1 << (vector % 32))) {
2511 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2514 __get_cpu_var(vector_irq)[vector] = -1;
2516 raw_spin_unlock(&desc->lock);
2522 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2524 struct irq_desc *desc = *descp;
2525 struct irq_cfg *cfg = desc->chip_data;
2528 if (likely(!cfg->move_in_progress))
2531 me = smp_processor_id();
2533 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2534 send_cleanup_vector(cfg);
2537 static void irq_complete_move(struct irq_desc **descp)
2539 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2542 void irq_force_complete_move(int irq)
2544 struct irq_desc *desc = irq_to_desc(irq);
2545 struct irq_cfg *cfg = desc->chip_data;
2547 __irq_complete_move(&desc, cfg->vector);
2550 static inline void irq_complete_move(struct irq_desc **descp) {}
2553 static void ack_apic_edge(unsigned int irq)
2555 struct irq_desc *desc = irq_to_desc(irq);
2557 irq_complete_move(&desc);
2558 move_native_irq(irq);
2562 atomic_t irq_mis_count;
2565 * IO-APIC versions below 0x20 don't support EOI register.
2566 * For the record, here is the information about various versions:
2568 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2569 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2572 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2573 * version as 0x2. This is an error with documentation and these ICH chips
2574 * use io-apic's of version 0x20.
2576 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2577 * Otherwise, we simulate the EOI message manually by changing the trigger
2578 * mode to edge and then back to level, with RTE being masked during this.
2580 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2582 struct irq_pin_list *entry;
2584 for_each_irq_pin(entry, cfg->irq_2_pin) {
2585 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2587 * Intr-remapping uses pin number as the virtual vector
2588 * in the RTE. Actual vector is programmed in
2589 * intr-remapping table entry. Hence for the io-apic
2590 * EOI we use the pin number.
2592 if (irq_remapped(irq))
2593 io_apic_eoi(entry->apic, entry->pin);
2595 io_apic_eoi(entry->apic, cfg->vector);
2597 __mask_and_edge_IO_APIC_irq(entry);
2598 __unmask_and_level_IO_APIC_irq(entry);
2603 static void eoi_ioapic_irq(struct irq_desc *desc)
2605 struct irq_cfg *cfg;
2606 unsigned long flags;
2610 cfg = desc->chip_data;
2612 raw_spin_lock_irqsave(&ioapic_lock, flags);
2613 __eoi_ioapic_irq(irq, cfg);
2614 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2617 static void ack_apic_level(unsigned int irq)
2619 struct irq_desc *desc = irq_to_desc(irq);
2622 struct irq_cfg *cfg;
2623 int do_unmask_irq = 0;
2625 irq_complete_move(&desc);
2626 #ifdef CONFIG_GENERIC_PENDING_IRQ
2627 /* If we are moving the irq we need to mask it */
2628 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2630 mask_IO_APIC_irq_desc(desc);
2635 * It appears there is an erratum which affects at least version 0x11
2636 * of I/O APIC (that's the 82093AA and cores integrated into various
2637 * chipsets). Under certain conditions a level-triggered interrupt is
2638 * erroneously delivered as edge-triggered one but the respective IRR
2639 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2640 * message but it will never arrive and further interrupts are blocked
2641 * from the source. The exact reason is so far unknown, but the
2642 * phenomenon was observed when two consecutive interrupt requests
2643 * from a given source get delivered to the same CPU and the source is
2644 * temporarily disabled in between.
2646 * A workaround is to simulate an EOI message manually. We achieve it
2647 * by setting the trigger mode to edge and then to level when the edge
2648 * trigger mode gets detected in the TMR of a local APIC for a
2649 * level-triggered interrupt. We mask the source for the time of the
2650 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2651 * The idea is from Manfred Spraul. --macro
2653 * Also in the case when cpu goes offline, fixup_irqs() will forward
2654 * any unhandled interrupt on the offlined cpu to the new cpu
2655 * destination that is handling the corresponding interrupt. This
2656 * interrupt forwarding is done via IPI's. Hence, in this case also
2657 * level-triggered io-apic interrupt will be seen as an edge
2658 * interrupt in the IRR. And we can't rely on the cpu's EOI
2659 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2660 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2661 * supporting EOI register, we do an explicit EOI to clear the
2662 * remote IRR and on IO-APIC's which don't have an EOI register,
2663 * we use the above logic (mask+edge followed by unmask+level) from
2664 * Manfred Spraul to clear the remote IRR.
2666 cfg = desc->chip_data;
2668 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2671 * We must acknowledge the irq before we move it or the acknowledge will
2672 * not propagate properly.
2677 * Tail end of clearing remote IRR bit (either by delivering the EOI
2678 * message via io-apic EOI register write or simulating it using
2679 * mask+edge followed by unnask+level logic) manually when the
2680 * level triggered interrupt is seen as the edge triggered interrupt
2683 if (!(v & (1 << (i & 0x1f)))) {
2684 atomic_inc(&irq_mis_count);
2686 eoi_ioapic_irq(desc);
2689 /* Now we can move and renable the irq */
2690 if (unlikely(do_unmask_irq)) {
2691 /* Only migrate the irq if the ack has been received.
2693 * On rare occasions the broadcast level triggered ack gets
2694 * delayed going to ioapics, and if we reprogram the
2695 * vector while Remote IRR is still set the irq will never
2698 * To prevent this scenario we read the Remote IRR bit
2699 * of the ioapic. This has two effects.
2700 * - On any sane system the read of the ioapic will
2701 * flush writes (and acks) going to the ioapic from
2703 * - We get to see if the ACK has actually been delivered.
2705 * Based on failed experiments of reprogramming the
2706 * ioapic entry from outside of irq context starting
2707 * with masking the ioapic entry and then polling until
2708 * Remote IRR was clear before reprogramming the
2709 * ioapic I don't trust the Remote IRR bit to be
2710 * completey accurate.
2712 * However there appears to be no other way to plug
2713 * this race, so if the Remote IRR bit is not
2714 * accurate and is causing problems then it is a hardware bug
2715 * and you can go talk to the chipset vendor about it.
2717 cfg = desc->chip_data;
2718 if (!io_apic_level_ack_pending(cfg))
2719 move_masked_irq(irq);
2720 unmask_IO_APIC_irq_desc(desc);
2724 #ifdef CONFIG_INTR_REMAP
2725 static void ir_ack_apic_edge(unsigned int irq)
2730 static void ir_ack_apic_level(unsigned int irq)
2732 struct irq_desc *desc = irq_to_desc(irq);
2735 eoi_ioapic_irq(desc);
2737 #endif /* CONFIG_INTR_REMAP */
2739 static struct irq_chip ioapic_chip __read_mostly = {
2741 .startup = startup_ioapic_irq,
2742 .mask = mask_IO_APIC_irq,
2743 .unmask = unmask_IO_APIC_irq,
2744 .ack = ack_apic_edge,
2745 .eoi = ack_apic_level,
2747 .set_affinity = set_ioapic_affinity_irq,
2749 .retrigger = ioapic_retrigger_irq,
2752 static struct irq_chip ir_ioapic_chip __read_mostly = {
2753 .name = "IR-IO-APIC",
2754 .startup = startup_ioapic_irq,
2755 .mask = mask_IO_APIC_irq,
2756 .unmask = unmask_IO_APIC_irq,
2757 #ifdef CONFIG_INTR_REMAP
2758 .ack = ir_ack_apic_edge,
2759 .eoi = ir_ack_apic_level,
2761 .set_affinity = set_ir_ioapic_affinity_irq,
2764 .retrigger = ioapic_retrigger_irq,
2767 static inline void init_IO_APIC_traps(void)
2770 struct irq_desc *desc;
2771 struct irq_cfg *cfg;
2774 * NOTE! The local APIC isn't very good at handling
2775 * multiple interrupts at the same interrupt level.
2776 * As the interrupt level is determined by taking the
2777 * vector number and shifting that right by 4, we
2778 * want to spread these out a bit so that they don't
2779 * all fall in the same interrupt level.
2781 * Also, we've got to be careful not to trash gate
2782 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2784 for_each_irq_desc(irq, desc) {
2785 cfg = desc->chip_data;
2786 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2788 * Hmm.. We don't have an entry for this,
2789 * so default to an old-fashioned 8259
2790 * interrupt if we can..
2792 if (irq < legacy_pic->nr_legacy_irqs)
2793 legacy_pic->make_irq(irq);
2795 /* Strange. Oh, well.. */
2796 desc->chip = &no_irq_chip;
2802 * The local APIC irq-chip implementation:
2805 static void mask_lapic_irq(unsigned int irq)
2809 v = apic_read(APIC_LVT0);
2810 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2813 static void unmask_lapic_irq(unsigned int irq)
2817 v = apic_read(APIC_LVT0);
2818 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2821 static void ack_lapic_irq(unsigned int irq)
2826 static struct irq_chip lapic_chip __read_mostly = {
2827 .name = "local-APIC",
2828 .mask = mask_lapic_irq,
2829 .unmask = unmask_lapic_irq,
2830 .ack = ack_lapic_irq,
2833 static void lapic_register_intr(int irq, struct irq_desc *desc)
2835 desc->status &= ~IRQ_LEVEL;
2836 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2840 static void __init setup_nmi(void)
2843 * Dirty trick to enable the NMI watchdog ...
2844 * We put the 8259A master into AEOI mode and
2845 * unmask on all local APICs LVT0 as NMI.
2847 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2848 * is from Maciej W. Rozycki - so we do not have to EOI from
2849 * the NMI handler or the timer interrupt.
2851 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2853 enable_NMI_through_LVT0();
2855 apic_printk(APIC_VERBOSE, " done.\n");
2859 * This looks a bit hackish but it's about the only one way of sending
2860 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2861 * not support the ExtINT mode, unfortunately. We need to send these
2862 * cycles as some i82489DX-based boards have glue logic that keeps the
2863 * 8259A interrupt line asserted until INTA. --macro
2865 static inline void __init unlock_ExtINT_logic(void)
2868 struct IO_APIC_route_entry entry0, entry1;
2869 unsigned char save_control, save_freq_select;
2871 pin = find_isa_irq_pin(8, mp_INT);
2876 apic = find_isa_irq_apic(8, mp_INT);
2882 entry0 = ioapic_read_entry(apic, pin);
2883 clear_IO_APIC_pin(apic, pin);
2885 memset(&entry1, 0, sizeof(entry1));
2887 entry1.dest_mode = 0; /* physical delivery */
2888 entry1.mask = 0; /* unmask IRQ now */
2889 entry1.dest = hard_smp_processor_id();
2890 entry1.delivery_mode = dest_ExtINT;
2891 entry1.polarity = entry0.polarity;
2895 ioapic_write_entry(apic, pin, entry1);
2897 save_control = CMOS_READ(RTC_CONTROL);
2898 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2899 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2901 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2906 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2910 CMOS_WRITE(save_control, RTC_CONTROL);
2911 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2912 clear_IO_APIC_pin(apic, pin);
2914 ioapic_write_entry(apic, pin, entry0);
2917 static int disable_timer_pin_1 __initdata;
2918 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2919 static int __init disable_timer_pin_setup(char *arg)
2921 disable_timer_pin_1 = 1;
2924 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2926 int timer_through_8259 __initdata;
2929 * This code may look a bit paranoid, but it's supposed to cooperate with
2930 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2931 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2932 * fanatically on his truly buggy board.
2934 * FIXME: really need to revamp this for all platforms.
2936 static inline void __init check_timer(void)
2938 struct irq_desc *desc = irq_to_desc(0);
2939 struct irq_cfg *cfg = desc->chip_data;
2940 int node = cpu_to_node(boot_cpu_id);
2941 int apic1, pin1, apic2, pin2;
2942 unsigned long flags;
2945 local_irq_save(flags);
2948 * get/set the timer IRQ vector:
2950 legacy_pic->chip->mask(0);
2951 assign_irq_vector(0, cfg, apic->target_cpus());
2954 * As IRQ0 is to be enabled in the 8259A, the virtual
2955 * wire has to be disabled in the local APIC. Also
2956 * timer interrupts need to be acknowledged manually in
2957 * the 8259A for the i82489DX when using the NMI
2958 * watchdog as that APIC treats NMIs as level-triggered.
2959 * The AEOI mode will finish them in the 8259A
2962 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2963 legacy_pic->init(1);
2964 #ifdef CONFIG_X86_32
2968 ver = apic_read(APIC_LVR);
2969 ver = GET_APIC_VERSION(ver);
2970 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2974 pin1 = find_isa_irq_pin(0, mp_INT);
2975 apic1 = find_isa_irq_apic(0, mp_INT);
2976 pin2 = ioapic_i8259.pin;
2977 apic2 = ioapic_i8259.apic;
2979 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2980 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2981 cfg->vector, apic1, pin1, apic2, pin2);
2984 * Some BIOS writers are clueless and report the ExtINTA
2985 * I/O APIC input from the cascaded 8259A as the timer
2986 * interrupt input. So just in case, if only one pin
2987 * was found above, try it both directly and through the
2991 if (intr_remapping_enabled)
2992 panic("BIOS bug: timer not connected to IO-APIC");
2996 } else if (pin2 == -1) {
3003 * Ok, does IRQ0 through the IOAPIC work?
3006 add_pin_to_irq_node(cfg, node, apic1, pin1);
3007 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
3009 /* for edge trigger, setup_IO_APIC_irq already
3010 * leave it unmasked.
3011 * so only need to unmask if it is level-trigger
3012 * do we really have level trigger timer?
3015 idx = find_irq_entry(apic1, pin1, mp_INT);
3016 if (idx != -1 && irq_trigger(idx))
3017 unmask_IO_APIC_irq_desc(desc);
3019 if (timer_irq_works()) {
3020 if (nmi_watchdog == NMI_IO_APIC) {
3022 legacy_pic->chip->unmask(0);
3024 if (disable_timer_pin_1 > 0)
3025 clear_IO_APIC_pin(0, pin1);
3028 if (intr_remapping_enabled)
3029 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3030 local_irq_disable();
3031 clear_IO_APIC_pin(apic1, pin1);
3033 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3034 "8254 timer not connected to IO-APIC\n");
3036 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3037 "(IRQ0) through the 8259A ...\n");
3038 apic_printk(APIC_QUIET, KERN_INFO
3039 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3041 * legacy devices should be connected to IO APIC #0
3043 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3044 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3045 legacy_pic->chip->unmask(0);
3046 if (timer_irq_works()) {
3047 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3048 timer_through_8259 = 1;
3049 if (nmi_watchdog == NMI_IO_APIC) {
3050 legacy_pic->chip->mask(0);
3052 legacy_pic->chip->unmask(0);
3057 * Cleanup, just in case ...
3059 local_irq_disable();
3060 legacy_pic->chip->mask(0);
3061 clear_IO_APIC_pin(apic2, pin2);
3062 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3065 if (nmi_watchdog == NMI_IO_APIC) {
3066 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3067 "through the IO-APIC - disabling NMI Watchdog!\n");
3068 nmi_watchdog = NMI_NONE;
3070 #ifdef CONFIG_X86_32
3074 apic_printk(APIC_QUIET, KERN_INFO
3075 "...trying to set up timer as Virtual Wire IRQ...\n");
3077 lapic_register_intr(0, desc);
3078 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3079 legacy_pic->chip->unmask(0);
3081 if (timer_irq_works()) {
3082 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3085 local_irq_disable();
3086 legacy_pic->chip->mask(0);
3087 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3088 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3090 apic_printk(APIC_QUIET, KERN_INFO
3091 "...trying to set up timer as ExtINT IRQ...\n");
3093 legacy_pic->init(0);
3094 legacy_pic->make_irq(0);
3095 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3097 unlock_ExtINT_logic();
3099 if (timer_irq_works()) {
3100 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3103 local_irq_disable();
3104 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3105 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3106 "report. Then try booting with the 'noapic' option.\n");
3108 local_irq_restore(flags);
3112 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3113 * to devices. However there may be an I/O APIC pin available for
3114 * this interrupt regardless. The pin may be left unconnected, but
3115 * typically it will be reused as an ExtINT cascade interrupt for
3116 * the master 8259A. In the MPS case such a pin will normally be
3117 * reported as an ExtINT interrupt in the MP table. With ACPI
3118 * there is no provision for ExtINT interrupts, and in the absence
3119 * of an override it would be treated as an ordinary ISA I/O APIC
3120 * interrupt, that is edge-triggered and unmasked by default. We
3121 * used to do this, but it caused problems on some systems because
3122 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3123 * the same ExtINT cascade interrupt to drive the local APIC of the
3124 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3125 * the I/O APIC in all cases now. No actual device should request
3126 * it anyway. --macro
3128 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3130 void __init setup_IO_APIC(void)
3134 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3136 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3138 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3140 * Set up IO-APIC IRQ routing.
3142 x86_init.mpparse.setup_ioapic_ids();
3145 setup_IO_APIC_irqs();
3146 init_IO_APIC_traps();
3147 if (legacy_pic->nr_legacy_irqs)
3152 * Called after all the initialization is done. If we didnt find any
3153 * APIC bugs then we can allow the modify fast path
3156 static int __init io_apic_bug_finalize(void)
3158 if (sis_apic_bug == -1)
3163 late_initcall(io_apic_bug_finalize);
3165 struct sysfs_ioapic_data {
3166 struct sys_device dev;
3167 struct IO_APIC_route_entry entry[0];
3169 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3171 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3173 struct IO_APIC_route_entry *entry;
3174 struct sysfs_ioapic_data *data;
3177 data = container_of(dev, struct sysfs_ioapic_data, dev);
3178 entry = data->entry;
3179 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3180 *entry = ioapic_read_entry(dev->id, i);
3185 static int ioapic_resume(struct sys_device *dev)
3187 struct IO_APIC_route_entry *entry;
3188 struct sysfs_ioapic_data *data;
3189 unsigned long flags;
3190 union IO_APIC_reg_00 reg_00;
3193 data = container_of(dev, struct sysfs_ioapic_data, dev);
3194 entry = data->entry;
3196 raw_spin_lock_irqsave(&ioapic_lock, flags);
3197 reg_00.raw = io_apic_read(dev->id, 0);
3198 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3199 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3200 io_apic_write(dev->id, 0, reg_00.raw);
3202 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3203 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3204 ioapic_write_entry(dev->id, i, entry[i]);
3209 static struct sysdev_class ioapic_sysdev_class = {
3211 .suspend = ioapic_suspend,
3212 .resume = ioapic_resume,
3215 static int __init ioapic_init_sysfs(void)
3217 struct sys_device * dev;
3220 error = sysdev_class_register(&ioapic_sysdev_class);
3224 for (i = 0; i < nr_ioapics; i++ ) {
3225 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3226 * sizeof(struct IO_APIC_route_entry);
3227 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3228 if (!mp_ioapic_data[i]) {
3229 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3232 dev = &mp_ioapic_data[i]->dev;
3234 dev->cls = &ioapic_sysdev_class;
3235 error = sysdev_register(dev);
3237 kfree(mp_ioapic_data[i]);
3238 mp_ioapic_data[i] = NULL;
3239 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3247 device_initcall(ioapic_init_sysfs);
3250 * Dynamic irq allocate and deallocation
3252 unsigned int create_irq_nr(unsigned int irq_want, int node)
3254 /* Allocate an unused irq */
3257 unsigned long flags;
3258 struct irq_cfg *cfg_new = NULL;
3259 struct irq_desc *desc_new = NULL;
3262 if (irq_want < nr_irqs_gsi)
3263 irq_want = nr_irqs_gsi;
3265 raw_spin_lock_irqsave(&vector_lock, flags);
3266 for (new = irq_want; new < nr_irqs; new++) {
3267 desc_new = irq_to_desc_alloc_node(new, node);
3269 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3272 cfg_new = desc_new->chip_data;
3274 if (cfg_new->vector != 0)
3277 desc_new = move_irq_desc(desc_new, node);
3278 cfg_new = desc_new->chip_data;
3280 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3284 raw_spin_unlock_irqrestore(&vector_lock, flags);
3287 dynamic_irq_init_keep_chip_data(irq);
3292 int create_irq(void)
3294 int node = cpu_to_node(boot_cpu_id);
3295 unsigned int irq_want;
3298 irq_want = nr_irqs_gsi;
3299 irq = create_irq_nr(irq_want, node);
3307 void destroy_irq(unsigned int irq)
3309 unsigned long flags;
3311 dynamic_irq_cleanup_keep_chip_data(irq);
3314 raw_spin_lock_irqsave(&vector_lock, flags);
3315 __clear_irq_vector(irq, get_irq_chip_data(irq));
3316 raw_spin_unlock_irqrestore(&vector_lock, flags);
3320 * MSI message composition
3322 #ifdef CONFIG_PCI_MSI
3323 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3324 struct msi_msg *msg, u8 hpet_id)
3326 struct irq_cfg *cfg;
3334 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3338 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3340 if (irq_remapped(irq)) {
3345 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3346 BUG_ON(ir_index == -1);
3348 memset (&irte, 0, sizeof(irte));
3351 irte.dst_mode = apic->irq_dest_mode;
3352 irte.trigger_mode = 0; /* edge */
3353 irte.dlvry_mode = apic->irq_delivery_mode;
3354 irte.vector = cfg->vector;
3355 irte.dest_id = IRTE_DEST(dest);
3357 /* Set source-id of interrupt request */
3359 set_msi_sid(&irte, pdev);
3361 set_hpet_sid(&irte, hpet_id);
3363 modify_irte(irq, &irte);
3365 msg->address_hi = MSI_ADDR_BASE_HI;
3366 msg->data = sub_handle;
3367 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3369 MSI_ADDR_IR_INDEX1(ir_index) |
3370 MSI_ADDR_IR_INDEX2(ir_index);
3372 if (x2apic_enabled())
3373 msg->address_hi = MSI_ADDR_BASE_HI |
3374 MSI_ADDR_EXT_DEST_ID(dest);
3376 msg->address_hi = MSI_ADDR_BASE_HI;
3380 ((apic->irq_dest_mode == 0) ?
3381 MSI_ADDR_DEST_MODE_PHYSICAL:
3382 MSI_ADDR_DEST_MODE_LOGICAL) |
3383 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3384 MSI_ADDR_REDIRECTION_CPU:
3385 MSI_ADDR_REDIRECTION_LOWPRI) |
3386 MSI_ADDR_DEST_ID(dest);
3389 MSI_DATA_TRIGGER_EDGE |
3390 MSI_DATA_LEVEL_ASSERT |
3391 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3392 MSI_DATA_DELIVERY_FIXED:
3393 MSI_DATA_DELIVERY_LOWPRI) |
3394 MSI_DATA_VECTOR(cfg->vector);
3400 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3402 struct irq_desc *desc = irq_to_desc(irq);
3403 struct irq_cfg *cfg;
3407 if (set_desc_affinity(desc, mask, &dest))
3410 cfg = desc->chip_data;
3412 read_msi_msg_desc(desc, &msg);
3414 msg.data &= ~MSI_DATA_VECTOR_MASK;
3415 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3416 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3417 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3419 write_msi_msg_desc(desc, &msg);
3423 #ifdef CONFIG_INTR_REMAP
3425 * Migrate the MSI irq to another cpumask. This migration is
3426 * done in the process context using interrupt-remapping hardware.
3429 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3431 struct irq_desc *desc = irq_to_desc(irq);
3432 struct irq_cfg *cfg = desc->chip_data;
3436 if (get_irte(irq, &irte))
3439 if (set_desc_affinity(desc, mask, &dest))
3442 irte.vector = cfg->vector;
3443 irte.dest_id = IRTE_DEST(dest);
3446 * atomically update the IRTE with the new destination and vector.
3448 modify_irte(irq, &irte);
3451 * After this point, all the interrupts will start arriving
3452 * at the new destination. So, time to cleanup the previous
3453 * vector allocation.
3455 if (cfg->move_in_progress)
3456 send_cleanup_vector(cfg);
3462 #endif /* CONFIG_SMP */
3465 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3466 * which implement the MSI or MSI-X Capability Structure.
3468 static struct irq_chip msi_chip = {
3470 .unmask = unmask_msi_irq,
3471 .mask = mask_msi_irq,
3472 .ack = ack_apic_edge,
3474 .set_affinity = set_msi_irq_affinity,
3476 .retrigger = ioapic_retrigger_irq,
3479 static struct irq_chip msi_ir_chip = {
3480 .name = "IR-PCI-MSI",
3481 .unmask = unmask_msi_irq,
3482 .mask = mask_msi_irq,
3483 #ifdef CONFIG_INTR_REMAP
3484 .ack = ir_ack_apic_edge,
3486 .set_affinity = ir_set_msi_irq_affinity,
3489 .retrigger = ioapic_retrigger_irq,
3493 * Map the PCI dev to the corresponding remapping hardware unit
3494 * and allocate 'nvec' consecutive interrupt-remapping table entries
3497 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3499 struct intel_iommu *iommu;
3502 iommu = map_dev_to_ir(dev);
3505 "Unable to map PCI %s to iommu\n", pci_name(dev));
3509 index = alloc_irte(iommu, irq, nvec);
3512 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3519 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3524 ret = msi_compose_msg(dev, irq, &msg, -1);
3528 set_irq_msi(irq, msidesc);
3529 write_msi_msg(irq, &msg);
3531 if (irq_remapped(irq)) {
3532 struct irq_desc *desc = irq_to_desc(irq);
3534 * irq migration in process context
3536 desc->status |= IRQ_MOVE_PCNTXT;
3537 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3539 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3541 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3546 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3549 int ret, sub_handle;
3550 struct msi_desc *msidesc;
3551 unsigned int irq_want;
3552 struct intel_iommu *iommu = NULL;
3556 /* x86 doesn't support multiple MSI yet */
3557 if (type == PCI_CAP_ID_MSI && nvec > 1)
3560 node = dev_to_node(&dev->dev);
3561 irq_want = nr_irqs_gsi;
3563 list_for_each_entry(msidesc, &dev->msi_list, list) {
3564 irq = create_irq_nr(irq_want, node);
3568 if (!intr_remapping_enabled)
3573 * allocate the consecutive block of IRTE's
3576 index = msi_alloc_irte(dev, irq, nvec);
3582 iommu = map_dev_to_ir(dev);
3588 * setup the mapping between the irq and the IRTE
3589 * base index, the sub_handle pointing to the
3590 * appropriate interrupt remap table entry.
3592 set_irte_irq(irq, iommu, index, sub_handle);
3595 ret = setup_msi_irq(dev, msidesc, irq);
3607 void arch_teardown_msi_irq(unsigned int irq)
3612 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3614 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3616 struct irq_desc *desc = irq_to_desc(irq);
3617 struct irq_cfg *cfg;
3621 if (set_desc_affinity(desc, mask, &dest))
3624 cfg = desc->chip_data;
3626 dmar_msi_read(irq, &msg);
3628 msg.data &= ~MSI_DATA_VECTOR_MASK;
3629 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3630 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3631 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3633 dmar_msi_write(irq, &msg);
3638 #endif /* CONFIG_SMP */
3640 static struct irq_chip dmar_msi_type = {
3642 .unmask = dmar_msi_unmask,
3643 .mask = dmar_msi_mask,
3644 .ack = ack_apic_edge,
3646 .set_affinity = dmar_msi_set_affinity,
3648 .retrigger = ioapic_retrigger_irq,
3651 int arch_setup_dmar_msi(unsigned int irq)
3656 ret = msi_compose_msg(NULL, irq, &msg, -1);
3659 dmar_msi_write(irq, &msg);
3660 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3666 #ifdef CONFIG_HPET_TIMER
3669 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3671 struct irq_desc *desc = irq_to_desc(irq);
3672 struct irq_cfg *cfg;
3676 if (set_desc_affinity(desc, mask, &dest))
3679 cfg = desc->chip_data;
3681 hpet_msi_read(irq, &msg);
3683 msg.data &= ~MSI_DATA_VECTOR_MASK;
3684 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3685 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3686 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3688 hpet_msi_write(irq, &msg);
3693 #endif /* CONFIG_SMP */
3695 static struct irq_chip ir_hpet_msi_type = {
3696 .name = "IR-HPET_MSI",
3697 .unmask = hpet_msi_unmask,
3698 .mask = hpet_msi_mask,
3699 #ifdef CONFIG_INTR_REMAP
3700 .ack = ir_ack_apic_edge,
3702 .set_affinity = ir_set_msi_irq_affinity,
3705 .retrigger = ioapic_retrigger_irq,
3708 static struct irq_chip hpet_msi_type = {
3710 .unmask = hpet_msi_unmask,
3711 .mask = hpet_msi_mask,
3712 .ack = ack_apic_edge,
3714 .set_affinity = hpet_msi_set_affinity,
3716 .retrigger = ioapic_retrigger_irq,
3719 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3723 struct irq_desc *desc = irq_to_desc(irq);
3725 if (intr_remapping_enabled) {
3726 struct intel_iommu *iommu = map_hpet_to_ir(id);
3732 index = alloc_irte(iommu, irq, 1);
3737 ret = msi_compose_msg(NULL, irq, &msg, id);
3741 hpet_msi_write(irq, &msg);
3742 desc->status |= IRQ_MOVE_PCNTXT;
3743 if (irq_remapped(irq))
3744 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3745 handle_edge_irq, "edge");
3747 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3748 handle_edge_irq, "edge");
3754 #endif /* CONFIG_PCI_MSI */
3756 * Hypertransport interrupt support
3758 #ifdef CONFIG_HT_IRQ
3762 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3764 struct ht_irq_msg msg;
3765 fetch_ht_irq_msg(irq, &msg);
3767 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3768 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3770 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3771 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3773 write_ht_irq_msg(irq, &msg);
3776 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3778 struct irq_desc *desc = irq_to_desc(irq);
3779 struct irq_cfg *cfg;
3782 if (set_desc_affinity(desc, mask, &dest))
3785 cfg = desc->chip_data;
3787 target_ht_irq(irq, dest, cfg->vector);
3794 static struct irq_chip ht_irq_chip = {
3796 .mask = mask_ht_irq,
3797 .unmask = unmask_ht_irq,
3798 .ack = ack_apic_edge,
3800 .set_affinity = set_ht_irq_affinity,
3802 .retrigger = ioapic_retrigger_irq,
3805 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3807 struct irq_cfg *cfg;
3814 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3816 struct ht_irq_msg msg;
3819 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3820 apic->target_cpus());
3822 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3826 HT_IRQ_LOW_DEST_ID(dest) |
3827 HT_IRQ_LOW_VECTOR(cfg->vector) |
3828 ((apic->irq_dest_mode == 0) ?
3829 HT_IRQ_LOW_DM_PHYSICAL :
3830 HT_IRQ_LOW_DM_LOGICAL) |
3831 HT_IRQ_LOW_RQEOI_EDGE |
3832 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3833 HT_IRQ_LOW_MT_FIXED :
3834 HT_IRQ_LOW_MT_ARBITRATED) |
3835 HT_IRQ_LOW_IRQ_MASKED;
3837 write_ht_irq_msg(irq, &msg);
3839 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3840 handle_edge_irq, "edge");
3842 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3846 #endif /* CONFIG_HT_IRQ */
3848 int __init io_apic_get_redir_entries (int ioapic)
3850 union IO_APIC_reg_01 reg_01;
3851 unsigned long flags;
3853 raw_spin_lock_irqsave(&ioapic_lock, flags);
3854 reg_01.raw = io_apic_read(ioapic, 1);
3855 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3857 return reg_01.bits.entries;
3860 void __init probe_nr_irqs_gsi(void)
3864 nr = acpi_probe_gsi();
3865 if (nr > nr_irqs_gsi) {
3868 /* for acpi=off or acpi is not compiled in */
3872 for (idx = 0; idx < nr_ioapics; idx++)
3873 nr += io_apic_get_redir_entries(idx) + 1;
3875 if (nr > nr_irqs_gsi)
3879 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3882 #ifdef CONFIG_SPARSE_IRQ
3883 int __init arch_probe_nr_irqs(void)
3887 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3888 nr_irqs = NR_VECTORS * nr_cpu_ids;
3890 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3891 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3893 * for MSI and HT dyn irq
3895 nr += nr_irqs_gsi * 16;
3904 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3905 struct io_apic_irq_attr *irq_attr)
3907 struct irq_desc *desc;
3908 struct irq_cfg *cfg;
3911 int trigger, polarity;
3913 ioapic = irq_attr->ioapic;
3914 if (!IO_APIC_IRQ(irq)) {
3915 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3921 node = dev_to_node(dev);
3923 node = cpu_to_node(boot_cpu_id);
3925 desc = irq_to_desc_alloc_node(irq, node);
3927 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3931 pin = irq_attr->ioapic_pin;
3932 trigger = irq_attr->trigger;
3933 polarity = irq_attr->polarity;
3936 * IRQs < 16 are already in the irq_2_pin[] map
3938 if (irq >= legacy_pic->nr_legacy_irqs) {
3939 cfg = desc->chip_data;
3940 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3941 printk(KERN_INFO "can not add pin %d for irq %d\n",
3947 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3952 int io_apic_set_pci_routing(struct device *dev, int irq,
3953 struct io_apic_irq_attr *irq_attr)
3957 * Avoid pin reprogramming. PRTs typically include entries
3958 * with redundant pin->gsi mappings (but unique PCI devices);
3959 * we only program the IOAPIC on the first.
3961 ioapic = irq_attr->ioapic;
3962 pin = irq_attr->ioapic_pin;
3963 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3964 pr_debug("Pin %d-%d already programmed\n",
3965 mp_ioapics[ioapic].apicid, pin);
3968 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3970 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3973 u8 __init io_apic_unique_id(u8 id)
3975 #ifdef CONFIG_X86_32
3976 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3977 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3978 return io_apic_get_unique_id(nr_ioapics, id);
3983 DECLARE_BITMAP(used, 256);
3985 bitmap_zero(used, 256);
3986 for (i = 0; i < nr_ioapics; i++) {
3987 struct mpc_ioapic *ia = &mp_ioapics[i];
3988 __set_bit(ia->apicid, used);
3990 if (!test_bit(id, used))
3992 return find_first_zero_bit(used, 256);
3996 #ifdef CONFIG_X86_32
3997 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3999 union IO_APIC_reg_00 reg_00;
4000 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
4002 unsigned long flags;
4006 * The P4 platform supports up to 256 APIC IDs on two separate APIC
4007 * buses (one for LAPICs, one for IOAPICs), where predecessors only
4008 * supports up to 16 on one shared APIC bus.
4010 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
4011 * advantage of new APIC bus architecture.
4014 if (physids_empty(apic_id_map))
4015 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
4017 raw_spin_lock_irqsave(&ioapic_lock, flags);
4018 reg_00.raw = io_apic_read(ioapic, 0);
4019 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4021 if (apic_id >= get_physical_broadcast()) {
4022 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
4023 "%d\n", ioapic, apic_id, reg_00.bits.ID);
4024 apic_id = reg_00.bits.ID;
4028 * Every APIC in a system must have a unique ID or we get lots of nice
4029 * 'stuck on smp_invalidate_needed IPI wait' messages.
4031 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
4033 for (i = 0; i < get_physical_broadcast(); i++) {
4034 if (!apic->check_apicid_used(&apic_id_map, i))
4038 if (i == get_physical_broadcast())
4039 panic("Max apic_id exceeded!\n");
4041 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
4042 "trying %d\n", ioapic, apic_id, i);
4047 apic->apicid_to_cpu_present(apic_id, &tmp);
4048 physids_or(apic_id_map, apic_id_map, tmp);
4050 if (reg_00.bits.ID != apic_id) {
4051 reg_00.bits.ID = apic_id;
4053 raw_spin_lock_irqsave(&ioapic_lock, flags);
4054 io_apic_write(ioapic, 0, reg_00.raw);
4055 reg_00.raw = io_apic_read(ioapic, 0);
4056 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4059 if (reg_00.bits.ID != apic_id) {
4060 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4065 apic_printk(APIC_VERBOSE, KERN_INFO
4066 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4072 int __init io_apic_get_version(int ioapic)
4074 union IO_APIC_reg_01 reg_01;
4075 unsigned long flags;
4077 raw_spin_lock_irqsave(&ioapic_lock, flags);
4078 reg_01.raw = io_apic_read(ioapic, 1);
4079 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4081 return reg_01.bits.version;
4084 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4088 if (skip_ioapic_setup)
4091 for (i = 0; i < mp_irq_entries; i++)
4092 if (mp_irqs[i].irqtype == mp_INT &&
4093 mp_irqs[i].srcbusirq == bus_irq)
4095 if (i >= mp_irq_entries)
4098 *trigger = irq_trigger(i);
4099 *polarity = irq_polarity(i);
4104 * This function currently is only a helper for the i386 smp boot process where
4105 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4106 * so mask in all cases should simply be apic->target_cpus()
4109 void __init setup_ioapic_dest(void)
4111 int pin, ioapic, irq, irq_entry;
4112 struct irq_desc *desc;
4113 const struct cpumask *mask;
4115 if (skip_ioapic_setup == 1)
4118 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
4119 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4120 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4121 if (irq_entry == -1)
4123 irq = pin_2_irq(irq_entry, ioapic, pin);
4125 if ((ioapic > 0) && (irq > 16))
4128 desc = irq_to_desc(irq);
4131 * Honour affinities which have been set in early boot
4134 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4135 mask = desc->affinity;
4137 mask = apic->target_cpus();
4139 if (intr_remapping_enabled)
4140 set_ir_ioapic_affinity_irq_desc(desc, mask);
4142 set_ioapic_affinity_irq_desc(desc, mask);
4148 #define IOAPIC_RESOURCE_NAME_SIZE 11
4150 static struct resource *ioapic_resources;
4152 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4155 struct resource *res;
4159 if (nr_ioapics <= 0)
4162 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4165 mem = alloc_bootmem(n);
4168 mem += sizeof(struct resource) * nr_ioapics;
4170 for (i = 0; i < nr_ioapics; i++) {
4172 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4173 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4174 mem += IOAPIC_RESOURCE_NAME_SIZE;
4177 ioapic_resources = res;
4182 void __init ioapic_init_mappings(void)
4184 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4185 struct resource *ioapic_res;
4188 ioapic_res = ioapic_setup_resources(nr_ioapics);
4189 for (i = 0; i < nr_ioapics; i++) {
4190 if (smp_found_config) {
4191 ioapic_phys = mp_ioapics[i].apicaddr;
4192 #ifdef CONFIG_X86_32
4195 "WARNING: bogus zero IO-APIC "
4196 "address found in MPTABLE, "
4197 "disabling IO/APIC support!\n");
4198 smp_found_config = 0;
4199 skip_ioapic_setup = 1;
4200 goto fake_ioapic_page;
4204 #ifdef CONFIG_X86_32
4207 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4208 ioapic_phys = __pa(ioapic_phys);
4210 set_fixmap_nocache(idx, ioapic_phys);
4211 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4212 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4216 ioapic_res->start = ioapic_phys;
4217 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4222 void __init ioapic_insert_resources(void)
4225 struct resource *r = ioapic_resources;
4230 "IO APIC resources couldn't be allocated.\n");
4234 for (i = 0; i < nr_ioapics; i++) {
4235 insert_resource(&iomem_resource, r);
4240 int mp_find_ioapic(int gsi)
4244 /* Find the IOAPIC that manages this GSI. */
4245 for (i = 0; i < nr_ioapics; i++) {
4246 if ((gsi >= mp_gsi_routing[i].gsi_base)
4247 && (gsi <= mp_gsi_routing[i].gsi_end))
4251 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4255 int mp_find_ioapic_pin(int ioapic, int gsi)
4257 if (WARN_ON(ioapic == -1))
4259 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4262 return gsi - mp_gsi_routing[ioapic].gsi_base;
4265 static int bad_ioapic(unsigned long address)
4267 if (nr_ioapics >= MAX_IO_APICS) {
4268 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4269 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4273 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4274 " found in table, skipping!\n");
4280 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4284 if (bad_ioapic(address))
4289 mp_ioapics[idx].type = MP_IOAPIC;
4290 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4291 mp_ioapics[idx].apicaddr = address;
4293 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4294 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4295 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4298 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4299 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4301 mp_gsi_routing[idx].gsi_base = gsi_base;
4302 mp_gsi_routing[idx].gsi_end = gsi_base +
4303 io_apic_get_redir_entries(idx);
4305 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4306 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4307 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4308 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4313 /* Enable IOAPIC early just for system timer */
4314 void __init pre_init_apic_IRQ0(void)
4316 struct irq_cfg *cfg;
4317 struct irq_desc *desc;
4319 printk(KERN_INFO "Early APIC setup for system timer0\n");
4321 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
4323 desc = irq_to_desc_alloc_node(0, 0);
4328 add_pin_to_irq_node(cfg, 0, 0, 0);
4329 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4331 setup_IO_APIC_irq(0, 0, 0, desc, 0, 0);