2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* The one past the highest gsi number used */
94 /* MP IRQ source entries */
95 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
97 /* # of MP IRQ source entries */
101 static int nr_irqs_gsi = NR_IRQS_LEGACY;
103 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
104 int mp_bus_id_to_type[MAX_MP_BUSSES];
107 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
109 int skip_ioapic_setup;
112 * disable_ioapic_support() - disables ioapic support at runtime
114 void disable_ioapic_support(void)
118 noioapicreroute = -1;
120 skip_ioapic_setup = 1;
123 static int __init parse_noapic(char *str)
125 /* disable IO-APIC */
126 disable_ioapic_support();
129 early_param("noapic", parse_noapic);
131 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
132 void mp_save_irq(struct mpc_intsrc *m)
136 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
137 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
138 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
139 m->srcbusirq, m->dstapic, m->dstirq);
141 for (i = 0; i < mp_irq_entries; i++) {
142 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
146 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
147 if (++mp_irq_entries == MAX_IRQ_SOURCES)
148 panic("Max # of irq sources exceeded!!\n");
151 struct irq_pin_list {
153 struct irq_pin_list *next;
156 static struct irq_pin_list *alloc_irq_pin_list(int node)
158 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
162 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
163 #ifdef CONFIG_SPARSE_IRQ
164 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
166 static struct irq_cfg irq_cfgx[NR_IRQS];
169 int __init arch_early_irq_init(void)
174 if (!legacy_pic->nr_legacy_irqs) {
180 count = ARRAY_SIZE(irq_cfgx);
181 node = cpu_to_node(0);
183 /* Make sure the legacy interrupts are marked in the bitmap */
184 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
186 for (i = 0; i < count; i++) {
187 set_irq_chip_data(i, &cfg[i]);
188 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
189 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
191 * For legacy IRQ's, start with assigning irq0 to irq15 to
192 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
194 if (i < legacy_pic->nr_legacy_irqs) {
195 cfg[i].vector = IRQ0_VECTOR + i;
196 cpumask_set_cpu(0, cfg[i].domain);
203 #ifdef CONFIG_SPARSE_IRQ
204 static struct irq_cfg *irq_cfg(unsigned int irq)
206 return get_irq_chip_data(irq);
209 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
213 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
216 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
218 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
222 free_cpumask_var(cfg->domain);
228 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
232 set_irq_chip_data(at, NULL);
233 free_cpumask_var(cfg->domain);
234 free_cpumask_var(cfg->old_domain);
240 struct irq_cfg *irq_cfg(unsigned int irq)
242 return irq < nr_irqs ? irq_cfgx + irq : NULL;
245 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
247 return irq_cfgx + irq;
250 static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { }
254 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
256 int res = irq_alloc_desc_at(at, node);
262 cfg = get_irq_chip_data(at);
267 cfg = alloc_irq_cfg(at, node);
269 set_irq_chip_data(at, cfg);
275 static int alloc_irq_from(unsigned int from, int node)
277 return irq_alloc_desc_from(from, node);
280 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
282 free_irq_cfg(at, cfg);
288 unsigned int unused[3];
290 unsigned int unused2[11];
294 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
296 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
297 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
300 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
302 struct io_apic __iomem *io_apic = io_apic_base(apic);
303 writel(vector, &io_apic->eoi);
306 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
308 struct io_apic __iomem *io_apic = io_apic_base(apic);
309 writel(reg, &io_apic->index);
310 return readl(&io_apic->data);
313 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
315 struct io_apic __iomem *io_apic = io_apic_base(apic);
316 writel(reg, &io_apic->index);
317 writel(value, &io_apic->data);
321 * Re-write a value: to be used for read-modify-write
322 * cycles where the read already set up the index register.
324 * Older SiS APIC requires we rewrite the index register
326 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
328 struct io_apic __iomem *io_apic = io_apic_base(apic);
331 writel(reg, &io_apic->index);
332 writel(value, &io_apic->data);
335 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
337 struct irq_pin_list *entry;
340 raw_spin_lock_irqsave(&ioapic_lock, flags);
341 for_each_irq_pin(entry, cfg->irq_2_pin) {
346 reg = io_apic_read(entry->apic, 0x10 + pin*2);
347 /* Is the remote IRR bit set? */
348 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
349 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
353 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
359 struct { u32 w1, w2; };
360 struct IO_APIC_route_entry entry;
363 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
365 union entry_union eu;
367 raw_spin_lock_irqsave(&ioapic_lock, flags);
368 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
369 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
370 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
375 * When we write a new IO APIC routing entry, we need to write the high
376 * word first! If the mask bit in the low word is clear, we will enable
377 * the interrupt, and we need to make sure the entry is fully populated
378 * before that happens.
381 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
383 union entry_union eu = {{0, 0}};
386 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
387 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
390 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
393 raw_spin_lock_irqsave(&ioapic_lock, flags);
394 __ioapic_write_entry(apic, pin, e);
395 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
399 * When we mask an IO APIC routing entry, we need to write the low
400 * word first, in order to set the mask bit before we change the
403 static void ioapic_mask_entry(int apic, int pin)
406 union entry_union eu = { .entry.mask = 1 };
408 raw_spin_lock_irqsave(&ioapic_lock, flags);
409 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
410 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
411 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
415 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
416 * shared ISA-space IRQs, so we have to support them. We are super
417 * fast in the common case, and fast for shared ISA-space IRQs.
420 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
422 struct irq_pin_list **last, *entry;
424 /* don't allow duplicates */
425 last = &cfg->irq_2_pin;
426 for_each_irq_pin(entry, cfg->irq_2_pin) {
427 if (entry->apic == apic && entry->pin == pin)
432 entry = alloc_irq_pin_list(node);
434 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
445 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
447 if (__add_pin_to_irq_node(cfg, node, apic, pin))
448 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
452 * Reroute an IRQ to a different pin.
454 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
455 int oldapic, int oldpin,
456 int newapic, int newpin)
458 struct irq_pin_list *entry;
460 for_each_irq_pin(entry, cfg->irq_2_pin) {
461 if (entry->apic == oldapic && entry->pin == oldpin) {
462 entry->apic = newapic;
464 /* every one is different, right? */
469 /* old apic/pin didn't exist, so just add new ones */
470 add_pin_to_irq_node(cfg, node, newapic, newpin);
473 static void __io_apic_modify_irq(struct irq_pin_list *entry,
474 int mask_and, int mask_or,
475 void (*final)(struct irq_pin_list *entry))
477 unsigned int reg, pin;
480 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
483 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
488 static void io_apic_modify_irq(struct irq_cfg *cfg,
489 int mask_and, int mask_or,
490 void (*final)(struct irq_pin_list *entry))
492 struct irq_pin_list *entry;
494 for_each_irq_pin(entry, cfg->irq_2_pin)
495 __io_apic_modify_irq(entry, mask_and, mask_or, final);
498 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
500 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
501 IO_APIC_REDIR_MASKED, NULL);
504 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
506 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
507 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
510 static void io_apic_sync(struct irq_pin_list *entry)
513 * Synchronize the IO-APIC and the CPU by doing
514 * a dummy read from the IO-APIC
516 struct io_apic __iomem *io_apic;
517 io_apic = io_apic_base(entry->apic);
518 readl(&io_apic->data);
521 static void mask_ioapic(struct irq_cfg *cfg)
525 raw_spin_lock_irqsave(&ioapic_lock, flags);
526 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
527 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
530 static void mask_ioapic_irq(struct irq_data *data)
532 mask_ioapic(data->chip_data);
535 static void __unmask_ioapic(struct irq_cfg *cfg)
537 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
540 static void unmask_ioapic(struct irq_cfg *cfg)
544 raw_spin_lock_irqsave(&ioapic_lock, flags);
545 __unmask_ioapic(cfg);
546 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
549 static void unmask_ioapic_irq(struct irq_data *data)
551 unmask_ioapic(data->chip_data);
554 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
556 struct IO_APIC_route_entry entry;
558 /* Check delivery_mode to be sure we're not clearing an SMI pin */
559 entry = ioapic_read_entry(apic, pin);
560 if (entry.delivery_mode == dest_SMI)
563 * Disable it in the IO-APIC irq-routing table:
565 ioapic_mask_entry(apic, pin);
568 static void clear_IO_APIC (void)
572 for (apic = 0; apic < nr_ioapics; apic++)
573 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
574 clear_IO_APIC_pin(apic, pin);
579 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
580 * specific CPU-side IRQs.
584 static int pirq_entries[MAX_PIRQS] = {
585 [0 ... MAX_PIRQS - 1] = -1
588 static int __init ioapic_pirq_setup(char *str)
591 int ints[MAX_PIRQS+1];
593 get_options(str, ARRAY_SIZE(ints), ints);
595 apic_printk(APIC_VERBOSE, KERN_INFO
596 "PIRQ redirection, working around broken MP-BIOS.\n");
598 if (ints[0] < MAX_PIRQS)
601 for (i = 0; i < max; i++) {
602 apic_printk(APIC_VERBOSE, KERN_DEBUG
603 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
605 * PIRQs are mapped upside down, usually.
607 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
612 __setup("pirq=", ioapic_pirq_setup);
613 #endif /* CONFIG_X86_32 */
615 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
618 struct IO_APIC_route_entry **ioapic_entries;
620 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
625 for (apic = 0; apic < nr_ioapics; apic++) {
626 ioapic_entries[apic] =
627 kzalloc(sizeof(struct IO_APIC_route_entry) *
628 nr_ioapic_registers[apic], GFP_KERNEL);
629 if (!ioapic_entries[apic])
633 return ioapic_entries;
637 kfree(ioapic_entries[apic]);
638 kfree(ioapic_entries);
644 * Saves all the IO-APIC RTE's
646 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
653 for (apic = 0; apic < nr_ioapics; apic++) {
654 if (!ioapic_entries[apic])
657 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
658 ioapic_entries[apic][pin] =
659 ioapic_read_entry(apic, pin);
666 * Mask all IO APIC entries.
668 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
675 for (apic = 0; apic < nr_ioapics; apic++) {
676 if (!ioapic_entries[apic])
679 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
680 struct IO_APIC_route_entry entry;
682 entry = ioapic_entries[apic][pin];
685 ioapic_write_entry(apic, pin, entry);
692 * Restore IO APIC entries which was saved in ioapic_entries.
694 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
701 for (apic = 0; apic < nr_ioapics; apic++) {
702 if (!ioapic_entries[apic])
705 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
706 ioapic_write_entry(apic, pin,
707 ioapic_entries[apic][pin]);
712 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
716 for (apic = 0; apic < nr_ioapics; apic++)
717 kfree(ioapic_entries[apic]);
719 kfree(ioapic_entries);
723 * Find the IRQ entry number of a certain pin.
725 static int find_irq_entry(int apic, int pin, int type)
729 for (i = 0; i < mp_irq_entries; i++)
730 if (mp_irqs[i].irqtype == type &&
731 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
732 mp_irqs[i].dstapic == MP_APIC_ALL) &&
733 mp_irqs[i].dstirq == pin)
740 * Find the pin to which IRQ[irq] (ISA) is connected
742 static int __init find_isa_irq_pin(int irq, int type)
746 for (i = 0; i < mp_irq_entries; i++) {
747 int lbus = mp_irqs[i].srcbus;
749 if (test_bit(lbus, mp_bus_not_pci) &&
750 (mp_irqs[i].irqtype == type) &&
751 (mp_irqs[i].srcbusirq == irq))
753 return mp_irqs[i].dstirq;
758 static int __init find_isa_irq_apic(int irq, int type)
762 for (i = 0; i < mp_irq_entries; i++) {
763 int lbus = mp_irqs[i].srcbus;
765 if (test_bit(lbus, mp_bus_not_pci) &&
766 (mp_irqs[i].irqtype == type) &&
767 (mp_irqs[i].srcbusirq == irq))
770 if (i < mp_irq_entries) {
772 for(apic = 0; apic < nr_ioapics; apic++) {
773 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
781 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
783 * EISA Edge/Level control register, ELCR
785 static int EISA_ELCR(unsigned int irq)
787 if (irq < legacy_pic->nr_legacy_irqs) {
788 unsigned int port = 0x4d0 + (irq >> 3);
789 return (inb(port) >> (irq & 7)) & 1;
791 apic_printk(APIC_VERBOSE, KERN_INFO
792 "Broken MPtable reports ISA irq %d\n", irq);
798 /* ISA interrupts are always polarity zero edge triggered,
799 * when listed as conforming in the MP table. */
801 #define default_ISA_trigger(idx) (0)
802 #define default_ISA_polarity(idx) (0)
804 /* EISA interrupts are always polarity zero and can be edge or level
805 * trigger depending on the ELCR value. If an interrupt is listed as
806 * EISA conforming in the MP table, that means its trigger type must
807 * be read in from the ELCR */
809 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
810 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
812 /* PCI interrupts are always polarity one level triggered,
813 * when listed as conforming in the MP table. */
815 #define default_PCI_trigger(idx) (1)
816 #define default_PCI_polarity(idx) (1)
818 /* MCA interrupts are always polarity zero level triggered,
819 * when listed as conforming in the MP table. */
821 #define default_MCA_trigger(idx) (1)
822 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
824 static int MPBIOS_polarity(int idx)
826 int bus = mp_irqs[idx].srcbus;
830 * Determine IRQ line polarity (high active or low active):
832 switch (mp_irqs[idx].irqflag & 3)
834 case 0: /* conforms, ie. bus-type dependent polarity */
835 if (test_bit(bus, mp_bus_not_pci))
836 polarity = default_ISA_polarity(idx);
838 polarity = default_PCI_polarity(idx);
840 case 1: /* high active */
845 case 2: /* reserved */
847 printk(KERN_WARNING "broken BIOS!!\n");
851 case 3: /* low active */
856 default: /* invalid */
858 printk(KERN_WARNING "broken BIOS!!\n");
866 static int MPBIOS_trigger(int idx)
868 int bus = mp_irqs[idx].srcbus;
872 * Determine IRQ trigger mode (edge or level sensitive):
874 switch ((mp_irqs[idx].irqflag>>2) & 3)
876 case 0: /* conforms, ie. bus-type dependent */
877 if (test_bit(bus, mp_bus_not_pci))
878 trigger = default_ISA_trigger(idx);
880 trigger = default_PCI_trigger(idx);
881 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
882 switch (mp_bus_id_to_type[bus]) {
883 case MP_BUS_ISA: /* ISA pin */
885 /* set before the switch */
888 case MP_BUS_EISA: /* EISA pin */
890 trigger = default_EISA_trigger(idx);
893 case MP_BUS_PCI: /* PCI pin */
895 /* set before the switch */
898 case MP_BUS_MCA: /* MCA pin */
900 trigger = default_MCA_trigger(idx);
905 printk(KERN_WARNING "broken BIOS!!\n");
917 case 2: /* reserved */
919 printk(KERN_WARNING "broken BIOS!!\n");
928 default: /* invalid */
930 printk(KERN_WARNING "broken BIOS!!\n");
938 static inline int irq_polarity(int idx)
940 return MPBIOS_polarity(idx);
943 static inline int irq_trigger(int idx)
945 return MPBIOS_trigger(idx);
948 static int pin_2_irq(int idx, int apic, int pin)
951 int bus = mp_irqs[idx].srcbus;
954 * Debugging check, we are in big trouble if this message pops up!
956 if (mp_irqs[idx].dstirq != pin)
957 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
959 if (test_bit(bus, mp_bus_not_pci)) {
960 irq = mp_irqs[idx].srcbusirq;
962 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
964 if (gsi >= NR_IRQS_LEGACY)
972 * PCI IRQ command line redirection. Yes, limits are hardcoded.
974 if ((pin >= 16) && (pin <= 23)) {
975 if (pirq_entries[pin-16] != -1) {
976 if (!pirq_entries[pin-16]) {
977 apic_printk(APIC_VERBOSE, KERN_DEBUG
978 "disabling PIRQ%d\n", pin-16);
980 irq = pirq_entries[pin-16];
981 apic_printk(APIC_VERBOSE, KERN_DEBUG
982 "using PIRQ%d -> IRQ %d\n",
993 * Find a specific PCI IRQ entry.
994 * Not an __init, possibly needed by modules
996 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
997 struct io_apic_irq_attr *irq_attr)
999 int apic, i, best_guess = -1;
1001 apic_printk(APIC_DEBUG,
1002 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1004 if (test_bit(bus, mp_bus_not_pci)) {
1005 apic_printk(APIC_VERBOSE,
1006 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1009 for (i = 0; i < mp_irq_entries; i++) {
1010 int lbus = mp_irqs[i].srcbus;
1012 for (apic = 0; apic < nr_ioapics; apic++)
1013 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1014 mp_irqs[i].dstapic == MP_APIC_ALL)
1017 if (!test_bit(lbus, mp_bus_not_pci) &&
1018 !mp_irqs[i].irqtype &&
1020 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1021 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1023 if (!(apic || IO_APIC_IRQ(irq)))
1026 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1027 set_io_apic_irq_attr(irq_attr, apic,
1034 * Use the first all-but-pin matching entry as a
1035 * best-guess fuzzy result for broken mptables.
1037 if (best_guess < 0) {
1038 set_io_apic_irq_attr(irq_attr, apic,
1048 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1050 void lock_vector_lock(void)
1052 /* Used to the online set of cpus does not change
1053 * during assign_irq_vector.
1055 raw_spin_lock(&vector_lock);
1058 void unlock_vector_lock(void)
1060 raw_spin_unlock(&vector_lock);
1064 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1067 * NOTE! The local APIC isn't very good at handling
1068 * multiple interrupts at the same interrupt level.
1069 * As the interrupt level is determined by taking the
1070 * vector number and shifting that right by 4, we
1071 * want to spread these out a bit so that they don't
1072 * all fall in the same interrupt level.
1074 * Also, we've got to be careful not to trash gate
1075 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1077 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1078 static int current_offset = VECTOR_OFFSET_START % 8;
1079 unsigned int old_vector;
1081 cpumask_var_t tmp_mask;
1083 if (cfg->move_in_progress)
1086 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1089 old_vector = cfg->vector;
1091 cpumask_and(tmp_mask, mask, cpu_online_mask);
1092 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1093 if (!cpumask_empty(tmp_mask)) {
1094 free_cpumask_var(tmp_mask);
1099 /* Only try and allocate irqs on cpus that are present */
1101 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1105 apic->vector_allocation_domain(cpu, tmp_mask);
1107 vector = current_vector;
1108 offset = current_offset;
1111 if (vector >= first_system_vector) {
1112 /* If out of vectors on large boxen, must share them. */
1113 offset = (offset + 1) % 8;
1114 vector = FIRST_EXTERNAL_VECTOR + offset;
1116 if (unlikely(current_vector == vector))
1119 if (test_bit(vector, used_vectors))
1122 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1123 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1126 current_vector = vector;
1127 current_offset = offset;
1129 cfg->move_in_progress = 1;
1130 cpumask_copy(cfg->old_domain, cfg->domain);
1132 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1133 per_cpu(vector_irq, new_cpu)[vector] = irq;
1134 cfg->vector = vector;
1135 cpumask_copy(cfg->domain, tmp_mask);
1139 free_cpumask_var(tmp_mask);
1143 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1146 unsigned long flags;
1148 raw_spin_lock_irqsave(&vector_lock, flags);
1149 err = __assign_irq_vector(irq, cfg, mask);
1150 raw_spin_unlock_irqrestore(&vector_lock, flags);
1154 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1158 BUG_ON(!cfg->vector);
1160 vector = cfg->vector;
1161 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1162 per_cpu(vector_irq, cpu)[vector] = -1;
1165 cpumask_clear(cfg->domain);
1167 if (likely(!cfg->move_in_progress))
1169 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1170 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1172 if (per_cpu(vector_irq, cpu)[vector] != irq)
1174 per_cpu(vector_irq, cpu)[vector] = -1;
1178 cfg->move_in_progress = 0;
1181 void __setup_vector_irq(int cpu)
1183 /* Initialize vector_irq on a new cpu */
1185 struct irq_cfg *cfg;
1188 * vector_lock will make sure that we don't run into irq vector
1189 * assignments that might be happening on another cpu in parallel,
1190 * while we setup our initial vector to irq mappings.
1192 raw_spin_lock(&vector_lock);
1193 /* Mark the inuse vectors */
1194 for_each_active_irq(irq) {
1195 cfg = get_irq_chip_data(irq);
1199 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1200 * will be part of the irq_cfg's domain.
1202 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1203 cpumask_set_cpu(cpu, cfg->domain);
1205 if (!cpumask_test_cpu(cpu, cfg->domain))
1207 vector = cfg->vector;
1208 per_cpu(vector_irq, cpu)[vector] = irq;
1210 /* Mark the free vectors */
1211 for (vector = 0; vector < NR_VECTORS; ++vector) {
1212 irq = per_cpu(vector_irq, cpu)[vector];
1217 if (!cpumask_test_cpu(cpu, cfg->domain))
1218 per_cpu(vector_irq, cpu)[vector] = -1;
1220 raw_spin_unlock(&vector_lock);
1223 static struct irq_chip ioapic_chip;
1224 static struct irq_chip ir_ioapic_chip;
1226 #define IOAPIC_AUTO -1
1227 #define IOAPIC_EDGE 0
1228 #define IOAPIC_LEVEL 1
1230 #ifdef CONFIG_X86_32
1231 static inline int IO_APIC_irq_trigger(int irq)
1235 for (apic = 0; apic < nr_ioapics; apic++) {
1236 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1237 idx = find_irq_entry(apic, pin, mp_INT);
1238 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1239 return irq_trigger(idx);
1243 * nonexistent IRQs are edge default
1248 static inline int IO_APIC_irq_trigger(int irq)
1254 static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
1257 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1258 trigger == IOAPIC_LEVEL)
1259 irq_set_status_flags(irq, IRQ_LEVEL);
1261 irq_clear_status_flags(irq, IRQ_LEVEL);
1263 if (irq_remapped(get_irq_chip_data(irq))) {
1264 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1266 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1270 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1271 handle_edge_irq, "edge");
1275 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1276 trigger == IOAPIC_LEVEL)
1277 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1281 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1282 handle_edge_irq, "edge");
1285 static int setup_ioapic_entry(int apic_id, int irq,
1286 struct IO_APIC_route_entry *entry,
1287 unsigned int destination, int trigger,
1288 int polarity, int vector, int pin)
1291 * add it to the IO-APIC irq-routing table:
1293 memset(entry,0,sizeof(*entry));
1295 if (intr_remapping_enabled) {
1296 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1298 struct IR_IO_APIC_route_entry *ir_entry =
1299 (struct IR_IO_APIC_route_entry *) entry;
1303 panic("No mapping iommu for ioapic %d\n", apic_id);
1305 index = alloc_irte(iommu, irq, 1);
1307 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1309 prepare_irte(&irte, vector, destination);
1311 /* Set source-id of interrupt request */
1312 set_ioapic_sid(&irte, apic_id);
1314 modify_irte(irq, &irte);
1316 ir_entry->index2 = (index >> 15) & 0x1;
1318 ir_entry->format = 1;
1319 ir_entry->index = (index & 0x7fff);
1321 * IO-APIC RTE will be configured with virtual vector.
1322 * irq handler will do the explicit EOI to the io-apic.
1324 ir_entry->vector = pin;
1326 entry->delivery_mode = apic->irq_delivery_mode;
1327 entry->dest_mode = apic->irq_dest_mode;
1328 entry->dest = destination;
1329 entry->vector = vector;
1332 entry->mask = 0; /* enable IRQ */
1333 entry->trigger = trigger;
1334 entry->polarity = polarity;
1336 /* Mask level triggered irqs.
1337 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1344 static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1345 struct irq_cfg *cfg, int trigger, int polarity)
1347 struct IO_APIC_route_entry entry;
1350 if (!IO_APIC_IRQ(irq))
1353 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1354 * controllers like 8259. Now that IO-APIC can handle this irq, update
1357 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1358 apic->vector_allocation_domain(0, cfg->domain);
1360 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1363 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1365 apic_printk(APIC_VERBOSE,KERN_DEBUG
1366 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1367 "IRQ %d Mode:%i Active:%i)\n",
1368 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1369 irq, trigger, polarity);
1372 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1373 dest, trigger, polarity, cfg->vector, pin)) {
1374 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1375 mp_ioapics[apic_id].apicid, pin);
1376 __clear_irq_vector(irq, cfg);
1380 ioapic_register_intr(irq, trigger);
1381 if (irq < legacy_pic->nr_legacy_irqs)
1382 legacy_pic->mask(irq);
1384 ioapic_write_entry(apic_id, pin, entry);
1388 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1389 } mp_ioapic_routing[MAX_IO_APICS];
1391 static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
1396 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1397 mp_ioapics[apic_id].apicid, pin);
1401 static void __init __io_apic_setup_irqs(unsigned int apic_id)
1403 int idx, node = cpu_to_node(0);
1404 struct io_apic_irq_attr attr;
1405 unsigned int pin, irq;
1407 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1408 idx = find_irq_entry(apic_id, pin, mp_INT);
1409 if (io_apic_pin_not_connected(idx, apic_id, pin))
1412 irq = pin_2_irq(idx, apic_id, pin);
1414 if ((apic_id > 0) && (irq > 16))
1418 * Skip the timer IRQ if there's a quirk handler
1419 * installed and if it returns 1:
1421 if (apic->multi_timer_check &&
1422 apic->multi_timer_check(apic_id, irq))
1425 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1428 io_apic_setup_irq_pin(irq, node, &attr);
1432 static void __init setup_IO_APIC_irqs(void)
1434 unsigned int apic_id;
1436 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1438 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1439 __io_apic_setup_irqs(apic_id);
1443 * for the gsit that is not in first ioapic
1444 * but could not use acpi_register_gsi()
1445 * like some special sci in IBM x3330
1447 void setup_IO_APIC_irq_extra(u32 gsi)
1449 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
1450 struct io_apic_irq_attr attr;
1453 * Convert 'gsi' to 'ioapic.pin'.
1455 apic_id = mp_find_ioapic(gsi);
1459 pin = mp_find_ioapic_pin(apic_id, gsi);
1460 idx = find_irq_entry(apic_id, pin, mp_INT);
1464 irq = pin_2_irq(idx, apic_id, pin);
1466 /* Only handle the non legacy irqs on secondary ioapics */
1467 if (apic_id == 0 || irq < NR_IRQS_LEGACY)
1470 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1471 pr_debug("Pin %d-%d already programmed\n",
1472 mp_ioapics[apic_id].apicid, pin);
1476 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1479 if (!io_apic_setup_irq_pin(irq, node, &attr))
1480 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1484 * Set up the timer pin, possibly with the 8259A-master behind.
1486 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1489 struct IO_APIC_route_entry entry;
1491 if (intr_remapping_enabled)
1494 memset(&entry, 0, sizeof(entry));
1497 * We use logical delivery to get the timer IRQ
1500 entry.dest_mode = apic->irq_dest_mode;
1501 entry.mask = 0; /* don't mask IRQ for edge */
1502 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1503 entry.delivery_mode = apic->irq_delivery_mode;
1506 entry.vector = vector;
1509 * The timer IRQ doesn't have to know that behind the
1510 * scene we may have a 8259A-master in AEOI mode ...
1512 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1515 * Add it to the IO-APIC irq-routing table:
1517 ioapic_write_entry(apic_id, pin, entry);
1521 __apicdebuginit(void) print_IO_APIC(void)
1524 union IO_APIC_reg_00 reg_00;
1525 union IO_APIC_reg_01 reg_01;
1526 union IO_APIC_reg_02 reg_02;
1527 union IO_APIC_reg_03 reg_03;
1528 unsigned long flags;
1529 struct irq_cfg *cfg;
1532 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1533 for (i = 0; i < nr_ioapics; i++)
1534 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1535 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1538 * We are a bit conservative about what we expect. We have to
1539 * know about every hardware change ASAP.
1541 printk(KERN_INFO "testing the IO APIC.......................\n");
1543 for (apic = 0; apic < nr_ioapics; apic++) {
1545 raw_spin_lock_irqsave(&ioapic_lock, flags);
1546 reg_00.raw = io_apic_read(apic, 0);
1547 reg_01.raw = io_apic_read(apic, 1);
1548 if (reg_01.bits.version >= 0x10)
1549 reg_02.raw = io_apic_read(apic, 2);
1550 if (reg_01.bits.version >= 0x20)
1551 reg_03.raw = io_apic_read(apic, 3);
1552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1555 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1556 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1557 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1558 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1559 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1561 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1562 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1564 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1565 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1568 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1569 * but the value of reg_02 is read as the previous read register
1570 * value, so ignore it if reg_02 == reg_01.
1572 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1573 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1574 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1578 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1579 * or reg_03, but the value of reg_0[23] is read as the previous read
1580 * register value, so ignore it if reg_03 == reg_0[12].
1582 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1583 reg_03.raw != reg_01.raw) {
1584 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1585 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1588 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1590 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1591 " Stat Dmod Deli Vect:\n");
1593 for (i = 0; i <= reg_01.bits.entries; i++) {
1594 struct IO_APIC_route_entry entry;
1596 entry = ioapic_read_entry(apic, i);
1598 printk(KERN_DEBUG " %02x %03X ",
1603 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1608 entry.delivery_status,
1610 entry.delivery_mode,
1615 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1616 for_each_active_irq(irq) {
1617 struct irq_pin_list *entry;
1619 cfg = get_irq_chip_data(irq);
1622 entry = cfg->irq_2_pin;
1625 printk(KERN_DEBUG "IRQ%d ", irq);
1626 for_each_irq_pin(entry, cfg->irq_2_pin)
1627 printk("-> %d:%d", entry->apic, entry->pin);
1631 printk(KERN_INFO ".................................... done.\n");
1636 __apicdebuginit(void) print_APIC_field(int base)
1642 for (i = 0; i < 8; i++)
1643 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1645 printk(KERN_CONT "\n");
1648 __apicdebuginit(void) print_local_APIC(void *dummy)
1650 unsigned int i, v, ver, maxlvt;
1653 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1654 smp_processor_id(), hard_smp_processor_id());
1655 v = apic_read(APIC_ID);
1656 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1657 v = apic_read(APIC_LVR);
1658 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1659 ver = GET_APIC_VERSION(v);
1660 maxlvt = lapic_get_maxlvt();
1662 v = apic_read(APIC_TASKPRI);
1663 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1665 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1666 if (!APIC_XAPIC(ver)) {
1667 v = apic_read(APIC_ARBPRI);
1668 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1669 v & APIC_ARBPRI_MASK);
1671 v = apic_read(APIC_PROCPRI);
1672 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1676 * Remote read supported only in the 82489DX and local APIC for
1677 * Pentium processors.
1679 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1680 v = apic_read(APIC_RRR);
1681 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1684 v = apic_read(APIC_LDR);
1685 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1686 if (!x2apic_enabled()) {
1687 v = apic_read(APIC_DFR);
1688 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1690 v = apic_read(APIC_SPIV);
1691 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1693 printk(KERN_DEBUG "... APIC ISR field:\n");
1694 print_APIC_field(APIC_ISR);
1695 printk(KERN_DEBUG "... APIC TMR field:\n");
1696 print_APIC_field(APIC_TMR);
1697 printk(KERN_DEBUG "... APIC IRR field:\n");
1698 print_APIC_field(APIC_IRR);
1700 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1701 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1702 apic_write(APIC_ESR, 0);
1704 v = apic_read(APIC_ESR);
1705 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1708 icr = apic_icr_read();
1709 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1710 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1712 v = apic_read(APIC_LVTT);
1713 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1715 if (maxlvt > 3) { /* PC is LVT#4. */
1716 v = apic_read(APIC_LVTPC);
1717 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1719 v = apic_read(APIC_LVT0);
1720 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1721 v = apic_read(APIC_LVT1);
1722 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1724 if (maxlvt > 2) { /* ERR is LVT#3. */
1725 v = apic_read(APIC_LVTERR);
1726 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1729 v = apic_read(APIC_TMICT);
1730 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1731 v = apic_read(APIC_TMCCT);
1732 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1733 v = apic_read(APIC_TDCR);
1734 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1736 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1737 v = apic_read(APIC_EFEAT);
1738 maxlvt = (v >> 16) & 0xff;
1739 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1740 v = apic_read(APIC_ECTRL);
1741 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1742 for (i = 0; i < maxlvt; i++) {
1743 v = apic_read(APIC_EILVTn(i));
1744 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1750 __apicdebuginit(void) print_local_APICs(int maxcpu)
1758 for_each_online_cpu(cpu) {
1761 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1766 __apicdebuginit(void) print_PIC(void)
1769 unsigned long flags;
1771 if (!legacy_pic->nr_legacy_irqs)
1774 printk(KERN_DEBUG "\nprinting PIC contents\n");
1776 raw_spin_lock_irqsave(&i8259A_lock, flags);
1778 v = inb(0xa1) << 8 | inb(0x21);
1779 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1781 v = inb(0xa0) << 8 | inb(0x20);
1782 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1786 v = inb(0xa0) << 8 | inb(0x20);
1790 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1792 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1794 v = inb(0x4d1) << 8 | inb(0x4d0);
1795 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1798 static int __initdata show_lapic = 1;
1799 static __init int setup_show_lapic(char *arg)
1803 if (strcmp(arg, "all") == 0) {
1804 show_lapic = CONFIG_NR_CPUS;
1806 get_option(&arg, &num);
1813 __setup("show_lapic=", setup_show_lapic);
1815 __apicdebuginit(int) print_ICs(void)
1817 if (apic_verbosity == APIC_QUIET)
1822 /* don't print out if apic is not there */
1823 if (!cpu_has_apic && !apic_from_smp_config())
1826 print_local_APICs(show_lapic);
1832 fs_initcall(print_ICs);
1835 /* Where if anywhere is the i8259 connect in external int mode */
1836 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1838 void __init enable_IO_APIC(void)
1840 int i8259_apic, i8259_pin;
1843 if (!legacy_pic->nr_legacy_irqs)
1846 for(apic = 0; apic < nr_ioapics; apic++) {
1848 /* See if any of the pins is in ExtINT mode */
1849 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1850 struct IO_APIC_route_entry entry;
1851 entry = ioapic_read_entry(apic, pin);
1853 /* If the interrupt line is enabled and in ExtInt mode
1854 * I have found the pin where the i8259 is connected.
1856 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1857 ioapic_i8259.apic = apic;
1858 ioapic_i8259.pin = pin;
1864 /* Look to see what if the MP table has reported the ExtINT */
1865 /* If we could not find the appropriate pin by looking at the ioapic
1866 * the i8259 probably is not connected the ioapic but give the
1867 * mptable a chance anyway.
1869 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1870 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1871 /* Trust the MP table if nothing is setup in the hardware */
1872 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1873 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1874 ioapic_i8259.pin = i8259_pin;
1875 ioapic_i8259.apic = i8259_apic;
1877 /* Complain if the MP table and the hardware disagree */
1878 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1879 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1881 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1885 * Do not trust the IO-APIC being empty at bootup
1891 * Not an __init, needed by the reboot code
1893 void disable_IO_APIC(void)
1896 * Clear the IO-APIC before rebooting:
1900 if (!legacy_pic->nr_legacy_irqs)
1904 * If the i8259 is routed through an IOAPIC
1905 * Put that IOAPIC in virtual wire mode
1906 * so legacy interrupts can be delivered.
1908 * With interrupt-remapping, for now we will use virtual wire A mode,
1909 * as virtual wire B is little complex (need to configure both
1910 * IOAPIC RTE aswell as interrupt-remapping table entry).
1911 * As this gets called during crash dump, keep this simple for now.
1913 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1914 struct IO_APIC_route_entry entry;
1916 memset(&entry, 0, sizeof(entry));
1917 entry.mask = 0; /* Enabled */
1918 entry.trigger = 0; /* Edge */
1920 entry.polarity = 0; /* High */
1921 entry.delivery_status = 0;
1922 entry.dest_mode = 0; /* Physical */
1923 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1925 entry.dest = read_apic_id();
1928 * Add it to the IO-APIC irq-routing table:
1930 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1934 * Use virtual wire A mode when interrupt remapping is enabled.
1936 if (cpu_has_apic || apic_from_smp_config())
1937 disconnect_bsp_APIC(!intr_remapping_enabled &&
1938 ioapic_i8259.pin != -1);
1941 #ifdef CONFIG_X86_32
1943 * function to set the IO-APIC physical IDs based on the
1944 * values stored in the MPC table.
1946 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1948 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1950 union IO_APIC_reg_00 reg_00;
1951 physid_mask_t phys_id_present_map;
1954 unsigned char old_id;
1955 unsigned long flags;
1958 * This is broken; anything with a real cpu count has to
1959 * circumvent this idiocy regardless.
1961 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1964 * Set the IOAPIC ID to the value stored in the MPC table.
1966 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1968 /* Read the register 0 value */
1969 raw_spin_lock_irqsave(&ioapic_lock, flags);
1970 reg_00.raw = io_apic_read(apic_id, 0);
1971 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1973 old_id = mp_ioapics[apic_id].apicid;
1975 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
1976 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1977 apic_id, mp_ioapics[apic_id].apicid);
1978 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1980 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
1984 * Sanity check, is the ID really free? Every APIC in a
1985 * system must have a unique ID or we get lots of nice
1986 * 'stuck on smp_invalidate_needed IPI wait' messages.
1988 if (apic->check_apicid_used(&phys_id_present_map,
1989 mp_ioapics[apic_id].apicid)) {
1990 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1991 apic_id, mp_ioapics[apic_id].apicid);
1992 for (i = 0; i < get_physical_broadcast(); i++)
1993 if (!physid_isset(i, phys_id_present_map))
1995 if (i >= get_physical_broadcast())
1996 panic("Max APIC ID exceeded!\n");
1997 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1999 physid_set(i, phys_id_present_map);
2000 mp_ioapics[apic_id].apicid = i;
2003 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2004 apic_printk(APIC_VERBOSE, "Setting %d in the "
2005 "phys_id_present_map\n",
2006 mp_ioapics[apic_id].apicid);
2007 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2011 * We need to adjust the IRQ routing table
2012 * if the ID changed.
2014 if (old_id != mp_ioapics[apic_id].apicid)
2015 for (i = 0; i < mp_irq_entries; i++)
2016 if (mp_irqs[i].dstapic == old_id)
2018 = mp_ioapics[apic_id].apicid;
2021 * Update the ID register according to the right value
2022 * from the MPC table if they are different.
2024 if (mp_ioapics[apic_id].apicid == reg_00.bits.ID)
2027 apic_printk(APIC_VERBOSE, KERN_INFO
2028 "...changing IO-APIC physical APIC ID to %d ...",
2029 mp_ioapics[apic_id].apicid);
2031 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2032 raw_spin_lock_irqsave(&ioapic_lock, flags);
2033 io_apic_write(apic_id, 0, reg_00.raw);
2034 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2039 raw_spin_lock_irqsave(&ioapic_lock, flags);
2040 reg_00.raw = io_apic_read(apic_id, 0);
2041 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2042 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2043 printk("could not set ID!\n");
2045 apic_printk(APIC_VERBOSE, " ok.\n");
2049 void __init setup_ioapic_ids_from_mpc(void)
2055 * Don't check I/O APIC IDs for xAPIC systems. They have
2056 * no meaning without the serial APIC bus.
2058 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2059 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2061 setup_ioapic_ids_from_mpc_nocheck();
2065 int no_timer_check __initdata;
2067 static int __init notimercheck(char *s)
2072 __setup("no_timer_check", notimercheck);
2075 * There is a nasty bug in some older SMP boards, their mptable lies
2076 * about the timer IRQ. We do the following to work around the situation:
2078 * - timer IRQ defaults to IO-APIC IRQ
2079 * - if this function detects that timer IRQs are defunct, then we fall
2080 * back to ISA timer IRQs
2082 static int __init timer_irq_works(void)
2084 unsigned long t1 = jiffies;
2085 unsigned long flags;
2090 local_save_flags(flags);
2092 /* Let ten ticks pass... */
2093 mdelay((10 * 1000) / HZ);
2094 local_irq_restore(flags);
2097 * Expect a few ticks at least, to be sure some possible
2098 * glue logic does not lock up after one or two first
2099 * ticks in a non-ExtINT mode. Also the local APIC
2100 * might have cached one ExtINT interrupt. Finally, at
2101 * least one tick may be lost due to delays.
2105 if (time_after(jiffies, t1 + 4))
2111 * In the SMP+IOAPIC case it might happen that there are an unspecified
2112 * number of pending IRQ events unhandled. These cases are very rare,
2113 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2114 * better to do it this way as thus we do not have to be aware of
2115 * 'pending' interrupts in the IRQ path, except at this point.
2118 * Edge triggered needs to resend any interrupt
2119 * that was delayed but this is now handled in the device
2124 * Starting up a edge-triggered IO-APIC interrupt is
2125 * nasty - we need to make sure that we get the edge.
2126 * If it is already asserted for some reason, we need
2127 * return 1 to indicate that is was pending.
2129 * This is not complete - we should be able to fake
2130 * an edge even if it isn't on the 8259A...
2133 static unsigned int startup_ioapic_irq(struct irq_data *data)
2135 int was_pending = 0, irq = data->irq;
2136 unsigned long flags;
2138 raw_spin_lock_irqsave(&ioapic_lock, flags);
2139 if (irq < legacy_pic->nr_legacy_irqs) {
2140 legacy_pic->mask(irq);
2141 if (legacy_pic->irq_pending(irq))
2144 __unmask_ioapic(data->chip_data);
2145 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2150 static int ioapic_retrigger_irq(struct irq_data *data)
2152 struct irq_cfg *cfg = data->chip_data;
2153 unsigned long flags;
2155 raw_spin_lock_irqsave(&vector_lock, flags);
2156 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2157 raw_spin_unlock_irqrestore(&vector_lock, flags);
2163 * Level and edge triggered IO-APIC interrupts need different handling,
2164 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2165 * handled with the level-triggered descriptor, but that one has slightly
2166 * more overhead. Level-triggered interrupts cannot be handled with the
2167 * edge-triggered handler, without risking IRQ storms and other ugly
2172 void send_cleanup_vector(struct irq_cfg *cfg)
2174 cpumask_var_t cleanup_mask;
2176 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2178 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2179 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2181 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2182 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2183 free_cpumask_var(cleanup_mask);
2185 cfg->move_in_progress = 0;
2188 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2191 struct irq_pin_list *entry;
2192 u8 vector = cfg->vector;
2194 for_each_irq_pin(entry, cfg->irq_2_pin) {
2200 * With interrupt-remapping, destination information comes
2201 * from interrupt-remapping table entry.
2203 if (!irq_remapped(cfg))
2204 io_apic_write(apic, 0x11 + pin*2, dest);
2205 reg = io_apic_read(apic, 0x10 + pin*2);
2206 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2208 io_apic_modify(apic, 0x10 + pin*2, reg);
2213 * Either sets data->affinity to a valid value, and returns
2214 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2215 * leaves data->affinity untouched.
2217 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2218 unsigned int *dest_id)
2220 struct irq_cfg *cfg = data->chip_data;
2222 if (!cpumask_intersects(mask, cpu_online_mask))
2225 if (assign_irq_vector(data->irq, data->chip_data, mask))
2228 cpumask_copy(data->affinity, mask);
2230 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2235 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2238 unsigned int dest, irq = data->irq;
2239 unsigned long flags;
2242 raw_spin_lock_irqsave(&ioapic_lock, flags);
2243 ret = __ioapic_set_affinity(data, mask, &dest);
2245 /* Only the high 8 bits are valid. */
2246 dest = SET_APIC_LOGICAL_ID(dest);
2247 __target_IO_APIC_irq(irq, dest, data->chip_data);
2249 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2253 #ifdef CONFIG_INTR_REMAP
2256 * Migrate the IO-APIC irq in the presence of intr-remapping.
2258 * For both level and edge triggered, irq migration is a simple atomic
2259 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2261 * For level triggered, we eliminate the io-apic RTE modification (with the
2262 * updated vector information), by using a virtual vector (io-apic pin number).
2263 * Real vector that is used for interrupting cpu will be coming from
2264 * the interrupt-remapping table entry.
2267 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2270 struct irq_cfg *cfg = data->chip_data;
2271 unsigned int dest, irq = data->irq;
2274 if (!cpumask_intersects(mask, cpu_online_mask))
2277 if (get_irte(irq, &irte))
2280 if (assign_irq_vector(irq, cfg, mask))
2283 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2285 irte.vector = cfg->vector;
2286 irte.dest_id = IRTE_DEST(dest);
2289 * Modified the IRTE and flushes the Interrupt entry cache.
2291 modify_irte(irq, &irte);
2293 if (cfg->move_in_progress)
2294 send_cleanup_vector(cfg);
2296 cpumask_copy(data->affinity, mask);
2302 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2309 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2311 unsigned vector, me;
2317 me = smp_processor_id();
2318 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2321 struct irq_desc *desc;
2322 struct irq_cfg *cfg;
2323 irq = __this_cpu_read(vector_irq[vector]);
2328 desc = irq_to_desc(irq);
2333 raw_spin_lock(&desc->lock);
2336 * Check if the irq migration is in progress. If so, we
2337 * haven't received the cleanup request yet for this irq.
2339 if (cfg->move_in_progress)
2342 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2345 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2347 * Check if the vector that needs to be cleanedup is
2348 * registered at the cpu's IRR. If so, then this is not
2349 * the best time to clean it up. Lets clean it up in the
2350 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2353 if (irr & (1 << (vector % 32))) {
2354 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2357 __this_cpu_write(vector_irq[vector], -1);
2359 raw_spin_unlock(&desc->lock);
2365 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2369 if (likely(!cfg->move_in_progress))
2372 me = smp_processor_id();
2374 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2375 send_cleanup_vector(cfg);
2378 static void irq_complete_move(struct irq_cfg *cfg)
2380 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2383 void irq_force_complete_move(int irq)
2385 struct irq_cfg *cfg = get_irq_chip_data(irq);
2390 __irq_complete_move(cfg, cfg->vector);
2393 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2396 static void ack_apic_edge(struct irq_data *data)
2398 irq_complete_move(data->chip_data);
2399 move_native_irq(data->irq);
2403 atomic_t irq_mis_count;
2406 * IO-APIC versions below 0x20 don't support EOI register.
2407 * For the record, here is the information about various versions:
2409 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2410 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2413 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2414 * version as 0x2. This is an error with documentation and these ICH chips
2415 * use io-apic's of version 0x20.
2417 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2418 * Otherwise, we simulate the EOI message manually by changing the trigger
2419 * mode to edge and then back to level, with RTE being masked during this.
2421 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2423 struct irq_pin_list *entry;
2424 unsigned long flags;
2426 raw_spin_lock_irqsave(&ioapic_lock, flags);
2427 for_each_irq_pin(entry, cfg->irq_2_pin) {
2428 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2430 * Intr-remapping uses pin number as the virtual vector
2431 * in the RTE. Actual vector is programmed in
2432 * intr-remapping table entry. Hence for the io-apic
2433 * EOI we use the pin number.
2435 if (irq_remapped(cfg))
2436 io_apic_eoi(entry->apic, entry->pin);
2438 io_apic_eoi(entry->apic, cfg->vector);
2440 __mask_and_edge_IO_APIC_irq(entry);
2441 __unmask_and_level_IO_APIC_irq(entry);
2444 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2447 static void ack_apic_level(struct irq_data *data)
2449 struct irq_cfg *cfg = data->chip_data;
2450 int i, do_unmask_irq = 0, irq = data->irq;
2453 irq_complete_move(cfg);
2454 #ifdef CONFIG_GENERIC_PENDING_IRQ
2455 /* If we are moving the irq we need to mask it */
2456 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2463 * It appears there is an erratum which affects at least version 0x11
2464 * of I/O APIC (that's the 82093AA and cores integrated into various
2465 * chipsets). Under certain conditions a level-triggered interrupt is
2466 * erroneously delivered as edge-triggered one but the respective IRR
2467 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2468 * message but it will never arrive and further interrupts are blocked
2469 * from the source. The exact reason is so far unknown, but the
2470 * phenomenon was observed when two consecutive interrupt requests
2471 * from a given source get delivered to the same CPU and the source is
2472 * temporarily disabled in between.
2474 * A workaround is to simulate an EOI message manually. We achieve it
2475 * by setting the trigger mode to edge and then to level when the edge
2476 * trigger mode gets detected in the TMR of a local APIC for a
2477 * level-triggered interrupt. We mask the source for the time of the
2478 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2479 * The idea is from Manfred Spraul. --macro
2481 * Also in the case when cpu goes offline, fixup_irqs() will forward
2482 * any unhandled interrupt on the offlined cpu to the new cpu
2483 * destination that is handling the corresponding interrupt. This
2484 * interrupt forwarding is done via IPI's. Hence, in this case also
2485 * level-triggered io-apic interrupt will be seen as an edge
2486 * interrupt in the IRR. And we can't rely on the cpu's EOI
2487 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2488 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2489 * supporting EOI register, we do an explicit EOI to clear the
2490 * remote IRR and on IO-APIC's which don't have an EOI register,
2491 * we use the above logic (mask+edge followed by unmask+level) from
2492 * Manfred Spraul to clear the remote IRR.
2495 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2498 * We must acknowledge the irq before we move it or the acknowledge will
2499 * not propagate properly.
2504 * Tail end of clearing remote IRR bit (either by delivering the EOI
2505 * message via io-apic EOI register write or simulating it using
2506 * mask+edge followed by unnask+level logic) manually when the
2507 * level triggered interrupt is seen as the edge triggered interrupt
2510 if (!(v & (1 << (i & 0x1f)))) {
2511 atomic_inc(&irq_mis_count);
2513 eoi_ioapic_irq(irq, cfg);
2516 /* Now we can move and renable the irq */
2517 if (unlikely(do_unmask_irq)) {
2518 /* Only migrate the irq if the ack has been received.
2520 * On rare occasions the broadcast level triggered ack gets
2521 * delayed going to ioapics, and if we reprogram the
2522 * vector while Remote IRR is still set the irq will never
2525 * To prevent this scenario we read the Remote IRR bit
2526 * of the ioapic. This has two effects.
2527 * - On any sane system the read of the ioapic will
2528 * flush writes (and acks) going to the ioapic from
2530 * - We get to see if the ACK has actually been delivered.
2532 * Based on failed experiments of reprogramming the
2533 * ioapic entry from outside of irq context starting
2534 * with masking the ioapic entry and then polling until
2535 * Remote IRR was clear before reprogramming the
2536 * ioapic I don't trust the Remote IRR bit to be
2537 * completey accurate.
2539 * However there appears to be no other way to plug
2540 * this race, so if the Remote IRR bit is not
2541 * accurate and is causing problems then it is a hardware bug
2542 * and you can go talk to the chipset vendor about it.
2544 if (!io_apic_level_ack_pending(cfg))
2545 move_masked_irq(irq);
2550 #ifdef CONFIG_INTR_REMAP
2551 static void ir_ack_apic_edge(struct irq_data *data)
2556 static void ir_ack_apic_level(struct irq_data *data)
2559 eoi_ioapic_irq(data->irq, data->chip_data);
2561 #endif /* CONFIG_INTR_REMAP */
2563 static struct irq_chip ioapic_chip __read_mostly = {
2565 .irq_startup = startup_ioapic_irq,
2566 .irq_mask = mask_ioapic_irq,
2567 .irq_unmask = unmask_ioapic_irq,
2568 .irq_ack = ack_apic_edge,
2569 .irq_eoi = ack_apic_level,
2571 .irq_set_affinity = ioapic_set_affinity,
2573 .irq_retrigger = ioapic_retrigger_irq,
2576 static struct irq_chip ir_ioapic_chip __read_mostly = {
2577 .name = "IR-IO-APIC",
2578 .irq_startup = startup_ioapic_irq,
2579 .irq_mask = mask_ioapic_irq,
2580 .irq_unmask = unmask_ioapic_irq,
2581 #ifdef CONFIG_INTR_REMAP
2582 .irq_ack = ir_ack_apic_edge,
2583 .irq_eoi = ir_ack_apic_level,
2585 .irq_set_affinity = ir_ioapic_set_affinity,
2588 .irq_retrigger = ioapic_retrigger_irq,
2591 static inline void init_IO_APIC_traps(void)
2593 struct irq_cfg *cfg;
2597 * NOTE! The local APIC isn't very good at handling
2598 * multiple interrupts at the same interrupt level.
2599 * As the interrupt level is determined by taking the
2600 * vector number and shifting that right by 4, we
2601 * want to spread these out a bit so that they don't
2602 * all fall in the same interrupt level.
2604 * Also, we've got to be careful not to trash gate
2605 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2607 for_each_active_irq(irq) {
2608 cfg = get_irq_chip_data(irq);
2609 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2611 * Hmm.. We don't have an entry for this,
2612 * so default to an old-fashioned 8259
2613 * interrupt if we can..
2615 if (irq < legacy_pic->nr_legacy_irqs)
2616 legacy_pic->make_irq(irq);
2618 /* Strange. Oh, well.. */
2619 set_irq_chip(irq, &no_irq_chip);
2625 * The local APIC irq-chip implementation:
2628 static void mask_lapic_irq(struct irq_data *data)
2632 v = apic_read(APIC_LVT0);
2633 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2636 static void unmask_lapic_irq(struct irq_data *data)
2640 v = apic_read(APIC_LVT0);
2641 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2644 static void ack_lapic_irq(struct irq_data *data)
2649 static struct irq_chip lapic_chip __read_mostly = {
2650 .name = "local-APIC",
2651 .irq_mask = mask_lapic_irq,
2652 .irq_unmask = unmask_lapic_irq,
2653 .irq_ack = ack_lapic_irq,
2656 static void lapic_register_intr(int irq)
2658 irq_clear_status_flags(irq, IRQ_LEVEL);
2659 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2664 * This looks a bit hackish but it's about the only one way of sending
2665 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2666 * not support the ExtINT mode, unfortunately. We need to send these
2667 * cycles as some i82489DX-based boards have glue logic that keeps the
2668 * 8259A interrupt line asserted until INTA. --macro
2670 static inline void __init unlock_ExtINT_logic(void)
2673 struct IO_APIC_route_entry entry0, entry1;
2674 unsigned char save_control, save_freq_select;
2676 pin = find_isa_irq_pin(8, mp_INT);
2681 apic = find_isa_irq_apic(8, mp_INT);
2687 entry0 = ioapic_read_entry(apic, pin);
2688 clear_IO_APIC_pin(apic, pin);
2690 memset(&entry1, 0, sizeof(entry1));
2692 entry1.dest_mode = 0; /* physical delivery */
2693 entry1.mask = 0; /* unmask IRQ now */
2694 entry1.dest = hard_smp_processor_id();
2695 entry1.delivery_mode = dest_ExtINT;
2696 entry1.polarity = entry0.polarity;
2700 ioapic_write_entry(apic, pin, entry1);
2702 save_control = CMOS_READ(RTC_CONTROL);
2703 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2704 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2706 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2711 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2715 CMOS_WRITE(save_control, RTC_CONTROL);
2716 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2717 clear_IO_APIC_pin(apic, pin);
2719 ioapic_write_entry(apic, pin, entry0);
2722 static int disable_timer_pin_1 __initdata;
2723 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2724 static int __init disable_timer_pin_setup(char *arg)
2726 disable_timer_pin_1 = 1;
2729 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2731 int timer_through_8259 __initdata;
2734 * This code may look a bit paranoid, but it's supposed to cooperate with
2735 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2736 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2737 * fanatically on his truly buggy board.
2739 * FIXME: really need to revamp this for all platforms.
2741 static inline void __init check_timer(void)
2743 struct irq_cfg *cfg = get_irq_chip_data(0);
2744 int node = cpu_to_node(0);
2745 int apic1, pin1, apic2, pin2;
2746 unsigned long flags;
2749 local_irq_save(flags);
2752 * get/set the timer IRQ vector:
2754 legacy_pic->mask(0);
2755 assign_irq_vector(0, cfg, apic->target_cpus());
2758 * As IRQ0 is to be enabled in the 8259A, the virtual
2759 * wire has to be disabled in the local APIC. Also
2760 * timer interrupts need to be acknowledged manually in
2761 * the 8259A for the i82489DX when using the NMI
2762 * watchdog as that APIC treats NMIs as level-triggered.
2763 * The AEOI mode will finish them in the 8259A
2766 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2767 legacy_pic->init(1);
2769 pin1 = find_isa_irq_pin(0, mp_INT);
2770 apic1 = find_isa_irq_apic(0, mp_INT);
2771 pin2 = ioapic_i8259.pin;
2772 apic2 = ioapic_i8259.apic;
2774 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2775 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2776 cfg->vector, apic1, pin1, apic2, pin2);
2779 * Some BIOS writers are clueless and report the ExtINTA
2780 * I/O APIC input from the cascaded 8259A as the timer
2781 * interrupt input. So just in case, if only one pin
2782 * was found above, try it both directly and through the
2786 if (intr_remapping_enabled)
2787 panic("BIOS bug: timer not connected to IO-APIC");
2791 } else if (pin2 == -1) {
2798 * Ok, does IRQ0 through the IOAPIC work?
2801 add_pin_to_irq_node(cfg, node, apic1, pin1);
2802 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2804 /* for edge trigger, setup_ioapic_irq already
2805 * leave it unmasked.
2806 * so only need to unmask if it is level-trigger
2807 * do we really have level trigger timer?
2810 idx = find_irq_entry(apic1, pin1, mp_INT);
2811 if (idx != -1 && irq_trigger(idx))
2814 if (timer_irq_works()) {
2815 if (disable_timer_pin_1 > 0)
2816 clear_IO_APIC_pin(0, pin1);
2819 if (intr_remapping_enabled)
2820 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2821 local_irq_disable();
2822 clear_IO_APIC_pin(apic1, pin1);
2824 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2825 "8254 timer not connected to IO-APIC\n");
2827 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2828 "(IRQ0) through the 8259A ...\n");
2829 apic_printk(APIC_QUIET, KERN_INFO
2830 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2832 * legacy devices should be connected to IO APIC #0
2834 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2835 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2836 legacy_pic->unmask(0);
2837 if (timer_irq_works()) {
2838 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2839 timer_through_8259 = 1;
2843 * Cleanup, just in case ...
2845 local_irq_disable();
2846 legacy_pic->mask(0);
2847 clear_IO_APIC_pin(apic2, pin2);
2848 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2851 apic_printk(APIC_QUIET, KERN_INFO
2852 "...trying to set up timer as Virtual Wire IRQ...\n");
2854 lapic_register_intr(0);
2855 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2856 legacy_pic->unmask(0);
2858 if (timer_irq_works()) {
2859 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2862 local_irq_disable();
2863 legacy_pic->mask(0);
2864 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2865 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2867 apic_printk(APIC_QUIET, KERN_INFO
2868 "...trying to set up timer as ExtINT IRQ...\n");
2870 legacy_pic->init(0);
2871 legacy_pic->make_irq(0);
2872 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2874 unlock_ExtINT_logic();
2876 if (timer_irq_works()) {
2877 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2880 local_irq_disable();
2881 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2882 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2883 "report. Then try booting with the 'noapic' option.\n");
2885 local_irq_restore(flags);
2889 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2890 * to devices. However there may be an I/O APIC pin available for
2891 * this interrupt regardless. The pin may be left unconnected, but
2892 * typically it will be reused as an ExtINT cascade interrupt for
2893 * the master 8259A. In the MPS case such a pin will normally be
2894 * reported as an ExtINT interrupt in the MP table. With ACPI
2895 * there is no provision for ExtINT interrupts, and in the absence
2896 * of an override it would be treated as an ordinary ISA I/O APIC
2897 * interrupt, that is edge-triggered and unmasked by default. We
2898 * used to do this, but it caused problems on some systems because
2899 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2900 * the same ExtINT cascade interrupt to drive the local APIC of the
2901 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2902 * the I/O APIC in all cases now. No actual device should request
2903 * it anyway. --macro
2905 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2907 void __init setup_IO_APIC(void)
2911 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2913 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2915 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2917 * Set up IO-APIC IRQ routing.
2919 x86_init.mpparse.setup_ioapic_ids();
2922 setup_IO_APIC_irqs();
2923 init_IO_APIC_traps();
2924 if (legacy_pic->nr_legacy_irqs)
2929 * Called after all the initialization is done. If we didnt find any
2930 * APIC bugs then we can allow the modify fast path
2933 static int __init io_apic_bug_finalize(void)
2935 if (sis_apic_bug == -1)
2940 late_initcall(io_apic_bug_finalize);
2942 struct sysfs_ioapic_data {
2943 struct sys_device dev;
2944 struct IO_APIC_route_entry entry[0];
2946 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2948 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2950 struct IO_APIC_route_entry *entry;
2951 struct sysfs_ioapic_data *data;
2954 data = container_of(dev, struct sysfs_ioapic_data, dev);
2955 entry = data->entry;
2956 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2957 *entry = ioapic_read_entry(dev->id, i);
2962 static int ioapic_resume(struct sys_device *dev)
2964 struct IO_APIC_route_entry *entry;
2965 struct sysfs_ioapic_data *data;
2966 unsigned long flags;
2967 union IO_APIC_reg_00 reg_00;
2970 data = container_of(dev, struct sysfs_ioapic_data, dev);
2971 entry = data->entry;
2973 raw_spin_lock_irqsave(&ioapic_lock, flags);
2974 reg_00.raw = io_apic_read(dev->id, 0);
2975 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
2976 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
2977 io_apic_write(dev->id, 0, reg_00.raw);
2979 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2980 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2981 ioapic_write_entry(dev->id, i, entry[i]);
2986 static struct sysdev_class ioapic_sysdev_class = {
2988 .suspend = ioapic_suspend,
2989 .resume = ioapic_resume,
2992 static int __init ioapic_init_sysfs(void)
2994 struct sys_device * dev;
2997 error = sysdev_class_register(&ioapic_sysdev_class);
3001 for (i = 0; i < nr_ioapics; i++ ) {
3002 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3003 * sizeof(struct IO_APIC_route_entry);
3004 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3005 if (!mp_ioapic_data[i]) {
3006 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3009 dev = &mp_ioapic_data[i]->dev;
3011 dev->cls = &ioapic_sysdev_class;
3012 error = sysdev_register(dev);
3014 kfree(mp_ioapic_data[i]);
3015 mp_ioapic_data[i] = NULL;
3016 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3024 device_initcall(ioapic_init_sysfs);
3027 * Dynamic irq allocate and deallocation
3029 unsigned int create_irq_nr(unsigned int from, int node)
3031 struct irq_cfg *cfg;
3032 unsigned long flags;
3033 unsigned int ret = 0;
3036 if (from < nr_irqs_gsi)
3039 irq = alloc_irq_from(from, node);
3042 cfg = alloc_irq_cfg(irq, node);
3044 free_irq_at(irq, NULL);
3048 raw_spin_lock_irqsave(&vector_lock, flags);
3049 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3051 raw_spin_unlock_irqrestore(&vector_lock, flags);
3054 set_irq_chip_data(irq, cfg);
3055 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3057 free_irq_at(irq, cfg);
3062 int create_irq(void)
3064 int node = cpu_to_node(0);
3065 unsigned int irq_want;
3068 irq_want = nr_irqs_gsi;
3069 irq = create_irq_nr(irq_want, node);
3077 void destroy_irq(unsigned int irq)
3079 struct irq_cfg *cfg = get_irq_chip_data(irq);
3080 unsigned long flags;
3082 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3084 if (irq_remapped(cfg))
3086 raw_spin_lock_irqsave(&vector_lock, flags);
3087 __clear_irq_vector(irq, cfg);
3088 raw_spin_unlock_irqrestore(&vector_lock, flags);
3089 free_irq_at(irq, cfg);
3093 * MSI message composition
3095 #ifdef CONFIG_PCI_MSI
3096 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3097 struct msi_msg *msg, u8 hpet_id)
3099 struct irq_cfg *cfg;
3107 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3111 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3113 if (irq_remapped(get_irq_chip_data(irq))) {
3118 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3119 BUG_ON(ir_index == -1);
3121 prepare_irte(&irte, cfg->vector, dest);
3123 /* Set source-id of interrupt request */
3125 set_msi_sid(&irte, pdev);
3127 set_hpet_sid(&irte, hpet_id);
3129 modify_irte(irq, &irte);
3131 msg->address_hi = MSI_ADDR_BASE_HI;
3132 msg->data = sub_handle;
3133 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3135 MSI_ADDR_IR_INDEX1(ir_index) |
3136 MSI_ADDR_IR_INDEX2(ir_index);
3138 if (x2apic_enabled())
3139 msg->address_hi = MSI_ADDR_BASE_HI |
3140 MSI_ADDR_EXT_DEST_ID(dest);
3142 msg->address_hi = MSI_ADDR_BASE_HI;
3146 ((apic->irq_dest_mode == 0) ?
3147 MSI_ADDR_DEST_MODE_PHYSICAL:
3148 MSI_ADDR_DEST_MODE_LOGICAL) |
3149 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3150 MSI_ADDR_REDIRECTION_CPU:
3151 MSI_ADDR_REDIRECTION_LOWPRI) |
3152 MSI_ADDR_DEST_ID(dest);
3155 MSI_DATA_TRIGGER_EDGE |
3156 MSI_DATA_LEVEL_ASSERT |
3157 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3158 MSI_DATA_DELIVERY_FIXED:
3159 MSI_DATA_DELIVERY_LOWPRI) |
3160 MSI_DATA_VECTOR(cfg->vector);
3167 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3169 struct irq_cfg *cfg = data->chip_data;
3173 if (__ioapic_set_affinity(data, mask, &dest))
3176 __get_cached_msi_msg(data->msi_desc, &msg);
3178 msg.data &= ~MSI_DATA_VECTOR_MASK;
3179 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3180 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3181 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3183 __write_msi_msg(data->msi_desc, &msg);
3187 #ifdef CONFIG_INTR_REMAP
3189 * Migrate the MSI irq to another cpumask. This migration is
3190 * done in the process context using interrupt-remapping hardware.
3193 ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3196 struct irq_cfg *cfg = data->chip_data;
3197 unsigned int dest, irq = data->irq;
3200 if (get_irte(irq, &irte))
3203 if (__ioapic_set_affinity(data, mask, &dest))
3206 irte.vector = cfg->vector;
3207 irte.dest_id = IRTE_DEST(dest);
3210 * atomically update the IRTE with the new destination and vector.
3212 modify_irte(irq, &irte);
3215 * After this point, all the interrupts will start arriving
3216 * at the new destination. So, time to cleanup the previous
3217 * vector allocation.
3219 if (cfg->move_in_progress)
3220 send_cleanup_vector(cfg);
3226 #endif /* CONFIG_SMP */
3229 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3230 * which implement the MSI or MSI-X Capability Structure.
3232 static struct irq_chip msi_chip = {
3234 .irq_unmask = unmask_msi_irq,
3235 .irq_mask = mask_msi_irq,
3236 .irq_ack = ack_apic_edge,
3238 .irq_set_affinity = msi_set_affinity,
3240 .irq_retrigger = ioapic_retrigger_irq,
3243 static struct irq_chip msi_ir_chip = {
3244 .name = "IR-PCI-MSI",
3245 .irq_unmask = unmask_msi_irq,
3246 .irq_mask = mask_msi_irq,
3247 #ifdef CONFIG_INTR_REMAP
3248 .irq_ack = ir_ack_apic_edge,
3250 .irq_set_affinity = ir_msi_set_affinity,
3253 .irq_retrigger = ioapic_retrigger_irq,
3257 * Map the PCI dev to the corresponding remapping hardware unit
3258 * and allocate 'nvec' consecutive interrupt-remapping table entries
3261 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3263 struct intel_iommu *iommu;
3266 iommu = map_dev_to_ir(dev);
3269 "Unable to map PCI %s to iommu\n", pci_name(dev));
3273 index = alloc_irte(iommu, irq, nvec);
3276 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3283 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3288 ret = msi_compose_msg(dev, irq, &msg, -1);
3292 set_irq_msi(irq, msidesc);
3293 write_msi_msg(irq, &msg);
3295 if (irq_remapped(get_irq_chip_data(irq))) {
3296 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3297 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3299 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3301 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3306 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3308 int node, ret, sub_handle, index = 0;
3309 unsigned int irq, irq_want;
3310 struct msi_desc *msidesc;
3311 struct intel_iommu *iommu = NULL;
3313 /* x86 doesn't support multiple MSI yet */
3314 if (type == PCI_CAP_ID_MSI && nvec > 1)
3317 node = dev_to_node(&dev->dev);
3318 irq_want = nr_irqs_gsi;
3320 list_for_each_entry(msidesc, &dev->msi_list, list) {
3321 irq = create_irq_nr(irq_want, node);
3325 if (!intr_remapping_enabled)
3330 * allocate the consecutive block of IRTE's
3333 index = msi_alloc_irte(dev, irq, nvec);
3339 iommu = map_dev_to_ir(dev);
3345 * setup the mapping between the irq and the IRTE
3346 * base index, the sub_handle pointing to the
3347 * appropriate interrupt remap table entry.
3349 set_irte_irq(irq, iommu, index, sub_handle);
3352 ret = setup_msi_irq(dev, msidesc, irq);
3364 void native_teardown_msi_irq(unsigned int irq)
3369 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3372 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3375 struct irq_cfg *cfg = data->chip_data;
3376 unsigned int dest, irq = data->irq;
3379 if (__ioapic_set_affinity(data, mask, &dest))
3382 dmar_msi_read(irq, &msg);
3384 msg.data &= ~MSI_DATA_VECTOR_MASK;
3385 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3386 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3387 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3388 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3390 dmar_msi_write(irq, &msg);
3395 #endif /* CONFIG_SMP */
3397 static struct irq_chip dmar_msi_type = {
3399 .irq_unmask = dmar_msi_unmask,
3400 .irq_mask = dmar_msi_mask,
3401 .irq_ack = ack_apic_edge,
3403 .irq_set_affinity = dmar_msi_set_affinity,
3405 .irq_retrigger = ioapic_retrigger_irq,
3408 int arch_setup_dmar_msi(unsigned int irq)
3413 ret = msi_compose_msg(NULL, irq, &msg, -1);
3416 dmar_msi_write(irq, &msg);
3417 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3423 #ifdef CONFIG_HPET_TIMER
3426 static int hpet_msi_set_affinity(struct irq_data *data,
3427 const struct cpumask *mask, bool force)
3429 struct irq_cfg *cfg = data->chip_data;
3433 if (__ioapic_set_affinity(data, mask, &dest))
3436 hpet_msi_read(data->handler_data, &msg);
3438 msg.data &= ~MSI_DATA_VECTOR_MASK;
3439 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3440 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3441 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3443 hpet_msi_write(data->handler_data, &msg);
3448 #endif /* CONFIG_SMP */
3450 static struct irq_chip ir_hpet_msi_type = {
3451 .name = "IR-HPET_MSI",
3452 .irq_unmask = hpet_msi_unmask,
3453 .irq_mask = hpet_msi_mask,
3454 #ifdef CONFIG_INTR_REMAP
3455 .irq_ack = ir_ack_apic_edge,
3457 .irq_set_affinity = ir_msi_set_affinity,
3460 .irq_retrigger = ioapic_retrigger_irq,
3463 static struct irq_chip hpet_msi_type = {
3465 .irq_unmask = hpet_msi_unmask,
3466 .irq_mask = hpet_msi_mask,
3467 .irq_ack = ack_apic_edge,
3469 .irq_set_affinity = hpet_msi_set_affinity,
3471 .irq_retrigger = ioapic_retrigger_irq,
3474 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3479 if (intr_remapping_enabled) {
3480 struct intel_iommu *iommu = map_hpet_to_ir(id);
3486 index = alloc_irte(iommu, irq, 1);
3491 ret = msi_compose_msg(NULL, irq, &msg, id);
3495 hpet_msi_write(get_irq_data(irq), &msg);
3496 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3497 if (irq_remapped(get_irq_chip_data(irq)))
3498 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3499 handle_edge_irq, "edge");
3501 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3502 handle_edge_irq, "edge");
3508 #endif /* CONFIG_PCI_MSI */
3510 * Hypertransport interrupt support
3512 #ifdef CONFIG_HT_IRQ
3516 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3518 struct ht_irq_msg msg;
3519 fetch_ht_irq_msg(irq, &msg);
3521 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3522 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3524 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3525 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3527 write_ht_irq_msg(irq, &msg);
3531 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3533 struct irq_cfg *cfg = data->chip_data;
3536 if (__ioapic_set_affinity(data, mask, &dest))
3539 target_ht_irq(data->irq, dest, cfg->vector);
3545 static struct irq_chip ht_irq_chip = {
3547 .irq_mask = mask_ht_irq,
3548 .irq_unmask = unmask_ht_irq,
3549 .irq_ack = ack_apic_edge,
3551 .irq_set_affinity = ht_set_affinity,
3553 .irq_retrigger = ioapic_retrigger_irq,
3556 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3558 struct irq_cfg *cfg;
3565 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3567 struct ht_irq_msg msg;
3570 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3571 apic->target_cpus());
3573 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3577 HT_IRQ_LOW_DEST_ID(dest) |
3578 HT_IRQ_LOW_VECTOR(cfg->vector) |
3579 ((apic->irq_dest_mode == 0) ?
3580 HT_IRQ_LOW_DM_PHYSICAL :
3581 HT_IRQ_LOW_DM_LOGICAL) |
3582 HT_IRQ_LOW_RQEOI_EDGE |
3583 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3584 HT_IRQ_LOW_MT_FIXED :
3585 HT_IRQ_LOW_MT_ARBITRATED) |
3586 HT_IRQ_LOW_IRQ_MASKED;
3588 write_ht_irq_msg(irq, &msg);
3590 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3591 handle_edge_irq, "edge");
3593 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3597 #endif /* CONFIG_HT_IRQ */
3600 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3602 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3607 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3609 setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg,
3610 attr->trigger, attr->polarity);
3614 static int __init io_apic_get_redir_entries(int ioapic)
3616 union IO_APIC_reg_01 reg_01;
3617 unsigned long flags;
3619 raw_spin_lock_irqsave(&ioapic_lock, flags);
3620 reg_01.raw = io_apic_read(ioapic, 1);
3621 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3623 /* The register returns the maximum index redir index
3624 * supported, which is one less than the total number of redir
3627 return reg_01.bits.entries + 1;
3630 static void __init probe_nr_irqs_gsi(void)
3634 nr = gsi_top + NR_IRQS_LEGACY;
3635 if (nr > nr_irqs_gsi)
3638 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3641 int get_nr_irqs_gsi(void)
3646 #ifdef CONFIG_SPARSE_IRQ
3647 int __init arch_probe_nr_irqs(void)
3651 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3652 nr_irqs = NR_VECTORS * nr_cpu_ids;
3654 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3655 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3657 * for MSI and HT dyn irq
3659 nr += nr_irqs_gsi * 16;
3664 return NR_IRQS_LEGACY;
3668 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3669 struct io_apic_irq_attr *irq_attr)
3673 if (!IO_APIC_IRQ(irq)) {
3674 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3679 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3681 return io_apic_setup_irq_pin(irq, node, irq_attr);
3684 int io_apic_set_pci_routing(struct device *dev, int irq,
3685 struct io_apic_irq_attr *irq_attr)
3689 * Avoid pin reprogramming. PRTs typically include entries
3690 * with redundant pin->gsi mappings (but unique PCI devices);
3691 * we only program the IOAPIC on the first.
3693 ioapic = irq_attr->ioapic;
3694 pin = irq_attr->ioapic_pin;
3695 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3696 pr_debug("Pin %d-%d already programmed\n",
3697 mp_ioapics[ioapic].apicid, pin);
3700 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3702 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3705 #ifdef CONFIG_X86_32
3706 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3708 union IO_APIC_reg_00 reg_00;
3709 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3711 unsigned long flags;
3715 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3716 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3717 * supports up to 16 on one shared APIC bus.
3719 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3720 * advantage of new APIC bus architecture.
3723 if (physids_empty(apic_id_map))
3724 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3726 raw_spin_lock_irqsave(&ioapic_lock, flags);
3727 reg_00.raw = io_apic_read(ioapic, 0);
3728 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3730 if (apic_id >= get_physical_broadcast()) {
3731 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3732 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3733 apic_id = reg_00.bits.ID;
3737 * Every APIC in a system must have a unique ID or we get lots of nice
3738 * 'stuck on smp_invalidate_needed IPI wait' messages.
3740 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3742 for (i = 0; i < get_physical_broadcast(); i++) {
3743 if (!apic->check_apicid_used(&apic_id_map, i))
3747 if (i == get_physical_broadcast())
3748 panic("Max apic_id exceeded!\n");
3750 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3751 "trying %d\n", ioapic, apic_id, i);
3756 apic->apicid_to_cpu_present(apic_id, &tmp);
3757 physids_or(apic_id_map, apic_id_map, tmp);
3759 if (reg_00.bits.ID != apic_id) {
3760 reg_00.bits.ID = apic_id;
3762 raw_spin_lock_irqsave(&ioapic_lock, flags);
3763 io_apic_write(ioapic, 0, reg_00.raw);
3764 reg_00.raw = io_apic_read(ioapic, 0);
3765 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3768 if (reg_00.bits.ID != apic_id) {
3769 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3774 apic_printk(APIC_VERBOSE, KERN_INFO
3775 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3780 static u8 __init io_apic_unique_id(u8 id)
3782 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3783 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3784 return io_apic_get_unique_id(nr_ioapics, id);
3789 static u8 __init io_apic_unique_id(u8 id)
3792 DECLARE_BITMAP(used, 256);
3794 bitmap_zero(used, 256);
3795 for (i = 0; i < nr_ioapics; i++) {
3796 struct mpc_ioapic *ia = &mp_ioapics[i];
3797 __set_bit(ia->apicid, used);
3799 if (!test_bit(id, used))
3801 return find_first_zero_bit(used, 256);
3805 static int __init io_apic_get_version(int ioapic)
3807 union IO_APIC_reg_01 reg_01;
3808 unsigned long flags;
3810 raw_spin_lock_irqsave(&ioapic_lock, flags);
3811 reg_01.raw = io_apic_read(ioapic, 1);
3812 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3814 return reg_01.bits.version;
3817 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3819 int ioapic, pin, idx;
3821 if (skip_ioapic_setup)
3824 ioapic = mp_find_ioapic(gsi);
3828 pin = mp_find_ioapic_pin(ioapic, gsi);
3832 idx = find_irq_entry(ioapic, pin, mp_INT);
3836 *trigger = irq_trigger(idx);
3837 *polarity = irq_polarity(idx);
3842 * This function currently is only a helper for the i386 smp boot process where
3843 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3844 * so mask in all cases should simply be apic->target_cpus()
3847 void __init setup_ioapic_dest(void)
3849 int pin, ioapic, irq, irq_entry;
3850 struct irq_desc *desc;
3851 const struct cpumask *mask;
3853 if (skip_ioapic_setup == 1)
3856 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3857 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3858 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3859 if (irq_entry == -1)
3861 irq = pin_2_irq(irq_entry, ioapic, pin);
3863 if ((ioapic > 0) && (irq > 16))
3866 desc = irq_to_desc(irq);
3869 * Honour affinities which have been set in early boot
3872 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
3873 mask = desc->irq_data.affinity;
3875 mask = apic->target_cpus();
3877 if (intr_remapping_enabled)
3878 ir_ioapic_set_affinity(&desc->irq_data, mask, false);
3880 ioapic_set_affinity(&desc->irq_data, mask, false);
3886 #define IOAPIC_RESOURCE_NAME_SIZE 11
3888 static struct resource *ioapic_resources;
3890 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3893 struct resource *res;
3897 if (nr_ioapics <= 0)
3900 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3903 mem = alloc_bootmem(n);
3906 mem += sizeof(struct resource) * nr_ioapics;
3908 for (i = 0; i < nr_ioapics; i++) {
3910 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3911 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3912 mem += IOAPIC_RESOURCE_NAME_SIZE;
3915 ioapic_resources = res;
3920 void __init ioapic_and_gsi_init(void)
3922 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3923 struct resource *ioapic_res;
3926 ioapic_res = ioapic_setup_resources(nr_ioapics);
3927 for (i = 0; i < nr_ioapics; i++) {
3928 if (smp_found_config) {
3929 ioapic_phys = mp_ioapics[i].apicaddr;
3930 #ifdef CONFIG_X86_32
3933 "WARNING: bogus zero IO-APIC "
3934 "address found in MPTABLE, "
3935 "disabling IO/APIC support!\n");
3936 smp_found_config = 0;
3937 skip_ioapic_setup = 1;
3938 goto fake_ioapic_page;
3942 #ifdef CONFIG_X86_32
3945 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3946 ioapic_phys = __pa(ioapic_phys);
3948 set_fixmap_nocache(idx, ioapic_phys);
3949 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3950 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3954 ioapic_res->start = ioapic_phys;
3955 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3959 probe_nr_irqs_gsi();
3962 void __init ioapic_insert_resources(void)
3965 struct resource *r = ioapic_resources;
3970 "IO APIC resources couldn't be allocated.\n");
3974 for (i = 0; i < nr_ioapics; i++) {
3975 insert_resource(&iomem_resource, r);
3980 int mp_find_ioapic(u32 gsi)
3984 if (nr_ioapics == 0)
3987 /* Find the IOAPIC that manages this GSI. */
3988 for (i = 0; i < nr_ioapics; i++) {
3989 if ((gsi >= mp_gsi_routing[i].gsi_base)
3990 && (gsi <= mp_gsi_routing[i].gsi_end))
3994 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3998 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4000 if (WARN_ON(ioapic == -1))
4002 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4005 return gsi - mp_gsi_routing[ioapic].gsi_base;
4008 static __init int bad_ioapic(unsigned long address)
4010 if (nr_ioapics >= MAX_IO_APICS) {
4011 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4012 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4016 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4017 " found in table, skipping!\n");
4023 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4028 if (bad_ioapic(address))
4033 mp_ioapics[idx].type = MP_IOAPIC;
4034 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4035 mp_ioapics[idx].apicaddr = address;
4037 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4038 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4039 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4042 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4043 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4045 entries = io_apic_get_redir_entries(idx);
4046 mp_gsi_routing[idx].gsi_base = gsi_base;
4047 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
4050 * The number of IO-APIC IRQ registers (== #pins):
4052 nr_ioapic_registers[idx] = entries;
4054 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
4055 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
4057 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4058 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4059 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4060 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4065 /* Enable IOAPIC early just for system timer */
4066 void __init pre_init_apic_IRQ0(void)
4068 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4070 printk(KERN_INFO "Early APIC setup for system timer0\n");
4072 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4073 &phys_cpu_present_map);
4077 io_apic_setup_irq_pin(0, 0, &attr);
4078 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");