2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* The one past the highest gsi number used */
94 /* MP IRQ source entries */
95 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
97 /* # of MP IRQ source entries */
101 static int nr_irqs_gsi = NR_IRQS_LEGACY;
104 * Saved I/O APIC state during suspend/resume.
106 static struct IO_APIC_route_entry *ioapic_saved_data[MAX_IO_APICS];
108 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
109 int mp_bus_id_to_type[MAX_MP_BUSSES];
112 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
114 int skip_ioapic_setup;
117 * disable_ioapic_support() - disables ioapic support at runtime
119 void disable_ioapic_support(void)
123 noioapicreroute = -1;
125 skip_ioapic_setup = 1;
128 static int __init parse_noapic(char *str)
130 /* disable IO-APIC */
131 disable_ioapic_support();
134 early_param("noapic", parse_noapic);
136 static int io_apic_setup_irq_pin(unsigned int irq, int node,
137 struct io_apic_irq_attr *attr);
139 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
140 void mp_save_irq(struct mpc_intsrc *m)
144 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
145 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
146 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
147 m->srcbusirq, m->dstapic, m->dstirq);
149 for (i = 0; i < mp_irq_entries; i++) {
150 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
154 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
155 if (++mp_irq_entries == MAX_IRQ_SOURCES)
156 panic("Max # of irq sources exceeded!!\n");
159 struct irq_pin_list {
161 struct irq_pin_list *next;
164 static struct irq_pin_list *alloc_irq_pin_list(int node)
166 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
170 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
171 #ifdef CONFIG_SPARSE_IRQ
172 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
174 static struct irq_cfg irq_cfgx[NR_IRQS];
177 int __init arch_early_irq_init(void)
182 if (!legacy_pic->nr_legacy_irqs) {
187 for (i = 0; i < nr_ioapics; i++) {
188 ioapic_saved_data[i] =
189 kzalloc(sizeof(struct IO_APIC_route_entry) *
190 nr_ioapic_registers[i], GFP_KERNEL);
191 if (!ioapic_saved_data[i])
192 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
196 count = ARRAY_SIZE(irq_cfgx);
197 node = cpu_to_node(0);
199 /* Make sure the legacy interrupts are marked in the bitmap */
200 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
202 for (i = 0; i < count; i++) {
203 irq_set_chip_data(i, &cfg[i]);
204 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
205 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
207 * For legacy IRQ's, start with assigning irq0 to irq15 to
208 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
210 if (i < legacy_pic->nr_legacy_irqs) {
211 cfg[i].vector = IRQ0_VECTOR + i;
212 cpumask_set_cpu(0, cfg[i].domain);
219 #ifdef CONFIG_SPARSE_IRQ
220 static struct irq_cfg *irq_cfg(unsigned int irq)
222 return irq_get_chip_data(irq);
225 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
229 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
232 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
234 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
238 free_cpumask_var(cfg->domain);
244 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
248 irq_set_chip_data(at, NULL);
249 free_cpumask_var(cfg->domain);
250 free_cpumask_var(cfg->old_domain);
256 struct irq_cfg *irq_cfg(unsigned int irq)
258 return irq < nr_irqs ? irq_cfgx + irq : NULL;
261 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
263 return irq_cfgx + irq;
266 static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { }
270 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
272 int res = irq_alloc_desc_at(at, node);
278 cfg = irq_get_chip_data(at);
283 cfg = alloc_irq_cfg(at, node);
285 irq_set_chip_data(at, cfg);
291 static int alloc_irq_from(unsigned int from, int node)
293 return irq_alloc_desc_from(from, node);
296 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
298 free_irq_cfg(at, cfg);
304 unsigned int unused[3];
306 unsigned int unused2[11];
310 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
312 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
313 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
316 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
318 struct io_apic __iomem *io_apic = io_apic_base(apic);
319 writel(vector, &io_apic->eoi);
322 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
324 struct io_apic __iomem *io_apic = io_apic_base(apic);
325 writel(reg, &io_apic->index);
326 return readl(&io_apic->data);
329 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
331 struct io_apic __iomem *io_apic = io_apic_base(apic);
332 writel(reg, &io_apic->index);
333 writel(value, &io_apic->data);
337 * Re-write a value: to be used for read-modify-write
338 * cycles where the read already set up the index register.
340 * Older SiS APIC requires we rewrite the index register
342 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
344 struct io_apic __iomem *io_apic = io_apic_base(apic);
347 writel(reg, &io_apic->index);
348 writel(value, &io_apic->data);
351 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
353 struct irq_pin_list *entry;
356 raw_spin_lock_irqsave(&ioapic_lock, flags);
357 for_each_irq_pin(entry, cfg->irq_2_pin) {
362 reg = io_apic_read(entry->apic, 0x10 + pin*2);
363 /* Is the remote IRR bit set? */
364 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
365 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
369 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
375 struct { u32 w1, w2; };
376 struct IO_APIC_route_entry entry;
379 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
381 union entry_union eu;
383 raw_spin_lock_irqsave(&ioapic_lock, flags);
384 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
385 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
386 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
391 * When we write a new IO APIC routing entry, we need to write the high
392 * word first! If the mask bit in the low word is clear, we will enable
393 * the interrupt, and we need to make sure the entry is fully populated
394 * before that happens.
397 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
399 union entry_union eu = {{0, 0}};
402 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
403 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
406 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
409 raw_spin_lock_irqsave(&ioapic_lock, flags);
410 __ioapic_write_entry(apic, pin, e);
411 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
415 * When we mask an IO APIC routing entry, we need to write the low
416 * word first, in order to set the mask bit before we change the
419 static void ioapic_mask_entry(int apic, int pin)
422 union entry_union eu = { .entry.mask = 1 };
424 raw_spin_lock_irqsave(&ioapic_lock, flags);
425 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
426 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
427 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
431 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
432 * shared ISA-space IRQs, so we have to support them. We are super
433 * fast in the common case, and fast for shared ISA-space IRQs.
436 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
438 struct irq_pin_list **last, *entry;
440 /* don't allow duplicates */
441 last = &cfg->irq_2_pin;
442 for_each_irq_pin(entry, cfg->irq_2_pin) {
443 if (entry->apic == apic && entry->pin == pin)
448 entry = alloc_irq_pin_list(node);
450 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
461 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
463 if (__add_pin_to_irq_node(cfg, node, apic, pin))
464 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
468 * Reroute an IRQ to a different pin.
470 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
471 int oldapic, int oldpin,
472 int newapic, int newpin)
474 struct irq_pin_list *entry;
476 for_each_irq_pin(entry, cfg->irq_2_pin) {
477 if (entry->apic == oldapic && entry->pin == oldpin) {
478 entry->apic = newapic;
480 /* every one is different, right? */
485 /* old apic/pin didn't exist, so just add new ones */
486 add_pin_to_irq_node(cfg, node, newapic, newpin);
489 static void __io_apic_modify_irq(struct irq_pin_list *entry,
490 int mask_and, int mask_or,
491 void (*final)(struct irq_pin_list *entry))
493 unsigned int reg, pin;
496 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
499 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
504 static void io_apic_modify_irq(struct irq_cfg *cfg,
505 int mask_and, int mask_or,
506 void (*final)(struct irq_pin_list *entry))
508 struct irq_pin_list *entry;
510 for_each_irq_pin(entry, cfg->irq_2_pin)
511 __io_apic_modify_irq(entry, mask_and, mask_or, final);
514 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
516 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
517 IO_APIC_REDIR_MASKED, NULL);
520 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
522 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
523 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
526 static void io_apic_sync(struct irq_pin_list *entry)
529 * Synchronize the IO-APIC and the CPU by doing
530 * a dummy read from the IO-APIC
532 struct io_apic __iomem *io_apic;
533 io_apic = io_apic_base(entry->apic);
534 readl(&io_apic->data);
537 static void mask_ioapic(struct irq_cfg *cfg)
541 raw_spin_lock_irqsave(&ioapic_lock, flags);
542 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
543 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
546 static void mask_ioapic_irq(struct irq_data *data)
548 mask_ioapic(data->chip_data);
551 static void __unmask_ioapic(struct irq_cfg *cfg)
553 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
556 static void unmask_ioapic(struct irq_cfg *cfg)
560 raw_spin_lock_irqsave(&ioapic_lock, flags);
561 __unmask_ioapic(cfg);
562 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
565 static void unmask_ioapic_irq(struct irq_data *data)
567 unmask_ioapic(data->chip_data);
570 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
572 struct IO_APIC_route_entry entry;
574 /* Check delivery_mode to be sure we're not clearing an SMI pin */
575 entry = ioapic_read_entry(apic, pin);
576 if (entry.delivery_mode == dest_SMI)
579 * Disable it in the IO-APIC irq-routing table:
581 ioapic_mask_entry(apic, pin);
584 static void clear_IO_APIC (void)
588 for (apic = 0; apic < nr_ioapics; apic++)
589 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
590 clear_IO_APIC_pin(apic, pin);
595 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
596 * specific CPU-side IRQs.
600 static int pirq_entries[MAX_PIRQS] = {
601 [0 ... MAX_PIRQS - 1] = -1
604 static int __init ioapic_pirq_setup(char *str)
607 int ints[MAX_PIRQS+1];
609 get_options(str, ARRAY_SIZE(ints), ints);
611 apic_printk(APIC_VERBOSE, KERN_INFO
612 "PIRQ redirection, working around broken MP-BIOS.\n");
614 if (ints[0] < MAX_PIRQS)
617 for (i = 0; i < max; i++) {
618 apic_printk(APIC_VERBOSE, KERN_DEBUG
619 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
621 * PIRQs are mapped upside down, usually.
623 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
628 __setup("pirq=", ioapic_pirq_setup);
629 #endif /* CONFIG_X86_32 */
631 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
634 struct IO_APIC_route_entry **ioapic_entries;
636 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
641 for (apic = 0; apic < nr_ioapics; apic++) {
642 ioapic_entries[apic] =
643 kzalloc(sizeof(struct IO_APIC_route_entry) *
644 nr_ioapic_registers[apic], GFP_ATOMIC);
645 if (!ioapic_entries[apic])
649 return ioapic_entries;
653 kfree(ioapic_entries[apic]);
654 kfree(ioapic_entries);
660 * Saves all the IO-APIC RTE's
662 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
669 for (apic = 0; apic < nr_ioapics; apic++) {
670 if (!ioapic_entries[apic])
673 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
674 ioapic_entries[apic][pin] =
675 ioapic_read_entry(apic, pin);
682 * Mask all IO APIC entries.
684 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
691 for (apic = 0; apic < nr_ioapics; apic++) {
692 if (!ioapic_entries[apic])
695 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
696 struct IO_APIC_route_entry entry;
698 entry = ioapic_entries[apic][pin];
701 ioapic_write_entry(apic, pin, entry);
708 * Restore IO APIC entries which was saved in ioapic_entries.
710 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
717 for (apic = 0; apic < nr_ioapics; apic++) {
718 if (!ioapic_entries[apic])
721 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
722 ioapic_write_entry(apic, pin,
723 ioapic_entries[apic][pin]);
728 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
732 for (apic = 0; apic < nr_ioapics; apic++)
733 kfree(ioapic_entries[apic]);
735 kfree(ioapic_entries);
739 * Find the IRQ entry number of a certain pin.
741 static int find_irq_entry(int apic, int pin, int type)
745 for (i = 0; i < mp_irq_entries; i++)
746 if (mp_irqs[i].irqtype == type &&
747 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
748 mp_irqs[i].dstapic == MP_APIC_ALL) &&
749 mp_irqs[i].dstirq == pin)
756 * Find the pin to which IRQ[irq] (ISA) is connected
758 static int __init find_isa_irq_pin(int irq, int type)
762 for (i = 0; i < mp_irq_entries; i++) {
763 int lbus = mp_irqs[i].srcbus;
765 if (test_bit(lbus, mp_bus_not_pci) &&
766 (mp_irqs[i].irqtype == type) &&
767 (mp_irqs[i].srcbusirq == irq))
769 return mp_irqs[i].dstirq;
774 static int __init find_isa_irq_apic(int irq, int type)
778 for (i = 0; i < mp_irq_entries; i++) {
779 int lbus = mp_irqs[i].srcbus;
781 if (test_bit(lbus, mp_bus_not_pci) &&
782 (mp_irqs[i].irqtype == type) &&
783 (mp_irqs[i].srcbusirq == irq))
786 if (i < mp_irq_entries) {
788 for(apic = 0; apic < nr_ioapics; apic++) {
789 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
797 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
799 * EISA Edge/Level control register, ELCR
801 static int EISA_ELCR(unsigned int irq)
803 if (irq < legacy_pic->nr_legacy_irqs) {
804 unsigned int port = 0x4d0 + (irq >> 3);
805 return (inb(port) >> (irq & 7)) & 1;
807 apic_printk(APIC_VERBOSE, KERN_INFO
808 "Broken MPtable reports ISA irq %d\n", irq);
814 /* ISA interrupts are always polarity zero edge triggered,
815 * when listed as conforming in the MP table. */
817 #define default_ISA_trigger(idx) (0)
818 #define default_ISA_polarity(idx) (0)
820 /* EISA interrupts are always polarity zero and can be edge or level
821 * trigger depending on the ELCR value. If an interrupt is listed as
822 * EISA conforming in the MP table, that means its trigger type must
823 * be read in from the ELCR */
825 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
826 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
828 /* PCI interrupts are always polarity one level triggered,
829 * when listed as conforming in the MP table. */
831 #define default_PCI_trigger(idx) (1)
832 #define default_PCI_polarity(idx) (1)
834 /* MCA interrupts are always polarity zero level triggered,
835 * when listed as conforming in the MP table. */
837 #define default_MCA_trigger(idx) (1)
838 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
840 static int irq_polarity(int idx)
842 int bus = mp_irqs[idx].srcbus;
846 * Determine IRQ line polarity (high active or low active):
848 switch (mp_irqs[idx].irqflag & 3)
850 case 0: /* conforms, ie. bus-type dependent polarity */
851 if (test_bit(bus, mp_bus_not_pci))
852 polarity = default_ISA_polarity(idx);
854 polarity = default_PCI_polarity(idx);
856 case 1: /* high active */
861 case 2: /* reserved */
863 printk(KERN_WARNING "broken BIOS!!\n");
867 case 3: /* low active */
872 default: /* invalid */
874 printk(KERN_WARNING "broken BIOS!!\n");
882 static int irq_trigger(int idx)
884 int bus = mp_irqs[idx].srcbus;
888 * Determine IRQ trigger mode (edge or level sensitive):
890 switch ((mp_irqs[idx].irqflag>>2) & 3)
892 case 0: /* conforms, ie. bus-type dependent */
893 if (test_bit(bus, mp_bus_not_pci))
894 trigger = default_ISA_trigger(idx);
896 trigger = default_PCI_trigger(idx);
897 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
898 switch (mp_bus_id_to_type[bus]) {
899 case MP_BUS_ISA: /* ISA pin */
901 /* set before the switch */
904 case MP_BUS_EISA: /* EISA pin */
906 trigger = default_EISA_trigger(idx);
909 case MP_BUS_PCI: /* PCI pin */
911 /* set before the switch */
914 case MP_BUS_MCA: /* MCA pin */
916 trigger = default_MCA_trigger(idx);
921 printk(KERN_WARNING "broken BIOS!!\n");
933 case 2: /* reserved */
935 printk(KERN_WARNING "broken BIOS!!\n");
944 default: /* invalid */
946 printk(KERN_WARNING "broken BIOS!!\n");
954 static int pin_2_irq(int idx, int apic, int pin)
957 int bus = mp_irqs[idx].srcbus;
960 * Debugging check, we are in big trouble if this message pops up!
962 if (mp_irqs[idx].dstirq != pin)
963 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
965 if (test_bit(bus, mp_bus_not_pci)) {
966 irq = mp_irqs[idx].srcbusirq;
968 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
970 if (gsi >= NR_IRQS_LEGACY)
978 * PCI IRQ command line redirection. Yes, limits are hardcoded.
980 if ((pin >= 16) && (pin <= 23)) {
981 if (pirq_entries[pin-16] != -1) {
982 if (!pirq_entries[pin-16]) {
983 apic_printk(APIC_VERBOSE, KERN_DEBUG
984 "disabling PIRQ%d\n", pin-16);
986 irq = pirq_entries[pin-16];
987 apic_printk(APIC_VERBOSE, KERN_DEBUG
988 "using PIRQ%d -> IRQ %d\n",
999 * Find a specific PCI IRQ entry.
1000 * Not an __init, possibly needed by modules
1002 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1003 struct io_apic_irq_attr *irq_attr)
1005 int apic, i, best_guess = -1;
1007 apic_printk(APIC_DEBUG,
1008 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1010 if (test_bit(bus, mp_bus_not_pci)) {
1011 apic_printk(APIC_VERBOSE,
1012 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1015 for (i = 0; i < mp_irq_entries; i++) {
1016 int lbus = mp_irqs[i].srcbus;
1018 for (apic = 0; apic < nr_ioapics; apic++)
1019 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1020 mp_irqs[i].dstapic == MP_APIC_ALL)
1023 if (!test_bit(lbus, mp_bus_not_pci) &&
1024 !mp_irqs[i].irqtype &&
1026 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1027 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1029 if (!(apic || IO_APIC_IRQ(irq)))
1032 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1033 set_io_apic_irq_attr(irq_attr, apic,
1040 * Use the first all-but-pin matching entry as a
1041 * best-guess fuzzy result for broken mptables.
1043 if (best_guess < 0) {
1044 set_io_apic_irq_attr(irq_attr, apic,
1054 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1056 void lock_vector_lock(void)
1058 /* Used to the online set of cpus does not change
1059 * during assign_irq_vector.
1061 raw_spin_lock(&vector_lock);
1064 void unlock_vector_lock(void)
1066 raw_spin_unlock(&vector_lock);
1070 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1073 * NOTE! The local APIC isn't very good at handling
1074 * multiple interrupts at the same interrupt level.
1075 * As the interrupt level is determined by taking the
1076 * vector number and shifting that right by 4, we
1077 * want to spread these out a bit so that they don't
1078 * all fall in the same interrupt level.
1080 * Also, we've got to be careful not to trash gate
1081 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1083 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1084 static int current_offset = VECTOR_OFFSET_START % 8;
1085 unsigned int old_vector;
1087 cpumask_var_t tmp_mask;
1089 if (cfg->move_in_progress)
1092 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1095 old_vector = cfg->vector;
1097 cpumask_and(tmp_mask, mask, cpu_online_mask);
1098 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1099 if (!cpumask_empty(tmp_mask)) {
1100 free_cpumask_var(tmp_mask);
1105 /* Only try and allocate irqs on cpus that are present */
1107 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1111 apic->vector_allocation_domain(cpu, tmp_mask);
1113 vector = current_vector;
1114 offset = current_offset;
1117 if (vector >= first_system_vector) {
1118 /* If out of vectors on large boxen, must share them. */
1119 offset = (offset + 1) % 8;
1120 vector = FIRST_EXTERNAL_VECTOR + offset;
1122 if (unlikely(current_vector == vector))
1125 if (test_bit(vector, used_vectors))
1128 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1129 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1132 current_vector = vector;
1133 current_offset = offset;
1135 cfg->move_in_progress = 1;
1136 cpumask_copy(cfg->old_domain, cfg->domain);
1138 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1139 per_cpu(vector_irq, new_cpu)[vector] = irq;
1140 cfg->vector = vector;
1141 cpumask_copy(cfg->domain, tmp_mask);
1145 free_cpumask_var(tmp_mask);
1149 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1152 unsigned long flags;
1154 raw_spin_lock_irqsave(&vector_lock, flags);
1155 err = __assign_irq_vector(irq, cfg, mask);
1156 raw_spin_unlock_irqrestore(&vector_lock, flags);
1160 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1164 BUG_ON(!cfg->vector);
1166 vector = cfg->vector;
1167 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1168 per_cpu(vector_irq, cpu)[vector] = -1;
1171 cpumask_clear(cfg->domain);
1173 if (likely(!cfg->move_in_progress))
1175 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1176 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1178 if (per_cpu(vector_irq, cpu)[vector] != irq)
1180 per_cpu(vector_irq, cpu)[vector] = -1;
1184 cfg->move_in_progress = 0;
1187 void __setup_vector_irq(int cpu)
1189 /* Initialize vector_irq on a new cpu */
1191 struct irq_cfg *cfg;
1194 * vector_lock will make sure that we don't run into irq vector
1195 * assignments that might be happening on another cpu in parallel,
1196 * while we setup our initial vector to irq mappings.
1198 raw_spin_lock(&vector_lock);
1199 /* Mark the inuse vectors */
1200 for_each_active_irq(irq) {
1201 cfg = irq_get_chip_data(irq);
1205 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1206 * will be part of the irq_cfg's domain.
1208 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1209 cpumask_set_cpu(cpu, cfg->domain);
1211 if (!cpumask_test_cpu(cpu, cfg->domain))
1213 vector = cfg->vector;
1214 per_cpu(vector_irq, cpu)[vector] = irq;
1216 /* Mark the free vectors */
1217 for (vector = 0; vector < NR_VECTORS; ++vector) {
1218 irq = per_cpu(vector_irq, cpu)[vector];
1223 if (!cpumask_test_cpu(cpu, cfg->domain))
1224 per_cpu(vector_irq, cpu)[vector] = -1;
1226 raw_spin_unlock(&vector_lock);
1229 static struct irq_chip ioapic_chip;
1230 static struct irq_chip ir_ioapic_chip;
1232 #ifdef CONFIG_X86_32
1233 static inline int IO_APIC_irq_trigger(int irq)
1237 for (apic = 0; apic < nr_ioapics; apic++) {
1238 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1239 idx = find_irq_entry(apic, pin, mp_INT);
1240 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1241 return irq_trigger(idx);
1245 * nonexistent IRQs are edge default
1250 static inline int IO_APIC_irq_trigger(int irq)
1256 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1257 unsigned long trigger)
1259 struct irq_chip *chip = &ioapic_chip;
1260 irq_flow_handler_t hdl;
1263 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1264 trigger == IOAPIC_LEVEL) {
1265 irq_set_status_flags(irq, IRQ_LEVEL);
1268 irq_clear_status_flags(irq, IRQ_LEVEL);
1272 if (irq_remapped(cfg)) {
1273 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1274 chip = &ir_ioapic_chip;
1275 fasteoi = trigger != 0;
1278 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1279 irq_set_chip_and_handler_name(irq, chip, hdl,
1280 fasteoi ? "fasteoi" : "edge");
1283 static int setup_ioapic_entry(int apic_id, int irq,
1284 struct IO_APIC_route_entry *entry,
1285 unsigned int destination, int trigger,
1286 int polarity, int vector, int pin)
1289 * add it to the IO-APIC irq-routing table:
1291 memset(entry,0,sizeof(*entry));
1293 if (intr_remapping_enabled) {
1294 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1296 struct IR_IO_APIC_route_entry *ir_entry =
1297 (struct IR_IO_APIC_route_entry *) entry;
1301 panic("No mapping iommu for ioapic %d\n", apic_id);
1303 index = alloc_irte(iommu, irq, 1);
1305 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1307 prepare_irte(&irte, vector, destination);
1309 /* Set source-id of interrupt request */
1310 set_ioapic_sid(&irte, apic_id);
1312 modify_irte(irq, &irte);
1314 ir_entry->index2 = (index >> 15) & 0x1;
1316 ir_entry->format = 1;
1317 ir_entry->index = (index & 0x7fff);
1319 * IO-APIC RTE will be configured with virtual vector.
1320 * irq handler will do the explicit EOI to the io-apic.
1322 ir_entry->vector = pin;
1324 entry->delivery_mode = apic->irq_delivery_mode;
1325 entry->dest_mode = apic->irq_dest_mode;
1326 entry->dest = destination;
1327 entry->vector = vector;
1330 entry->mask = 0; /* enable IRQ */
1331 entry->trigger = trigger;
1332 entry->polarity = polarity;
1334 /* Mask level triggered irqs.
1335 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1342 static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1343 struct irq_cfg *cfg, int trigger, int polarity)
1345 struct IO_APIC_route_entry entry;
1348 if (!IO_APIC_IRQ(irq))
1351 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1352 * controllers like 8259. Now that IO-APIC can handle this irq, update
1355 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1356 apic->vector_allocation_domain(0, cfg->domain);
1358 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1361 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1363 apic_printk(APIC_VERBOSE,KERN_DEBUG
1364 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1365 "IRQ %d Mode:%i Active:%i)\n",
1366 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1367 irq, trigger, polarity);
1370 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1371 dest, trigger, polarity, cfg->vector, pin)) {
1372 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1373 mp_ioapics[apic_id].apicid, pin);
1374 __clear_irq_vector(irq, cfg);
1378 ioapic_register_intr(irq, cfg, trigger);
1379 if (irq < legacy_pic->nr_legacy_irqs)
1380 legacy_pic->mask(irq);
1382 ioapic_write_entry(apic_id, pin, entry);
1386 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1387 } mp_ioapic_routing[MAX_IO_APICS];
1389 static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
1394 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1395 mp_ioapics[apic_id].apicid, pin);
1399 static void __init __io_apic_setup_irqs(unsigned int apic_id)
1401 int idx, node = cpu_to_node(0);
1402 struct io_apic_irq_attr attr;
1403 unsigned int pin, irq;
1405 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1406 idx = find_irq_entry(apic_id, pin, mp_INT);
1407 if (io_apic_pin_not_connected(idx, apic_id, pin))
1410 irq = pin_2_irq(idx, apic_id, pin);
1412 if ((apic_id > 0) && (irq > 16))
1416 * Skip the timer IRQ if there's a quirk handler
1417 * installed and if it returns 1:
1419 if (apic->multi_timer_check &&
1420 apic->multi_timer_check(apic_id, irq))
1423 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1426 io_apic_setup_irq_pin(irq, node, &attr);
1430 static void __init setup_IO_APIC_irqs(void)
1432 unsigned int apic_id;
1434 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1436 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1437 __io_apic_setup_irqs(apic_id);
1441 * for the gsit that is not in first ioapic
1442 * but could not use acpi_register_gsi()
1443 * like some special sci in IBM x3330
1445 void setup_IO_APIC_irq_extra(u32 gsi)
1447 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
1448 struct io_apic_irq_attr attr;
1451 * Convert 'gsi' to 'ioapic.pin'.
1453 apic_id = mp_find_ioapic(gsi);
1457 pin = mp_find_ioapic_pin(apic_id, gsi);
1458 idx = find_irq_entry(apic_id, pin, mp_INT);
1462 irq = pin_2_irq(idx, apic_id, pin);
1464 /* Only handle the non legacy irqs on secondary ioapics */
1465 if (apic_id == 0 || irq < NR_IRQS_LEGACY)
1468 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1471 io_apic_setup_irq_pin_once(irq, node, &attr);
1475 * Set up the timer pin, possibly with the 8259A-master behind.
1477 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1480 struct IO_APIC_route_entry entry;
1482 if (intr_remapping_enabled)
1485 memset(&entry, 0, sizeof(entry));
1488 * We use logical delivery to get the timer IRQ
1491 entry.dest_mode = apic->irq_dest_mode;
1492 entry.mask = 0; /* don't mask IRQ for edge */
1493 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1494 entry.delivery_mode = apic->irq_delivery_mode;
1497 entry.vector = vector;
1500 * The timer IRQ doesn't have to know that behind the
1501 * scene we may have a 8259A-master in AEOI mode ...
1503 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1507 * Add it to the IO-APIC irq-routing table:
1509 ioapic_write_entry(apic_id, pin, entry);
1513 __apicdebuginit(void) print_IO_APIC(void)
1516 union IO_APIC_reg_00 reg_00;
1517 union IO_APIC_reg_01 reg_01;
1518 union IO_APIC_reg_02 reg_02;
1519 union IO_APIC_reg_03 reg_03;
1520 unsigned long flags;
1521 struct irq_cfg *cfg;
1524 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1525 for (i = 0; i < nr_ioapics; i++)
1526 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1527 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1530 * We are a bit conservative about what we expect. We have to
1531 * know about every hardware change ASAP.
1533 printk(KERN_INFO "testing the IO APIC.......................\n");
1535 for (apic = 0; apic < nr_ioapics; apic++) {
1537 raw_spin_lock_irqsave(&ioapic_lock, flags);
1538 reg_00.raw = io_apic_read(apic, 0);
1539 reg_01.raw = io_apic_read(apic, 1);
1540 if (reg_01.bits.version >= 0x10)
1541 reg_02.raw = io_apic_read(apic, 2);
1542 if (reg_01.bits.version >= 0x20)
1543 reg_03.raw = io_apic_read(apic, 3);
1544 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1547 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1548 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1549 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1550 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1551 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1553 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1554 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1556 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1557 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1560 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1561 * but the value of reg_02 is read as the previous read register
1562 * value, so ignore it if reg_02 == reg_01.
1564 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1565 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1566 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1570 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1571 * or reg_03, but the value of reg_0[23] is read as the previous read
1572 * register value, so ignore it if reg_03 == reg_0[12].
1574 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1575 reg_03.raw != reg_01.raw) {
1576 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1577 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1580 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1582 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1583 " Stat Dmod Deli Vect:\n");
1585 for (i = 0; i <= reg_01.bits.entries; i++) {
1586 struct IO_APIC_route_entry entry;
1588 entry = ioapic_read_entry(apic, i);
1590 printk(KERN_DEBUG " %02x %03X ",
1595 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1600 entry.delivery_status,
1602 entry.delivery_mode,
1607 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1608 for_each_active_irq(irq) {
1609 struct irq_pin_list *entry;
1611 cfg = irq_get_chip_data(irq);
1614 entry = cfg->irq_2_pin;
1617 printk(KERN_DEBUG "IRQ%d ", irq);
1618 for_each_irq_pin(entry, cfg->irq_2_pin)
1619 printk("-> %d:%d", entry->apic, entry->pin);
1623 printk(KERN_INFO ".................................... done.\n");
1628 __apicdebuginit(void) print_APIC_field(int base)
1634 for (i = 0; i < 8; i++)
1635 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1637 printk(KERN_CONT "\n");
1640 __apicdebuginit(void) print_local_APIC(void *dummy)
1642 unsigned int i, v, ver, maxlvt;
1645 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1646 smp_processor_id(), hard_smp_processor_id());
1647 v = apic_read(APIC_ID);
1648 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1649 v = apic_read(APIC_LVR);
1650 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1651 ver = GET_APIC_VERSION(v);
1652 maxlvt = lapic_get_maxlvt();
1654 v = apic_read(APIC_TASKPRI);
1655 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1657 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1658 if (!APIC_XAPIC(ver)) {
1659 v = apic_read(APIC_ARBPRI);
1660 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1661 v & APIC_ARBPRI_MASK);
1663 v = apic_read(APIC_PROCPRI);
1664 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1668 * Remote read supported only in the 82489DX and local APIC for
1669 * Pentium processors.
1671 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1672 v = apic_read(APIC_RRR);
1673 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1676 v = apic_read(APIC_LDR);
1677 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1678 if (!x2apic_enabled()) {
1679 v = apic_read(APIC_DFR);
1680 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1682 v = apic_read(APIC_SPIV);
1683 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1685 printk(KERN_DEBUG "... APIC ISR field:\n");
1686 print_APIC_field(APIC_ISR);
1687 printk(KERN_DEBUG "... APIC TMR field:\n");
1688 print_APIC_field(APIC_TMR);
1689 printk(KERN_DEBUG "... APIC IRR field:\n");
1690 print_APIC_field(APIC_IRR);
1692 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1693 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1694 apic_write(APIC_ESR, 0);
1696 v = apic_read(APIC_ESR);
1697 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1700 icr = apic_icr_read();
1701 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1702 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1704 v = apic_read(APIC_LVTT);
1705 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1707 if (maxlvt > 3) { /* PC is LVT#4. */
1708 v = apic_read(APIC_LVTPC);
1709 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1711 v = apic_read(APIC_LVT0);
1712 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1713 v = apic_read(APIC_LVT1);
1714 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1716 if (maxlvt > 2) { /* ERR is LVT#3. */
1717 v = apic_read(APIC_LVTERR);
1718 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1721 v = apic_read(APIC_TMICT);
1722 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1723 v = apic_read(APIC_TMCCT);
1724 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1725 v = apic_read(APIC_TDCR);
1726 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1728 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1729 v = apic_read(APIC_EFEAT);
1730 maxlvt = (v >> 16) & 0xff;
1731 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1732 v = apic_read(APIC_ECTRL);
1733 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1734 for (i = 0; i < maxlvt; i++) {
1735 v = apic_read(APIC_EILVTn(i));
1736 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1742 __apicdebuginit(void) print_local_APICs(int maxcpu)
1750 for_each_online_cpu(cpu) {
1753 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1758 __apicdebuginit(void) print_PIC(void)
1761 unsigned long flags;
1763 if (!legacy_pic->nr_legacy_irqs)
1766 printk(KERN_DEBUG "\nprinting PIC contents\n");
1768 raw_spin_lock_irqsave(&i8259A_lock, flags);
1770 v = inb(0xa1) << 8 | inb(0x21);
1771 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1773 v = inb(0xa0) << 8 | inb(0x20);
1774 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1778 v = inb(0xa0) << 8 | inb(0x20);
1782 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1784 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1786 v = inb(0x4d1) << 8 | inb(0x4d0);
1787 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1790 static int __initdata show_lapic = 1;
1791 static __init int setup_show_lapic(char *arg)
1795 if (strcmp(arg, "all") == 0) {
1796 show_lapic = CONFIG_NR_CPUS;
1798 get_option(&arg, &num);
1805 __setup("show_lapic=", setup_show_lapic);
1807 __apicdebuginit(int) print_ICs(void)
1809 if (apic_verbosity == APIC_QUIET)
1814 /* don't print out if apic is not there */
1815 if (!cpu_has_apic && !apic_from_smp_config())
1818 print_local_APICs(show_lapic);
1824 fs_initcall(print_ICs);
1827 /* Where if anywhere is the i8259 connect in external int mode */
1828 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1830 void __init enable_IO_APIC(void)
1832 int i8259_apic, i8259_pin;
1835 if (!legacy_pic->nr_legacy_irqs)
1838 for(apic = 0; apic < nr_ioapics; apic++) {
1840 /* See if any of the pins is in ExtINT mode */
1841 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1842 struct IO_APIC_route_entry entry;
1843 entry = ioapic_read_entry(apic, pin);
1845 /* If the interrupt line is enabled and in ExtInt mode
1846 * I have found the pin where the i8259 is connected.
1848 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1849 ioapic_i8259.apic = apic;
1850 ioapic_i8259.pin = pin;
1856 /* Look to see what if the MP table has reported the ExtINT */
1857 /* If we could not find the appropriate pin by looking at the ioapic
1858 * the i8259 probably is not connected the ioapic but give the
1859 * mptable a chance anyway.
1861 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1862 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1863 /* Trust the MP table if nothing is setup in the hardware */
1864 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1865 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1866 ioapic_i8259.pin = i8259_pin;
1867 ioapic_i8259.apic = i8259_apic;
1869 /* Complain if the MP table and the hardware disagree */
1870 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1871 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1873 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1877 * Do not trust the IO-APIC being empty at bootup
1883 * Not an __init, needed by the reboot code
1885 void disable_IO_APIC(void)
1888 * Clear the IO-APIC before rebooting:
1892 if (!legacy_pic->nr_legacy_irqs)
1896 * If the i8259 is routed through an IOAPIC
1897 * Put that IOAPIC in virtual wire mode
1898 * so legacy interrupts can be delivered.
1900 * With interrupt-remapping, for now we will use virtual wire A mode,
1901 * as virtual wire B is little complex (need to configure both
1902 * IOAPIC RTE as well as interrupt-remapping table entry).
1903 * As this gets called during crash dump, keep this simple for now.
1905 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1906 struct IO_APIC_route_entry entry;
1908 memset(&entry, 0, sizeof(entry));
1909 entry.mask = 0; /* Enabled */
1910 entry.trigger = 0; /* Edge */
1912 entry.polarity = 0; /* High */
1913 entry.delivery_status = 0;
1914 entry.dest_mode = 0; /* Physical */
1915 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1917 entry.dest = read_apic_id();
1920 * Add it to the IO-APIC irq-routing table:
1922 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1926 * Use virtual wire A mode when interrupt remapping is enabled.
1928 if (cpu_has_apic || apic_from_smp_config())
1929 disconnect_bsp_APIC(!intr_remapping_enabled &&
1930 ioapic_i8259.pin != -1);
1933 #ifdef CONFIG_X86_32
1935 * function to set the IO-APIC physical IDs based on the
1936 * values stored in the MPC table.
1938 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1940 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1942 union IO_APIC_reg_00 reg_00;
1943 physid_mask_t phys_id_present_map;
1946 unsigned char old_id;
1947 unsigned long flags;
1950 * This is broken; anything with a real cpu count has to
1951 * circumvent this idiocy regardless.
1953 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1956 * Set the IOAPIC ID to the value stored in the MPC table.
1958 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1960 /* Read the register 0 value */
1961 raw_spin_lock_irqsave(&ioapic_lock, flags);
1962 reg_00.raw = io_apic_read(apic_id, 0);
1963 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1965 old_id = mp_ioapics[apic_id].apicid;
1967 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
1968 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1969 apic_id, mp_ioapics[apic_id].apicid);
1970 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1972 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
1976 * Sanity check, is the ID really free? Every APIC in a
1977 * system must have a unique ID or we get lots of nice
1978 * 'stuck on smp_invalidate_needed IPI wait' messages.
1980 if (apic->check_apicid_used(&phys_id_present_map,
1981 mp_ioapics[apic_id].apicid)) {
1982 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1983 apic_id, mp_ioapics[apic_id].apicid);
1984 for (i = 0; i < get_physical_broadcast(); i++)
1985 if (!physid_isset(i, phys_id_present_map))
1987 if (i >= get_physical_broadcast())
1988 panic("Max APIC ID exceeded!\n");
1989 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1991 physid_set(i, phys_id_present_map);
1992 mp_ioapics[apic_id].apicid = i;
1995 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
1996 apic_printk(APIC_VERBOSE, "Setting %d in the "
1997 "phys_id_present_map\n",
1998 mp_ioapics[apic_id].apicid);
1999 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2003 * We need to adjust the IRQ routing table
2004 * if the ID changed.
2006 if (old_id != mp_ioapics[apic_id].apicid)
2007 for (i = 0; i < mp_irq_entries; i++)
2008 if (mp_irqs[i].dstapic == old_id)
2010 = mp_ioapics[apic_id].apicid;
2013 * Update the ID register according to the right value
2014 * from the MPC table if they are different.
2016 if (mp_ioapics[apic_id].apicid == reg_00.bits.ID)
2019 apic_printk(APIC_VERBOSE, KERN_INFO
2020 "...changing IO-APIC physical APIC ID to %d ...",
2021 mp_ioapics[apic_id].apicid);
2023 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2024 raw_spin_lock_irqsave(&ioapic_lock, flags);
2025 io_apic_write(apic_id, 0, reg_00.raw);
2026 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2031 raw_spin_lock_irqsave(&ioapic_lock, flags);
2032 reg_00.raw = io_apic_read(apic_id, 0);
2033 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2034 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2035 printk("could not set ID!\n");
2037 apic_printk(APIC_VERBOSE, " ok.\n");
2041 void __init setup_ioapic_ids_from_mpc(void)
2047 * Don't check I/O APIC IDs for xAPIC systems. They have
2048 * no meaning without the serial APIC bus.
2050 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2051 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2053 setup_ioapic_ids_from_mpc_nocheck();
2057 int no_timer_check __initdata;
2059 static int __init notimercheck(char *s)
2064 __setup("no_timer_check", notimercheck);
2067 * There is a nasty bug in some older SMP boards, their mptable lies
2068 * about the timer IRQ. We do the following to work around the situation:
2070 * - timer IRQ defaults to IO-APIC IRQ
2071 * - if this function detects that timer IRQs are defunct, then we fall
2072 * back to ISA timer IRQs
2074 static int __init timer_irq_works(void)
2076 unsigned long t1 = jiffies;
2077 unsigned long flags;
2082 local_save_flags(flags);
2084 /* Let ten ticks pass... */
2085 mdelay((10 * 1000) / HZ);
2086 local_irq_restore(flags);
2089 * Expect a few ticks at least, to be sure some possible
2090 * glue logic does not lock up after one or two first
2091 * ticks in a non-ExtINT mode. Also the local APIC
2092 * might have cached one ExtINT interrupt. Finally, at
2093 * least one tick may be lost due to delays.
2097 if (time_after(jiffies, t1 + 4))
2103 * In the SMP+IOAPIC case it might happen that there are an unspecified
2104 * number of pending IRQ events unhandled. These cases are very rare,
2105 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2106 * better to do it this way as thus we do not have to be aware of
2107 * 'pending' interrupts in the IRQ path, except at this point.
2110 * Edge triggered needs to resend any interrupt
2111 * that was delayed but this is now handled in the device
2116 * Starting up a edge-triggered IO-APIC interrupt is
2117 * nasty - we need to make sure that we get the edge.
2118 * If it is already asserted for some reason, we need
2119 * return 1 to indicate that is was pending.
2121 * This is not complete - we should be able to fake
2122 * an edge even if it isn't on the 8259A...
2125 static unsigned int startup_ioapic_irq(struct irq_data *data)
2127 int was_pending = 0, irq = data->irq;
2128 unsigned long flags;
2130 raw_spin_lock_irqsave(&ioapic_lock, flags);
2131 if (irq < legacy_pic->nr_legacy_irqs) {
2132 legacy_pic->mask(irq);
2133 if (legacy_pic->irq_pending(irq))
2136 __unmask_ioapic(data->chip_data);
2137 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2142 static int ioapic_retrigger_irq(struct irq_data *data)
2144 struct irq_cfg *cfg = data->chip_data;
2145 unsigned long flags;
2147 raw_spin_lock_irqsave(&vector_lock, flags);
2148 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2149 raw_spin_unlock_irqrestore(&vector_lock, flags);
2155 * Level and edge triggered IO-APIC interrupts need different handling,
2156 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2157 * handled with the level-triggered descriptor, but that one has slightly
2158 * more overhead. Level-triggered interrupts cannot be handled with the
2159 * edge-triggered handler, without risking IRQ storms and other ugly
2164 void send_cleanup_vector(struct irq_cfg *cfg)
2166 cpumask_var_t cleanup_mask;
2168 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2170 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2171 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2173 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2174 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2175 free_cpumask_var(cleanup_mask);
2177 cfg->move_in_progress = 0;
2180 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2183 struct irq_pin_list *entry;
2184 u8 vector = cfg->vector;
2186 for_each_irq_pin(entry, cfg->irq_2_pin) {
2192 * With interrupt-remapping, destination information comes
2193 * from interrupt-remapping table entry.
2195 if (!irq_remapped(cfg))
2196 io_apic_write(apic, 0x11 + pin*2, dest);
2197 reg = io_apic_read(apic, 0x10 + pin*2);
2198 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2200 io_apic_modify(apic, 0x10 + pin*2, reg);
2205 * Either sets data->affinity to a valid value, and returns
2206 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2207 * leaves data->affinity untouched.
2209 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2210 unsigned int *dest_id)
2212 struct irq_cfg *cfg = data->chip_data;
2214 if (!cpumask_intersects(mask, cpu_online_mask))
2217 if (assign_irq_vector(data->irq, data->chip_data, mask))
2220 cpumask_copy(data->affinity, mask);
2222 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2227 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2230 unsigned int dest, irq = data->irq;
2231 unsigned long flags;
2234 raw_spin_lock_irqsave(&ioapic_lock, flags);
2235 ret = __ioapic_set_affinity(data, mask, &dest);
2237 /* Only the high 8 bits are valid. */
2238 dest = SET_APIC_LOGICAL_ID(dest);
2239 __target_IO_APIC_irq(irq, dest, data->chip_data);
2241 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2245 #ifdef CONFIG_INTR_REMAP
2248 * Migrate the IO-APIC irq in the presence of intr-remapping.
2250 * For both level and edge triggered, irq migration is a simple atomic
2251 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2253 * For level triggered, we eliminate the io-apic RTE modification (with the
2254 * updated vector information), by using a virtual vector (io-apic pin number).
2255 * Real vector that is used for interrupting cpu will be coming from
2256 * the interrupt-remapping table entry.
2259 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2262 struct irq_cfg *cfg = data->chip_data;
2263 unsigned int dest, irq = data->irq;
2266 if (!cpumask_intersects(mask, cpu_online_mask))
2269 if (get_irte(irq, &irte))
2272 if (assign_irq_vector(irq, cfg, mask))
2275 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2277 irte.vector = cfg->vector;
2278 irte.dest_id = IRTE_DEST(dest);
2281 * Modified the IRTE and flushes the Interrupt entry cache.
2283 modify_irte(irq, &irte);
2285 if (cfg->move_in_progress)
2286 send_cleanup_vector(cfg);
2288 cpumask_copy(data->affinity, mask);
2294 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2301 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2303 unsigned vector, me;
2309 me = smp_processor_id();
2310 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2313 struct irq_desc *desc;
2314 struct irq_cfg *cfg;
2315 irq = __this_cpu_read(vector_irq[vector]);
2320 desc = irq_to_desc(irq);
2325 raw_spin_lock(&desc->lock);
2328 * Check if the irq migration is in progress. If so, we
2329 * haven't received the cleanup request yet for this irq.
2331 if (cfg->move_in_progress)
2334 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2337 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2339 * Check if the vector that needs to be cleanedup is
2340 * registered at the cpu's IRR. If so, then this is not
2341 * the best time to clean it up. Lets clean it up in the
2342 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2345 if (irr & (1 << (vector % 32))) {
2346 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2349 __this_cpu_write(vector_irq[vector], -1);
2351 raw_spin_unlock(&desc->lock);
2357 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2361 if (likely(!cfg->move_in_progress))
2364 me = smp_processor_id();
2366 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2367 send_cleanup_vector(cfg);
2370 static void irq_complete_move(struct irq_cfg *cfg)
2372 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2375 void irq_force_complete_move(int irq)
2377 struct irq_cfg *cfg = irq_get_chip_data(irq);
2382 __irq_complete_move(cfg, cfg->vector);
2385 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2388 static void ack_apic_edge(struct irq_data *data)
2390 irq_complete_move(data->chip_data);
2395 atomic_t irq_mis_count;
2398 * IO-APIC versions below 0x20 don't support EOI register.
2399 * For the record, here is the information about various versions:
2401 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2402 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2405 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2406 * version as 0x2. This is an error with documentation and these ICH chips
2407 * use io-apic's of version 0x20.
2409 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2410 * Otherwise, we simulate the EOI message manually by changing the trigger
2411 * mode to edge and then back to level, with RTE being masked during this.
2413 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2415 struct irq_pin_list *entry;
2416 unsigned long flags;
2418 raw_spin_lock_irqsave(&ioapic_lock, flags);
2419 for_each_irq_pin(entry, cfg->irq_2_pin) {
2420 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2422 * Intr-remapping uses pin number as the virtual vector
2423 * in the RTE. Actual vector is programmed in
2424 * intr-remapping table entry. Hence for the io-apic
2425 * EOI we use the pin number.
2427 if (irq_remapped(cfg))
2428 io_apic_eoi(entry->apic, entry->pin);
2430 io_apic_eoi(entry->apic, cfg->vector);
2432 __mask_and_edge_IO_APIC_irq(entry);
2433 __unmask_and_level_IO_APIC_irq(entry);
2436 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2439 static void ack_apic_level(struct irq_data *data)
2441 struct irq_cfg *cfg = data->chip_data;
2442 int i, do_unmask_irq = 0, irq = data->irq;
2445 irq_complete_move(cfg);
2446 #ifdef CONFIG_GENERIC_PENDING_IRQ
2447 /* If we are moving the irq we need to mask it */
2448 if (unlikely(irqd_is_setaffinity_pending(data))) {
2455 * It appears there is an erratum which affects at least version 0x11
2456 * of I/O APIC (that's the 82093AA and cores integrated into various
2457 * chipsets). Under certain conditions a level-triggered interrupt is
2458 * erroneously delivered as edge-triggered one but the respective IRR
2459 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2460 * message but it will never arrive and further interrupts are blocked
2461 * from the source. The exact reason is so far unknown, but the
2462 * phenomenon was observed when two consecutive interrupt requests
2463 * from a given source get delivered to the same CPU and the source is
2464 * temporarily disabled in between.
2466 * A workaround is to simulate an EOI message manually. We achieve it
2467 * by setting the trigger mode to edge and then to level when the edge
2468 * trigger mode gets detected in the TMR of a local APIC for a
2469 * level-triggered interrupt. We mask the source for the time of the
2470 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2471 * The idea is from Manfred Spraul. --macro
2473 * Also in the case when cpu goes offline, fixup_irqs() will forward
2474 * any unhandled interrupt on the offlined cpu to the new cpu
2475 * destination that is handling the corresponding interrupt. This
2476 * interrupt forwarding is done via IPI's. Hence, in this case also
2477 * level-triggered io-apic interrupt will be seen as an edge
2478 * interrupt in the IRR. And we can't rely on the cpu's EOI
2479 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2480 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2481 * supporting EOI register, we do an explicit EOI to clear the
2482 * remote IRR and on IO-APIC's which don't have an EOI register,
2483 * we use the above logic (mask+edge followed by unmask+level) from
2484 * Manfred Spraul to clear the remote IRR.
2487 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2490 * We must acknowledge the irq before we move it or the acknowledge will
2491 * not propagate properly.
2496 * Tail end of clearing remote IRR bit (either by delivering the EOI
2497 * message via io-apic EOI register write or simulating it using
2498 * mask+edge followed by unnask+level logic) manually when the
2499 * level triggered interrupt is seen as the edge triggered interrupt
2502 if (!(v & (1 << (i & 0x1f)))) {
2503 atomic_inc(&irq_mis_count);
2505 eoi_ioapic_irq(irq, cfg);
2508 /* Now we can move and renable the irq */
2509 if (unlikely(do_unmask_irq)) {
2510 /* Only migrate the irq if the ack has been received.
2512 * On rare occasions the broadcast level triggered ack gets
2513 * delayed going to ioapics, and if we reprogram the
2514 * vector while Remote IRR is still set the irq will never
2517 * To prevent this scenario we read the Remote IRR bit
2518 * of the ioapic. This has two effects.
2519 * - On any sane system the read of the ioapic will
2520 * flush writes (and acks) going to the ioapic from
2522 * - We get to see if the ACK has actually been delivered.
2524 * Based on failed experiments of reprogramming the
2525 * ioapic entry from outside of irq context starting
2526 * with masking the ioapic entry and then polling until
2527 * Remote IRR was clear before reprogramming the
2528 * ioapic I don't trust the Remote IRR bit to be
2529 * completey accurate.
2531 * However there appears to be no other way to plug
2532 * this race, so if the Remote IRR bit is not
2533 * accurate and is causing problems then it is a hardware bug
2534 * and you can go talk to the chipset vendor about it.
2536 if (!io_apic_level_ack_pending(cfg))
2537 irq_move_masked_irq(data);
2542 #ifdef CONFIG_INTR_REMAP
2543 static void ir_ack_apic_edge(struct irq_data *data)
2548 static void ir_ack_apic_level(struct irq_data *data)
2551 eoi_ioapic_irq(data->irq, data->chip_data);
2553 #endif /* CONFIG_INTR_REMAP */
2555 static struct irq_chip ioapic_chip __read_mostly = {
2557 .irq_startup = startup_ioapic_irq,
2558 .irq_mask = mask_ioapic_irq,
2559 .irq_unmask = unmask_ioapic_irq,
2560 .irq_ack = ack_apic_edge,
2561 .irq_eoi = ack_apic_level,
2563 .irq_set_affinity = ioapic_set_affinity,
2565 .irq_retrigger = ioapic_retrigger_irq,
2568 static struct irq_chip ir_ioapic_chip __read_mostly = {
2569 .name = "IR-IO-APIC",
2570 .irq_startup = startup_ioapic_irq,
2571 .irq_mask = mask_ioapic_irq,
2572 .irq_unmask = unmask_ioapic_irq,
2573 #ifdef CONFIG_INTR_REMAP
2574 .irq_ack = ir_ack_apic_edge,
2575 .irq_eoi = ir_ack_apic_level,
2577 .irq_set_affinity = ir_ioapic_set_affinity,
2580 .irq_retrigger = ioapic_retrigger_irq,
2583 static inline void init_IO_APIC_traps(void)
2585 struct irq_cfg *cfg;
2589 * NOTE! The local APIC isn't very good at handling
2590 * multiple interrupts at the same interrupt level.
2591 * As the interrupt level is determined by taking the
2592 * vector number and shifting that right by 4, we
2593 * want to spread these out a bit so that they don't
2594 * all fall in the same interrupt level.
2596 * Also, we've got to be careful not to trash gate
2597 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2599 for_each_active_irq(irq) {
2600 cfg = irq_get_chip_data(irq);
2601 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2603 * Hmm.. We don't have an entry for this,
2604 * so default to an old-fashioned 8259
2605 * interrupt if we can..
2607 if (irq < legacy_pic->nr_legacy_irqs)
2608 legacy_pic->make_irq(irq);
2610 /* Strange. Oh, well.. */
2611 irq_set_chip(irq, &no_irq_chip);
2617 * The local APIC irq-chip implementation:
2620 static void mask_lapic_irq(struct irq_data *data)
2624 v = apic_read(APIC_LVT0);
2625 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2628 static void unmask_lapic_irq(struct irq_data *data)
2632 v = apic_read(APIC_LVT0);
2633 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2636 static void ack_lapic_irq(struct irq_data *data)
2641 static struct irq_chip lapic_chip __read_mostly = {
2642 .name = "local-APIC",
2643 .irq_mask = mask_lapic_irq,
2644 .irq_unmask = unmask_lapic_irq,
2645 .irq_ack = ack_lapic_irq,
2648 static void lapic_register_intr(int irq)
2650 irq_clear_status_flags(irq, IRQ_LEVEL);
2651 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2656 * This looks a bit hackish but it's about the only one way of sending
2657 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2658 * not support the ExtINT mode, unfortunately. We need to send these
2659 * cycles as some i82489DX-based boards have glue logic that keeps the
2660 * 8259A interrupt line asserted until INTA. --macro
2662 static inline void __init unlock_ExtINT_logic(void)
2665 struct IO_APIC_route_entry entry0, entry1;
2666 unsigned char save_control, save_freq_select;
2668 pin = find_isa_irq_pin(8, mp_INT);
2673 apic = find_isa_irq_apic(8, mp_INT);
2679 entry0 = ioapic_read_entry(apic, pin);
2680 clear_IO_APIC_pin(apic, pin);
2682 memset(&entry1, 0, sizeof(entry1));
2684 entry1.dest_mode = 0; /* physical delivery */
2685 entry1.mask = 0; /* unmask IRQ now */
2686 entry1.dest = hard_smp_processor_id();
2687 entry1.delivery_mode = dest_ExtINT;
2688 entry1.polarity = entry0.polarity;
2692 ioapic_write_entry(apic, pin, entry1);
2694 save_control = CMOS_READ(RTC_CONTROL);
2695 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2696 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2698 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2703 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2707 CMOS_WRITE(save_control, RTC_CONTROL);
2708 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2709 clear_IO_APIC_pin(apic, pin);
2711 ioapic_write_entry(apic, pin, entry0);
2714 static int disable_timer_pin_1 __initdata;
2715 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2716 static int __init disable_timer_pin_setup(char *arg)
2718 disable_timer_pin_1 = 1;
2721 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2723 int timer_through_8259 __initdata;
2726 * This code may look a bit paranoid, but it's supposed to cooperate with
2727 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2728 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2729 * fanatically on his truly buggy board.
2731 * FIXME: really need to revamp this for all platforms.
2733 static inline void __init check_timer(void)
2735 struct irq_cfg *cfg = irq_get_chip_data(0);
2736 int node = cpu_to_node(0);
2737 int apic1, pin1, apic2, pin2;
2738 unsigned long flags;
2741 local_irq_save(flags);
2744 * get/set the timer IRQ vector:
2746 legacy_pic->mask(0);
2747 assign_irq_vector(0, cfg, apic->target_cpus());
2750 * As IRQ0 is to be enabled in the 8259A, the virtual
2751 * wire has to be disabled in the local APIC. Also
2752 * timer interrupts need to be acknowledged manually in
2753 * the 8259A for the i82489DX when using the NMI
2754 * watchdog as that APIC treats NMIs as level-triggered.
2755 * The AEOI mode will finish them in the 8259A
2758 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2759 legacy_pic->init(1);
2761 pin1 = find_isa_irq_pin(0, mp_INT);
2762 apic1 = find_isa_irq_apic(0, mp_INT);
2763 pin2 = ioapic_i8259.pin;
2764 apic2 = ioapic_i8259.apic;
2766 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2767 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2768 cfg->vector, apic1, pin1, apic2, pin2);
2771 * Some BIOS writers are clueless and report the ExtINTA
2772 * I/O APIC input from the cascaded 8259A as the timer
2773 * interrupt input. So just in case, if only one pin
2774 * was found above, try it both directly and through the
2778 if (intr_remapping_enabled)
2779 panic("BIOS bug: timer not connected to IO-APIC");
2783 } else if (pin2 == -1) {
2790 * Ok, does IRQ0 through the IOAPIC work?
2793 add_pin_to_irq_node(cfg, node, apic1, pin1);
2794 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2796 /* for edge trigger, setup_ioapic_irq already
2797 * leave it unmasked.
2798 * so only need to unmask if it is level-trigger
2799 * do we really have level trigger timer?
2802 idx = find_irq_entry(apic1, pin1, mp_INT);
2803 if (idx != -1 && irq_trigger(idx))
2806 if (timer_irq_works()) {
2807 if (disable_timer_pin_1 > 0)
2808 clear_IO_APIC_pin(0, pin1);
2811 if (intr_remapping_enabled)
2812 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2813 local_irq_disable();
2814 clear_IO_APIC_pin(apic1, pin1);
2816 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2817 "8254 timer not connected to IO-APIC\n");
2819 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2820 "(IRQ0) through the 8259A ...\n");
2821 apic_printk(APIC_QUIET, KERN_INFO
2822 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2824 * legacy devices should be connected to IO APIC #0
2826 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2827 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2828 legacy_pic->unmask(0);
2829 if (timer_irq_works()) {
2830 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2831 timer_through_8259 = 1;
2835 * Cleanup, just in case ...
2837 local_irq_disable();
2838 legacy_pic->mask(0);
2839 clear_IO_APIC_pin(apic2, pin2);
2840 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2843 apic_printk(APIC_QUIET, KERN_INFO
2844 "...trying to set up timer as Virtual Wire IRQ...\n");
2846 lapic_register_intr(0);
2847 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2848 legacy_pic->unmask(0);
2850 if (timer_irq_works()) {
2851 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2854 local_irq_disable();
2855 legacy_pic->mask(0);
2856 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2857 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2859 apic_printk(APIC_QUIET, KERN_INFO
2860 "...trying to set up timer as ExtINT IRQ...\n");
2862 legacy_pic->init(0);
2863 legacy_pic->make_irq(0);
2864 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2866 unlock_ExtINT_logic();
2868 if (timer_irq_works()) {
2869 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2872 local_irq_disable();
2873 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2874 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2875 "report. Then try booting with the 'noapic' option.\n");
2877 local_irq_restore(flags);
2881 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2882 * to devices. However there may be an I/O APIC pin available for
2883 * this interrupt regardless. The pin may be left unconnected, but
2884 * typically it will be reused as an ExtINT cascade interrupt for
2885 * the master 8259A. In the MPS case such a pin will normally be
2886 * reported as an ExtINT interrupt in the MP table. With ACPI
2887 * there is no provision for ExtINT interrupts, and in the absence
2888 * of an override it would be treated as an ordinary ISA I/O APIC
2889 * interrupt, that is edge-triggered and unmasked by default. We
2890 * used to do this, but it caused problems on some systems because
2891 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2892 * the same ExtINT cascade interrupt to drive the local APIC of the
2893 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2894 * the I/O APIC in all cases now. No actual device should request
2895 * it anyway. --macro
2897 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2899 void __init setup_IO_APIC(void)
2903 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2905 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2907 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2909 * Set up IO-APIC IRQ routing.
2911 x86_init.mpparse.setup_ioapic_ids();
2914 setup_IO_APIC_irqs();
2915 init_IO_APIC_traps();
2916 if (legacy_pic->nr_legacy_irqs)
2921 * Called after all the initialization is done. If we didn't find any
2922 * APIC bugs then we can allow the modify fast path
2925 static int __init io_apic_bug_finalize(void)
2927 if (sis_apic_bug == -1)
2932 late_initcall(io_apic_bug_finalize);
2934 static void suspend_ioapic(int ioapic_id)
2936 struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id];
2942 for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++)
2943 saved_data[i] = ioapic_read_entry(ioapic_id, i);
2946 static int ioapic_suspend(void)
2950 for (ioapic_id = 0; ioapic_id < nr_ioapics; ioapic_id++)
2951 suspend_ioapic(ioapic_id);
2956 static void resume_ioapic(int ioapic_id)
2958 struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id];
2959 unsigned long flags;
2960 union IO_APIC_reg_00 reg_00;
2966 raw_spin_lock_irqsave(&ioapic_lock, flags);
2967 reg_00.raw = io_apic_read(ioapic_id, 0);
2968 if (reg_00.bits.ID != mp_ioapics[ioapic_id].apicid) {
2969 reg_00.bits.ID = mp_ioapics[ioapic_id].apicid;
2970 io_apic_write(ioapic_id, 0, reg_00.raw);
2972 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2973 for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++)
2974 ioapic_write_entry(ioapic_id, i, saved_data[i]);
2977 static void ioapic_resume(void)
2981 for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--)
2982 resume_ioapic(ioapic_id);
2985 static struct syscore_ops ioapic_syscore_ops = {
2986 .suspend = ioapic_suspend,
2987 .resume = ioapic_resume,
2990 static int __init ioapic_init_ops(void)
2992 register_syscore_ops(&ioapic_syscore_ops);
2997 device_initcall(ioapic_init_ops);
3000 * Dynamic irq allocate and deallocation
3002 unsigned int create_irq_nr(unsigned int from, int node)
3004 struct irq_cfg *cfg;
3005 unsigned long flags;
3006 unsigned int ret = 0;
3009 if (from < nr_irqs_gsi)
3012 irq = alloc_irq_from(from, node);
3015 cfg = alloc_irq_cfg(irq, node);
3017 free_irq_at(irq, NULL);
3021 raw_spin_lock_irqsave(&vector_lock, flags);
3022 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3024 raw_spin_unlock_irqrestore(&vector_lock, flags);
3027 irq_set_chip_data(irq, cfg);
3028 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3030 free_irq_at(irq, cfg);
3035 int create_irq(void)
3037 int node = cpu_to_node(0);
3038 unsigned int irq_want;
3041 irq_want = nr_irqs_gsi;
3042 irq = create_irq_nr(irq_want, node);
3050 void destroy_irq(unsigned int irq)
3052 struct irq_cfg *cfg = irq_get_chip_data(irq);
3053 unsigned long flags;
3055 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3057 if (irq_remapped(cfg))
3059 raw_spin_lock_irqsave(&vector_lock, flags);
3060 __clear_irq_vector(irq, cfg);
3061 raw_spin_unlock_irqrestore(&vector_lock, flags);
3062 free_irq_at(irq, cfg);
3066 * MSI message composition
3068 #ifdef CONFIG_PCI_MSI
3069 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3070 struct msi_msg *msg, u8 hpet_id)
3072 struct irq_cfg *cfg;
3080 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3084 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3086 if (irq_remapped(cfg)) {
3091 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3092 BUG_ON(ir_index == -1);
3094 prepare_irte(&irte, cfg->vector, dest);
3096 /* Set source-id of interrupt request */
3098 set_msi_sid(&irte, pdev);
3100 set_hpet_sid(&irte, hpet_id);
3102 modify_irte(irq, &irte);
3104 msg->address_hi = MSI_ADDR_BASE_HI;
3105 msg->data = sub_handle;
3106 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3108 MSI_ADDR_IR_INDEX1(ir_index) |
3109 MSI_ADDR_IR_INDEX2(ir_index);
3111 if (x2apic_enabled())
3112 msg->address_hi = MSI_ADDR_BASE_HI |
3113 MSI_ADDR_EXT_DEST_ID(dest);
3115 msg->address_hi = MSI_ADDR_BASE_HI;
3119 ((apic->irq_dest_mode == 0) ?
3120 MSI_ADDR_DEST_MODE_PHYSICAL:
3121 MSI_ADDR_DEST_MODE_LOGICAL) |
3122 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3123 MSI_ADDR_REDIRECTION_CPU:
3124 MSI_ADDR_REDIRECTION_LOWPRI) |
3125 MSI_ADDR_DEST_ID(dest);
3128 MSI_DATA_TRIGGER_EDGE |
3129 MSI_DATA_LEVEL_ASSERT |
3130 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3131 MSI_DATA_DELIVERY_FIXED:
3132 MSI_DATA_DELIVERY_LOWPRI) |
3133 MSI_DATA_VECTOR(cfg->vector);
3140 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3142 struct irq_cfg *cfg = data->chip_data;
3146 if (__ioapic_set_affinity(data, mask, &dest))
3149 __get_cached_msi_msg(data->msi_desc, &msg);
3151 msg.data &= ~MSI_DATA_VECTOR_MASK;
3152 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3153 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3154 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3156 __write_msi_msg(data->msi_desc, &msg);
3160 #ifdef CONFIG_INTR_REMAP
3162 * Migrate the MSI irq to another cpumask. This migration is
3163 * done in the process context using interrupt-remapping hardware.
3166 ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3169 struct irq_cfg *cfg = data->chip_data;
3170 unsigned int dest, irq = data->irq;
3173 if (get_irte(irq, &irte))
3176 if (__ioapic_set_affinity(data, mask, &dest))
3179 irte.vector = cfg->vector;
3180 irte.dest_id = IRTE_DEST(dest);
3183 * atomically update the IRTE with the new destination and vector.
3185 modify_irte(irq, &irte);
3188 * After this point, all the interrupts will start arriving
3189 * at the new destination. So, time to cleanup the previous
3190 * vector allocation.
3192 if (cfg->move_in_progress)
3193 send_cleanup_vector(cfg);
3199 #endif /* CONFIG_SMP */
3202 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3203 * which implement the MSI or MSI-X Capability Structure.
3205 static struct irq_chip msi_chip = {
3207 .irq_unmask = unmask_msi_irq,
3208 .irq_mask = mask_msi_irq,
3209 .irq_ack = ack_apic_edge,
3211 .irq_set_affinity = msi_set_affinity,
3213 .irq_retrigger = ioapic_retrigger_irq,
3216 static struct irq_chip msi_ir_chip = {
3217 .name = "IR-PCI-MSI",
3218 .irq_unmask = unmask_msi_irq,
3219 .irq_mask = mask_msi_irq,
3220 #ifdef CONFIG_INTR_REMAP
3221 .irq_ack = ir_ack_apic_edge,
3223 .irq_set_affinity = ir_msi_set_affinity,
3226 .irq_retrigger = ioapic_retrigger_irq,
3230 * Map the PCI dev to the corresponding remapping hardware unit
3231 * and allocate 'nvec' consecutive interrupt-remapping table entries
3234 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3236 struct intel_iommu *iommu;
3239 iommu = map_dev_to_ir(dev);
3242 "Unable to map PCI %s to iommu\n", pci_name(dev));
3246 index = alloc_irte(iommu, irq, nvec);
3249 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3256 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3258 struct irq_chip *chip = &msi_chip;
3262 ret = msi_compose_msg(dev, irq, &msg, -1);
3266 irq_set_msi_desc(irq, msidesc);
3267 write_msi_msg(irq, &msg);
3269 if (irq_remapped(irq_get_chip_data(irq))) {
3270 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3271 chip = &msi_ir_chip;
3274 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3276 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3281 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3283 int node, ret, sub_handle, index = 0;
3284 unsigned int irq, irq_want;
3285 struct msi_desc *msidesc;
3286 struct intel_iommu *iommu = NULL;
3288 /* x86 doesn't support multiple MSI yet */
3289 if (type == PCI_CAP_ID_MSI && nvec > 1)
3292 node = dev_to_node(&dev->dev);
3293 irq_want = nr_irqs_gsi;
3295 list_for_each_entry(msidesc, &dev->msi_list, list) {
3296 irq = create_irq_nr(irq_want, node);
3300 if (!intr_remapping_enabled)
3305 * allocate the consecutive block of IRTE's
3308 index = msi_alloc_irte(dev, irq, nvec);
3314 iommu = map_dev_to_ir(dev);
3320 * setup the mapping between the irq and the IRTE
3321 * base index, the sub_handle pointing to the
3322 * appropriate interrupt remap table entry.
3324 set_irte_irq(irq, iommu, index, sub_handle);
3327 ret = setup_msi_irq(dev, msidesc, irq);
3339 void native_teardown_msi_irq(unsigned int irq)
3344 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3347 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3350 struct irq_cfg *cfg = data->chip_data;
3351 unsigned int dest, irq = data->irq;
3354 if (__ioapic_set_affinity(data, mask, &dest))
3357 dmar_msi_read(irq, &msg);
3359 msg.data &= ~MSI_DATA_VECTOR_MASK;
3360 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3361 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3362 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3363 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3365 dmar_msi_write(irq, &msg);
3370 #endif /* CONFIG_SMP */
3372 static struct irq_chip dmar_msi_type = {
3374 .irq_unmask = dmar_msi_unmask,
3375 .irq_mask = dmar_msi_mask,
3376 .irq_ack = ack_apic_edge,
3378 .irq_set_affinity = dmar_msi_set_affinity,
3380 .irq_retrigger = ioapic_retrigger_irq,
3383 int arch_setup_dmar_msi(unsigned int irq)
3388 ret = msi_compose_msg(NULL, irq, &msg, -1);
3391 dmar_msi_write(irq, &msg);
3392 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3398 #ifdef CONFIG_HPET_TIMER
3401 static int hpet_msi_set_affinity(struct irq_data *data,
3402 const struct cpumask *mask, bool force)
3404 struct irq_cfg *cfg = data->chip_data;
3408 if (__ioapic_set_affinity(data, mask, &dest))
3411 hpet_msi_read(data->handler_data, &msg);
3413 msg.data &= ~MSI_DATA_VECTOR_MASK;
3414 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3415 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3416 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3418 hpet_msi_write(data->handler_data, &msg);
3423 #endif /* CONFIG_SMP */
3425 static struct irq_chip ir_hpet_msi_type = {
3426 .name = "IR-HPET_MSI",
3427 .irq_unmask = hpet_msi_unmask,
3428 .irq_mask = hpet_msi_mask,
3429 #ifdef CONFIG_INTR_REMAP
3430 .irq_ack = ir_ack_apic_edge,
3432 .irq_set_affinity = ir_msi_set_affinity,
3435 .irq_retrigger = ioapic_retrigger_irq,
3438 static struct irq_chip hpet_msi_type = {
3440 .irq_unmask = hpet_msi_unmask,
3441 .irq_mask = hpet_msi_mask,
3442 .irq_ack = ack_apic_edge,
3444 .irq_set_affinity = hpet_msi_set_affinity,
3446 .irq_retrigger = ioapic_retrigger_irq,
3449 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3451 struct irq_chip *chip = &hpet_msi_type;
3455 if (intr_remapping_enabled) {
3456 struct intel_iommu *iommu = map_hpet_to_ir(id);
3462 index = alloc_irte(iommu, irq, 1);
3467 ret = msi_compose_msg(NULL, irq, &msg, id);
3471 hpet_msi_write(irq_get_handler_data(irq), &msg);
3472 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3473 if (irq_remapped(irq_get_chip_data(irq)))
3474 chip = &ir_hpet_msi_type;
3476 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3481 #endif /* CONFIG_PCI_MSI */
3483 * Hypertransport interrupt support
3485 #ifdef CONFIG_HT_IRQ
3489 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3491 struct ht_irq_msg msg;
3492 fetch_ht_irq_msg(irq, &msg);
3494 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3495 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3497 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3498 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3500 write_ht_irq_msg(irq, &msg);
3504 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3506 struct irq_cfg *cfg = data->chip_data;
3509 if (__ioapic_set_affinity(data, mask, &dest))
3512 target_ht_irq(data->irq, dest, cfg->vector);
3518 static struct irq_chip ht_irq_chip = {
3520 .irq_mask = mask_ht_irq,
3521 .irq_unmask = unmask_ht_irq,
3522 .irq_ack = ack_apic_edge,
3524 .irq_set_affinity = ht_set_affinity,
3526 .irq_retrigger = ioapic_retrigger_irq,
3529 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3531 struct irq_cfg *cfg;
3538 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3540 struct ht_irq_msg msg;
3543 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3544 apic->target_cpus());
3546 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3550 HT_IRQ_LOW_DEST_ID(dest) |
3551 HT_IRQ_LOW_VECTOR(cfg->vector) |
3552 ((apic->irq_dest_mode == 0) ?
3553 HT_IRQ_LOW_DM_PHYSICAL :
3554 HT_IRQ_LOW_DM_LOGICAL) |
3555 HT_IRQ_LOW_RQEOI_EDGE |
3556 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3557 HT_IRQ_LOW_MT_FIXED :
3558 HT_IRQ_LOW_MT_ARBITRATED) |
3559 HT_IRQ_LOW_IRQ_MASKED;
3561 write_ht_irq_msg(irq, &msg);
3563 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3564 handle_edge_irq, "edge");
3566 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3570 #endif /* CONFIG_HT_IRQ */
3573 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3575 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3580 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3582 setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg,
3583 attr->trigger, attr->polarity);
3587 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3588 struct io_apic_irq_attr *attr)
3590 unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
3593 /* Avoid redundant programming */
3594 if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) {
3595 pr_debug("Pin %d-%d already programmed\n",
3596 mp_ioapics[id].apicid, pin);
3599 ret = io_apic_setup_irq_pin(irq, node, attr);
3601 set_bit(pin, mp_ioapic_routing[id].pin_programmed);
3605 static int __init io_apic_get_redir_entries(int ioapic)
3607 union IO_APIC_reg_01 reg_01;
3608 unsigned long flags;
3610 raw_spin_lock_irqsave(&ioapic_lock, flags);
3611 reg_01.raw = io_apic_read(ioapic, 1);
3612 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3614 /* The register returns the maximum index redir index
3615 * supported, which is one less than the total number of redir
3618 return reg_01.bits.entries + 1;
3621 static void __init probe_nr_irqs_gsi(void)
3625 nr = gsi_top + NR_IRQS_LEGACY;
3626 if (nr > nr_irqs_gsi)
3629 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3632 int get_nr_irqs_gsi(void)
3637 #ifdef CONFIG_SPARSE_IRQ
3638 int __init arch_probe_nr_irqs(void)
3642 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3643 nr_irqs = NR_VECTORS * nr_cpu_ids;
3645 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3646 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3648 * for MSI and HT dyn irq
3650 nr += nr_irqs_gsi * 16;
3655 return NR_IRQS_LEGACY;
3659 int io_apic_set_pci_routing(struct device *dev, int irq,
3660 struct io_apic_irq_attr *irq_attr)
3664 if (!IO_APIC_IRQ(irq)) {
3665 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3670 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3672 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3675 #ifdef CONFIG_X86_32
3676 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3678 union IO_APIC_reg_00 reg_00;
3679 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3681 unsigned long flags;
3685 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3686 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3687 * supports up to 16 on one shared APIC bus.
3689 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3690 * advantage of new APIC bus architecture.
3693 if (physids_empty(apic_id_map))
3694 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3696 raw_spin_lock_irqsave(&ioapic_lock, flags);
3697 reg_00.raw = io_apic_read(ioapic, 0);
3698 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3700 if (apic_id >= get_physical_broadcast()) {
3701 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3702 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3703 apic_id = reg_00.bits.ID;
3707 * Every APIC in a system must have a unique ID or we get lots of nice
3708 * 'stuck on smp_invalidate_needed IPI wait' messages.
3710 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3712 for (i = 0; i < get_physical_broadcast(); i++) {
3713 if (!apic->check_apicid_used(&apic_id_map, i))
3717 if (i == get_physical_broadcast())
3718 panic("Max apic_id exceeded!\n");
3720 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3721 "trying %d\n", ioapic, apic_id, i);
3726 apic->apicid_to_cpu_present(apic_id, &tmp);
3727 physids_or(apic_id_map, apic_id_map, tmp);
3729 if (reg_00.bits.ID != apic_id) {
3730 reg_00.bits.ID = apic_id;
3732 raw_spin_lock_irqsave(&ioapic_lock, flags);
3733 io_apic_write(ioapic, 0, reg_00.raw);
3734 reg_00.raw = io_apic_read(ioapic, 0);
3735 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3738 if (reg_00.bits.ID != apic_id) {
3739 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3744 apic_printk(APIC_VERBOSE, KERN_INFO
3745 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3750 static u8 __init io_apic_unique_id(u8 id)
3752 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3753 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3754 return io_apic_get_unique_id(nr_ioapics, id);
3759 static u8 __init io_apic_unique_id(u8 id)
3762 DECLARE_BITMAP(used, 256);
3764 bitmap_zero(used, 256);
3765 for (i = 0; i < nr_ioapics; i++) {
3766 struct mpc_ioapic *ia = &mp_ioapics[i];
3767 __set_bit(ia->apicid, used);
3769 if (!test_bit(id, used))
3771 return find_first_zero_bit(used, 256);
3775 static int __init io_apic_get_version(int ioapic)
3777 union IO_APIC_reg_01 reg_01;
3778 unsigned long flags;
3780 raw_spin_lock_irqsave(&ioapic_lock, flags);
3781 reg_01.raw = io_apic_read(ioapic, 1);
3782 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3784 return reg_01.bits.version;
3787 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3789 int ioapic, pin, idx;
3791 if (skip_ioapic_setup)
3794 ioapic = mp_find_ioapic(gsi);
3798 pin = mp_find_ioapic_pin(ioapic, gsi);
3802 idx = find_irq_entry(ioapic, pin, mp_INT);
3806 *trigger = irq_trigger(idx);
3807 *polarity = irq_polarity(idx);
3812 * This function currently is only a helper for the i386 smp boot process where
3813 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3814 * so mask in all cases should simply be apic->target_cpus()
3817 void __init setup_ioapic_dest(void)
3819 int pin, ioapic, irq, irq_entry;
3820 const struct cpumask *mask;
3821 struct irq_data *idata;
3823 if (skip_ioapic_setup == 1)
3826 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3827 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3828 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3829 if (irq_entry == -1)
3831 irq = pin_2_irq(irq_entry, ioapic, pin);
3833 if ((ioapic > 0) && (irq > 16))
3836 idata = irq_get_irq_data(irq);
3839 * Honour affinities which have been set in early boot
3841 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3842 mask = idata->affinity;
3844 mask = apic->target_cpus();
3846 if (intr_remapping_enabled)
3847 ir_ioapic_set_affinity(idata, mask, false);
3849 ioapic_set_affinity(idata, mask, false);
3855 #define IOAPIC_RESOURCE_NAME_SIZE 11
3857 static struct resource *ioapic_resources;
3859 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3862 struct resource *res;
3866 if (nr_ioapics <= 0)
3869 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3872 mem = alloc_bootmem(n);
3875 mem += sizeof(struct resource) * nr_ioapics;
3877 for (i = 0; i < nr_ioapics; i++) {
3879 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3880 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3881 mem += IOAPIC_RESOURCE_NAME_SIZE;
3884 ioapic_resources = res;
3889 void __init ioapic_and_gsi_init(void)
3891 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3892 struct resource *ioapic_res;
3895 ioapic_res = ioapic_setup_resources(nr_ioapics);
3896 for (i = 0; i < nr_ioapics; i++) {
3897 if (smp_found_config) {
3898 ioapic_phys = mp_ioapics[i].apicaddr;
3899 #ifdef CONFIG_X86_32
3902 "WARNING: bogus zero IO-APIC "
3903 "address found in MPTABLE, "
3904 "disabling IO/APIC support!\n");
3905 smp_found_config = 0;
3906 skip_ioapic_setup = 1;
3907 goto fake_ioapic_page;
3911 #ifdef CONFIG_X86_32
3914 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3915 ioapic_phys = __pa(ioapic_phys);
3917 set_fixmap_nocache(idx, ioapic_phys);
3918 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3919 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3923 ioapic_res->start = ioapic_phys;
3924 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3928 probe_nr_irqs_gsi();
3931 void __init ioapic_insert_resources(void)
3934 struct resource *r = ioapic_resources;
3939 "IO APIC resources couldn't be allocated.\n");
3943 for (i = 0; i < nr_ioapics; i++) {
3944 insert_resource(&iomem_resource, r);
3949 int mp_find_ioapic(u32 gsi)
3953 if (nr_ioapics == 0)
3956 /* Find the IOAPIC that manages this GSI. */
3957 for (i = 0; i < nr_ioapics; i++) {
3958 if ((gsi >= mp_gsi_routing[i].gsi_base)
3959 && (gsi <= mp_gsi_routing[i].gsi_end))
3963 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3967 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3969 if (WARN_ON(ioapic == -1))
3971 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
3974 return gsi - mp_gsi_routing[ioapic].gsi_base;
3977 static __init int bad_ioapic(unsigned long address)
3979 if (nr_ioapics >= MAX_IO_APICS) {
3980 printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded "
3981 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
3985 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
3986 " found in table, skipping!\n");
3992 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3997 if (bad_ioapic(address))
4002 mp_ioapics[idx].type = MP_IOAPIC;
4003 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4004 mp_ioapics[idx].apicaddr = address;
4006 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4007 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4008 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4011 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4012 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4014 entries = io_apic_get_redir_entries(idx);
4015 mp_gsi_routing[idx].gsi_base = gsi_base;
4016 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
4019 * The number of IO-APIC IRQ registers (== #pins):
4021 nr_ioapic_registers[idx] = entries;
4023 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
4024 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
4026 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4027 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4028 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4029 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4034 /* Enable IOAPIC early just for system timer */
4035 void __init pre_init_apic_IRQ0(void)
4037 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4039 printk(KERN_INFO "Early APIC setup for system timer0\n");
4041 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4042 &phys_cpu_present_map);
4046 io_apic_setup_irq_pin(0, 0, &attr);
4047 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,