2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug = -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock);
78 static DEFINE_RAW_SPINLOCK(vector_lock);
81 * # of IRQ routing registers
83 int nr_ioapic_registers[MAX_IO_APICS];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
92 /* The one past the highest gsi number used */
95 /* MP IRQ source entries */
96 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
98 /* # of MP IRQ source entries */
102 static int nr_irqs_gsi = NR_IRQS_LEGACY;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type[MAX_MP_BUSSES];
108 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
110 int skip_ioapic_setup;
112 void arch_disable_smp_support(void)
116 noioapicreroute = -1;
118 skip_ioapic_setup = 1;
121 static int __init parse_noapic(char *str)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic);
129 struct irq_pin_list {
131 struct irq_pin_list *next;
134 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
136 struct irq_pin_list *pin;
138 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
143 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
144 #ifdef CONFIG_SPARSE_IRQ
145 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
147 static struct irq_cfg irq_cfgx[NR_IRQS];
150 int __init arch_early_irq_init(void)
153 struct irq_desc *desc;
158 if (!legacy_pic->nr_legacy_irqs) {
164 count = ARRAY_SIZE(irq_cfgx);
165 node = cpu_to_node(0);
167 for (i = 0; i < count; i++) {
168 desc = irq_to_desc(i);
169 desc->chip_data = &cfg[i];
170 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
171 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
173 * For legacy IRQ's, start with assigning irq0 to irq15 to
174 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
176 if (i < legacy_pic->nr_legacy_irqs) {
177 cfg[i].vector = IRQ0_VECTOR + i;
178 cpumask_set_cpu(0, cfg[i].domain);
185 #ifdef CONFIG_SPARSE_IRQ
186 struct irq_cfg *irq_cfg(unsigned int irq)
188 struct irq_cfg *cfg = NULL;
189 struct irq_desc *desc;
191 desc = irq_to_desc(irq);
193 cfg = desc->chip_data;
198 static struct irq_cfg *get_one_free_irq_cfg(int node)
202 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
204 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
207 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
209 free_cpumask_var(cfg->domain);
218 int arch_init_chip_data(struct irq_desc *desc, int node)
222 cfg = desc->chip_data;
224 desc->chip_data = get_one_free_irq_cfg(node);
225 if (!desc->chip_data) {
226 printk(KERN_ERR "can not alloc irq_cfg\n");
234 /* for move_irq_desc */
236 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
238 struct irq_pin_list *old_entry, *head, *tail, *entry;
240 cfg->irq_2_pin = NULL;
241 old_entry = old_cfg->irq_2_pin;
245 entry = get_one_free_irq_2_pin(node);
249 entry->apic = old_entry->apic;
250 entry->pin = old_entry->pin;
253 old_entry = old_entry->next;
255 entry = get_one_free_irq_2_pin(node);
263 /* still use the old one */
266 entry->apic = old_entry->apic;
267 entry->pin = old_entry->pin;
270 old_entry = old_entry->next;
274 cfg->irq_2_pin = head;
277 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
279 struct irq_pin_list *entry, *next;
281 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
284 entry = old_cfg->irq_2_pin;
291 old_cfg->irq_2_pin = NULL;
294 void arch_init_copy_chip_data(struct irq_desc *old_desc,
295 struct irq_desc *desc, int node)
298 struct irq_cfg *old_cfg;
300 cfg = get_one_free_irq_cfg(node);
305 desc->chip_data = cfg;
307 old_cfg = old_desc->chip_data;
309 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
311 init_copy_irq_2_pin(old_cfg, cfg, node);
314 static void free_irq_cfg(struct irq_cfg *old_cfg)
319 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
321 struct irq_cfg *old_cfg, *cfg;
323 old_cfg = old_desc->chip_data;
324 cfg = desc->chip_data;
330 free_irq_2_pin(old_cfg, cfg);
331 free_irq_cfg(old_cfg);
332 old_desc->chip_data = NULL;
335 /* end for move_irq_desc */
338 struct irq_cfg *irq_cfg(unsigned int irq)
340 return irq < nr_irqs ? irq_cfgx + irq : NULL;
347 unsigned int unused[3];
349 unsigned int unused2[11];
353 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
355 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
356 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
359 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
361 struct io_apic __iomem *io_apic = io_apic_base(apic);
362 writel(vector, &io_apic->eoi);
365 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 return readl(&io_apic->data);
372 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
374 struct io_apic __iomem *io_apic = io_apic_base(apic);
375 writel(reg, &io_apic->index);
376 writel(value, &io_apic->data);
380 * Re-write a value: to be used for read-modify-write
381 * cycles where the read already set up the index register.
383 * Older SiS APIC requires we rewrite the index register
385 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
387 struct io_apic __iomem *io_apic = io_apic_base(apic);
390 writel(reg, &io_apic->index);
391 writel(value, &io_apic->data);
394 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
396 struct irq_pin_list *entry;
399 raw_spin_lock_irqsave(&ioapic_lock, flags);
400 for_each_irq_pin(entry, cfg->irq_2_pin) {
405 reg = io_apic_read(entry->apic, 0x10 + pin*2);
406 /* Is the remote IRR bit set? */
407 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
408 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
412 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
418 struct { u32 w1, w2; };
419 struct IO_APIC_route_entry entry;
422 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
424 union entry_union eu;
426 raw_spin_lock_irqsave(&ioapic_lock, flags);
427 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
428 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
434 * When we write a new IO APIC routing entry, we need to write the high
435 * word first! If the mask bit in the low word is clear, we will enable
436 * the interrupt, and we need to make sure the entry is fully populated
437 * before that happens.
440 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
442 union entry_union eu = {{0, 0}};
445 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
446 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
449 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
452 raw_spin_lock_irqsave(&ioapic_lock, flags);
453 __ioapic_write_entry(apic, pin, e);
454 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
458 * When we mask an IO APIC routing entry, we need to write the low
459 * word first, in order to set the mask bit before we change the
462 static void ioapic_mask_entry(int apic, int pin)
465 union entry_union eu = { .entry.mask = 1 };
467 raw_spin_lock_irqsave(&ioapic_lock, flags);
468 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
469 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
470 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
474 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
475 * shared ISA-space IRQs, so we have to support them. We are super
476 * fast in the common case, and fast for shared ISA-space IRQs.
479 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
481 struct irq_pin_list **last, *entry;
483 /* don't allow duplicates */
484 last = &cfg->irq_2_pin;
485 for_each_irq_pin(entry, cfg->irq_2_pin) {
486 if (entry->apic == apic && entry->pin == pin)
491 entry = get_one_free_irq_2_pin(node);
493 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
504 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
506 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
507 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
511 * Reroute an IRQ to a different pin.
513 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
514 int oldapic, int oldpin,
515 int newapic, int newpin)
517 struct irq_pin_list *entry;
519 for_each_irq_pin(entry, cfg->irq_2_pin) {
520 if (entry->apic == oldapic && entry->pin == oldpin) {
521 entry->apic = newapic;
523 /* every one is different, right? */
528 /* old apic/pin didn't exist, so just add new ones */
529 add_pin_to_irq_node(cfg, node, newapic, newpin);
532 static void __io_apic_modify_irq(struct irq_pin_list *entry,
533 int mask_and, int mask_or,
534 void (*final)(struct irq_pin_list *entry))
536 unsigned int reg, pin;
539 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
542 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
547 static void io_apic_modify_irq(struct irq_cfg *cfg,
548 int mask_and, int mask_or,
549 void (*final)(struct irq_pin_list *entry))
551 struct irq_pin_list *entry;
553 for_each_irq_pin(entry, cfg->irq_2_pin)
554 __io_apic_modify_irq(entry, mask_and, mask_or, final);
557 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
559 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
560 IO_APIC_REDIR_MASKED, NULL);
563 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
565 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
566 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
569 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
571 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
574 static void io_apic_sync(struct irq_pin_list *entry)
577 * Synchronize the IO-APIC and the CPU by doing
578 * a dummy read from the IO-APIC
580 struct io_apic __iomem *io_apic;
581 io_apic = io_apic_base(entry->apic);
582 readl(&io_apic->data);
585 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
587 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
590 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
592 struct irq_cfg *cfg = desc->chip_data;
597 raw_spin_lock_irqsave(&ioapic_lock, flags);
598 __mask_IO_APIC_irq(cfg);
599 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
602 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
604 struct irq_cfg *cfg = desc->chip_data;
607 raw_spin_lock_irqsave(&ioapic_lock, flags);
608 __unmask_IO_APIC_irq(cfg);
609 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
612 static void mask_IO_APIC_irq(unsigned int irq)
614 struct irq_desc *desc = irq_to_desc(irq);
616 mask_IO_APIC_irq_desc(desc);
618 static void unmask_IO_APIC_irq(unsigned int irq)
620 struct irq_desc *desc = irq_to_desc(irq);
622 unmask_IO_APIC_irq_desc(desc);
625 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
627 struct IO_APIC_route_entry entry;
629 /* Check delivery_mode to be sure we're not clearing an SMI pin */
630 entry = ioapic_read_entry(apic, pin);
631 if (entry.delivery_mode == dest_SMI)
634 * Disable it in the IO-APIC irq-routing table:
636 ioapic_mask_entry(apic, pin);
639 static void clear_IO_APIC (void)
643 for (apic = 0; apic < nr_ioapics; apic++)
644 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
645 clear_IO_APIC_pin(apic, pin);
650 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
651 * specific CPU-side IRQs.
655 static int pirq_entries[MAX_PIRQS] = {
656 [0 ... MAX_PIRQS - 1] = -1
659 static int __init ioapic_pirq_setup(char *str)
662 int ints[MAX_PIRQS+1];
664 get_options(str, ARRAY_SIZE(ints), ints);
666 apic_printk(APIC_VERBOSE, KERN_INFO
667 "PIRQ redirection, working around broken MP-BIOS.\n");
669 if (ints[0] < MAX_PIRQS)
672 for (i = 0; i < max; i++) {
673 apic_printk(APIC_VERBOSE, KERN_DEBUG
674 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
676 * PIRQs are mapped upside down, usually.
678 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
683 __setup("pirq=", ioapic_pirq_setup);
684 #endif /* CONFIG_X86_32 */
686 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
689 struct IO_APIC_route_entry **ioapic_entries;
691 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
696 for (apic = 0; apic < nr_ioapics; apic++) {
697 ioapic_entries[apic] =
698 kzalloc(sizeof(struct IO_APIC_route_entry) *
699 nr_ioapic_registers[apic], GFP_ATOMIC);
700 if (!ioapic_entries[apic])
704 return ioapic_entries;
708 kfree(ioapic_entries[apic]);
709 kfree(ioapic_entries);
715 * Saves all the IO-APIC RTE's
717 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
724 for (apic = 0; apic < nr_ioapics; apic++) {
725 if (!ioapic_entries[apic])
728 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
729 ioapic_entries[apic][pin] =
730 ioapic_read_entry(apic, pin);
737 * Mask all IO APIC entries.
739 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
746 for (apic = 0; apic < nr_ioapics; apic++) {
747 if (!ioapic_entries[apic])
750 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
751 struct IO_APIC_route_entry entry;
753 entry = ioapic_entries[apic][pin];
756 ioapic_write_entry(apic, pin, entry);
763 * Restore IO APIC entries which was saved in ioapic_entries.
765 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
772 for (apic = 0; apic < nr_ioapics; apic++) {
773 if (!ioapic_entries[apic])
776 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
777 ioapic_write_entry(apic, pin,
778 ioapic_entries[apic][pin]);
783 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
787 for (apic = 0; apic < nr_ioapics; apic++)
788 kfree(ioapic_entries[apic]);
790 kfree(ioapic_entries);
794 * Find the IRQ entry number of a certain pin.
796 static int find_irq_entry(int apic, int pin, int type)
800 for (i = 0; i < mp_irq_entries; i++)
801 if (mp_irqs[i].irqtype == type &&
802 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
803 mp_irqs[i].dstapic == MP_APIC_ALL) &&
804 mp_irqs[i].dstirq == pin)
811 * Find the pin to which IRQ[irq] (ISA) is connected
813 static int __init find_isa_irq_pin(int irq, int type)
817 for (i = 0; i < mp_irq_entries; i++) {
818 int lbus = mp_irqs[i].srcbus;
820 if (test_bit(lbus, mp_bus_not_pci) &&
821 (mp_irqs[i].irqtype == type) &&
822 (mp_irqs[i].srcbusirq == irq))
824 return mp_irqs[i].dstirq;
829 static int __init find_isa_irq_apic(int irq, int type)
833 for (i = 0; i < mp_irq_entries; i++) {
834 int lbus = mp_irqs[i].srcbus;
836 if (test_bit(lbus, mp_bus_not_pci) &&
837 (mp_irqs[i].irqtype == type) &&
838 (mp_irqs[i].srcbusirq == irq))
841 if (i < mp_irq_entries) {
843 for(apic = 0; apic < nr_ioapics; apic++) {
844 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
852 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
854 * EISA Edge/Level control register, ELCR
856 static int EISA_ELCR(unsigned int irq)
858 if (irq < legacy_pic->nr_legacy_irqs) {
859 unsigned int port = 0x4d0 + (irq >> 3);
860 return (inb(port) >> (irq & 7)) & 1;
862 apic_printk(APIC_VERBOSE, KERN_INFO
863 "Broken MPtable reports ISA irq %d\n", irq);
869 /* ISA interrupts are always polarity zero edge triggered,
870 * when listed as conforming in the MP table. */
872 #define default_ISA_trigger(idx) (0)
873 #define default_ISA_polarity(idx) (0)
875 /* EISA interrupts are always polarity zero and can be edge or level
876 * trigger depending on the ELCR value. If an interrupt is listed as
877 * EISA conforming in the MP table, that means its trigger type must
878 * be read in from the ELCR */
880 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
881 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
883 /* PCI interrupts are always polarity one level triggered,
884 * when listed as conforming in the MP table. */
886 #define default_PCI_trigger(idx) (1)
887 #define default_PCI_polarity(idx) (1)
889 /* MCA interrupts are always polarity zero level triggered,
890 * when listed as conforming in the MP table. */
892 #define default_MCA_trigger(idx) (1)
893 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
895 static int MPBIOS_polarity(int idx)
897 int bus = mp_irqs[idx].srcbus;
901 * Determine IRQ line polarity (high active or low active):
903 switch (mp_irqs[idx].irqflag & 3)
905 case 0: /* conforms, ie. bus-type dependent polarity */
906 if (test_bit(bus, mp_bus_not_pci))
907 polarity = default_ISA_polarity(idx);
909 polarity = default_PCI_polarity(idx);
911 case 1: /* high active */
916 case 2: /* reserved */
918 printk(KERN_WARNING "broken BIOS!!\n");
922 case 3: /* low active */
927 default: /* invalid */
929 printk(KERN_WARNING "broken BIOS!!\n");
937 static int MPBIOS_trigger(int idx)
939 int bus = mp_irqs[idx].srcbus;
943 * Determine IRQ trigger mode (edge or level sensitive):
945 switch ((mp_irqs[idx].irqflag>>2) & 3)
947 case 0: /* conforms, ie. bus-type dependent */
948 if (test_bit(bus, mp_bus_not_pci))
949 trigger = default_ISA_trigger(idx);
951 trigger = default_PCI_trigger(idx);
952 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
953 switch (mp_bus_id_to_type[bus]) {
954 case MP_BUS_ISA: /* ISA pin */
956 /* set before the switch */
959 case MP_BUS_EISA: /* EISA pin */
961 trigger = default_EISA_trigger(idx);
964 case MP_BUS_PCI: /* PCI pin */
966 /* set before the switch */
969 case MP_BUS_MCA: /* MCA pin */
971 trigger = default_MCA_trigger(idx);
976 printk(KERN_WARNING "broken BIOS!!\n");
988 case 2: /* reserved */
990 printk(KERN_WARNING "broken BIOS!!\n");
999 default: /* invalid */
1001 printk(KERN_WARNING "broken BIOS!!\n");
1009 static inline int irq_polarity(int idx)
1011 return MPBIOS_polarity(idx);
1014 static inline int irq_trigger(int idx)
1016 return MPBIOS_trigger(idx);
1019 static int pin_2_irq(int idx, int apic, int pin)
1022 int bus = mp_irqs[idx].srcbus;
1025 * Debugging check, we are in big trouble if this message pops up!
1027 if (mp_irqs[idx].dstirq != pin)
1028 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1030 if (test_bit(bus, mp_bus_not_pci)) {
1031 irq = mp_irqs[idx].srcbusirq;
1033 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
1035 if (gsi >= NR_IRQS_LEGACY)
1038 irq = gsi_top + gsi;
1041 #ifdef CONFIG_X86_32
1043 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1045 if ((pin >= 16) && (pin <= 23)) {
1046 if (pirq_entries[pin-16] != -1) {
1047 if (!pirq_entries[pin-16]) {
1048 apic_printk(APIC_VERBOSE, KERN_DEBUG
1049 "disabling PIRQ%d\n", pin-16);
1051 irq = pirq_entries[pin-16];
1052 apic_printk(APIC_VERBOSE, KERN_DEBUG
1053 "using PIRQ%d -> IRQ %d\n",
1064 * Find a specific PCI IRQ entry.
1065 * Not an __init, possibly needed by modules
1067 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1068 struct io_apic_irq_attr *irq_attr)
1070 int apic, i, best_guess = -1;
1072 apic_printk(APIC_DEBUG,
1073 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1075 if (test_bit(bus, mp_bus_not_pci)) {
1076 apic_printk(APIC_VERBOSE,
1077 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1080 for (i = 0; i < mp_irq_entries; i++) {
1081 int lbus = mp_irqs[i].srcbus;
1083 for (apic = 0; apic < nr_ioapics; apic++)
1084 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1085 mp_irqs[i].dstapic == MP_APIC_ALL)
1088 if (!test_bit(lbus, mp_bus_not_pci) &&
1089 !mp_irqs[i].irqtype &&
1091 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1092 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1094 if (!(apic || IO_APIC_IRQ(irq)))
1097 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1098 set_io_apic_irq_attr(irq_attr, apic,
1105 * Use the first all-but-pin matching entry as a
1106 * best-guess fuzzy result for broken mptables.
1108 if (best_guess < 0) {
1109 set_io_apic_irq_attr(irq_attr, apic,
1119 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1121 void lock_vector_lock(void)
1123 /* Used to the online set of cpus does not change
1124 * during assign_irq_vector.
1126 raw_spin_lock(&vector_lock);
1129 void unlock_vector_lock(void)
1131 raw_spin_unlock(&vector_lock);
1135 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1138 * NOTE! The local APIC isn't very good at handling
1139 * multiple interrupts at the same interrupt level.
1140 * As the interrupt level is determined by taking the
1141 * vector number and shifting that right by 4, we
1142 * want to spread these out a bit so that they don't
1143 * all fall in the same interrupt level.
1145 * Also, we've got to be careful not to trash gate
1146 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1148 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1149 static int current_offset = VECTOR_OFFSET_START % 8;
1150 unsigned int old_vector;
1152 cpumask_var_t tmp_mask;
1154 if (cfg->move_in_progress)
1157 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1160 old_vector = cfg->vector;
1162 cpumask_and(tmp_mask, mask, cpu_online_mask);
1163 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1164 if (!cpumask_empty(tmp_mask)) {
1165 free_cpumask_var(tmp_mask);
1170 /* Only try and allocate irqs on cpus that are present */
1172 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1176 apic->vector_allocation_domain(cpu, tmp_mask);
1178 vector = current_vector;
1179 offset = current_offset;
1182 if (vector >= first_system_vector) {
1183 /* If out of vectors on large boxen, must share them. */
1184 offset = (offset + 1) % 8;
1185 vector = FIRST_EXTERNAL_VECTOR + offset;
1187 if (unlikely(current_vector == vector))
1190 if (test_bit(vector, used_vectors))
1193 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1194 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1197 current_vector = vector;
1198 current_offset = offset;
1200 cfg->move_in_progress = 1;
1201 cpumask_copy(cfg->old_domain, cfg->domain);
1203 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1204 per_cpu(vector_irq, new_cpu)[vector] = irq;
1205 cfg->vector = vector;
1206 cpumask_copy(cfg->domain, tmp_mask);
1210 free_cpumask_var(tmp_mask);
1214 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1217 unsigned long flags;
1219 raw_spin_lock_irqsave(&vector_lock, flags);
1220 err = __assign_irq_vector(irq, cfg, mask);
1221 raw_spin_unlock_irqrestore(&vector_lock, flags);
1225 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1229 BUG_ON(!cfg->vector);
1231 vector = cfg->vector;
1232 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1233 per_cpu(vector_irq, cpu)[vector] = -1;
1236 cpumask_clear(cfg->domain);
1238 if (likely(!cfg->move_in_progress))
1240 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1241 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1243 if (per_cpu(vector_irq, cpu)[vector] != irq)
1245 per_cpu(vector_irq, cpu)[vector] = -1;
1249 cfg->move_in_progress = 0;
1252 void __setup_vector_irq(int cpu)
1254 /* Initialize vector_irq on a new cpu */
1256 struct irq_cfg *cfg;
1257 struct irq_desc *desc;
1260 * vector_lock will make sure that we don't run into irq vector
1261 * assignments that might be happening on another cpu in parallel,
1262 * while we setup our initial vector to irq mappings.
1264 raw_spin_lock(&vector_lock);
1265 /* Mark the inuse vectors */
1266 for_each_irq_desc(irq, desc) {
1267 cfg = desc->chip_data;
1270 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1271 * will be part of the irq_cfg's domain.
1273 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1274 cpumask_set_cpu(cpu, cfg->domain);
1276 if (!cpumask_test_cpu(cpu, cfg->domain))
1278 vector = cfg->vector;
1279 per_cpu(vector_irq, cpu)[vector] = irq;
1281 /* Mark the free vectors */
1282 for (vector = 0; vector < NR_VECTORS; ++vector) {
1283 irq = per_cpu(vector_irq, cpu)[vector];
1288 if (!cpumask_test_cpu(cpu, cfg->domain))
1289 per_cpu(vector_irq, cpu)[vector] = -1;
1291 raw_spin_unlock(&vector_lock);
1294 static struct irq_chip ioapic_chip;
1295 static struct irq_chip ir_ioapic_chip;
1297 #define IOAPIC_AUTO -1
1298 #define IOAPIC_EDGE 0
1299 #define IOAPIC_LEVEL 1
1301 #ifdef CONFIG_X86_32
1302 static inline int IO_APIC_irq_trigger(int irq)
1306 for (apic = 0; apic < nr_ioapics; apic++) {
1307 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1308 idx = find_irq_entry(apic, pin, mp_INT);
1309 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1310 return irq_trigger(idx);
1314 * nonexistent IRQs are edge default
1319 static inline int IO_APIC_irq_trigger(int irq)
1325 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1328 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1329 trigger == IOAPIC_LEVEL)
1330 desc->status |= IRQ_LEVEL;
1332 desc->status &= ~IRQ_LEVEL;
1334 if (irq_remapped(irq)) {
1335 desc->status |= IRQ_MOVE_PCNTXT;
1337 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1341 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1342 handle_edge_irq, "edge");
1346 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1347 trigger == IOAPIC_LEVEL)
1348 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1352 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1353 handle_edge_irq, "edge");
1356 int setup_ioapic_entry(int apic_id, int irq,
1357 struct IO_APIC_route_entry *entry,
1358 unsigned int destination, int trigger,
1359 int polarity, int vector, int pin)
1362 * add it to the IO-APIC irq-routing table:
1364 memset(entry,0,sizeof(*entry));
1366 if (intr_remapping_enabled) {
1367 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1369 struct IR_IO_APIC_route_entry *ir_entry =
1370 (struct IR_IO_APIC_route_entry *) entry;
1374 panic("No mapping iommu for ioapic %d\n", apic_id);
1376 index = alloc_irte(iommu, irq, 1);
1378 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1380 prepare_irte(&irte, vector, destination);
1382 /* Set source-id of interrupt request */
1383 set_ioapic_sid(&irte, apic_id);
1385 modify_irte(irq, &irte);
1387 ir_entry->index2 = (index >> 15) & 0x1;
1389 ir_entry->format = 1;
1390 ir_entry->index = (index & 0x7fff);
1392 * IO-APIC RTE will be configured with virtual vector.
1393 * irq handler will do the explicit EOI to the io-apic.
1395 ir_entry->vector = pin;
1397 entry->delivery_mode = apic->irq_delivery_mode;
1398 entry->dest_mode = apic->irq_dest_mode;
1399 entry->dest = destination;
1400 entry->vector = vector;
1403 entry->mask = 0; /* enable IRQ */
1404 entry->trigger = trigger;
1405 entry->polarity = polarity;
1407 /* Mask level triggered irqs.
1408 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1415 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1416 int trigger, int polarity)
1418 struct irq_cfg *cfg;
1419 struct IO_APIC_route_entry entry;
1422 if (!IO_APIC_IRQ(irq))
1425 cfg = desc->chip_data;
1428 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1429 * controllers like 8259. Now that IO-APIC can handle this irq, update
1432 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1433 apic->vector_allocation_domain(0, cfg->domain);
1435 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1438 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1440 apic_printk(APIC_VERBOSE,KERN_DEBUG
1441 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1442 "IRQ %d Mode:%i Active:%i)\n",
1443 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1444 irq, trigger, polarity);
1447 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1448 dest, trigger, polarity, cfg->vector, pin)) {
1449 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1450 mp_ioapics[apic_id].apicid, pin);
1451 __clear_irq_vector(irq, cfg);
1455 ioapic_register_intr(irq, desc, trigger);
1456 if (irq < legacy_pic->nr_legacy_irqs)
1457 legacy_pic->chip->mask(irq);
1459 ioapic_write_entry(apic_id, pin, entry);
1463 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1464 } mp_ioapic_routing[MAX_IO_APICS];
1466 static void __init setup_IO_APIC_irqs(void)
1468 int apic_id, pin, idx, irq;
1470 struct irq_desc *desc;
1471 struct irq_cfg *cfg;
1472 int node = cpu_to_node(0);
1474 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1476 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1477 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1478 idx = find_irq_entry(apic_id, pin, mp_INT);
1482 apic_printk(APIC_VERBOSE,
1483 KERN_DEBUG " %d-%d",
1484 mp_ioapics[apic_id].apicid, pin);
1486 apic_printk(APIC_VERBOSE, " %d-%d",
1487 mp_ioapics[apic_id].apicid, pin);
1491 apic_printk(APIC_VERBOSE,
1492 " (apicid-pin) not connected\n");
1496 irq = pin_2_irq(idx, apic_id, pin);
1498 if ((apic_id > 0) && (irq > 16))
1502 * Skip the timer IRQ if there's a quirk handler
1503 * installed and if it returns 1:
1505 if (apic->multi_timer_check &&
1506 apic->multi_timer_check(apic_id, irq))
1509 desc = irq_to_desc_alloc_node(irq, node);
1511 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1514 cfg = desc->chip_data;
1515 add_pin_to_irq_node(cfg, node, apic_id, pin);
1517 * don't mark it in pin_programmed, so later acpi could
1518 * set it correctly when irq < 16
1520 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1521 irq_trigger(idx), irq_polarity(idx));
1525 apic_printk(APIC_VERBOSE,
1526 " (apicid-pin) not connected\n");
1530 * for the gsit that is not in first ioapic
1531 * but could not use acpi_register_gsi()
1532 * like some special sci in IBM x3330
1534 void setup_IO_APIC_irq_extra(u32 gsi)
1536 int apic_id = 0, pin, idx, irq;
1537 int node = cpu_to_node(0);
1538 struct irq_desc *desc;
1539 struct irq_cfg *cfg;
1542 * Convert 'gsi' to 'ioapic.pin'.
1544 apic_id = mp_find_ioapic(gsi);
1548 pin = mp_find_ioapic_pin(apic_id, gsi);
1549 idx = find_irq_entry(apic_id, pin, mp_INT);
1553 irq = pin_2_irq(idx, apic_id, pin);
1554 #ifdef CONFIG_SPARSE_IRQ
1555 desc = irq_to_desc(irq);
1559 desc = irq_to_desc_alloc_node(irq, node);
1561 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1565 cfg = desc->chip_data;
1566 add_pin_to_irq_node(cfg, node, apic_id, pin);
1568 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1569 pr_debug("Pin %d-%d already programmed\n",
1570 mp_ioapics[apic_id].apicid, pin);
1573 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1575 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1576 irq_trigger(idx), irq_polarity(idx));
1580 * Set up the timer pin, possibly with the 8259A-master behind.
1582 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1585 struct IO_APIC_route_entry entry;
1587 if (intr_remapping_enabled)
1590 memset(&entry, 0, sizeof(entry));
1593 * We use logical delivery to get the timer IRQ
1596 entry.dest_mode = apic->irq_dest_mode;
1597 entry.mask = 0; /* don't mask IRQ for edge */
1598 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1599 entry.delivery_mode = apic->irq_delivery_mode;
1602 entry.vector = vector;
1605 * The timer IRQ doesn't have to know that behind the
1606 * scene we may have a 8259A-master in AEOI mode ...
1608 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1611 * Add it to the IO-APIC irq-routing table:
1613 ioapic_write_entry(apic_id, pin, entry);
1617 __apicdebuginit(void) print_IO_APIC(void)
1620 union IO_APIC_reg_00 reg_00;
1621 union IO_APIC_reg_01 reg_01;
1622 union IO_APIC_reg_02 reg_02;
1623 union IO_APIC_reg_03 reg_03;
1624 unsigned long flags;
1625 struct irq_cfg *cfg;
1626 struct irq_desc *desc;
1629 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1630 for (i = 0; i < nr_ioapics; i++)
1631 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1632 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1635 * We are a bit conservative about what we expect. We have to
1636 * know about every hardware change ASAP.
1638 printk(KERN_INFO "testing the IO APIC.......................\n");
1640 for (apic = 0; apic < nr_ioapics; apic++) {
1642 raw_spin_lock_irqsave(&ioapic_lock, flags);
1643 reg_00.raw = io_apic_read(apic, 0);
1644 reg_01.raw = io_apic_read(apic, 1);
1645 if (reg_01.bits.version >= 0x10)
1646 reg_02.raw = io_apic_read(apic, 2);
1647 if (reg_01.bits.version >= 0x20)
1648 reg_03.raw = io_apic_read(apic, 3);
1649 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1652 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1653 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1654 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1655 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1656 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1658 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1659 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1661 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1662 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1665 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1666 * but the value of reg_02 is read as the previous read register
1667 * value, so ignore it if reg_02 == reg_01.
1669 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1670 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1671 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1675 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1676 * or reg_03, but the value of reg_0[23] is read as the previous read
1677 * register value, so ignore it if reg_03 == reg_0[12].
1679 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1680 reg_03.raw != reg_01.raw) {
1681 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1682 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1685 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1687 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1688 " Stat Dmod Deli Vect:\n");
1690 for (i = 0; i <= reg_01.bits.entries; i++) {
1691 struct IO_APIC_route_entry entry;
1693 entry = ioapic_read_entry(apic, i);
1695 printk(KERN_DEBUG " %02x %03X ",
1700 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1705 entry.delivery_status,
1707 entry.delivery_mode,
1712 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1713 for_each_irq_desc(irq, desc) {
1714 struct irq_pin_list *entry;
1716 cfg = desc->chip_data;
1719 entry = cfg->irq_2_pin;
1722 printk(KERN_DEBUG "IRQ%d ", irq);
1723 for_each_irq_pin(entry, cfg->irq_2_pin)
1724 printk("-> %d:%d", entry->apic, entry->pin);
1728 printk(KERN_INFO ".................................... done.\n");
1733 __apicdebuginit(void) print_APIC_field(int base)
1739 for (i = 0; i < 8; i++)
1740 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1742 printk(KERN_CONT "\n");
1745 __apicdebuginit(void) print_local_APIC(void *dummy)
1747 unsigned int i, v, ver, maxlvt;
1750 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1751 smp_processor_id(), hard_smp_processor_id());
1752 v = apic_read(APIC_ID);
1753 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1754 v = apic_read(APIC_LVR);
1755 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1756 ver = GET_APIC_VERSION(v);
1757 maxlvt = lapic_get_maxlvt();
1759 v = apic_read(APIC_TASKPRI);
1760 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1762 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1763 if (!APIC_XAPIC(ver)) {
1764 v = apic_read(APIC_ARBPRI);
1765 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1766 v & APIC_ARBPRI_MASK);
1768 v = apic_read(APIC_PROCPRI);
1769 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1773 * Remote read supported only in the 82489DX and local APIC for
1774 * Pentium processors.
1776 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1777 v = apic_read(APIC_RRR);
1778 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1781 v = apic_read(APIC_LDR);
1782 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1783 if (!x2apic_enabled()) {
1784 v = apic_read(APIC_DFR);
1785 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1787 v = apic_read(APIC_SPIV);
1788 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1790 printk(KERN_DEBUG "... APIC ISR field:\n");
1791 print_APIC_field(APIC_ISR);
1792 printk(KERN_DEBUG "... APIC TMR field:\n");
1793 print_APIC_field(APIC_TMR);
1794 printk(KERN_DEBUG "... APIC IRR field:\n");
1795 print_APIC_field(APIC_IRR);
1797 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1798 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1799 apic_write(APIC_ESR, 0);
1801 v = apic_read(APIC_ESR);
1802 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1805 icr = apic_icr_read();
1806 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1807 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1809 v = apic_read(APIC_LVTT);
1810 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1812 if (maxlvt > 3) { /* PC is LVT#4. */
1813 v = apic_read(APIC_LVTPC);
1814 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1816 v = apic_read(APIC_LVT0);
1817 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1818 v = apic_read(APIC_LVT1);
1819 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1821 if (maxlvt > 2) { /* ERR is LVT#3. */
1822 v = apic_read(APIC_LVTERR);
1823 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1826 v = apic_read(APIC_TMICT);
1827 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1828 v = apic_read(APIC_TMCCT);
1829 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1830 v = apic_read(APIC_TDCR);
1831 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1833 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1834 v = apic_read(APIC_EFEAT);
1835 maxlvt = (v >> 16) & 0xff;
1836 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1837 v = apic_read(APIC_ECTRL);
1838 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1839 for (i = 0; i < maxlvt; i++) {
1840 v = apic_read(APIC_EILVTn(i));
1841 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1847 __apicdebuginit(void) print_local_APICs(int maxcpu)
1855 for_each_online_cpu(cpu) {
1858 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1863 __apicdebuginit(void) print_PIC(void)
1866 unsigned long flags;
1868 if (!legacy_pic->nr_legacy_irqs)
1871 printk(KERN_DEBUG "\nprinting PIC contents\n");
1873 raw_spin_lock_irqsave(&i8259A_lock, flags);
1875 v = inb(0xa1) << 8 | inb(0x21);
1876 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1878 v = inb(0xa0) << 8 | inb(0x20);
1879 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1883 v = inb(0xa0) << 8 | inb(0x20);
1887 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1889 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1891 v = inb(0x4d1) << 8 | inb(0x4d0);
1892 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1895 static int __initdata show_lapic = 1;
1896 static __init int setup_show_lapic(char *arg)
1900 if (strcmp(arg, "all") == 0) {
1901 show_lapic = CONFIG_NR_CPUS;
1903 get_option(&arg, &num);
1910 __setup("show_lapic=", setup_show_lapic);
1912 __apicdebuginit(int) print_ICs(void)
1914 if (apic_verbosity == APIC_QUIET)
1919 /* don't print out if apic is not there */
1920 if (!cpu_has_apic && !apic_from_smp_config())
1923 print_local_APICs(show_lapic);
1929 fs_initcall(print_ICs);
1932 /* Where if anywhere is the i8259 connect in external int mode */
1933 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1935 void __init enable_IO_APIC(void)
1937 int i8259_apic, i8259_pin;
1940 if (!legacy_pic->nr_legacy_irqs)
1943 for(apic = 0; apic < nr_ioapics; apic++) {
1945 /* See if any of the pins is in ExtINT mode */
1946 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1947 struct IO_APIC_route_entry entry;
1948 entry = ioapic_read_entry(apic, pin);
1950 /* If the interrupt line is enabled and in ExtInt mode
1951 * I have found the pin where the i8259 is connected.
1953 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1954 ioapic_i8259.apic = apic;
1955 ioapic_i8259.pin = pin;
1961 /* Look to see what if the MP table has reported the ExtINT */
1962 /* If we could not find the appropriate pin by looking at the ioapic
1963 * the i8259 probably is not connected the ioapic but give the
1964 * mptable a chance anyway.
1966 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1967 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1968 /* Trust the MP table if nothing is setup in the hardware */
1969 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1970 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1971 ioapic_i8259.pin = i8259_pin;
1972 ioapic_i8259.apic = i8259_apic;
1974 /* Complain if the MP table and the hardware disagree */
1975 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1976 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1978 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1982 * Do not trust the IO-APIC being empty at bootup
1988 * Not an __init, needed by the reboot code
1990 void disable_IO_APIC(void)
1993 * Clear the IO-APIC before rebooting:
1997 if (!legacy_pic->nr_legacy_irqs)
2001 * If the i8259 is routed through an IOAPIC
2002 * Put that IOAPIC in virtual wire mode
2003 * so legacy interrupts can be delivered.
2005 * With interrupt-remapping, for now we will use virtual wire A mode,
2006 * as virtual wire B is little complex (need to configure both
2007 * IOAPIC RTE aswell as interrupt-remapping table entry).
2008 * As this gets called during crash dump, keep this simple for now.
2010 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2011 struct IO_APIC_route_entry entry;
2013 memset(&entry, 0, sizeof(entry));
2014 entry.mask = 0; /* Enabled */
2015 entry.trigger = 0; /* Edge */
2017 entry.polarity = 0; /* High */
2018 entry.delivery_status = 0;
2019 entry.dest_mode = 0; /* Physical */
2020 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2022 entry.dest = read_apic_id();
2025 * Add it to the IO-APIC irq-routing table:
2027 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2031 * Use virtual wire A mode when interrupt remapping is enabled.
2033 if (cpu_has_apic || apic_from_smp_config())
2034 disconnect_bsp_APIC(!intr_remapping_enabled &&
2035 ioapic_i8259.pin != -1);
2038 #ifdef CONFIG_X86_32
2040 * function to set the IO-APIC physical IDs based on the
2041 * values stored in the MPC table.
2043 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2046 void __init setup_ioapic_ids_from_mpc(void)
2048 union IO_APIC_reg_00 reg_00;
2049 physid_mask_t phys_id_present_map;
2052 unsigned char old_id;
2053 unsigned long flags;
2058 * Don't check I/O APIC IDs for xAPIC systems. They have
2059 * no meaning without the serial APIC bus.
2061 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2062 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2065 * This is broken; anything with a real cpu count has to
2066 * circumvent this idiocy regardless.
2068 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2071 * Set the IOAPIC ID to the value stored in the MPC table.
2073 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2075 /* Read the register 0 value */
2076 raw_spin_lock_irqsave(&ioapic_lock, flags);
2077 reg_00.raw = io_apic_read(apic_id, 0);
2078 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2080 old_id = mp_ioapics[apic_id].apicid;
2082 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2083 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2084 apic_id, mp_ioapics[apic_id].apicid);
2085 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2087 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2091 * Sanity check, is the ID really free? Every APIC in a
2092 * system must have a unique ID or we get lots of nice
2093 * 'stuck on smp_invalidate_needed IPI wait' messages.
2095 if (apic->check_apicid_used(&phys_id_present_map,
2096 mp_ioapics[apic_id].apicid)) {
2097 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2098 apic_id, mp_ioapics[apic_id].apicid);
2099 for (i = 0; i < get_physical_broadcast(); i++)
2100 if (!physid_isset(i, phys_id_present_map))
2102 if (i >= get_physical_broadcast())
2103 panic("Max APIC ID exceeded!\n");
2104 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2106 physid_set(i, phys_id_present_map);
2107 mp_ioapics[apic_id].apicid = i;
2110 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2111 apic_printk(APIC_VERBOSE, "Setting %d in the "
2112 "phys_id_present_map\n",
2113 mp_ioapics[apic_id].apicid);
2114 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2119 * We need to adjust the IRQ routing table
2120 * if the ID changed.
2122 if (old_id != mp_ioapics[apic_id].apicid)
2123 for (i = 0; i < mp_irq_entries; i++)
2124 if (mp_irqs[i].dstapic == old_id)
2126 = mp_ioapics[apic_id].apicid;
2129 * Read the right value from the MPC table and
2130 * write it into the ID register.
2132 apic_printk(APIC_VERBOSE, KERN_INFO
2133 "...changing IO-APIC physical APIC ID to %d ...",
2134 mp_ioapics[apic_id].apicid);
2136 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2137 raw_spin_lock_irqsave(&ioapic_lock, flags);
2138 io_apic_write(apic_id, 0, reg_00.raw);
2139 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2144 raw_spin_lock_irqsave(&ioapic_lock, flags);
2145 reg_00.raw = io_apic_read(apic_id, 0);
2146 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2147 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2148 printk("could not set ID!\n");
2150 apic_printk(APIC_VERBOSE, " ok.\n");
2155 int no_timer_check __initdata;
2157 static int __init notimercheck(char *s)
2162 __setup("no_timer_check", notimercheck);
2165 * There is a nasty bug in some older SMP boards, their mptable lies
2166 * about the timer IRQ. We do the following to work around the situation:
2168 * - timer IRQ defaults to IO-APIC IRQ
2169 * - if this function detects that timer IRQs are defunct, then we fall
2170 * back to ISA timer IRQs
2172 static int __init timer_irq_works(void)
2174 unsigned long t1 = jiffies;
2175 unsigned long flags;
2180 local_save_flags(flags);
2182 /* Let ten ticks pass... */
2183 mdelay((10 * 1000) / HZ);
2184 local_irq_restore(flags);
2187 * Expect a few ticks at least, to be sure some possible
2188 * glue logic does not lock up after one or two first
2189 * ticks in a non-ExtINT mode. Also the local APIC
2190 * might have cached one ExtINT interrupt. Finally, at
2191 * least one tick may be lost due to delays.
2195 if (time_after(jiffies, t1 + 4))
2201 * In the SMP+IOAPIC case it might happen that there are an unspecified
2202 * number of pending IRQ events unhandled. These cases are very rare,
2203 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2204 * better to do it this way as thus we do not have to be aware of
2205 * 'pending' interrupts in the IRQ path, except at this point.
2208 * Edge triggered needs to resend any interrupt
2209 * that was delayed but this is now handled in the device
2214 * Starting up a edge-triggered IO-APIC interrupt is
2215 * nasty - we need to make sure that we get the edge.
2216 * If it is already asserted for some reason, we need
2217 * return 1 to indicate that is was pending.
2219 * This is not complete - we should be able to fake
2220 * an edge even if it isn't on the 8259A...
2223 static unsigned int startup_ioapic_irq(unsigned int irq)
2225 int was_pending = 0;
2226 unsigned long flags;
2227 struct irq_cfg *cfg;
2229 raw_spin_lock_irqsave(&ioapic_lock, flags);
2230 if (irq < legacy_pic->nr_legacy_irqs) {
2231 legacy_pic->chip->mask(irq);
2232 if (legacy_pic->irq_pending(irq))
2236 __unmask_IO_APIC_irq(cfg);
2237 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2242 static int ioapic_retrigger_irq(unsigned int irq)
2245 struct irq_cfg *cfg = irq_cfg(irq);
2246 unsigned long flags;
2248 raw_spin_lock_irqsave(&vector_lock, flags);
2249 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2250 raw_spin_unlock_irqrestore(&vector_lock, flags);
2256 * Level and edge triggered IO-APIC interrupts need different handling,
2257 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2258 * handled with the level-triggered descriptor, but that one has slightly
2259 * more overhead. Level-triggered interrupts cannot be handled with the
2260 * edge-triggered handler, without risking IRQ storms and other ugly
2265 void send_cleanup_vector(struct irq_cfg *cfg)
2267 cpumask_var_t cleanup_mask;
2269 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2271 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2272 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2274 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2275 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2276 free_cpumask_var(cleanup_mask);
2278 cfg->move_in_progress = 0;
2281 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2284 struct irq_pin_list *entry;
2285 u8 vector = cfg->vector;
2287 for_each_irq_pin(entry, cfg->irq_2_pin) {
2293 * With interrupt-remapping, destination information comes
2294 * from interrupt-remapping table entry.
2296 if (!irq_remapped(irq))
2297 io_apic_write(apic, 0x11 + pin*2, dest);
2298 reg = io_apic_read(apic, 0x10 + pin*2);
2299 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2301 io_apic_modify(apic, 0x10 + pin*2, reg);
2306 * Either sets desc->affinity to a valid value, and returns
2307 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2308 * leaves desc->affinity untouched.
2311 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2312 unsigned int *dest_id)
2314 struct irq_cfg *cfg;
2317 if (!cpumask_intersects(mask, cpu_online_mask))
2321 cfg = desc->chip_data;
2322 if (assign_irq_vector(irq, cfg, mask))
2325 cpumask_copy(desc->affinity, mask);
2327 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2332 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2334 struct irq_cfg *cfg;
2335 unsigned long flags;
2341 cfg = desc->chip_data;
2343 raw_spin_lock_irqsave(&ioapic_lock, flags);
2344 ret = set_desc_affinity(desc, mask, &dest);
2346 /* Only the high 8 bits are valid. */
2347 dest = SET_APIC_LOGICAL_ID(dest);
2348 __target_IO_APIC_irq(irq, dest, cfg);
2350 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2356 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2358 struct irq_desc *desc;
2360 desc = irq_to_desc(irq);
2362 return set_ioapic_affinity_irq_desc(desc, mask);
2365 #ifdef CONFIG_INTR_REMAP
2368 * Migrate the IO-APIC irq in the presence of intr-remapping.
2370 * For both level and edge triggered, irq migration is a simple atomic
2371 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2373 * For level triggered, we eliminate the io-apic RTE modification (with the
2374 * updated vector information), by using a virtual vector (io-apic pin number).
2375 * Real vector that is used for interrupting cpu will be coming from
2376 * the interrupt-remapping table entry.
2379 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2381 struct irq_cfg *cfg;
2387 if (!cpumask_intersects(mask, cpu_online_mask))
2391 if (get_irte(irq, &irte))
2394 cfg = desc->chip_data;
2395 if (assign_irq_vector(irq, cfg, mask))
2398 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2400 irte.vector = cfg->vector;
2401 irte.dest_id = IRTE_DEST(dest);
2404 * Modified the IRTE and flushes the Interrupt entry cache.
2406 modify_irte(irq, &irte);
2408 if (cfg->move_in_progress)
2409 send_cleanup_vector(cfg);
2411 cpumask_copy(desc->affinity, mask);
2417 * Migrates the IRQ destination in the process context.
2419 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2420 const struct cpumask *mask)
2422 return migrate_ioapic_irq_desc(desc, mask);
2424 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2425 const struct cpumask *mask)
2427 struct irq_desc *desc = irq_to_desc(irq);
2429 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2432 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2433 const struct cpumask *mask)
2439 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2441 unsigned vector, me;
2447 me = smp_processor_id();
2448 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2451 struct irq_desc *desc;
2452 struct irq_cfg *cfg;
2453 irq = __get_cpu_var(vector_irq)[vector];
2458 desc = irq_to_desc(irq);
2463 raw_spin_lock(&desc->lock);
2466 * Check if the irq migration is in progress. If so, we
2467 * haven't received the cleanup request yet for this irq.
2469 if (cfg->move_in_progress)
2472 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2475 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2477 * Check if the vector that needs to be cleanedup is
2478 * registered at the cpu's IRR. If so, then this is not
2479 * the best time to clean it up. Lets clean it up in the
2480 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2483 if (irr & (1 << (vector % 32))) {
2484 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2487 __get_cpu_var(vector_irq)[vector] = -1;
2489 raw_spin_unlock(&desc->lock);
2495 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2497 struct irq_desc *desc = *descp;
2498 struct irq_cfg *cfg = desc->chip_data;
2501 if (likely(!cfg->move_in_progress))
2504 me = smp_processor_id();
2506 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2507 send_cleanup_vector(cfg);
2510 static void irq_complete_move(struct irq_desc **descp)
2512 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2515 void irq_force_complete_move(int irq)
2517 struct irq_desc *desc = irq_to_desc(irq);
2518 struct irq_cfg *cfg = desc->chip_data;
2523 __irq_complete_move(&desc, cfg->vector);
2526 static inline void irq_complete_move(struct irq_desc **descp) {}
2529 static void ack_apic_edge(unsigned int irq)
2531 struct irq_desc *desc = irq_to_desc(irq);
2533 irq_complete_move(&desc);
2534 move_native_irq(irq);
2538 atomic_t irq_mis_count;
2541 * IO-APIC versions below 0x20 don't support EOI register.
2542 * For the record, here is the information about various versions:
2544 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2545 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2548 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2549 * version as 0x2. This is an error with documentation and these ICH chips
2550 * use io-apic's of version 0x20.
2552 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2553 * Otherwise, we simulate the EOI message manually by changing the trigger
2554 * mode to edge and then back to level, with RTE being masked during this.
2556 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2558 struct irq_pin_list *entry;
2560 for_each_irq_pin(entry, cfg->irq_2_pin) {
2561 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2563 * Intr-remapping uses pin number as the virtual vector
2564 * in the RTE. Actual vector is programmed in
2565 * intr-remapping table entry. Hence for the io-apic
2566 * EOI we use the pin number.
2568 if (irq_remapped(irq))
2569 io_apic_eoi(entry->apic, entry->pin);
2571 io_apic_eoi(entry->apic, cfg->vector);
2573 __mask_and_edge_IO_APIC_irq(entry);
2574 __unmask_and_level_IO_APIC_irq(entry);
2579 static void eoi_ioapic_irq(struct irq_desc *desc)
2581 struct irq_cfg *cfg;
2582 unsigned long flags;
2586 cfg = desc->chip_data;
2588 raw_spin_lock_irqsave(&ioapic_lock, flags);
2589 __eoi_ioapic_irq(irq, cfg);
2590 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2593 static void ack_apic_level(unsigned int irq)
2595 struct irq_desc *desc = irq_to_desc(irq);
2598 struct irq_cfg *cfg;
2599 int do_unmask_irq = 0;
2601 irq_complete_move(&desc);
2602 #ifdef CONFIG_GENERIC_PENDING_IRQ
2603 /* If we are moving the irq we need to mask it */
2604 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2606 mask_IO_APIC_irq_desc(desc);
2611 * It appears there is an erratum which affects at least version 0x11
2612 * of I/O APIC (that's the 82093AA and cores integrated into various
2613 * chipsets). Under certain conditions a level-triggered interrupt is
2614 * erroneously delivered as edge-triggered one but the respective IRR
2615 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2616 * message but it will never arrive and further interrupts are blocked
2617 * from the source. The exact reason is so far unknown, but the
2618 * phenomenon was observed when two consecutive interrupt requests
2619 * from a given source get delivered to the same CPU and the source is
2620 * temporarily disabled in between.
2622 * A workaround is to simulate an EOI message manually. We achieve it
2623 * by setting the trigger mode to edge and then to level when the edge
2624 * trigger mode gets detected in the TMR of a local APIC for a
2625 * level-triggered interrupt. We mask the source for the time of the
2626 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2627 * The idea is from Manfred Spraul. --macro
2629 * Also in the case when cpu goes offline, fixup_irqs() will forward
2630 * any unhandled interrupt on the offlined cpu to the new cpu
2631 * destination that is handling the corresponding interrupt. This
2632 * interrupt forwarding is done via IPI's. Hence, in this case also
2633 * level-triggered io-apic interrupt will be seen as an edge
2634 * interrupt in the IRR. And we can't rely on the cpu's EOI
2635 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2636 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2637 * supporting EOI register, we do an explicit EOI to clear the
2638 * remote IRR and on IO-APIC's which don't have an EOI register,
2639 * we use the above logic (mask+edge followed by unmask+level) from
2640 * Manfred Spraul to clear the remote IRR.
2642 cfg = desc->chip_data;
2644 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2647 * We must acknowledge the irq before we move it or the acknowledge will
2648 * not propagate properly.
2653 * Tail end of clearing remote IRR bit (either by delivering the EOI
2654 * message via io-apic EOI register write or simulating it using
2655 * mask+edge followed by unnask+level logic) manually when the
2656 * level triggered interrupt is seen as the edge triggered interrupt
2659 if (!(v & (1 << (i & 0x1f)))) {
2660 atomic_inc(&irq_mis_count);
2662 eoi_ioapic_irq(desc);
2665 /* Now we can move and renable the irq */
2666 if (unlikely(do_unmask_irq)) {
2667 /* Only migrate the irq if the ack has been received.
2669 * On rare occasions the broadcast level triggered ack gets
2670 * delayed going to ioapics, and if we reprogram the
2671 * vector while Remote IRR is still set the irq will never
2674 * To prevent this scenario we read the Remote IRR bit
2675 * of the ioapic. This has two effects.
2676 * - On any sane system the read of the ioapic will
2677 * flush writes (and acks) going to the ioapic from
2679 * - We get to see if the ACK has actually been delivered.
2681 * Based on failed experiments of reprogramming the
2682 * ioapic entry from outside of irq context starting
2683 * with masking the ioapic entry and then polling until
2684 * Remote IRR was clear before reprogramming the
2685 * ioapic I don't trust the Remote IRR bit to be
2686 * completey accurate.
2688 * However there appears to be no other way to plug
2689 * this race, so if the Remote IRR bit is not
2690 * accurate and is causing problems then it is a hardware bug
2691 * and you can go talk to the chipset vendor about it.
2693 cfg = desc->chip_data;
2694 if (!io_apic_level_ack_pending(cfg))
2695 move_masked_irq(irq);
2696 unmask_IO_APIC_irq_desc(desc);
2700 #ifdef CONFIG_INTR_REMAP
2701 static void ir_ack_apic_edge(unsigned int irq)
2706 static void ir_ack_apic_level(unsigned int irq)
2708 struct irq_desc *desc = irq_to_desc(irq);
2711 eoi_ioapic_irq(desc);
2713 #endif /* CONFIG_INTR_REMAP */
2715 static struct irq_chip ioapic_chip __read_mostly = {
2717 .startup = startup_ioapic_irq,
2718 .mask = mask_IO_APIC_irq,
2719 .unmask = unmask_IO_APIC_irq,
2720 .ack = ack_apic_edge,
2721 .eoi = ack_apic_level,
2723 .set_affinity = set_ioapic_affinity_irq,
2725 .retrigger = ioapic_retrigger_irq,
2728 static struct irq_chip ir_ioapic_chip __read_mostly = {
2729 .name = "IR-IO-APIC",
2730 .startup = startup_ioapic_irq,
2731 .mask = mask_IO_APIC_irq,
2732 .unmask = unmask_IO_APIC_irq,
2733 #ifdef CONFIG_INTR_REMAP
2734 .ack = ir_ack_apic_edge,
2735 .eoi = ir_ack_apic_level,
2737 .set_affinity = set_ir_ioapic_affinity_irq,
2740 .retrigger = ioapic_retrigger_irq,
2743 static inline void init_IO_APIC_traps(void)
2746 struct irq_desc *desc;
2747 struct irq_cfg *cfg;
2750 * NOTE! The local APIC isn't very good at handling
2751 * multiple interrupts at the same interrupt level.
2752 * As the interrupt level is determined by taking the
2753 * vector number and shifting that right by 4, we
2754 * want to spread these out a bit so that they don't
2755 * all fall in the same interrupt level.
2757 * Also, we've got to be careful not to trash gate
2758 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2760 for_each_irq_desc(irq, desc) {
2761 cfg = desc->chip_data;
2762 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2764 * Hmm.. We don't have an entry for this,
2765 * so default to an old-fashioned 8259
2766 * interrupt if we can..
2768 if (irq < legacy_pic->nr_legacy_irqs)
2769 legacy_pic->make_irq(irq);
2771 /* Strange. Oh, well.. */
2772 desc->chip = &no_irq_chip;
2778 * The local APIC irq-chip implementation:
2781 static void mask_lapic_irq(unsigned int irq)
2785 v = apic_read(APIC_LVT0);
2786 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2789 static void unmask_lapic_irq(unsigned int irq)
2793 v = apic_read(APIC_LVT0);
2794 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2797 static void ack_lapic_irq(unsigned int irq)
2802 static struct irq_chip lapic_chip __read_mostly = {
2803 .name = "local-APIC",
2804 .mask = mask_lapic_irq,
2805 .unmask = unmask_lapic_irq,
2806 .ack = ack_lapic_irq,
2809 static void lapic_register_intr(int irq, struct irq_desc *desc)
2811 desc->status &= ~IRQ_LEVEL;
2812 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2816 static void __init setup_nmi(void)
2819 * Dirty trick to enable the NMI watchdog ...
2820 * We put the 8259A master into AEOI mode and
2821 * unmask on all local APICs LVT0 as NMI.
2823 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2824 * is from Maciej W. Rozycki - so we do not have to EOI from
2825 * the NMI handler or the timer interrupt.
2827 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2829 enable_NMI_through_LVT0();
2831 apic_printk(APIC_VERBOSE, " done.\n");
2835 * This looks a bit hackish but it's about the only one way of sending
2836 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2837 * not support the ExtINT mode, unfortunately. We need to send these
2838 * cycles as some i82489DX-based boards have glue logic that keeps the
2839 * 8259A interrupt line asserted until INTA. --macro
2841 static inline void __init unlock_ExtINT_logic(void)
2844 struct IO_APIC_route_entry entry0, entry1;
2845 unsigned char save_control, save_freq_select;
2847 pin = find_isa_irq_pin(8, mp_INT);
2852 apic = find_isa_irq_apic(8, mp_INT);
2858 entry0 = ioapic_read_entry(apic, pin);
2859 clear_IO_APIC_pin(apic, pin);
2861 memset(&entry1, 0, sizeof(entry1));
2863 entry1.dest_mode = 0; /* physical delivery */
2864 entry1.mask = 0; /* unmask IRQ now */
2865 entry1.dest = hard_smp_processor_id();
2866 entry1.delivery_mode = dest_ExtINT;
2867 entry1.polarity = entry0.polarity;
2871 ioapic_write_entry(apic, pin, entry1);
2873 save_control = CMOS_READ(RTC_CONTROL);
2874 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2875 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2877 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2882 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2886 CMOS_WRITE(save_control, RTC_CONTROL);
2887 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2888 clear_IO_APIC_pin(apic, pin);
2890 ioapic_write_entry(apic, pin, entry0);
2893 static int disable_timer_pin_1 __initdata;
2894 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2895 static int __init disable_timer_pin_setup(char *arg)
2897 disable_timer_pin_1 = 1;
2900 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2902 int timer_through_8259 __initdata;
2905 * This code may look a bit paranoid, but it's supposed to cooperate with
2906 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2907 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2908 * fanatically on his truly buggy board.
2910 * FIXME: really need to revamp this for all platforms.
2912 static inline void __init check_timer(void)
2914 struct irq_desc *desc = irq_to_desc(0);
2915 struct irq_cfg *cfg = desc->chip_data;
2916 int node = cpu_to_node(0);
2917 int apic1, pin1, apic2, pin2;
2918 unsigned long flags;
2921 local_irq_save(flags);
2924 * get/set the timer IRQ vector:
2926 legacy_pic->chip->mask(0);
2927 assign_irq_vector(0, cfg, apic->target_cpus());
2930 * As IRQ0 is to be enabled in the 8259A, the virtual
2931 * wire has to be disabled in the local APIC. Also
2932 * timer interrupts need to be acknowledged manually in
2933 * the 8259A for the i82489DX when using the NMI
2934 * watchdog as that APIC treats NMIs as level-triggered.
2935 * The AEOI mode will finish them in the 8259A
2938 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2939 legacy_pic->init(1);
2940 #ifdef CONFIG_X86_32
2944 ver = apic_read(APIC_LVR);
2945 ver = GET_APIC_VERSION(ver);
2946 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2950 pin1 = find_isa_irq_pin(0, mp_INT);
2951 apic1 = find_isa_irq_apic(0, mp_INT);
2952 pin2 = ioapic_i8259.pin;
2953 apic2 = ioapic_i8259.apic;
2955 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2956 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2957 cfg->vector, apic1, pin1, apic2, pin2);
2960 * Some BIOS writers are clueless and report the ExtINTA
2961 * I/O APIC input from the cascaded 8259A as the timer
2962 * interrupt input. So just in case, if only one pin
2963 * was found above, try it both directly and through the
2967 if (intr_remapping_enabled)
2968 panic("BIOS bug: timer not connected to IO-APIC");
2972 } else if (pin2 == -1) {
2979 * Ok, does IRQ0 through the IOAPIC work?
2982 add_pin_to_irq_node(cfg, node, apic1, pin1);
2983 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2985 /* for edge trigger, setup_IO_APIC_irq already
2986 * leave it unmasked.
2987 * so only need to unmask if it is level-trigger
2988 * do we really have level trigger timer?
2991 idx = find_irq_entry(apic1, pin1, mp_INT);
2992 if (idx != -1 && irq_trigger(idx))
2993 unmask_IO_APIC_irq_desc(desc);
2995 if (timer_irq_works()) {
2996 if (nmi_watchdog == NMI_IO_APIC) {
2998 legacy_pic->chip->unmask(0);
3000 if (disable_timer_pin_1 > 0)
3001 clear_IO_APIC_pin(0, pin1);
3004 if (intr_remapping_enabled)
3005 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3006 local_irq_disable();
3007 clear_IO_APIC_pin(apic1, pin1);
3009 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3010 "8254 timer not connected to IO-APIC\n");
3012 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3013 "(IRQ0) through the 8259A ...\n");
3014 apic_printk(APIC_QUIET, KERN_INFO
3015 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3017 * legacy devices should be connected to IO APIC #0
3019 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3020 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3021 legacy_pic->chip->unmask(0);
3022 if (timer_irq_works()) {
3023 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3024 timer_through_8259 = 1;
3025 if (nmi_watchdog == NMI_IO_APIC) {
3026 legacy_pic->chip->mask(0);
3028 legacy_pic->chip->unmask(0);
3033 * Cleanup, just in case ...
3035 local_irq_disable();
3036 legacy_pic->chip->mask(0);
3037 clear_IO_APIC_pin(apic2, pin2);
3038 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3041 if (nmi_watchdog == NMI_IO_APIC) {
3042 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3043 "through the IO-APIC - disabling NMI Watchdog!\n");
3044 nmi_watchdog = NMI_NONE;
3046 #ifdef CONFIG_X86_32
3050 apic_printk(APIC_QUIET, KERN_INFO
3051 "...trying to set up timer as Virtual Wire IRQ...\n");
3053 lapic_register_intr(0, desc);
3054 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3055 legacy_pic->chip->unmask(0);
3057 if (timer_irq_works()) {
3058 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3061 local_irq_disable();
3062 legacy_pic->chip->mask(0);
3063 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3064 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3066 apic_printk(APIC_QUIET, KERN_INFO
3067 "...trying to set up timer as ExtINT IRQ...\n");
3069 legacy_pic->init(0);
3070 legacy_pic->make_irq(0);
3071 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3073 unlock_ExtINT_logic();
3075 if (timer_irq_works()) {
3076 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3079 local_irq_disable();
3080 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3081 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3082 "report. Then try booting with the 'noapic' option.\n");
3084 local_irq_restore(flags);
3088 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3089 * to devices. However there may be an I/O APIC pin available for
3090 * this interrupt regardless. The pin may be left unconnected, but
3091 * typically it will be reused as an ExtINT cascade interrupt for
3092 * the master 8259A. In the MPS case such a pin will normally be
3093 * reported as an ExtINT interrupt in the MP table. With ACPI
3094 * there is no provision for ExtINT interrupts, and in the absence
3095 * of an override it would be treated as an ordinary ISA I/O APIC
3096 * interrupt, that is edge-triggered and unmasked by default. We
3097 * used to do this, but it caused problems on some systems because
3098 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3099 * the same ExtINT cascade interrupt to drive the local APIC of the
3100 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3101 * the I/O APIC in all cases now. No actual device should request
3102 * it anyway. --macro
3104 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3106 void __init setup_IO_APIC(void)
3110 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3112 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3114 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3116 * Set up IO-APIC IRQ routing.
3118 x86_init.mpparse.setup_ioapic_ids();
3121 setup_IO_APIC_irqs();
3122 init_IO_APIC_traps();
3123 if (legacy_pic->nr_legacy_irqs)
3128 * Called after all the initialization is done. If we didnt find any
3129 * APIC bugs then we can allow the modify fast path
3132 static int __init io_apic_bug_finalize(void)
3134 if (sis_apic_bug == -1)
3139 late_initcall(io_apic_bug_finalize);
3141 struct sysfs_ioapic_data {
3142 struct sys_device dev;
3143 struct IO_APIC_route_entry entry[0];
3145 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3147 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3149 struct IO_APIC_route_entry *entry;
3150 struct sysfs_ioapic_data *data;
3153 data = container_of(dev, struct sysfs_ioapic_data, dev);
3154 entry = data->entry;
3155 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3156 *entry = ioapic_read_entry(dev->id, i);
3161 static int ioapic_resume(struct sys_device *dev)
3163 struct IO_APIC_route_entry *entry;
3164 struct sysfs_ioapic_data *data;
3165 unsigned long flags;
3166 union IO_APIC_reg_00 reg_00;
3169 data = container_of(dev, struct sysfs_ioapic_data, dev);
3170 entry = data->entry;
3172 raw_spin_lock_irqsave(&ioapic_lock, flags);
3173 reg_00.raw = io_apic_read(dev->id, 0);
3174 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3175 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3176 io_apic_write(dev->id, 0, reg_00.raw);
3178 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3179 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3180 ioapic_write_entry(dev->id, i, entry[i]);
3185 static struct sysdev_class ioapic_sysdev_class = {
3187 .suspend = ioapic_suspend,
3188 .resume = ioapic_resume,
3191 static int __init ioapic_init_sysfs(void)
3193 struct sys_device * dev;
3196 error = sysdev_class_register(&ioapic_sysdev_class);
3200 for (i = 0; i < nr_ioapics; i++ ) {
3201 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3202 * sizeof(struct IO_APIC_route_entry);
3203 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3204 if (!mp_ioapic_data[i]) {
3205 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3208 dev = &mp_ioapic_data[i]->dev;
3210 dev->cls = &ioapic_sysdev_class;
3211 error = sysdev_register(dev);
3213 kfree(mp_ioapic_data[i]);
3214 mp_ioapic_data[i] = NULL;
3215 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3223 device_initcall(ioapic_init_sysfs);
3226 * Dynamic irq allocate and deallocation
3228 unsigned int create_irq_nr(unsigned int irq_want, int node)
3230 /* Allocate an unused irq */
3233 unsigned long flags;
3234 struct irq_cfg *cfg_new = NULL;
3235 struct irq_desc *desc_new = NULL;
3238 if (irq_want < nr_irqs_gsi)
3239 irq_want = nr_irqs_gsi;
3241 raw_spin_lock_irqsave(&vector_lock, flags);
3242 for (new = irq_want; new < nr_irqs; new++) {
3243 desc_new = irq_to_desc_alloc_node(new, node);
3245 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3248 cfg_new = desc_new->chip_data;
3250 if (cfg_new->vector != 0)
3253 desc_new = move_irq_desc(desc_new, node);
3254 cfg_new = desc_new->chip_data;
3256 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3260 raw_spin_unlock_irqrestore(&vector_lock, flags);
3263 dynamic_irq_init_keep_chip_data(irq);
3268 int create_irq(void)
3270 int node = cpu_to_node(0);
3271 unsigned int irq_want;
3274 irq_want = nr_irqs_gsi;
3275 irq = create_irq_nr(irq_want, node);
3283 void destroy_irq(unsigned int irq)
3285 unsigned long flags;
3287 dynamic_irq_cleanup_keep_chip_data(irq);
3290 raw_spin_lock_irqsave(&vector_lock, flags);
3291 __clear_irq_vector(irq, get_irq_chip_data(irq));
3292 raw_spin_unlock_irqrestore(&vector_lock, flags);
3296 * MSI message composition
3298 #ifdef CONFIG_PCI_MSI
3299 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3300 struct msi_msg *msg, u8 hpet_id)
3302 struct irq_cfg *cfg;
3310 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3314 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3316 if (irq_remapped(irq)) {
3321 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3322 BUG_ON(ir_index == -1);
3324 prepare_irte(&irte, cfg->vector, dest);
3326 /* Set source-id of interrupt request */
3328 set_msi_sid(&irte, pdev);
3330 set_hpet_sid(&irte, hpet_id);
3332 modify_irte(irq, &irte);
3334 msg->address_hi = MSI_ADDR_BASE_HI;
3335 msg->data = sub_handle;
3336 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3338 MSI_ADDR_IR_INDEX1(ir_index) |
3339 MSI_ADDR_IR_INDEX2(ir_index);
3341 if (x2apic_enabled())
3342 msg->address_hi = MSI_ADDR_BASE_HI |
3343 MSI_ADDR_EXT_DEST_ID(dest);
3345 msg->address_hi = MSI_ADDR_BASE_HI;
3349 ((apic->irq_dest_mode == 0) ?
3350 MSI_ADDR_DEST_MODE_PHYSICAL:
3351 MSI_ADDR_DEST_MODE_LOGICAL) |
3352 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3353 MSI_ADDR_REDIRECTION_CPU:
3354 MSI_ADDR_REDIRECTION_LOWPRI) |
3355 MSI_ADDR_DEST_ID(dest);
3358 MSI_DATA_TRIGGER_EDGE |
3359 MSI_DATA_LEVEL_ASSERT |
3360 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3361 MSI_DATA_DELIVERY_FIXED:
3362 MSI_DATA_DELIVERY_LOWPRI) |
3363 MSI_DATA_VECTOR(cfg->vector);
3369 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3371 struct irq_desc *desc = irq_to_desc(irq);
3372 struct irq_cfg *cfg;
3376 if (set_desc_affinity(desc, mask, &dest))
3379 cfg = desc->chip_data;
3381 get_cached_msi_msg_desc(desc, &msg);
3383 msg.data &= ~MSI_DATA_VECTOR_MASK;
3384 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3385 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3386 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3388 write_msi_msg_desc(desc, &msg);
3392 #ifdef CONFIG_INTR_REMAP
3394 * Migrate the MSI irq to another cpumask. This migration is
3395 * done in the process context using interrupt-remapping hardware.
3398 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3400 struct irq_desc *desc = irq_to_desc(irq);
3401 struct irq_cfg *cfg = desc->chip_data;
3405 if (get_irte(irq, &irte))
3408 if (set_desc_affinity(desc, mask, &dest))
3411 irte.vector = cfg->vector;
3412 irte.dest_id = IRTE_DEST(dest);
3415 * atomically update the IRTE with the new destination and vector.
3417 modify_irte(irq, &irte);
3420 * After this point, all the interrupts will start arriving
3421 * at the new destination. So, time to cleanup the previous
3422 * vector allocation.
3424 if (cfg->move_in_progress)
3425 send_cleanup_vector(cfg);
3431 #endif /* CONFIG_SMP */
3434 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3435 * which implement the MSI or MSI-X Capability Structure.
3437 static struct irq_chip msi_chip = {
3439 .unmask = unmask_msi_irq,
3440 .mask = mask_msi_irq,
3441 .ack = ack_apic_edge,
3443 .set_affinity = set_msi_irq_affinity,
3445 .retrigger = ioapic_retrigger_irq,
3448 static struct irq_chip msi_ir_chip = {
3449 .name = "IR-PCI-MSI",
3450 .unmask = unmask_msi_irq,
3451 .mask = mask_msi_irq,
3452 #ifdef CONFIG_INTR_REMAP
3453 .ack = ir_ack_apic_edge,
3455 .set_affinity = ir_set_msi_irq_affinity,
3458 .retrigger = ioapic_retrigger_irq,
3462 * Map the PCI dev to the corresponding remapping hardware unit
3463 * and allocate 'nvec' consecutive interrupt-remapping table entries
3466 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3468 struct intel_iommu *iommu;
3471 iommu = map_dev_to_ir(dev);
3474 "Unable to map PCI %s to iommu\n", pci_name(dev));
3478 index = alloc_irte(iommu, irq, nvec);
3481 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3488 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3493 ret = msi_compose_msg(dev, irq, &msg, -1);
3497 set_irq_msi(irq, msidesc);
3498 write_msi_msg(irq, &msg);
3500 if (irq_remapped(irq)) {
3501 struct irq_desc *desc = irq_to_desc(irq);
3503 * irq migration in process context
3505 desc->status |= IRQ_MOVE_PCNTXT;
3506 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3508 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3510 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3515 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3518 int ret, sub_handle;
3519 struct msi_desc *msidesc;
3520 unsigned int irq_want;
3521 struct intel_iommu *iommu = NULL;
3525 /* x86 doesn't support multiple MSI yet */
3526 if (type == PCI_CAP_ID_MSI && nvec > 1)
3529 node = dev_to_node(&dev->dev);
3530 irq_want = nr_irqs_gsi;
3532 list_for_each_entry(msidesc, &dev->msi_list, list) {
3533 irq = create_irq_nr(irq_want, node);
3537 if (!intr_remapping_enabled)
3542 * allocate the consecutive block of IRTE's
3545 index = msi_alloc_irte(dev, irq, nvec);
3551 iommu = map_dev_to_ir(dev);
3557 * setup the mapping between the irq and the IRTE
3558 * base index, the sub_handle pointing to the
3559 * appropriate interrupt remap table entry.
3561 set_irte_irq(irq, iommu, index, sub_handle);
3564 ret = setup_msi_irq(dev, msidesc, irq);
3576 void arch_teardown_msi_irq(unsigned int irq)
3581 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3583 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3585 struct irq_desc *desc = irq_to_desc(irq);
3586 struct irq_cfg *cfg;
3590 if (set_desc_affinity(desc, mask, &dest))
3593 cfg = desc->chip_data;
3595 dmar_msi_read(irq, &msg);
3597 msg.data &= ~MSI_DATA_VECTOR_MASK;
3598 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3599 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3600 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3602 dmar_msi_write(irq, &msg);
3607 #endif /* CONFIG_SMP */
3609 static struct irq_chip dmar_msi_type = {
3611 .unmask = dmar_msi_unmask,
3612 .mask = dmar_msi_mask,
3613 .ack = ack_apic_edge,
3615 .set_affinity = dmar_msi_set_affinity,
3617 .retrigger = ioapic_retrigger_irq,
3620 int arch_setup_dmar_msi(unsigned int irq)
3625 ret = msi_compose_msg(NULL, irq, &msg, -1);
3628 dmar_msi_write(irq, &msg);
3629 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3635 #ifdef CONFIG_HPET_TIMER
3638 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3640 struct irq_desc *desc = irq_to_desc(irq);
3641 struct irq_cfg *cfg;
3645 if (set_desc_affinity(desc, mask, &dest))
3648 cfg = desc->chip_data;
3650 hpet_msi_read(irq, &msg);
3652 msg.data &= ~MSI_DATA_VECTOR_MASK;
3653 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3654 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3655 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3657 hpet_msi_write(irq, &msg);
3662 #endif /* CONFIG_SMP */
3664 static struct irq_chip ir_hpet_msi_type = {
3665 .name = "IR-HPET_MSI",
3666 .unmask = hpet_msi_unmask,
3667 .mask = hpet_msi_mask,
3668 #ifdef CONFIG_INTR_REMAP
3669 .ack = ir_ack_apic_edge,
3671 .set_affinity = ir_set_msi_irq_affinity,
3674 .retrigger = ioapic_retrigger_irq,
3677 static struct irq_chip hpet_msi_type = {
3679 .unmask = hpet_msi_unmask,
3680 .mask = hpet_msi_mask,
3681 .ack = ack_apic_edge,
3683 .set_affinity = hpet_msi_set_affinity,
3685 .retrigger = ioapic_retrigger_irq,
3688 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3692 struct irq_desc *desc = irq_to_desc(irq);
3694 if (intr_remapping_enabled) {
3695 struct intel_iommu *iommu = map_hpet_to_ir(id);
3701 index = alloc_irte(iommu, irq, 1);
3706 ret = msi_compose_msg(NULL, irq, &msg, id);
3710 hpet_msi_write(irq, &msg);
3711 desc->status |= IRQ_MOVE_PCNTXT;
3712 if (irq_remapped(irq))
3713 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3714 handle_edge_irq, "edge");
3716 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3717 handle_edge_irq, "edge");
3723 #endif /* CONFIG_PCI_MSI */
3725 * Hypertransport interrupt support
3727 #ifdef CONFIG_HT_IRQ
3731 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3733 struct ht_irq_msg msg;
3734 fetch_ht_irq_msg(irq, &msg);
3736 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3737 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3739 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3740 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3742 write_ht_irq_msg(irq, &msg);
3745 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3747 struct irq_desc *desc = irq_to_desc(irq);
3748 struct irq_cfg *cfg;
3751 if (set_desc_affinity(desc, mask, &dest))
3754 cfg = desc->chip_data;
3756 target_ht_irq(irq, dest, cfg->vector);
3763 static struct irq_chip ht_irq_chip = {
3765 .mask = mask_ht_irq,
3766 .unmask = unmask_ht_irq,
3767 .ack = ack_apic_edge,
3769 .set_affinity = set_ht_irq_affinity,
3771 .retrigger = ioapic_retrigger_irq,
3774 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3776 struct irq_cfg *cfg;
3783 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3785 struct ht_irq_msg msg;
3788 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3789 apic->target_cpus());
3791 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3795 HT_IRQ_LOW_DEST_ID(dest) |
3796 HT_IRQ_LOW_VECTOR(cfg->vector) |
3797 ((apic->irq_dest_mode == 0) ?
3798 HT_IRQ_LOW_DM_PHYSICAL :
3799 HT_IRQ_LOW_DM_LOGICAL) |
3800 HT_IRQ_LOW_RQEOI_EDGE |
3801 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3802 HT_IRQ_LOW_MT_FIXED :
3803 HT_IRQ_LOW_MT_ARBITRATED) |
3804 HT_IRQ_LOW_IRQ_MASKED;
3806 write_ht_irq_msg(irq, &msg);
3808 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3809 handle_edge_irq, "edge");
3811 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3815 #endif /* CONFIG_HT_IRQ */
3817 int __init io_apic_get_redir_entries (int ioapic)
3819 union IO_APIC_reg_01 reg_01;
3820 unsigned long flags;
3822 raw_spin_lock_irqsave(&ioapic_lock, flags);
3823 reg_01.raw = io_apic_read(ioapic, 1);
3824 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3826 /* The register returns the maximum index redir index
3827 * supported, which is one less than the total number of redir
3830 return reg_01.bits.entries + 1;
3833 void __init probe_nr_irqs_gsi(void)
3837 nr = gsi_top + NR_IRQS_LEGACY;
3838 if (nr > nr_irqs_gsi)
3841 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3844 #ifdef CONFIG_SPARSE_IRQ
3845 int __init arch_probe_nr_irqs(void)
3849 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3850 nr_irqs = NR_VECTORS * nr_cpu_ids;
3852 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3853 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3855 * for MSI and HT dyn irq
3857 nr += nr_irqs_gsi * 16;
3862 return NR_IRQS_LEGACY;
3866 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3867 struct io_apic_irq_attr *irq_attr)
3869 struct irq_desc *desc;
3870 struct irq_cfg *cfg;
3873 int trigger, polarity;
3875 ioapic = irq_attr->ioapic;
3876 if (!IO_APIC_IRQ(irq)) {
3877 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3883 node = dev_to_node(dev);
3885 node = cpu_to_node(0);
3887 desc = irq_to_desc_alloc_node(irq, node);
3889 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3893 pin = irq_attr->ioapic_pin;
3894 trigger = irq_attr->trigger;
3895 polarity = irq_attr->polarity;
3898 * IRQs < 16 are already in the irq_2_pin[] map
3900 if (irq >= legacy_pic->nr_legacy_irqs) {
3901 cfg = desc->chip_data;
3902 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3903 printk(KERN_INFO "can not add pin %d for irq %d\n",
3909 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3914 int io_apic_set_pci_routing(struct device *dev, int irq,
3915 struct io_apic_irq_attr *irq_attr)
3919 * Avoid pin reprogramming. PRTs typically include entries
3920 * with redundant pin->gsi mappings (but unique PCI devices);
3921 * we only program the IOAPIC on the first.
3923 ioapic = irq_attr->ioapic;
3924 pin = irq_attr->ioapic_pin;
3925 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3926 pr_debug("Pin %d-%d already programmed\n",
3927 mp_ioapics[ioapic].apicid, pin);
3930 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3932 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3935 u8 __init io_apic_unique_id(u8 id)
3937 #ifdef CONFIG_X86_32
3938 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3939 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3940 return io_apic_get_unique_id(nr_ioapics, id);
3945 DECLARE_BITMAP(used, 256);
3947 bitmap_zero(used, 256);
3948 for (i = 0; i < nr_ioapics; i++) {
3949 struct mpc_ioapic *ia = &mp_ioapics[i];
3950 __set_bit(ia->apicid, used);
3952 if (!test_bit(id, used))
3954 return find_first_zero_bit(used, 256);
3958 #ifdef CONFIG_X86_32
3959 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3961 union IO_APIC_reg_00 reg_00;
3962 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3964 unsigned long flags;
3968 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3969 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3970 * supports up to 16 on one shared APIC bus.
3972 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3973 * advantage of new APIC bus architecture.
3976 if (physids_empty(apic_id_map))
3977 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3979 raw_spin_lock_irqsave(&ioapic_lock, flags);
3980 reg_00.raw = io_apic_read(ioapic, 0);
3981 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3983 if (apic_id >= get_physical_broadcast()) {
3984 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3985 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3986 apic_id = reg_00.bits.ID;
3990 * Every APIC in a system must have a unique ID or we get lots of nice
3991 * 'stuck on smp_invalidate_needed IPI wait' messages.
3993 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3995 for (i = 0; i < get_physical_broadcast(); i++) {
3996 if (!apic->check_apicid_used(&apic_id_map, i))
4000 if (i == get_physical_broadcast())
4001 panic("Max apic_id exceeded!\n");
4003 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
4004 "trying %d\n", ioapic, apic_id, i);
4009 apic->apicid_to_cpu_present(apic_id, &tmp);
4010 physids_or(apic_id_map, apic_id_map, tmp);
4012 if (reg_00.bits.ID != apic_id) {
4013 reg_00.bits.ID = apic_id;
4015 raw_spin_lock_irqsave(&ioapic_lock, flags);
4016 io_apic_write(ioapic, 0, reg_00.raw);
4017 reg_00.raw = io_apic_read(ioapic, 0);
4018 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4021 if (reg_00.bits.ID != apic_id) {
4022 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4027 apic_printk(APIC_VERBOSE, KERN_INFO
4028 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4034 int __init io_apic_get_version(int ioapic)
4036 union IO_APIC_reg_01 reg_01;
4037 unsigned long flags;
4039 raw_spin_lock_irqsave(&ioapic_lock, flags);
4040 reg_01.raw = io_apic_read(ioapic, 1);
4041 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4043 return reg_01.bits.version;
4046 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
4048 int ioapic, pin, idx;
4050 if (skip_ioapic_setup)
4053 ioapic = mp_find_ioapic(gsi);
4057 pin = mp_find_ioapic_pin(ioapic, gsi);
4061 idx = find_irq_entry(ioapic, pin, mp_INT);
4065 *trigger = irq_trigger(idx);
4066 *polarity = irq_polarity(idx);
4071 * This function currently is only a helper for the i386 smp boot process where
4072 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4073 * so mask in all cases should simply be apic->target_cpus()
4076 void __init setup_ioapic_dest(void)
4078 int pin, ioapic, irq, irq_entry;
4079 struct irq_desc *desc;
4080 const struct cpumask *mask;
4082 if (skip_ioapic_setup == 1)
4085 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
4086 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4087 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4088 if (irq_entry == -1)
4090 irq = pin_2_irq(irq_entry, ioapic, pin);
4092 if ((ioapic > 0) && (irq > 16))
4095 desc = irq_to_desc(irq);
4098 * Honour affinities which have been set in early boot
4101 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4102 mask = desc->affinity;
4104 mask = apic->target_cpus();
4106 if (intr_remapping_enabled)
4107 set_ir_ioapic_affinity_irq_desc(desc, mask);
4109 set_ioapic_affinity_irq_desc(desc, mask);
4115 #define IOAPIC_RESOURCE_NAME_SIZE 11
4117 static struct resource *ioapic_resources;
4119 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4122 struct resource *res;
4126 if (nr_ioapics <= 0)
4129 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4132 mem = alloc_bootmem(n);
4135 mem += sizeof(struct resource) * nr_ioapics;
4137 for (i = 0; i < nr_ioapics; i++) {
4139 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4140 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4141 mem += IOAPIC_RESOURCE_NAME_SIZE;
4144 ioapic_resources = res;
4149 void __init ioapic_init_mappings(void)
4151 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4152 struct resource *ioapic_res;
4155 ioapic_res = ioapic_setup_resources(nr_ioapics);
4156 for (i = 0; i < nr_ioapics; i++) {
4157 if (smp_found_config) {
4158 ioapic_phys = mp_ioapics[i].apicaddr;
4159 #ifdef CONFIG_X86_32
4162 "WARNING: bogus zero IO-APIC "
4163 "address found in MPTABLE, "
4164 "disabling IO/APIC support!\n");
4165 smp_found_config = 0;
4166 skip_ioapic_setup = 1;
4167 goto fake_ioapic_page;
4171 #ifdef CONFIG_X86_32
4174 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4175 ioapic_phys = __pa(ioapic_phys);
4177 set_fixmap_nocache(idx, ioapic_phys);
4178 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4179 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4183 ioapic_res->start = ioapic_phys;
4184 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4189 void __init ioapic_insert_resources(void)
4192 struct resource *r = ioapic_resources;
4197 "IO APIC resources couldn't be allocated.\n");
4201 for (i = 0; i < nr_ioapics; i++) {
4202 insert_resource(&iomem_resource, r);
4207 int mp_find_ioapic(u32 gsi)
4211 /* Find the IOAPIC that manages this GSI. */
4212 for (i = 0; i < nr_ioapics; i++) {
4213 if ((gsi >= mp_gsi_routing[i].gsi_base)
4214 && (gsi <= mp_gsi_routing[i].gsi_end))
4218 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4222 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4224 if (WARN_ON(ioapic == -1))
4226 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4229 return gsi - mp_gsi_routing[ioapic].gsi_base;
4232 static int bad_ioapic(unsigned long address)
4234 if (nr_ioapics >= MAX_IO_APICS) {
4235 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4236 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4240 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4241 " found in table, skipping!\n");
4247 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4252 if (bad_ioapic(address))
4257 mp_ioapics[idx].type = MP_IOAPIC;
4258 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4259 mp_ioapics[idx].apicaddr = address;
4261 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4262 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4263 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4266 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4267 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4269 entries = io_apic_get_redir_entries(idx);
4270 mp_gsi_routing[idx].gsi_base = gsi_base;
4271 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
4274 * The number of IO-APIC IRQ registers (== #pins):
4276 nr_ioapic_registers[idx] = entries;
4278 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
4279 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
4281 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4282 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4283 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4284 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4289 /* Enable IOAPIC early just for system timer */
4290 void __init pre_init_apic_IRQ0(void)
4292 struct irq_cfg *cfg;
4293 struct irq_desc *desc;
4295 printk(KERN_INFO "Early APIC setup for system timer0\n");
4297 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
4299 desc = irq_to_desc_alloc_node(0, 0);
4304 add_pin_to_irq_node(cfg, 0, 0, 0);
4305 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4307 setup_IO_APIC_irq(0, 0, 0, desc, 0, 0);