2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 void arch_disable_smp_support(void)
106 noioapicreroute = -1;
108 skip_ioapic_setup = 1;
111 static int __init parse_noapic(char *str)
113 /* disable IO-APIC */
114 arch_disable_smp_support();
117 early_param("noapic", parse_noapic);
120 * This is performance-critical, we want to do it O(1)
122 * the indexing order of this array favors 1:1 mappings
123 * between pins and IRQs.
126 struct irq_pin_list {
128 struct irq_pin_list *next;
131 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
133 struct irq_pin_list *pin;
135 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
141 struct irq_pin_list *irq_2_pin;
142 cpumask_var_t domain;
143 cpumask_var_t old_domain;
144 unsigned move_cleanup_count;
146 u8 move_in_progress : 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx[] = {
153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
155 [0] = { .vector = IRQ0_VECTOR, },
156 [1] = { .vector = IRQ1_VECTOR, },
157 [2] = { .vector = IRQ2_VECTOR, },
158 [3] = { .vector = IRQ3_VECTOR, },
159 [4] = { .vector = IRQ4_VECTOR, },
160 [5] = { .vector = IRQ5_VECTOR, },
161 [6] = { .vector = IRQ6_VECTOR, },
162 [7] = { .vector = IRQ7_VECTOR, },
163 [8] = { .vector = IRQ8_VECTOR, },
164 [9] = { .vector = IRQ9_VECTOR, },
165 [10] = { .vector = IRQ10_VECTOR, },
166 [11] = { .vector = IRQ11_VECTOR, },
167 [12] = { .vector = IRQ12_VECTOR, },
168 [13] = { .vector = IRQ13_VECTOR, },
169 [14] = { .vector = IRQ14_VECTOR, },
170 [15] = { .vector = IRQ15_VECTOR, },
173 int __init arch_early_irq_init(void)
176 struct irq_desc *desc;
182 count = ARRAY_SIZE(irq_cfgx);
183 node= cpu_to_node(boot_cpu_id);
185 for (i = 0; i < count; i++) {
186 desc = irq_to_desc(i);
187 desc->chip_data = &cfg[i];
188 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
189 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
190 if (i < NR_IRQS_LEGACY)
191 cpumask_setall(cfg[i].domain);
197 #ifdef CONFIG_SPARSE_IRQ
198 static struct irq_cfg *irq_cfg(unsigned int irq)
200 struct irq_cfg *cfg = NULL;
201 struct irq_desc *desc;
203 desc = irq_to_desc(irq);
205 cfg = desc->chip_data;
210 static struct irq_cfg *get_one_free_irq_cfg(int node)
214 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
216 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
219 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
221 free_cpumask_var(cfg->domain);
225 cpumask_clear(cfg->domain);
226 cpumask_clear(cfg->old_domain);
233 int arch_init_chip_data(struct irq_desc *desc, int node)
237 cfg = desc->chip_data;
239 desc->chip_data = get_one_free_irq_cfg(node);
240 if (!desc->chip_data) {
241 printk(KERN_ERR "can not alloc irq_cfg\n");
249 /* for move_irq_desc */
251 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
253 struct irq_pin_list *old_entry, *head, *tail, *entry;
255 cfg->irq_2_pin = NULL;
256 old_entry = old_cfg->irq_2_pin;
260 entry = get_one_free_irq_2_pin(node);
264 entry->apic = old_entry->apic;
265 entry->pin = old_entry->pin;
268 old_entry = old_entry->next;
270 entry = get_one_free_irq_2_pin(node);
278 /* still use the old one */
281 entry->apic = old_entry->apic;
282 entry->pin = old_entry->pin;
285 old_entry = old_entry->next;
289 cfg->irq_2_pin = head;
292 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
294 struct irq_pin_list *entry, *next;
296 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
299 entry = old_cfg->irq_2_pin;
306 old_cfg->irq_2_pin = NULL;
309 void arch_init_copy_chip_data(struct irq_desc *old_desc,
310 struct irq_desc *desc, int node)
313 struct irq_cfg *old_cfg;
315 cfg = get_one_free_irq_cfg(node);
320 desc->chip_data = cfg;
322 old_cfg = old_desc->chip_data;
324 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
326 init_copy_irq_2_pin(old_cfg, cfg, node);
329 static void free_irq_cfg(struct irq_cfg *old_cfg)
334 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
336 struct irq_cfg *old_cfg, *cfg;
338 old_cfg = old_desc->chip_data;
339 cfg = desc->chip_data;
345 free_irq_2_pin(old_cfg, cfg);
346 free_irq_cfg(old_cfg);
347 old_desc->chip_data = NULL;
350 /* end for move_irq_desc */
353 static struct irq_cfg *irq_cfg(unsigned int irq)
355 return irq < nr_irqs ? irq_cfgx + irq : NULL;
362 unsigned int unused[3];
364 unsigned int unused2[11];
368 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
370 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
371 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
374 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
376 struct io_apic __iomem *io_apic = io_apic_base(apic);
377 writel(vector, &io_apic->eoi);
380 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
382 struct io_apic __iomem *io_apic = io_apic_base(apic);
383 writel(reg, &io_apic->index);
384 return readl(&io_apic->data);
387 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
389 struct io_apic __iomem *io_apic = io_apic_base(apic);
390 writel(reg, &io_apic->index);
391 writel(value, &io_apic->data);
395 * Re-write a value: to be used for read-modify-write
396 * cycles where the read already set up the index register.
398 * Older SiS APIC requires we rewrite the index register
400 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
402 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(reg, &io_apic->index);
406 writel(value, &io_apic->data);
409 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
411 struct irq_pin_list *entry;
414 spin_lock_irqsave(&ioapic_lock, flags);
415 entry = cfg->irq_2_pin;
423 reg = io_apic_read(entry->apic, 0x10 + pin*2);
424 /* Is the remote IRR bit set? */
425 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
426 spin_unlock_irqrestore(&ioapic_lock, flags);
433 spin_unlock_irqrestore(&ioapic_lock, flags);
439 struct { u32 w1, w2; };
440 struct IO_APIC_route_entry entry;
443 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
445 union entry_union eu;
447 spin_lock_irqsave(&ioapic_lock, flags);
448 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
449 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
450 spin_unlock_irqrestore(&ioapic_lock, flags);
455 * When we write a new IO APIC routing entry, we need to write the high
456 * word first! If the mask bit in the low word is clear, we will enable
457 * the interrupt, and we need to make sure the entry is fully populated
458 * before that happens.
461 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
463 union entry_union eu = {{0, 0}};
466 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
467 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
470 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
473 spin_lock_irqsave(&ioapic_lock, flags);
474 __ioapic_write_entry(apic, pin, e);
475 spin_unlock_irqrestore(&ioapic_lock, flags);
479 * When we mask an IO APIC routing entry, we need to write the low
480 * word first, in order to set the mask bit before we change the
483 static void ioapic_mask_entry(int apic, int pin)
486 union entry_union eu = { .entry.mask = 1 };
488 spin_lock_irqsave(&ioapic_lock, flags);
489 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
490 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
491 spin_unlock_irqrestore(&ioapic_lock, flags);
495 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
496 * shared ISA-space IRQs, so we have to support them. We are super
497 * fast in the common case, and fast for shared ISA-space IRQs.
499 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
501 struct irq_pin_list *entry;
503 entry = cfg->irq_2_pin;
505 entry = get_one_free_irq_2_pin(node);
507 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
511 cfg->irq_2_pin = entry;
517 while (entry->next) {
518 /* not again, please */
519 if (entry->apic == apic && entry->pin == pin)
525 entry->next = get_one_free_irq_2_pin(node);
532 * Reroute an IRQ to a different pin.
534 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
535 int oldapic, int oldpin,
536 int newapic, int newpin)
538 struct irq_pin_list *entry = cfg->irq_2_pin;
542 if (entry->apic == oldapic && entry->pin == oldpin) {
543 entry->apic = newapic;
546 /* every one is different, right? */
552 /* why? call replace before add? */
554 add_pin_to_irq_node(cfg, node, newapic, newpin);
557 static void io_apic_modify_irq(struct irq_cfg *cfg,
558 int mask_and, int mask_or,
559 void (*final)(struct irq_pin_list *entry))
562 struct irq_pin_list *entry;
564 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
567 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
570 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
576 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
578 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
581 static void io_apic_sync(struct irq_pin_list *entry)
584 * Synchronize the IO-APIC and the CPU by doing
585 * a dummy read from the IO-APIC
587 struct io_apic __iomem *io_apic;
588 io_apic = io_apic_base(entry->apic);
589 readl(&io_apic->data);
592 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
594 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
597 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
599 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
600 IO_APIC_REDIR_MASKED, NULL);
603 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
605 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
606 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
609 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
611 struct irq_cfg *cfg = desc->chip_data;
616 spin_lock_irqsave(&ioapic_lock, flags);
617 __mask_IO_APIC_irq(cfg);
618 spin_unlock_irqrestore(&ioapic_lock, flags);
621 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
623 struct irq_cfg *cfg = desc->chip_data;
626 spin_lock_irqsave(&ioapic_lock, flags);
627 __unmask_IO_APIC_irq(cfg);
628 spin_unlock_irqrestore(&ioapic_lock, flags);
631 static void mask_IO_APIC_irq(unsigned int irq)
633 struct irq_desc *desc = irq_to_desc(irq);
635 mask_IO_APIC_irq_desc(desc);
637 static void unmask_IO_APIC_irq(unsigned int irq)
639 struct irq_desc *desc = irq_to_desc(irq);
641 unmask_IO_APIC_irq_desc(desc);
644 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
646 struct IO_APIC_route_entry entry;
648 /* Check delivery_mode to be sure we're not clearing an SMI pin */
649 entry = ioapic_read_entry(apic, pin);
650 if (entry.delivery_mode == dest_SMI)
653 * Disable it in the IO-APIC irq-routing table:
655 ioapic_mask_entry(apic, pin);
658 static void clear_IO_APIC (void)
662 for (apic = 0; apic < nr_ioapics; apic++)
663 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
664 clear_IO_APIC_pin(apic, pin);
669 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
670 * specific CPU-side IRQs.
674 static int pirq_entries[MAX_PIRQS] = {
675 [0 ... MAX_PIRQS - 1] = -1
678 static int __init ioapic_pirq_setup(char *str)
681 int ints[MAX_PIRQS+1];
683 get_options(str, ARRAY_SIZE(ints), ints);
685 apic_printk(APIC_VERBOSE, KERN_INFO
686 "PIRQ redirection, working around broken MP-BIOS.\n");
688 if (ints[0] < MAX_PIRQS)
691 for (i = 0; i < max; i++) {
692 apic_printk(APIC_VERBOSE, KERN_DEBUG
693 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
695 * PIRQs are mapped upside down, usually.
697 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
702 __setup("pirq=", ioapic_pirq_setup);
703 #endif /* CONFIG_X86_32 */
705 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
708 struct IO_APIC_route_entry **ioapic_entries;
710 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
715 for (apic = 0; apic < nr_ioapics; apic++) {
716 ioapic_entries[apic] =
717 kzalloc(sizeof(struct IO_APIC_route_entry) *
718 nr_ioapic_registers[apic], GFP_ATOMIC);
719 if (!ioapic_entries[apic])
723 return ioapic_entries;
727 kfree(ioapic_entries[apic]);
728 kfree(ioapic_entries);
734 * Saves all the IO-APIC RTE's
736 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
743 for (apic = 0; apic < nr_ioapics; apic++) {
744 if (!ioapic_entries[apic])
747 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
748 ioapic_entries[apic][pin] =
749 ioapic_read_entry(apic, pin);
756 * Mask all IO APIC entries.
758 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
765 for (apic = 0; apic < nr_ioapics; apic++) {
766 if (!ioapic_entries[apic])
769 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
770 struct IO_APIC_route_entry entry;
772 entry = ioapic_entries[apic][pin];
775 ioapic_write_entry(apic, pin, entry);
782 * Restore IO APIC entries which was saved in ioapic_entries.
784 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
791 for (apic = 0; apic < nr_ioapics; apic++) {
792 if (!ioapic_entries[apic])
795 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
796 ioapic_write_entry(apic, pin,
797 ioapic_entries[apic][pin]);
802 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
806 for (apic = 0; apic < nr_ioapics; apic++)
807 kfree(ioapic_entries[apic]);
809 kfree(ioapic_entries);
813 * Find the IRQ entry number of a certain pin.
815 static int find_irq_entry(int apic, int pin, int type)
819 for (i = 0; i < mp_irq_entries; i++)
820 if (mp_irqs[i].irqtype == type &&
821 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
822 mp_irqs[i].dstapic == MP_APIC_ALL) &&
823 mp_irqs[i].dstirq == pin)
830 * Find the pin to which IRQ[irq] (ISA) is connected
832 static int __init find_isa_irq_pin(int irq, int type)
836 for (i = 0; i < mp_irq_entries; i++) {
837 int lbus = mp_irqs[i].srcbus;
839 if (test_bit(lbus, mp_bus_not_pci) &&
840 (mp_irqs[i].irqtype == type) &&
841 (mp_irqs[i].srcbusirq == irq))
843 return mp_irqs[i].dstirq;
848 static int __init find_isa_irq_apic(int irq, int type)
852 for (i = 0; i < mp_irq_entries; i++) {
853 int lbus = mp_irqs[i].srcbus;
855 if (test_bit(lbus, mp_bus_not_pci) &&
856 (mp_irqs[i].irqtype == type) &&
857 (mp_irqs[i].srcbusirq == irq))
860 if (i < mp_irq_entries) {
862 for(apic = 0; apic < nr_ioapics; apic++) {
863 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
871 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
873 * EISA Edge/Level control register, ELCR
875 static int EISA_ELCR(unsigned int irq)
877 if (irq < NR_IRQS_LEGACY) {
878 unsigned int port = 0x4d0 + (irq >> 3);
879 return (inb(port) >> (irq & 7)) & 1;
881 apic_printk(APIC_VERBOSE, KERN_INFO
882 "Broken MPtable reports ISA irq %d\n", irq);
888 /* ISA interrupts are always polarity zero edge triggered,
889 * when listed as conforming in the MP table. */
891 #define default_ISA_trigger(idx) (0)
892 #define default_ISA_polarity(idx) (0)
894 /* EISA interrupts are always polarity zero and can be edge or level
895 * trigger depending on the ELCR value. If an interrupt is listed as
896 * EISA conforming in the MP table, that means its trigger type must
897 * be read in from the ELCR */
899 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
900 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
902 /* PCI interrupts are always polarity one level triggered,
903 * when listed as conforming in the MP table. */
905 #define default_PCI_trigger(idx) (1)
906 #define default_PCI_polarity(idx) (1)
908 /* MCA interrupts are always polarity zero level triggered,
909 * when listed as conforming in the MP table. */
911 #define default_MCA_trigger(idx) (1)
912 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
914 static int MPBIOS_polarity(int idx)
916 int bus = mp_irqs[idx].srcbus;
920 * Determine IRQ line polarity (high active or low active):
922 switch (mp_irqs[idx].irqflag & 3)
924 case 0: /* conforms, ie. bus-type dependent polarity */
925 if (test_bit(bus, mp_bus_not_pci))
926 polarity = default_ISA_polarity(idx);
928 polarity = default_PCI_polarity(idx);
930 case 1: /* high active */
935 case 2: /* reserved */
937 printk(KERN_WARNING "broken BIOS!!\n");
941 case 3: /* low active */
946 default: /* invalid */
948 printk(KERN_WARNING "broken BIOS!!\n");
956 static int MPBIOS_trigger(int idx)
958 int bus = mp_irqs[idx].srcbus;
962 * Determine IRQ trigger mode (edge or level sensitive):
964 switch ((mp_irqs[idx].irqflag>>2) & 3)
966 case 0: /* conforms, ie. bus-type dependent */
967 if (test_bit(bus, mp_bus_not_pci))
968 trigger = default_ISA_trigger(idx);
970 trigger = default_PCI_trigger(idx);
971 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
972 switch (mp_bus_id_to_type[bus]) {
973 case MP_BUS_ISA: /* ISA pin */
975 /* set before the switch */
978 case MP_BUS_EISA: /* EISA pin */
980 trigger = default_EISA_trigger(idx);
983 case MP_BUS_PCI: /* PCI pin */
985 /* set before the switch */
988 case MP_BUS_MCA: /* MCA pin */
990 trigger = default_MCA_trigger(idx);
995 printk(KERN_WARNING "broken BIOS!!\n");
1007 case 2: /* reserved */
1009 printk(KERN_WARNING "broken BIOS!!\n");
1018 default: /* invalid */
1020 printk(KERN_WARNING "broken BIOS!!\n");
1028 static inline int irq_polarity(int idx)
1030 return MPBIOS_polarity(idx);
1033 static inline int irq_trigger(int idx)
1035 return MPBIOS_trigger(idx);
1038 int (*ioapic_renumber_irq)(int ioapic, int irq);
1039 static int pin_2_irq(int idx, int apic, int pin)
1042 int bus = mp_irqs[idx].srcbus;
1045 * Debugging check, we are in big trouble if this message pops up!
1047 if (mp_irqs[idx].dstirq != pin)
1048 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1050 if (test_bit(bus, mp_bus_not_pci)) {
1051 irq = mp_irqs[idx].srcbusirq;
1054 * PCI IRQs are mapped in order
1058 irq += nr_ioapic_registers[i++];
1061 * For MPS mode, so far only needed by ES7000 platform
1063 if (ioapic_renumber_irq)
1064 irq = ioapic_renumber_irq(apic, irq);
1067 #ifdef CONFIG_X86_32
1069 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1071 if ((pin >= 16) && (pin <= 23)) {
1072 if (pirq_entries[pin-16] != -1) {
1073 if (!pirq_entries[pin-16]) {
1074 apic_printk(APIC_VERBOSE, KERN_DEBUG
1075 "disabling PIRQ%d\n", pin-16);
1077 irq = pirq_entries[pin-16];
1078 apic_printk(APIC_VERBOSE, KERN_DEBUG
1079 "using PIRQ%d -> IRQ %d\n",
1090 * Find a specific PCI IRQ entry.
1091 * Not an __init, possibly needed by modules
1093 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1094 struct io_apic_irq_attr *irq_attr)
1096 int apic, i, best_guess = -1;
1098 apic_printk(APIC_DEBUG,
1099 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1101 if (test_bit(bus, mp_bus_not_pci)) {
1102 apic_printk(APIC_VERBOSE,
1103 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1106 for (i = 0; i < mp_irq_entries; i++) {
1107 int lbus = mp_irqs[i].srcbus;
1109 for (apic = 0; apic < nr_ioapics; apic++)
1110 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1111 mp_irqs[i].dstapic == MP_APIC_ALL)
1114 if (!test_bit(lbus, mp_bus_not_pci) &&
1115 !mp_irqs[i].irqtype &&
1117 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1118 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1120 if (!(apic || IO_APIC_IRQ(irq)))
1123 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1124 set_io_apic_irq_attr(irq_attr, apic,
1131 * Use the first all-but-pin matching entry as a
1132 * best-guess fuzzy result for broken mptables.
1134 if (best_guess < 0) {
1135 set_io_apic_irq_attr(irq_attr, apic,
1145 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1147 void lock_vector_lock(void)
1149 /* Used to the online set of cpus does not change
1150 * during assign_irq_vector.
1152 spin_lock(&vector_lock);
1155 void unlock_vector_lock(void)
1157 spin_unlock(&vector_lock);
1161 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1164 * NOTE! The local APIC isn't very good at handling
1165 * multiple interrupts at the same interrupt level.
1166 * As the interrupt level is determined by taking the
1167 * vector number and shifting that right by 4, we
1168 * want to spread these out a bit so that they don't
1169 * all fall in the same interrupt level.
1171 * Also, we've got to be careful not to trash gate
1172 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1174 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1175 unsigned int old_vector;
1177 cpumask_var_t tmp_mask;
1179 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1182 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1185 old_vector = cfg->vector;
1187 cpumask_and(tmp_mask, mask, cpu_online_mask);
1188 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1189 if (!cpumask_empty(tmp_mask)) {
1190 free_cpumask_var(tmp_mask);
1195 /* Only try and allocate irqs on cpus that are present */
1197 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1201 apic->vector_allocation_domain(cpu, tmp_mask);
1203 vector = current_vector;
1204 offset = current_offset;
1207 if (vector >= first_system_vector) {
1208 /* If out of vectors on large boxen, must share them. */
1209 offset = (offset + 1) % 8;
1210 vector = FIRST_DEVICE_VECTOR + offset;
1212 if (unlikely(current_vector == vector))
1215 if (test_bit(vector, used_vectors))
1218 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1219 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1222 current_vector = vector;
1223 current_offset = offset;
1225 cfg->move_in_progress = 1;
1226 cpumask_copy(cfg->old_domain, cfg->domain);
1228 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1229 per_cpu(vector_irq, new_cpu)[vector] = irq;
1230 cfg->vector = vector;
1231 cpumask_copy(cfg->domain, tmp_mask);
1235 free_cpumask_var(tmp_mask);
1240 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1243 unsigned long flags;
1245 spin_lock_irqsave(&vector_lock, flags);
1246 err = __assign_irq_vector(irq, cfg, mask);
1247 spin_unlock_irqrestore(&vector_lock, flags);
1251 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1255 BUG_ON(!cfg->vector);
1257 vector = cfg->vector;
1258 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1259 per_cpu(vector_irq, cpu)[vector] = -1;
1262 cpumask_clear(cfg->domain);
1264 if (likely(!cfg->move_in_progress))
1266 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1267 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1269 if (per_cpu(vector_irq, cpu)[vector] != irq)
1271 per_cpu(vector_irq, cpu)[vector] = -1;
1275 cfg->move_in_progress = 0;
1278 void __setup_vector_irq(int cpu)
1280 /* Initialize vector_irq on a new cpu */
1281 /* This function must be called with vector_lock held */
1283 struct irq_cfg *cfg;
1284 struct irq_desc *desc;
1286 /* Mark the inuse vectors */
1287 for_each_irq_desc(irq, desc) {
1288 cfg = desc->chip_data;
1289 if (!cpumask_test_cpu(cpu, cfg->domain))
1291 vector = cfg->vector;
1292 per_cpu(vector_irq, cpu)[vector] = irq;
1294 /* Mark the free vectors */
1295 for (vector = 0; vector < NR_VECTORS; ++vector) {
1296 irq = per_cpu(vector_irq, cpu)[vector];
1301 if (!cpumask_test_cpu(cpu, cfg->domain))
1302 per_cpu(vector_irq, cpu)[vector] = -1;
1306 static struct irq_chip ioapic_chip;
1307 static struct irq_chip ir_ioapic_chip;
1309 #define IOAPIC_AUTO -1
1310 #define IOAPIC_EDGE 0
1311 #define IOAPIC_LEVEL 1
1313 #ifdef CONFIG_X86_32
1314 static inline int IO_APIC_irq_trigger(int irq)
1318 for (apic = 0; apic < nr_ioapics; apic++) {
1319 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1320 idx = find_irq_entry(apic, pin, mp_INT);
1321 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1322 return irq_trigger(idx);
1326 * nonexistent IRQs are edge default
1331 static inline int IO_APIC_irq_trigger(int irq)
1337 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1340 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1341 trigger == IOAPIC_LEVEL)
1342 desc->status |= IRQ_LEVEL;
1344 desc->status &= ~IRQ_LEVEL;
1346 if (irq_remapped(irq)) {
1347 desc->status |= IRQ_MOVE_PCNTXT;
1349 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1353 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1354 handle_edge_irq, "edge");
1358 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1359 trigger == IOAPIC_LEVEL)
1360 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1364 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1365 handle_edge_irq, "edge");
1368 int setup_ioapic_entry(int apic_id, int irq,
1369 struct IO_APIC_route_entry *entry,
1370 unsigned int destination, int trigger,
1371 int polarity, int vector, int pin)
1374 * add it to the IO-APIC irq-routing table:
1376 memset(entry,0,sizeof(*entry));
1378 if (intr_remapping_enabled) {
1379 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1381 struct IR_IO_APIC_route_entry *ir_entry =
1382 (struct IR_IO_APIC_route_entry *) entry;
1386 panic("No mapping iommu for ioapic %d\n", apic_id);
1388 index = alloc_irte(iommu, irq, 1);
1390 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1392 memset(&irte, 0, sizeof(irte));
1395 irte.dst_mode = apic->irq_dest_mode;
1397 * Trigger mode in the IRTE will always be edge, and the
1398 * actual level or edge trigger will be setup in the IO-APIC
1399 * RTE. This will help simplify level triggered irq migration.
1400 * For more details, see the comments above explainig IO-APIC
1401 * irq migration in the presence of interrupt-remapping.
1403 irte.trigger_mode = 0;
1404 irte.dlvry_mode = apic->irq_delivery_mode;
1405 irte.vector = vector;
1406 irte.dest_id = IRTE_DEST(destination);
1408 /* Set source-id of interrupt request */
1409 set_ioapic_sid(&irte, apic_id);
1411 modify_irte(irq, &irte);
1413 ir_entry->index2 = (index >> 15) & 0x1;
1415 ir_entry->format = 1;
1416 ir_entry->index = (index & 0x7fff);
1418 * IO-APIC RTE will be configured with virtual vector.
1419 * irq handler will do the explicit EOI to the io-apic.
1421 ir_entry->vector = pin;
1423 entry->delivery_mode = apic->irq_delivery_mode;
1424 entry->dest_mode = apic->irq_dest_mode;
1425 entry->dest = destination;
1426 entry->vector = vector;
1429 entry->mask = 0; /* enable IRQ */
1430 entry->trigger = trigger;
1431 entry->polarity = polarity;
1433 /* Mask level triggered irqs.
1434 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1441 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1442 int trigger, int polarity)
1444 struct irq_cfg *cfg;
1445 struct IO_APIC_route_entry entry;
1448 if (!IO_APIC_IRQ(irq))
1451 cfg = desc->chip_data;
1453 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1456 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1458 apic_printk(APIC_VERBOSE,KERN_DEBUG
1459 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1460 "IRQ %d Mode:%i Active:%i)\n",
1461 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1462 irq, trigger, polarity);
1465 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1466 dest, trigger, polarity, cfg->vector, pin)) {
1467 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1468 mp_ioapics[apic_id].apicid, pin);
1469 __clear_irq_vector(irq, cfg);
1473 ioapic_register_intr(irq, desc, trigger);
1474 if (irq < NR_IRQS_LEGACY)
1475 disable_8259A_irq(irq);
1477 ioapic_write_entry(apic_id, pin, entry);
1481 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1482 } mp_ioapic_routing[MAX_IO_APICS];
1484 static void __init setup_IO_APIC_irqs(void)
1486 int apic_id = 0, pin, idx, irq;
1488 struct irq_desc *desc;
1489 struct irq_cfg *cfg;
1490 int node = cpu_to_node(boot_cpu_id);
1492 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1495 if (!acpi_disabled && acpi_ioapic) {
1496 apic_id = mp_find_ioapic(0);
1502 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1503 idx = find_irq_entry(apic_id, pin, mp_INT);
1507 apic_printk(APIC_VERBOSE,
1508 KERN_DEBUG " %d-%d",
1509 mp_ioapics[apic_id].apicid, pin);
1511 apic_printk(APIC_VERBOSE, " %d-%d",
1512 mp_ioapics[apic_id].apicid, pin);
1516 apic_printk(APIC_VERBOSE,
1517 " (apicid-pin) not connected\n");
1521 irq = pin_2_irq(idx, apic_id, pin);
1524 * Skip the timer IRQ if there's a quirk handler
1525 * installed and if it returns 1:
1527 if (apic->multi_timer_check &&
1528 apic->multi_timer_check(apic_id, irq))
1531 desc = irq_to_desc_alloc_node(irq, node);
1533 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1536 cfg = desc->chip_data;
1537 add_pin_to_irq_node(cfg, node, apic_id, pin);
1539 * don't mark it in pin_programmed, so later acpi could
1540 * set it correctly when irq < 16
1542 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1543 irq_trigger(idx), irq_polarity(idx));
1547 apic_printk(APIC_VERBOSE,
1548 " (apicid-pin) not connected\n");
1552 * Set up the timer pin, possibly with the 8259A-master behind.
1554 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1557 struct IO_APIC_route_entry entry;
1559 if (intr_remapping_enabled)
1562 memset(&entry, 0, sizeof(entry));
1565 * We use logical delivery to get the timer IRQ
1568 entry.dest_mode = apic->irq_dest_mode;
1569 entry.mask = 0; /* don't mask IRQ for edge */
1570 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1571 entry.delivery_mode = apic->irq_delivery_mode;
1574 entry.vector = vector;
1577 * The timer IRQ doesn't have to know that behind the
1578 * scene we may have a 8259A-master in AEOI mode ...
1580 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1583 * Add it to the IO-APIC irq-routing table:
1585 ioapic_write_entry(apic_id, pin, entry);
1589 __apicdebuginit(void) print_IO_APIC(void)
1592 union IO_APIC_reg_00 reg_00;
1593 union IO_APIC_reg_01 reg_01;
1594 union IO_APIC_reg_02 reg_02;
1595 union IO_APIC_reg_03 reg_03;
1596 unsigned long flags;
1597 struct irq_cfg *cfg;
1598 struct irq_desc *desc;
1601 if (apic_verbosity == APIC_QUIET)
1604 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1605 for (i = 0; i < nr_ioapics; i++)
1606 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1607 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1610 * We are a bit conservative about what we expect. We have to
1611 * know about every hardware change ASAP.
1613 printk(KERN_INFO "testing the IO APIC.......................\n");
1615 for (apic = 0; apic < nr_ioapics; apic++) {
1617 spin_lock_irqsave(&ioapic_lock, flags);
1618 reg_00.raw = io_apic_read(apic, 0);
1619 reg_01.raw = io_apic_read(apic, 1);
1620 if (reg_01.bits.version >= 0x10)
1621 reg_02.raw = io_apic_read(apic, 2);
1622 if (reg_01.bits.version >= 0x20)
1623 reg_03.raw = io_apic_read(apic, 3);
1624 spin_unlock_irqrestore(&ioapic_lock, flags);
1627 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1628 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1629 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1630 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1631 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1633 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1634 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1636 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1637 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1640 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1641 * but the value of reg_02 is read as the previous read register
1642 * value, so ignore it if reg_02 == reg_01.
1644 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1645 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1646 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1650 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1651 * or reg_03, but the value of reg_0[23] is read as the previous read
1652 * register value, so ignore it if reg_03 == reg_0[12].
1654 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1655 reg_03.raw != reg_01.raw) {
1656 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1657 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1660 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1662 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1663 " Stat Dmod Deli Vect: \n");
1665 for (i = 0; i <= reg_01.bits.entries; i++) {
1666 struct IO_APIC_route_entry entry;
1668 entry = ioapic_read_entry(apic, i);
1670 printk(KERN_DEBUG " %02x %03X ",
1675 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1680 entry.delivery_status,
1682 entry.delivery_mode,
1687 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1688 for_each_irq_desc(irq, desc) {
1689 struct irq_pin_list *entry;
1691 cfg = desc->chip_data;
1692 entry = cfg->irq_2_pin;
1695 printk(KERN_DEBUG "IRQ%d ", irq);
1697 printk("-> %d:%d", entry->apic, entry->pin);
1700 entry = entry->next;
1705 printk(KERN_INFO ".................................... done.\n");
1710 __apicdebuginit(void) print_APIC_field(int base)
1714 if (apic_verbosity == APIC_QUIET)
1719 for (i = 0; i < 8; i++)
1720 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1722 printk(KERN_CONT "\n");
1725 __apicdebuginit(void) print_local_APIC(void *dummy)
1727 unsigned int i, v, ver, maxlvt;
1730 if (apic_verbosity == APIC_QUIET)
1733 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1734 smp_processor_id(), hard_smp_processor_id());
1735 v = apic_read(APIC_ID);
1736 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1737 v = apic_read(APIC_LVR);
1738 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1739 ver = GET_APIC_VERSION(v);
1740 maxlvt = lapic_get_maxlvt();
1742 v = apic_read(APIC_TASKPRI);
1743 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1745 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1746 if (!APIC_XAPIC(ver)) {
1747 v = apic_read(APIC_ARBPRI);
1748 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1749 v & APIC_ARBPRI_MASK);
1751 v = apic_read(APIC_PROCPRI);
1752 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1756 * Remote read supported only in the 82489DX and local APIC for
1757 * Pentium processors.
1759 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1760 v = apic_read(APIC_RRR);
1761 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1764 v = apic_read(APIC_LDR);
1765 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1766 if (!x2apic_enabled()) {
1767 v = apic_read(APIC_DFR);
1768 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1770 v = apic_read(APIC_SPIV);
1771 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1773 printk(KERN_DEBUG "... APIC ISR field:\n");
1774 print_APIC_field(APIC_ISR);
1775 printk(KERN_DEBUG "... APIC TMR field:\n");
1776 print_APIC_field(APIC_TMR);
1777 printk(KERN_DEBUG "... APIC IRR field:\n");
1778 print_APIC_field(APIC_IRR);
1780 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1781 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1782 apic_write(APIC_ESR, 0);
1784 v = apic_read(APIC_ESR);
1785 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1788 icr = apic_icr_read();
1789 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1790 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1792 v = apic_read(APIC_LVTT);
1793 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1795 if (maxlvt > 3) { /* PC is LVT#4. */
1796 v = apic_read(APIC_LVTPC);
1797 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1799 v = apic_read(APIC_LVT0);
1800 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1801 v = apic_read(APIC_LVT1);
1802 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1804 if (maxlvt > 2) { /* ERR is LVT#3. */
1805 v = apic_read(APIC_LVTERR);
1806 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1809 v = apic_read(APIC_TMICT);
1810 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1811 v = apic_read(APIC_TMCCT);
1812 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1813 v = apic_read(APIC_TDCR);
1814 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1816 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1817 v = apic_read(APIC_EFEAT);
1818 maxlvt = (v >> 16) & 0xff;
1819 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1820 v = apic_read(APIC_ECTRL);
1821 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1822 for (i = 0; i < maxlvt; i++) {
1823 v = apic_read(APIC_EILVTn(i));
1824 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1830 __apicdebuginit(void) print_all_local_APICs(void)
1835 for_each_online_cpu(cpu)
1836 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1840 __apicdebuginit(void) print_PIC(void)
1843 unsigned long flags;
1845 if (apic_verbosity == APIC_QUIET)
1848 printk(KERN_DEBUG "\nprinting PIC contents\n");
1850 spin_lock_irqsave(&i8259A_lock, flags);
1852 v = inb(0xa1) << 8 | inb(0x21);
1853 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1855 v = inb(0xa0) << 8 | inb(0x20);
1856 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1860 v = inb(0xa0) << 8 | inb(0x20);
1864 spin_unlock_irqrestore(&i8259A_lock, flags);
1866 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1868 v = inb(0x4d1) << 8 | inb(0x4d0);
1869 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1872 __apicdebuginit(int) print_all_ICs(void)
1876 /* don't print out if apic is not there */
1877 if (!cpu_has_apic || disable_apic)
1880 print_all_local_APICs();
1886 fs_initcall(print_all_ICs);
1889 /* Where if anywhere is the i8259 connect in external int mode */
1890 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1892 void __init enable_IO_APIC(void)
1894 union IO_APIC_reg_01 reg_01;
1895 int i8259_apic, i8259_pin;
1897 unsigned long flags;
1900 * The number of IO-APIC IRQ registers (== #pins):
1902 for (apic = 0; apic < nr_ioapics; apic++) {
1903 spin_lock_irqsave(&ioapic_lock, flags);
1904 reg_01.raw = io_apic_read(apic, 1);
1905 spin_unlock_irqrestore(&ioapic_lock, flags);
1906 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1908 for(apic = 0; apic < nr_ioapics; apic++) {
1910 /* See if any of the pins is in ExtINT mode */
1911 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1912 struct IO_APIC_route_entry entry;
1913 entry = ioapic_read_entry(apic, pin);
1915 /* If the interrupt line is enabled and in ExtInt mode
1916 * I have found the pin where the i8259 is connected.
1918 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1919 ioapic_i8259.apic = apic;
1920 ioapic_i8259.pin = pin;
1926 /* Look to see what if the MP table has reported the ExtINT */
1927 /* If we could not find the appropriate pin by looking at the ioapic
1928 * the i8259 probably is not connected the ioapic but give the
1929 * mptable a chance anyway.
1931 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1932 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1933 /* Trust the MP table if nothing is setup in the hardware */
1934 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1935 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1936 ioapic_i8259.pin = i8259_pin;
1937 ioapic_i8259.apic = i8259_apic;
1939 /* Complain if the MP table and the hardware disagree */
1940 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1941 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1943 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1947 * Do not trust the IO-APIC being empty at bootup
1953 * Not an __init, needed by the reboot code
1955 void disable_IO_APIC(void)
1958 * Clear the IO-APIC before rebooting:
1963 * If the i8259 is routed through an IOAPIC
1964 * Put that IOAPIC in virtual wire mode
1965 * so legacy interrupts can be delivered.
1967 * With interrupt-remapping, for now we will use virtual wire A mode,
1968 * as virtual wire B is little complex (need to configure both
1969 * IOAPIC RTE aswell as interrupt-remapping table entry).
1970 * As this gets called during crash dump, keep this simple for now.
1972 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1973 struct IO_APIC_route_entry entry;
1975 memset(&entry, 0, sizeof(entry));
1976 entry.mask = 0; /* Enabled */
1977 entry.trigger = 0; /* Edge */
1979 entry.polarity = 0; /* High */
1980 entry.delivery_status = 0;
1981 entry.dest_mode = 0; /* Physical */
1982 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1984 entry.dest = read_apic_id();
1987 * Add it to the IO-APIC irq-routing table:
1989 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1993 * Use virtual wire A mode when interrupt remapping is enabled.
1996 disconnect_bsp_APIC(!intr_remapping_enabled &&
1997 ioapic_i8259.pin != -1);
2000 #ifdef CONFIG_X86_32
2002 * function to set the IO-APIC physical IDs based on the
2003 * values stored in the MPC table.
2005 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2008 static void __init setup_ioapic_ids_from_mpc(void)
2010 union IO_APIC_reg_00 reg_00;
2011 physid_mask_t phys_id_present_map;
2014 unsigned char old_id;
2015 unsigned long flags;
2017 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2021 * Don't check I/O APIC IDs for xAPIC systems. They have
2022 * no meaning without the serial APIC bus.
2024 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2025 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2028 * This is broken; anything with a real cpu count has to
2029 * circumvent this idiocy regardless.
2031 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2034 * Set the IOAPIC ID to the value stored in the MPC table.
2036 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2038 /* Read the register 0 value */
2039 spin_lock_irqsave(&ioapic_lock, flags);
2040 reg_00.raw = io_apic_read(apic_id, 0);
2041 spin_unlock_irqrestore(&ioapic_lock, flags);
2043 old_id = mp_ioapics[apic_id].apicid;
2045 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2046 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2047 apic_id, mp_ioapics[apic_id].apicid);
2048 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2050 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2054 * Sanity check, is the ID really free? Every APIC in a
2055 * system must have a unique ID or we get lots of nice
2056 * 'stuck on smp_invalidate_needed IPI wait' messages.
2058 if (apic->check_apicid_used(phys_id_present_map,
2059 mp_ioapics[apic_id].apicid)) {
2060 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2061 apic_id, mp_ioapics[apic_id].apicid);
2062 for (i = 0; i < get_physical_broadcast(); i++)
2063 if (!physid_isset(i, phys_id_present_map))
2065 if (i >= get_physical_broadcast())
2066 panic("Max APIC ID exceeded!\n");
2067 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2069 physid_set(i, phys_id_present_map);
2070 mp_ioapics[apic_id].apicid = i;
2073 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2074 apic_printk(APIC_VERBOSE, "Setting %d in the "
2075 "phys_id_present_map\n",
2076 mp_ioapics[apic_id].apicid);
2077 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2082 * We need to adjust the IRQ routing table
2083 * if the ID changed.
2085 if (old_id != mp_ioapics[apic_id].apicid)
2086 for (i = 0; i < mp_irq_entries; i++)
2087 if (mp_irqs[i].dstapic == old_id)
2089 = mp_ioapics[apic_id].apicid;
2092 * Read the right value from the MPC table and
2093 * write it into the ID register.
2095 apic_printk(APIC_VERBOSE, KERN_INFO
2096 "...changing IO-APIC physical APIC ID to %d ...",
2097 mp_ioapics[apic_id].apicid);
2099 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2100 spin_lock_irqsave(&ioapic_lock, flags);
2101 io_apic_write(apic_id, 0, reg_00.raw);
2102 spin_unlock_irqrestore(&ioapic_lock, flags);
2107 spin_lock_irqsave(&ioapic_lock, flags);
2108 reg_00.raw = io_apic_read(apic_id, 0);
2109 spin_unlock_irqrestore(&ioapic_lock, flags);
2110 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2111 printk("could not set ID!\n");
2113 apic_printk(APIC_VERBOSE, " ok.\n");
2118 int no_timer_check __initdata;
2120 static int __init notimercheck(char *s)
2125 __setup("no_timer_check", notimercheck);
2128 * There is a nasty bug in some older SMP boards, their mptable lies
2129 * about the timer IRQ. We do the following to work around the situation:
2131 * - timer IRQ defaults to IO-APIC IRQ
2132 * - if this function detects that timer IRQs are defunct, then we fall
2133 * back to ISA timer IRQs
2135 static int __init timer_irq_works(void)
2137 unsigned long t1 = jiffies;
2138 unsigned long flags;
2143 local_save_flags(flags);
2145 /* Let ten ticks pass... */
2146 mdelay((10 * 1000) / HZ);
2147 local_irq_restore(flags);
2150 * Expect a few ticks at least, to be sure some possible
2151 * glue logic does not lock up after one or two first
2152 * ticks in a non-ExtINT mode. Also the local APIC
2153 * might have cached one ExtINT interrupt. Finally, at
2154 * least one tick may be lost due to delays.
2158 if (time_after(jiffies, t1 + 4))
2164 * In the SMP+IOAPIC case it might happen that there are an unspecified
2165 * number of pending IRQ events unhandled. These cases are very rare,
2166 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2167 * better to do it this way as thus we do not have to be aware of
2168 * 'pending' interrupts in the IRQ path, except at this point.
2171 * Edge triggered needs to resend any interrupt
2172 * that was delayed but this is now handled in the device
2177 * Starting up a edge-triggered IO-APIC interrupt is
2178 * nasty - we need to make sure that we get the edge.
2179 * If it is already asserted for some reason, we need
2180 * return 1 to indicate that is was pending.
2182 * This is not complete - we should be able to fake
2183 * an edge even if it isn't on the 8259A...
2186 static unsigned int startup_ioapic_irq(unsigned int irq)
2188 int was_pending = 0;
2189 unsigned long flags;
2190 struct irq_cfg *cfg;
2192 spin_lock_irqsave(&ioapic_lock, flags);
2193 if (irq < NR_IRQS_LEGACY) {
2194 disable_8259A_irq(irq);
2195 if (i8259A_irq_pending(irq))
2199 __unmask_IO_APIC_irq(cfg);
2200 spin_unlock_irqrestore(&ioapic_lock, flags);
2205 #ifdef CONFIG_X86_64
2206 static int ioapic_retrigger_irq(unsigned int irq)
2209 struct irq_cfg *cfg = irq_cfg(irq);
2210 unsigned long flags;
2212 spin_lock_irqsave(&vector_lock, flags);
2213 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2214 spin_unlock_irqrestore(&vector_lock, flags);
2219 static int ioapic_retrigger_irq(unsigned int irq)
2221 apic->send_IPI_self(irq_cfg(irq)->vector);
2228 * Level and edge triggered IO-APIC interrupts need different handling,
2229 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2230 * handled with the level-triggered descriptor, but that one has slightly
2231 * more overhead. Level-triggered interrupts cannot be handled with the
2232 * edge-triggered handler, without risking IRQ storms and other ugly
2237 static void send_cleanup_vector(struct irq_cfg *cfg)
2239 cpumask_var_t cleanup_mask;
2241 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2243 cfg->move_cleanup_count = 0;
2244 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2245 cfg->move_cleanup_count++;
2246 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2247 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2249 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2250 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2251 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2252 free_cpumask_var(cleanup_mask);
2254 cfg->move_in_progress = 0;
2257 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2260 struct irq_pin_list *entry;
2261 u8 vector = cfg->vector;
2263 entry = cfg->irq_2_pin;
2273 * With interrupt-remapping, destination information comes
2274 * from interrupt-remapping table entry.
2276 if (!irq_remapped(irq))
2277 io_apic_write(apic, 0x11 + pin*2, dest);
2278 reg = io_apic_read(apic, 0x10 + pin*2);
2279 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2281 io_apic_modify(apic, 0x10 + pin*2, reg);
2284 entry = entry->next;
2289 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2292 * Either sets desc->affinity to a valid value, and returns
2293 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2294 * leaves desc->affinity untouched.
2297 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2299 struct irq_cfg *cfg;
2302 if (!cpumask_intersects(mask, cpu_online_mask))
2306 cfg = desc->chip_data;
2307 if (assign_irq_vector(irq, cfg, mask))
2310 cpumask_copy(desc->affinity, mask);
2312 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2316 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2318 struct irq_cfg *cfg;
2319 unsigned long flags;
2325 cfg = desc->chip_data;
2327 spin_lock_irqsave(&ioapic_lock, flags);
2328 dest = set_desc_affinity(desc, mask);
2329 if (dest != BAD_APICID) {
2330 /* Only the high 8 bits are valid. */
2331 dest = SET_APIC_LOGICAL_ID(dest);
2332 __target_IO_APIC_irq(irq, dest, cfg);
2335 spin_unlock_irqrestore(&ioapic_lock, flags);
2341 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2343 struct irq_desc *desc;
2345 desc = irq_to_desc(irq);
2347 return set_ioapic_affinity_irq_desc(desc, mask);
2350 #ifdef CONFIG_INTR_REMAP
2353 * Migrate the IO-APIC irq in the presence of intr-remapping.
2355 * For both level and edge triggered, irq migration is a simple atomic
2356 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2358 * For level triggered, we eliminate the io-apic RTE modification (with the
2359 * updated vector information), by using a virtual vector (io-apic pin number).
2360 * Real vector that is used for interrupting cpu will be coming from
2361 * the interrupt-remapping table entry.
2364 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2366 struct irq_cfg *cfg;
2372 if (!cpumask_intersects(mask, cpu_online_mask))
2376 if (get_irte(irq, &irte))
2379 cfg = desc->chip_data;
2380 if (assign_irq_vector(irq, cfg, mask))
2383 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2385 irte.vector = cfg->vector;
2386 irte.dest_id = IRTE_DEST(dest);
2389 * Modified the IRTE and flushes the Interrupt entry cache.
2391 modify_irte(irq, &irte);
2393 if (cfg->move_in_progress)
2394 send_cleanup_vector(cfg);
2396 cpumask_copy(desc->affinity, mask);
2402 * Migrates the IRQ destination in the process context.
2404 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2405 const struct cpumask *mask)
2407 return migrate_ioapic_irq_desc(desc, mask);
2409 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2410 const struct cpumask *mask)
2412 struct irq_desc *desc = irq_to_desc(irq);
2414 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2417 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2418 const struct cpumask *mask)
2424 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2426 unsigned vector, me;
2432 me = smp_processor_id();
2433 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2436 struct irq_desc *desc;
2437 struct irq_cfg *cfg;
2438 irq = __get_cpu_var(vector_irq)[vector];
2443 desc = irq_to_desc(irq);
2448 spin_lock(&desc->lock);
2449 if (!cfg->move_cleanup_count)
2452 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2455 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2457 * Check if the vector that needs to be cleanedup is
2458 * registered at the cpu's IRR. If so, then this is not
2459 * the best time to clean it up. Lets clean it up in the
2460 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2463 if (irr & (1 << (vector % 32))) {
2464 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2467 __get_cpu_var(vector_irq)[vector] = -1;
2468 cfg->move_cleanup_count--;
2470 spin_unlock(&desc->lock);
2476 static void irq_complete_move(struct irq_desc **descp)
2478 struct irq_desc *desc = *descp;
2479 struct irq_cfg *cfg = desc->chip_data;
2480 unsigned vector, me;
2482 if (likely(!cfg->move_in_progress))
2485 vector = ~get_irq_regs()->orig_ax;
2486 me = smp_processor_id();
2488 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2489 send_cleanup_vector(cfg);
2492 static inline void irq_complete_move(struct irq_desc **descp) {}
2495 static void ack_apic_edge(unsigned int irq)
2497 struct irq_desc *desc = irq_to_desc(irq);
2499 irq_complete_move(&desc);
2500 move_native_irq(irq);
2504 atomic_t irq_mis_count;
2506 static void ack_apic_level(unsigned int irq)
2508 struct irq_desc *desc = irq_to_desc(irq);
2511 struct irq_cfg *cfg;
2512 int do_unmask_irq = 0;
2514 irq_complete_move(&desc);
2515 #ifdef CONFIG_GENERIC_PENDING_IRQ
2516 /* If we are moving the irq we need to mask it */
2517 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2519 mask_IO_APIC_irq_desc(desc);
2524 * It appears there is an erratum which affects at least version 0x11
2525 * of I/O APIC (that's the 82093AA and cores integrated into various
2526 * chipsets). Under certain conditions a level-triggered interrupt is
2527 * erroneously delivered as edge-triggered one but the respective IRR
2528 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2529 * message but it will never arrive and further interrupts are blocked
2530 * from the source. The exact reason is so far unknown, but the
2531 * phenomenon was observed when two consecutive interrupt requests
2532 * from a given source get delivered to the same CPU and the source is
2533 * temporarily disabled in between.
2535 * A workaround is to simulate an EOI message manually. We achieve it
2536 * by setting the trigger mode to edge and then to level when the edge
2537 * trigger mode gets detected in the TMR of a local APIC for a
2538 * level-triggered interrupt. We mask the source for the time of the
2539 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2540 * The idea is from Manfred Spraul. --macro
2542 cfg = desc->chip_data;
2544 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2547 * We must acknowledge the irq before we move it or the acknowledge will
2548 * not propagate properly.
2552 /* Now we can move and renable the irq */
2553 if (unlikely(do_unmask_irq)) {
2554 /* Only migrate the irq if the ack has been received.
2556 * On rare occasions the broadcast level triggered ack gets
2557 * delayed going to ioapics, and if we reprogram the
2558 * vector while Remote IRR is still set the irq will never
2561 * To prevent this scenario we read the Remote IRR bit
2562 * of the ioapic. This has two effects.
2563 * - On any sane system the read of the ioapic will
2564 * flush writes (and acks) going to the ioapic from
2566 * - We get to see if the ACK has actually been delivered.
2568 * Based on failed experiments of reprogramming the
2569 * ioapic entry from outside of irq context starting
2570 * with masking the ioapic entry and then polling until
2571 * Remote IRR was clear before reprogramming the
2572 * ioapic I don't trust the Remote IRR bit to be
2573 * completey accurate.
2575 * However there appears to be no other way to plug
2576 * this race, so if the Remote IRR bit is not
2577 * accurate and is causing problems then it is a hardware bug
2578 * and you can go talk to the chipset vendor about it.
2580 cfg = desc->chip_data;
2581 if (!io_apic_level_ack_pending(cfg))
2582 move_masked_irq(irq);
2583 unmask_IO_APIC_irq_desc(desc);
2586 /* Tail end of version 0x11 I/O APIC bug workaround */
2587 if (!(v & (1 << (i & 0x1f)))) {
2588 atomic_inc(&irq_mis_count);
2589 spin_lock(&ioapic_lock);
2590 __mask_and_edge_IO_APIC_irq(cfg);
2591 __unmask_and_level_IO_APIC_irq(cfg);
2592 spin_unlock(&ioapic_lock);
2596 #ifdef CONFIG_INTR_REMAP
2597 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2600 struct irq_pin_list *entry;
2602 entry = cfg->irq_2_pin;
2610 io_apic_eoi(apic, pin);
2611 entry = entry->next;
2616 eoi_ioapic_irq(struct irq_desc *desc)
2618 struct irq_cfg *cfg;
2619 unsigned long flags;
2623 cfg = desc->chip_data;
2625 spin_lock_irqsave(&ioapic_lock, flags);
2626 __eoi_ioapic_irq(irq, cfg);
2627 spin_unlock_irqrestore(&ioapic_lock, flags);
2630 static void ir_ack_apic_edge(unsigned int irq)
2635 static void ir_ack_apic_level(unsigned int irq)
2637 struct irq_desc *desc = irq_to_desc(irq);
2640 eoi_ioapic_irq(desc);
2642 #endif /* CONFIG_INTR_REMAP */
2644 static struct irq_chip ioapic_chip __read_mostly = {
2646 .startup = startup_ioapic_irq,
2647 .mask = mask_IO_APIC_irq,
2648 .unmask = unmask_IO_APIC_irq,
2649 .ack = ack_apic_edge,
2650 .eoi = ack_apic_level,
2652 .set_affinity = set_ioapic_affinity_irq,
2654 .retrigger = ioapic_retrigger_irq,
2657 static struct irq_chip ir_ioapic_chip __read_mostly = {
2658 .name = "IR-IO-APIC",
2659 .startup = startup_ioapic_irq,
2660 .mask = mask_IO_APIC_irq,
2661 .unmask = unmask_IO_APIC_irq,
2662 #ifdef CONFIG_INTR_REMAP
2663 .ack = ir_ack_apic_edge,
2664 .eoi = ir_ack_apic_level,
2666 .set_affinity = set_ir_ioapic_affinity_irq,
2669 .retrigger = ioapic_retrigger_irq,
2672 static inline void init_IO_APIC_traps(void)
2675 struct irq_desc *desc;
2676 struct irq_cfg *cfg;
2679 * NOTE! The local APIC isn't very good at handling
2680 * multiple interrupts at the same interrupt level.
2681 * As the interrupt level is determined by taking the
2682 * vector number and shifting that right by 4, we
2683 * want to spread these out a bit so that they don't
2684 * all fall in the same interrupt level.
2686 * Also, we've got to be careful not to trash gate
2687 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2689 for_each_irq_desc(irq, desc) {
2690 cfg = desc->chip_data;
2691 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2693 * Hmm.. We don't have an entry for this,
2694 * so default to an old-fashioned 8259
2695 * interrupt if we can..
2697 if (irq < NR_IRQS_LEGACY)
2698 make_8259A_irq(irq);
2700 /* Strange. Oh, well.. */
2701 desc->chip = &no_irq_chip;
2707 * The local APIC irq-chip implementation:
2710 static void mask_lapic_irq(unsigned int irq)
2714 v = apic_read(APIC_LVT0);
2715 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2718 static void unmask_lapic_irq(unsigned int irq)
2722 v = apic_read(APIC_LVT0);
2723 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2726 static void ack_lapic_irq(unsigned int irq)
2731 static struct irq_chip lapic_chip __read_mostly = {
2732 .name = "local-APIC",
2733 .mask = mask_lapic_irq,
2734 .unmask = unmask_lapic_irq,
2735 .ack = ack_lapic_irq,
2738 static void lapic_register_intr(int irq, struct irq_desc *desc)
2740 desc->status &= ~IRQ_LEVEL;
2741 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2745 static void __init setup_nmi(void)
2748 * Dirty trick to enable the NMI watchdog ...
2749 * We put the 8259A master into AEOI mode and
2750 * unmask on all local APICs LVT0 as NMI.
2752 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2753 * is from Maciej W. Rozycki - so we do not have to EOI from
2754 * the NMI handler or the timer interrupt.
2756 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2758 enable_NMI_through_LVT0();
2760 apic_printk(APIC_VERBOSE, " done.\n");
2764 * This looks a bit hackish but it's about the only one way of sending
2765 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2766 * not support the ExtINT mode, unfortunately. We need to send these
2767 * cycles as some i82489DX-based boards have glue logic that keeps the
2768 * 8259A interrupt line asserted until INTA. --macro
2770 static inline void __init unlock_ExtINT_logic(void)
2773 struct IO_APIC_route_entry entry0, entry1;
2774 unsigned char save_control, save_freq_select;
2776 pin = find_isa_irq_pin(8, mp_INT);
2781 apic = find_isa_irq_apic(8, mp_INT);
2787 entry0 = ioapic_read_entry(apic, pin);
2788 clear_IO_APIC_pin(apic, pin);
2790 memset(&entry1, 0, sizeof(entry1));
2792 entry1.dest_mode = 0; /* physical delivery */
2793 entry1.mask = 0; /* unmask IRQ now */
2794 entry1.dest = hard_smp_processor_id();
2795 entry1.delivery_mode = dest_ExtINT;
2796 entry1.polarity = entry0.polarity;
2800 ioapic_write_entry(apic, pin, entry1);
2802 save_control = CMOS_READ(RTC_CONTROL);
2803 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2804 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2806 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2811 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2815 CMOS_WRITE(save_control, RTC_CONTROL);
2816 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2817 clear_IO_APIC_pin(apic, pin);
2819 ioapic_write_entry(apic, pin, entry0);
2822 static int disable_timer_pin_1 __initdata;
2823 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2824 static int __init disable_timer_pin_setup(char *arg)
2826 disable_timer_pin_1 = 1;
2829 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2831 int timer_through_8259 __initdata;
2834 * This code may look a bit paranoid, but it's supposed to cooperate with
2835 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2836 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2837 * fanatically on his truly buggy board.
2839 * FIXME: really need to revamp this for all platforms.
2841 static inline void __init check_timer(void)
2843 struct irq_desc *desc = irq_to_desc(0);
2844 struct irq_cfg *cfg = desc->chip_data;
2845 int node = cpu_to_node(boot_cpu_id);
2846 int apic1, pin1, apic2, pin2;
2847 unsigned long flags;
2850 local_irq_save(flags);
2853 * get/set the timer IRQ vector:
2855 disable_8259A_irq(0);
2856 assign_irq_vector(0, cfg, apic->target_cpus());
2859 * As IRQ0 is to be enabled in the 8259A, the virtual
2860 * wire has to be disabled in the local APIC. Also
2861 * timer interrupts need to be acknowledged manually in
2862 * the 8259A for the i82489DX when using the NMI
2863 * watchdog as that APIC treats NMIs as level-triggered.
2864 * The AEOI mode will finish them in the 8259A
2867 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2869 #ifdef CONFIG_X86_32
2873 ver = apic_read(APIC_LVR);
2874 ver = GET_APIC_VERSION(ver);
2875 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2879 pin1 = find_isa_irq_pin(0, mp_INT);
2880 apic1 = find_isa_irq_apic(0, mp_INT);
2881 pin2 = ioapic_i8259.pin;
2882 apic2 = ioapic_i8259.apic;
2884 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2885 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2886 cfg->vector, apic1, pin1, apic2, pin2);
2889 * Some BIOS writers are clueless and report the ExtINTA
2890 * I/O APIC input from the cascaded 8259A as the timer
2891 * interrupt input. So just in case, if only one pin
2892 * was found above, try it both directly and through the
2896 if (intr_remapping_enabled)
2897 panic("BIOS bug: timer not connected to IO-APIC");
2901 } else if (pin2 == -1) {
2908 * Ok, does IRQ0 through the IOAPIC work?
2911 add_pin_to_irq_node(cfg, node, apic1, pin1);
2912 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2914 /* for edge trigger, setup_IO_APIC_irq already
2915 * leave it unmasked.
2916 * so only need to unmask if it is level-trigger
2917 * do we really have level trigger timer?
2920 idx = find_irq_entry(apic1, pin1, mp_INT);
2921 if (idx != -1 && irq_trigger(idx))
2922 unmask_IO_APIC_irq_desc(desc);
2924 if (timer_irq_works()) {
2925 if (nmi_watchdog == NMI_IO_APIC) {
2927 enable_8259A_irq(0);
2929 if (disable_timer_pin_1 > 0)
2930 clear_IO_APIC_pin(0, pin1);
2933 if (intr_remapping_enabled)
2934 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2935 local_irq_disable();
2936 clear_IO_APIC_pin(apic1, pin1);
2938 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2939 "8254 timer not connected to IO-APIC\n");
2941 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2942 "(IRQ0) through the 8259A ...\n");
2943 apic_printk(APIC_QUIET, KERN_INFO
2944 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2946 * legacy devices should be connected to IO APIC #0
2948 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2949 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2950 enable_8259A_irq(0);
2951 if (timer_irq_works()) {
2952 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2953 timer_through_8259 = 1;
2954 if (nmi_watchdog == NMI_IO_APIC) {
2955 disable_8259A_irq(0);
2957 enable_8259A_irq(0);
2962 * Cleanup, just in case ...
2964 local_irq_disable();
2965 disable_8259A_irq(0);
2966 clear_IO_APIC_pin(apic2, pin2);
2967 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2970 if (nmi_watchdog == NMI_IO_APIC) {
2971 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2972 "through the IO-APIC - disabling NMI Watchdog!\n");
2973 nmi_watchdog = NMI_NONE;
2975 #ifdef CONFIG_X86_32
2979 apic_printk(APIC_QUIET, KERN_INFO
2980 "...trying to set up timer as Virtual Wire IRQ...\n");
2982 lapic_register_intr(0, desc);
2983 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2984 enable_8259A_irq(0);
2986 if (timer_irq_works()) {
2987 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2990 local_irq_disable();
2991 disable_8259A_irq(0);
2992 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2993 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2995 apic_printk(APIC_QUIET, KERN_INFO
2996 "...trying to set up timer as ExtINT IRQ...\n");
3000 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3002 unlock_ExtINT_logic();
3004 if (timer_irq_works()) {
3005 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3008 local_irq_disable();
3009 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3010 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3011 "report. Then try booting with the 'noapic' option.\n");
3013 local_irq_restore(flags);
3017 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3018 * to devices. However there may be an I/O APIC pin available for
3019 * this interrupt regardless. The pin may be left unconnected, but
3020 * typically it will be reused as an ExtINT cascade interrupt for
3021 * the master 8259A. In the MPS case such a pin will normally be
3022 * reported as an ExtINT interrupt in the MP table. With ACPI
3023 * there is no provision for ExtINT interrupts, and in the absence
3024 * of an override it would be treated as an ordinary ISA I/O APIC
3025 * interrupt, that is edge-triggered and unmasked by default. We
3026 * used to do this, but it caused problems on some systems because
3027 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3028 * the same ExtINT cascade interrupt to drive the local APIC of the
3029 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3030 * the I/O APIC in all cases now. No actual device should request
3031 * it anyway. --macro
3033 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3035 void __init setup_IO_APIC(void)
3039 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3042 io_apic_irqs = ~PIC_IRQS;
3044 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3046 * Set up IO-APIC IRQ routing.
3048 #ifdef CONFIG_X86_32
3050 setup_ioapic_ids_from_mpc();
3053 setup_IO_APIC_irqs();
3054 init_IO_APIC_traps();
3059 * Called after all the initialization is done. If we didnt find any
3060 * APIC bugs then we can allow the modify fast path
3063 static int __init io_apic_bug_finalize(void)
3065 if (sis_apic_bug == -1)
3070 late_initcall(io_apic_bug_finalize);
3072 struct sysfs_ioapic_data {
3073 struct sys_device dev;
3074 struct IO_APIC_route_entry entry[0];
3076 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3078 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3080 struct IO_APIC_route_entry *entry;
3081 struct sysfs_ioapic_data *data;
3084 data = container_of(dev, struct sysfs_ioapic_data, dev);
3085 entry = data->entry;
3086 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3087 *entry = ioapic_read_entry(dev->id, i);
3092 static int ioapic_resume(struct sys_device *dev)
3094 struct IO_APIC_route_entry *entry;
3095 struct sysfs_ioapic_data *data;
3096 unsigned long flags;
3097 union IO_APIC_reg_00 reg_00;
3100 data = container_of(dev, struct sysfs_ioapic_data, dev);
3101 entry = data->entry;
3103 spin_lock_irqsave(&ioapic_lock, flags);
3104 reg_00.raw = io_apic_read(dev->id, 0);
3105 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3106 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3107 io_apic_write(dev->id, 0, reg_00.raw);
3109 spin_unlock_irqrestore(&ioapic_lock, flags);
3110 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3111 ioapic_write_entry(dev->id, i, entry[i]);
3116 static struct sysdev_class ioapic_sysdev_class = {
3118 .suspend = ioapic_suspend,
3119 .resume = ioapic_resume,
3122 static int __init ioapic_init_sysfs(void)
3124 struct sys_device * dev;
3127 error = sysdev_class_register(&ioapic_sysdev_class);
3131 for (i = 0; i < nr_ioapics; i++ ) {
3132 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3133 * sizeof(struct IO_APIC_route_entry);
3134 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3135 if (!mp_ioapic_data[i]) {
3136 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3139 dev = &mp_ioapic_data[i]->dev;
3141 dev->cls = &ioapic_sysdev_class;
3142 error = sysdev_register(dev);
3144 kfree(mp_ioapic_data[i]);
3145 mp_ioapic_data[i] = NULL;
3146 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3154 device_initcall(ioapic_init_sysfs);
3156 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3158 * Dynamic irq allocate and deallocation
3160 unsigned int create_irq_nr(unsigned int irq_want, int node)
3162 /* Allocate an unused irq */
3165 unsigned long flags;
3166 struct irq_cfg *cfg_new = NULL;
3167 struct irq_desc *desc_new = NULL;
3170 if (irq_want < nr_irqs_gsi)
3171 irq_want = nr_irqs_gsi;
3173 spin_lock_irqsave(&vector_lock, flags);
3174 for (new = irq_want; new < nr_irqs; new++) {
3175 desc_new = irq_to_desc_alloc_node(new, node);
3177 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3180 cfg_new = desc_new->chip_data;
3182 if (cfg_new->vector != 0)
3185 desc_new = move_irq_desc(desc_new, node);
3187 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3191 spin_unlock_irqrestore(&vector_lock, flags);
3194 dynamic_irq_init(irq);
3195 /* restore it, in case dynamic_irq_init clear it */
3197 desc_new->chip_data = cfg_new;
3202 int create_irq(void)
3204 int node = cpu_to_node(boot_cpu_id);
3205 unsigned int irq_want;
3208 irq_want = nr_irqs_gsi;
3209 irq = create_irq_nr(irq_want, node);
3217 void destroy_irq(unsigned int irq)
3219 unsigned long flags;
3220 struct irq_cfg *cfg;
3221 struct irq_desc *desc;
3223 /* store it, in case dynamic_irq_cleanup clear it */
3224 desc = irq_to_desc(irq);
3225 cfg = desc->chip_data;
3226 dynamic_irq_cleanup(irq);
3227 /* connect back irq_cfg */
3229 desc->chip_data = cfg;
3232 spin_lock_irqsave(&vector_lock, flags);
3233 __clear_irq_vector(irq, cfg);
3234 spin_unlock_irqrestore(&vector_lock, flags);
3238 * MSI message composition
3240 #ifdef CONFIG_PCI_MSI
3241 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3243 struct irq_cfg *cfg;
3251 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3255 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3257 if (irq_remapped(irq)) {
3262 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3263 BUG_ON(ir_index == -1);
3265 memset (&irte, 0, sizeof(irte));
3268 irte.dst_mode = apic->irq_dest_mode;
3269 irte.trigger_mode = 0; /* edge */
3270 irte.dlvry_mode = apic->irq_delivery_mode;
3271 irte.vector = cfg->vector;
3272 irte.dest_id = IRTE_DEST(dest);
3274 /* Set source-id of interrupt request */
3275 set_msi_sid(&irte, pdev);
3277 modify_irte(irq, &irte);
3279 msg->address_hi = MSI_ADDR_BASE_HI;
3280 msg->data = sub_handle;
3281 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3283 MSI_ADDR_IR_INDEX1(ir_index) |
3284 MSI_ADDR_IR_INDEX2(ir_index);
3286 if (x2apic_enabled())
3287 msg->address_hi = MSI_ADDR_BASE_HI |
3288 MSI_ADDR_EXT_DEST_ID(dest);
3290 msg->address_hi = MSI_ADDR_BASE_HI;
3294 ((apic->irq_dest_mode == 0) ?
3295 MSI_ADDR_DEST_MODE_PHYSICAL:
3296 MSI_ADDR_DEST_MODE_LOGICAL) |
3297 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3298 MSI_ADDR_REDIRECTION_CPU:
3299 MSI_ADDR_REDIRECTION_LOWPRI) |
3300 MSI_ADDR_DEST_ID(dest);
3303 MSI_DATA_TRIGGER_EDGE |
3304 MSI_DATA_LEVEL_ASSERT |
3305 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3306 MSI_DATA_DELIVERY_FIXED:
3307 MSI_DATA_DELIVERY_LOWPRI) |
3308 MSI_DATA_VECTOR(cfg->vector);
3314 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3316 struct irq_desc *desc = irq_to_desc(irq);
3317 struct irq_cfg *cfg;
3321 dest = set_desc_affinity(desc, mask);
3322 if (dest == BAD_APICID)
3325 cfg = desc->chip_data;
3327 read_msi_msg_desc(desc, &msg);
3329 msg.data &= ~MSI_DATA_VECTOR_MASK;
3330 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3331 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3332 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3334 write_msi_msg_desc(desc, &msg);
3338 #ifdef CONFIG_INTR_REMAP
3340 * Migrate the MSI irq to another cpumask. This migration is
3341 * done in the process context using interrupt-remapping hardware.
3344 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3346 struct irq_desc *desc = irq_to_desc(irq);
3347 struct irq_cfg *cfg = desc->chip_data;
3351 if (get_irte(irq, &irte))
3354 dest = set_desc_affinity(desc, mask);
3355 if (dest == BAD_APICID)
3358 irte.vector = cfg->vector;
3359 irte.dest_id = IRTE_DEST(dest);
3362 * atomically update the IRTE with the new destination and vector.
3364 modify_irte(irq, &irte);
3367 * After this point, all the interrupts will start arriving
3368 * at the new destination. So, time to cleanup the previous
3369 * vector allocation.
3371 if (cfg->move_in_progress)
3372 send_cleanup_vector(cfg);
3378 #endif /* CONFIG_SMP */
3381 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3382 * which implement the MSI or MSI-X Capability Structure.
3384 static struct irq_chip msi_chip = {
3386 .unmask = unmask_msi_irq,
3387 .mask = mask_msi_irq,
3388 .ack = ack_apic_edge,
3390 .set_affinity = set_msi_irq_affinity,
3392 .retrigger = ioapic_retrigger_irq,
3395 static struct irq_chip msi_ir_chip = {
3396 .name = "IR-PCI-MSI",
3397 .unmask = unmask_msi_irq,
3398 .mask = mask_msi_irq,
3399 #ifdef CONFIG_INTR_REMAP
3400 .ack = ir_ack_apic_edge,
3402 .set_affinity = ir_set_msi_irq_affinity,
3405 .retrigger = ioapic_retrigger_irq,
3409 * Map the PCI dev to the corresponding remapping hardware unit
3410 * and allocate 'nvec' consecutive interrupt-remapping table entries
3413 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3415 struct intel_iommu *iommu;
3418 iommu = map_dev_to_ir(dev);
3421 "Unable to map PCI %s to iommu\n", pci_name(dev));
3425 index = alloc_irte(iommu, irq, nvec);
3428 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3435 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3440 ret = msi_compose_msg(dev, irq, &msg);
3444 set_irq_msi(irq, msidesc);
3445 write_msi_msg(irq, &msg);
3447 if (irq_remapped(irq)) {
3448 struct irq_desc *desc = irq_to_desc(irq);
3450 * irq migration in process context
3452 desc->status |= IRQ_MOVE_PCNTXT;
3453 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3455 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3457 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3462 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3465 int ret, sub_handle;
3466 struct msi_desc *msidesc;
3467 unsigned int irq_want;
3468 struct intel_iommu *iommu = NULL;
3472 /* x86 doesn't support multiple MSI yet */
3473 if (type == PCI_CAP_ID_MSI && nvec > 1)
3476 node = dev_to_node(&dev->dev);
3477 irq_want = nr_irqs_gsi;
3479 list_for_each_entry(msidesc, &dev->msi_list, list) {
3480 irq = create_irq_nr(irq_want, node);
3484 if (!intr_remapping_enabled)
3489 * allocate the consecutive block of IRTE's
3492 index = msi_alloc_irte(dev, irq, nvec);
3498 iommu = map_dev_to_ir(dev);
3504 * setup the mapping between the irq and the IRTE
3505 * base index, the sub_handle pointing to the
3506 * appropriate interrupt remap table entry.
3508 set_irte_irq(irq, iommu, index, sub_handle);
3511 ret = setup_msi_irq(dev, msidesc, irq);
3523 void arch_teardown_msi_irq(unsigned int irq)
3528 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3530 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3532 struct irq_desc *desc = irq_to_desc(irq);
3533 struct irq_cfg *cfg;
3537 dest = set_desc_affinity(desc, mask);
3538 if (dest == BAD_APICID)
3541 cfg = desc->chip_data;
3543 dmar_msi_read(irq, &msg);
3545 msg.data &= ~MSI_DATA_VECTOR_MASK;
3546 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3547 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3548 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3550 dmar_msi_write(irq, &msg);
3555 #endif /* CONFIG_SMP */
3557 static struct irq_chip dmar_msi_type = {
3559 .unmask = dmar_msi_unmask,
3560 .mask = dmar_msi_mask,
3561 .ack = ack_apic_edge,
3563 .set_affinity = dmar_msi_set_affinity,
3565 .retrigger = ioapic_retrigger_irq,
3568 int arch_setup_dmar_msi(unsigned int irq)
3573 ret = msi_compose_msg(NULL, irq, &msg);
3576 dmar_msi_write(irq, &msg);
3577 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3583 #ifdef CONFIG_HPET_TIMER
3586 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3588 struct irq_desc *desc = irq_to_desc(irq);
3589 struct irq_cfg *cfg;
3593 dest = set_desc_affinity(desc, mask);
3594 if (dest == BAD_APICID)
3597 cfg = desc->chip_data;
3599 hpet_msi_read(irq, &msg);
3601 msg.data &= ~MSI_DATA_VECTOR_MASK;
3602 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3603 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3604 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3606 hpet_msi_write(irq, &msg);
3611 #endif /* CONFIG_SMP */
3613 static struct irq_chip hpet_msi_type = {
3615 .unmask = hpet_msi_unmask,
3616 .mask = hpet_msi_mask,
3617 .ack = ack_apic_edge,
3619 .set_affinity = hpet_msi_set_affinity,
3621 .retrigger = ioapic_retrigger_irq,
3624 int arch_setup_hpet_msi(unsigned int irq)
3628 struct irq_desc *desc = irq_to_desc(irq);
3630 ret = msi_compose_msg(NULL, irq, &msg);
3634 hpet_msi_write(irq, &msg);
3635 desc->status |= IRQ_MOVE_PCNTXT;
3636 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3643 #endif /* CONFIG_PCI_MSI */
3645 * Hypertransport interrupt support
3647 #ifdef CONFIG_HT_IRQ
3651 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3653 struct ht_irq_msg msg;
3654 fetch_ht_irq_msg(irq, &msg);
3656 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3657 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3659 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3660 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3662 write_ht_irq_msg(irq, &msg);
3665 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3667 struct irq_desc *desc = irq_to_desc(irq);
3668 struct irq_cfg *cfg;
3671 dest = set_desc_affinity(desc, mask);
3672 if (dest == BAD_APICID)
3675 cfg = desc->chip_data;
3677 target_ht_irq(irq, dest, cfg->vector);
3684 static struct irq_chip ht_irq_chip = {
3686 .mask = mask_ht_irq,
3687 .unmask = unmask_ht_irq,
3688 .ack = ack_apic_edge,
3690 .set_affinity = set_ht_irq_affinity,
3692 .retrigger = ioapic_retrigger_irq,
3695 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3697 struct irq_cfg *cfg;
3704 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3706 struct ht_irq_msg msg;
3709 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3710 apic->target_cpus());
3712 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3716 HT_IRQ_LOW_DEST_ID(dest) |
3717 HT_IRQ_LOW_VECTOR(cfg->vector) |
3718 ((apic->irq_dest_mode == 0) ?
3719 HT_IRQ_LOW_DM_PHYSICAL :
3720 HT_IRQ_LOW_DM_LOGICAL) |
3721 HT_IRQ_LOW_RQEOI_EDGE |
3722 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3723 HT_IRQ_LOW_MT_FIXED :
3724 HT_IRQ_LOW_MT_ARBITRATED) |
3725 HT_IRQ_LOW_IRQ_MASKED;
3727 write_ht_irq_msg(irq, &msg);
3729 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3730 handle_edge_irq, "edge");
3732 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3736 #endif /* CONFIG_HT_IRQ */
3738 #ifdef CONFIG_X86_UV
3740 * Re-target the irq to the specified CPU and enable the specified MMR located
3741 * on the specified blade to allow the sending of MSIs to the specified CPU.
3743 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3744 unsigned long mmr_offset)
3746 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3747 struct irq_cfg *cfg;
3749 unsigned long mmr_value;
3750 struct uv_IO_APIC_route_entry *entry;
3751 unsigned long flags;
3754 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3758 err = assign_irq_vector(irq, cfg, eligible_cpu);
3762 spin_lock_irqsave(&vector_lock, flags);
3763 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3765 spin_unlock_irqrestore(&vector_lock, flags);
3768 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3769 entry->vector = cfg->vector;
3770 entry->delivery_mode = apic->irq_delivery_mode;
3771 entry->dest_mode = apic->irq_dest_mode;
3772 entry->polarity = 0;
3775 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3777 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3778 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3784 * Disable the specified MMR located on the specified blade so that MSIs are
3785 * longer allowed to be sent.
3787 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3789 unsigned long mmr_value;
3790 struct uv_IO_APIC_route_entry *entry;
3793 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3796 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3799 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3800 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3802 #endif /* CONFIG_X86_64 */
3804 int __init io_apic_get_redir_entries (int ioapic)
3806 union IO_APIC_reg_01 reg_01;
3807 unsigned long flags;
3809 spin_lock_irqsave(&ioapic_lock, flags);
3810 reg_01.raw = io_apic_read(ioapic, 1);
3811 spin_unlock_irqrestore(&ioapic_lock, flags);
3813 return reg_01.bits.entries;
3816 void __init probe_nr_irqs_gsi(void)
3820 nr = acpi_probe_gsi();
3821 if (nr > nr_irqs_gsi) {
3824 /* for acpi=off or acpi is not compiled in */
3828 for (idx = 0; idx < nr_ioapics; idx++)
3829 nr += io_apic_get_redir_entries(idx) + 1;
3831 if (nr > nr_irqs_gsi)
3835 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3838 #ifdef CONFIG_SPARSE_IRQ
3839 int __init arch_probe_nr_irqs(void)
3843 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3844 nr_irqs = NR_VECTORS * nr_cpu_ids;
3846 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3847 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3849 * for MSI and HT dyn irq
3851 nr += nr_irqs_gsi * 16;
3860 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3861 struct io_apic_irq_attr *irq_attr)
3863 struct irq_desc *desc;
3864 struct irq_cfg *cfg;
3867 int trigger, polarity;
3869 ioapic = irq_attr->ioapic;
3870 if (!IO_APIC_IRQ(irq)) {
3871 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3877 node = dev_to_node(dev);
3879 node = cpu_to_node(boot_cpu_id);
3881 desc = irq_to_desc_alloc_node(irq, node);
3883 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3887 pin = irq_attr->ioapic_pin;
3888 trigger = irq_attr->trigger;
3889 polarity = irq_attr->polarity;
3892 * IRQs < 16 are already in the irq_2_pin[] map
3894 if (irq >= NR_IRQS_LEGACY) {
3895 cfg = desc->chip_data;
3896 add_pin_to_irq_node(cfg, node, ioapic, pin);
3899 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3904 int io_apic_set_pci_routing(struct device *dev, int irq,
3905 struct io_apic_irq_attr *irq_attr)
3909 * Avoid pin reprogramming. PRTs typically include entries
3910 * with redundant pin->gsi mappings (but unique PCI devices);
3911 * we only program the IOAPIC on the first.
3913 ioapic = irq_attr->ioapic;
3914 pin = irq_attr->ioapic_pin;
3915 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3916 pr_debug("Pin %d-%d already programmed\n",
3917 mp_ioapics[ioapic].apicid, pin);
3920 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3922 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3925 /* --------------------------------------------------------------------------
3926 ACPI-based IOAPIC Configuration
3927 -------------------------------------------------------------------------- */
3931 #ifdef CONFIG_X86_32
3932 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3934 union IO_APIC_reg_00 reg_00;
3935 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3937 unsigned long flags;
3941 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3942 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3943 * supports up to 16 on one shared APIC bus.
3945 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3946 * advantage of new APIC bus architecture.
3949 if (physids_empty(apic_id_map))
3950 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3952 spin_lock_irqsave(&ioapic_lock, flags);
3953 reg_00.raw = io_apic_read(ioapic, 0);
3954 spin_unlock_irqrestore(&ioapic_lock, flags);
3956 if (apic_id >= get_physical_broadcast()) {
3957 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3958 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3959 apic_id = reg_00.bits.ID;
3963 * Every APIC in a system must have a unique ID or we get lots of nice
3964 * 'stuck on smp_invalidate_needed IPI wait' messages.
3966 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3968 for (i = 0; i < get_physical_broadcast(); i++) {
3969 if (!apic->check_apicid_used(apic_id_map, i))
3973 if (i == get_physical_broadcast())
3974 panic("Max apic_id exceeded!\n");
3976 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3977 "trying %d\n", ioapic, apic_id, i);
3982 tmp = apic->apicid_to_cpu_present(apic_id);
3983 physids_or(apic_id_map, apic_id_map, tmp);
3985 if (reg_00.bits.ID != apic_id) {
3986 reg_00.bits.ID = apic_id;
3988 spin_lock_irqsave(&ioapic_lock, flags);
3989 io_apic_write(ioapic, 0, reg_00.raw);
3990 reg_00.raw = io_apic_read(ioapic, 0);
3991 spin_unlock_irqrestore(&ioapic_lock, flags);
3994 if (reg_00.bits.ID != apic_id) {
3995 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4000 apic_printk(APIC_VERBOSE, KERN_INFO
4001 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4007 int __init io_apic_get_version(int ioapic)
4009 union IO_APIC_reg_01 reg_01;
4010 unsigned long flags;
4012 spin_lock_irqsave(&ioapic_lock, flags);
4013 reg_01.raw = io_apic_read(ioapic, 1);
4014 spin_unlock_irqrestore(&ioapic_lock, flags);
4016 return reg_01.bits.version;
4019 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4023 if (skip_ioapic_setup)
4026 for (i = 0; i < mp_irq_entries; i++)
4027 if (mp_irqs[i].irqtype == mp_INT &&
4028 mp_irqs[i].srcbusirq == bus_irq)
4030 if (i >= mp_irq_entries)
4033 *trigger = irq_trigger(i);
4034 *polarity = irq_polarity(i);
4038 #endif /* CONFIG_ACPI */
4041 * This function currently is only a helper for the i386 smp boot process where
4042 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4043 * so mask in all cases should simply be apic->target_cpus()
4046 void __init setup_ioapic_dest(void)
4048 int pin, ioapic = 0, irq, irq_entry;
4049 struct irq_desc *desc;
4050 const struct cpumask *mask;
4052 if (skip_ioapic_setup == 1)
4056 if (!acpi_disabled && acpi_ioapic) {
4057 ioapic = mp_find_ioapic(0);
4063 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4064 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4065 if (irq_entry == -1)
4067 irq = pin_2_irq(irq_entry, ioapic, pin);
4069 desc = irq_to_desc(irq);
4072 * Honour affinities which have been set in early boot
4075 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4076 mask = desc->affinity;
4078 mask = apic->target_cpus();
4080 if (intr_remapping_enabled)
4081 set_ir_ioapic_affinity_irq_desc(desc, mask);
4083 set_ioapic_affinity_irq_desc(desc, mask);
4089 #define IOAPIC_RESOURCE_NAME_SIZE 11
4091 static struct resource *ioapic_resources;
4093 static struct resource * __init ioapic_setup_resources(void)
4096 struct resource *res;
4100 if (nr_ioapics <= 0)
4103 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4106 mem = alloc_bootmem(n);
4110 mem += sizeof(struct resource) * nr_ioapics;
4112 for (i = 0; i < nr_ioapics; i++) {
4114 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4115 sprintf(mem, "IOAPIC %u", i);
4116 mem += IOAPIC_RESOURCE_NAME_SIZE;
4120 ioapic_resources = res;
4125 void __init ioapic_init_mappings(void)
4127 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4128 struct resource *ioapic_res;
4131 ioapic_res = ioapic_setup_resources();
4132 for (i = 0; i < nr_ioapics; i++) {
4133 if (smp_found_config) {
4134 ioapic_phys = mp_ioapics[i].apicaddr;
4135 #ifdef CONFIG_X86_32
4138 "WARNING: bogus zero IO-APIC "
4139 "address found in MPTABLE, "
4140 "disabling IO/APIC support!\n");
4141 smp_found_config = 0;
4142 skip_ioapic_setup = 1;
4143 goto fake_ioapic_page;
4147 #ifdef CONFIG_X86_32
4150 ioapic_phys = (unsigned long)
4151 alloc_bootmem_pages(PAGE_SIZE);
4152 ioapic_phys = __pa(ioapic_phys);
4154 set_fixmap_nocache(idx, ioapic_phys);
4155 apic_printk(APIC_VERBOSE,
4156 "mapped IOAPIC to %08lx (%08lx)\n",
4157 __fix_to_virt(idx), ioapic_phys);
4160 if (ioapic_res != NULL) {
4161 ioapic_res->start = ioapic_phys;
4162 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4168 static int __init ioapic_insert_resources(void)
4171 struct resource *r = ioapic_resources;
4174 if (nr_ioapics > 0) {
4176 "IO APIC resources couldn't be allocated.\n");
4182 for (i = 0; i < nr_ioapics; i++) {
4183 insert_resource(&iomem_resource, r);
4190 /* Insert the IO APIC resources after PCI initialization has occured to handle
4191 * IO APICS that are mapped in on a BAR in PCI space. */
4192 late_initcall(ioapic_insert_resources);