2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
94 /* # of MP IRQ source entries */
98 static int nr_irqs_gsi = NR_IRQS_LEGACY;
100 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
101 int mp_bus_id_to_type[MAX_MP_BUSSES];
104 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
106 int skip_ioapic_setup;
108 void arch_disable_smp_support(void)
112 noioapicreroute = -1;
114 skip_ioapic_setup = 1;
117 static int __init parse_noapic(char *str)
119 /* disable IO-APIC */
120 arch_disable_smp_support();
123 early_param("noapic", parse_noapic);
125 struct irq_pin_list {
127 struct irq_pin_list *next;
130 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
132 struct irq_pin_list *pin;
134 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
139 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
140 #ifdef CONFIG_SPARSE_IRQ
141 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
143 static struct irq_cfg irq_cfgx[NR_IRQS];
146 void __init io_apic_disable_legacy(void)
152 int __init arch_early_irq_init(void)
155 struct irq_desc *desc;
161 count = ARRAY_SIZE(irq_cfgx);
162 node= cpu_to_node(boot_cpu_id);
164 for (i = 0; i < count; i++) {
165 desc = irq_to_desc(i);
166 desc->chip_data = &cfg[i];
167 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
168 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
170 * For legacy IRQ's, start with assigning irq0 to irq15 to
171 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
173 if (i < nr_legacy_irqs) {
174 cfg[i].vector = IRQ0_VECTOR + i;
175 cpumask_set_cpu(0, cfg[i].domain);
182 #ifdef CONFIG_SPARSE_IRQ
183 struct irq_cfg *irq_cfg(unsigned int irq)
185 struct irq_cfg *cfg = NULL;
186 struct irq_desc *desc;
188 desc = irq_to_desc(irq);
190 cfg = desc->chip_data;
195 static struct irq_cfg *get_one_free_irq_cfg(int node)
199 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
201 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
204 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
206 free_cpumask_var(cfg->domain);
215 int arch_init_chip_data(struct irq_desc *desc, int node)
219 cfg = desc->chip_data;
221 desc->chip_data = get_one_free_irq_cfg(node);
222 if (!desc->chip_data) {
223 printk(KERN_ERR "can not alloc irq_cfg\n");
231 /* for move_irq_desc */
233 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
235 struct irq_pin_list *old_entry, *head, *tail, *entry;
237 cfg->irq_2_pin = NULL;
238 old_entry = old_cfg->irq_2_pin;
242 entry = get_one_free_irq_2_pin(node);
246 entry->apic = old_entry->apic;
247 entry->pin = old_entry->pin;
250 old_entry = old_entry->next;
252 entry = get_one_free_irq_2_pin(node);
260 /* still use the old one */
263 entry->apic = old_entry->apic;
264 entry->pin = old_entry->pin;
267 old_entry = old_entry->next;
271 cfg->irq_2_pin = head;
274 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
276 struct irq_pin_list *entry, *next;
278 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
281 entry = old_cfg->irq_2_pin;
288 old_cfg->irq_2_pin = NULL;
291 void arch_init_copy_chip_data(struct irq_desc *old_desc,
292 struct irq_desc *desc, int node)
295 struct irq_cfg *old_cfg;
297 cfg = get_one_free_irq_cfg(node);
302 desc->chip_data = cfg;
304 old_cfg = old_desc->chip_data;
306 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
308 init_copy_irq_2_pin(old_cfg, cfg, node);
311 static void free_irq_cfg(struct irq_cfg *old_cfg)
316 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
318 struct irq_cfg *old_cfg, *cfg;
320 old_cfg = old_desc->chip_data;
321 cfg = desc->chip_data;
327 free_irq_2_pin(old_cfg, cfg);
328 free_irq_cfg(old_cfg);
329 old_desc->chip_data = NULL;
332 /* end for move_irq_desc */
335 struct irq_cfg *irq_cfg(unsigned int irq)
337 return irq < nr_irqs ? irq_cfgx + irq : NULL;
344 unsigned int unused[3];
346 unsigned int unused2[11];
350 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
352 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
353 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
356 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
358 struct io_apic __iomem *io_apic = io_apic_base(apic);
359 writel(vector, &io_apic->eoi);
362 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
364 struct io_apic __iomem *io_apic = io_apic_base(apic);
365 writel(reg, &io_apic->index);
366 return readl(&io_apic->data);
369 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
371 struct io_apic __iomem *io_apic = io_apic_base(apic);
372 writel(reg, &io_apic->index);
373 writel(value, &io_apic->data);
377 * Re-write a value: to be used for read-modify-write
378 * cycles where the read already set up the index register.
380 * Older SiS APIC requires we rewrite the index register
382 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
387 writel(reg, &io_apic->index);
388 writel(value, &io_apic->data);
391 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
393 struct irq_pin_list *entry;
396 raw_spin_lock_irqsave(&ioapic_lock, flags);
397 for_each_irq_pin(entry, cfg->irq_2_pin) {
402 reg = io_apic_read(entry->apic, 0x10 + pin*2);
403 /* Is the remote IRR bit set? */
404 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
405 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
409 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
415 struct { u32 w1, w2; };
416 struct IO_APIC_route_entry entry;
419 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
421 union entry_union eu;
423 raw_spin_lock_irqsave(&ioapic_lock, flags);
424 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
425 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
426 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
431 * When we write a new IO APIC routing entry, we need to write the high
432 * word first! If the mask bit in the low word is clear, we will enable
433 * the interrupt, and we need to make sure the entry is fully populated
434 * before that happens.
437 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
439 union entry_union eu = {{0, 0}};
442 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
443 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
446 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
449 raw_spin_lock_irqsave(&ioapic_lock, flags);
450 __ioapic_write_entry(apic, pin, e);
451 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
455 * When we mask an IO APIC routing entry, we need to write the low
456 * word first, in order to set the mask bit before we change the
459 static void ioapic_mask_entry(int apic, int pin)
462 union entry_union eu = { .entry.mask = 1 };
464 raw_spin_lock_irqsave(&ioapic_lock, flags);
465 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
466 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
467 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
471 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
472 * shared ISA-space IRQs, so we have to support them. We are super
473 * fast in the common case, and fast for shared ISA-space IRQs.
476 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
478 struct irq_pin_list **last, *entry;
480 /* don't allow duplicates */
481 last = &cfg->irq_2_pin;
482 for_each_irq_pin(entry, cfg->irq_2_pin) {
483 if (entry->apic == apic && entry->pin == pin)
488 entry = get_one_free_irq_2_pin(node);
490 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
501 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
503 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
504 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
508 * Reroute an IRQ to a different pin.
510 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
511 int oldapic, int oldpin,
512 int newapic, int newpin)
514 struct irq_pin_list *entry;
516 for_each_irq_pin(entry, cfg->irq_2_pin) {
517 if (entry->apic == oldapic && entry->pin == oldpin) {
518 entry->apic = newapic;
520 /* every one is different, right? */
525 /* old apic/pin didn't exist, so just add new ones */
526 add_pin_to_irq_node(cfg, node, newapic, newpin);
529 static void __io_apic_modify_irq(struct irq_pin_list *entry,
530 int mask_and, int mask_or,
531 void (*final)(struct irq_pin_list *entry))
533 unsigned int reg, pin;
536 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
539 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
544 static void io_apic_modify_irq(struct irq_cfg *cfg,
545 int mask_and, int mask_or,
546 void (*final)(struct irq_pin_list *entry))
548 struct irq_pin_list *entry;
550 for_each_irq_pin(entry, cfg->irq_2_pin)
551 __io_apic_modify_irq(entry, mask_and, mask_or, final);
554 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
556 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
557 IO_APIC_REDIR_MASKED, NULL);
560 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
562 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
563 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
566 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
568 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
571 static void io_apic_sync(struct irq_pin_list *entry)
574 * Synchronize the IO-APIC and the CPU by doing
575 * a dummy read from the IO-APIC
577 struct io_apic __iomem *io_apic;
578 io_apic = io_apic_base(entry->apic);
579 readl(&io_apic->data);
582 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
584 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
587 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
589 struct irq_cfg *cfg = desc->chip_data;
594 raw_spin_lock_irqsave(&ioapic_lock, flags);
595 __mask_IO_APIC_irq(cfg);
596 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
599 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
601 struct irq_cfg *cfg = desc->chip_data;
604 raw_spin_lock_irqsave(&ioapic_lock, flags);
605 __unmask_IO_APIC_irq(cfg);
606 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
609 static void mask_IO_APIC_irq(unsigned int irq)
611 struct irq_desc *desc = irq_to_desc(irq);
613 mask_IO_APIC_irq_desc(desc);
615 static void unmask_IO_APIC_irq(unsigned int irq)
617 struct irq_desc *desc = irq_to_desc(irq);
619 unmask_IO_APIC_irq_desc(desc);
622 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
624 struct IO_APIC_route_entry entry;
626 /* Check delivery_mode to be sure we're not clearing an SMI pin */
627 entry = ioapic_read_entry(apic, pin);
628 if (entry.delivery_mode == dest_SMI)
631 * Disable it in the IO-APIC irq-routing table:
633 ioapic_mask_entry(apic, pin);
636 static void clear_IO_APIC (void)
640 for (apic = 0; apic < nr_ioapics; apic++)
641 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
642 clear_IO_APIC_pin(apic, pin);
647 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
648 * specific CPU-side IRQs.
652 static int pirq_entries[MAX_PIRQS] = {
653 [0 ... MAX_PIRQS - 1] = -1
656 static int __init ioapic_pirq_setup(char *str)
659 int ints[MAX_PIRQS+1];
661 get_options(str, ARRAY_SIZE(ints), ints);
663 apic_printk(APIC_VERBOSE, KERN_INFO
664 "PIRQ redirection, working around broken MP-BIOS.\n");
666 if (ints[0] < MAX_PIRQS)
669 for (i = 0; i < max; i++) {
670 apic_printk(APIC_VERBOSE, KERN_DEBUG
671 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
673 * PIRQs are mapped upside down, usually.
675 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
680 __setup("pirq=", ioapic_pirq_setup);
681 #endif /* CONFIG_X86_32 */
683 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
686 struct IO_APIC_route_entry **ioapic_entries;
688 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
693 for (apic = 0; apic < nr_ioapics; apic++) {
694 ioapic_entries[apic] =
695 kzalloc(sizeof(struct IO_APIC_route_entry) *
696 nr_ioapic_registers[apic], GFP_ATOMIC);
697 if (!ioapic_entries[apic])
701 return ioapic_entries;
705 kfree(ioapic_entries[apic]);
706 kfree(ioapic_entries);
712 * Saves all the IO-APIC RTE's
714 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
721 for (apic = 0; apic < nr_ioapics; apic++) {
722 if (!ioapic_entries[apic])
725 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
726 ioapic_entries[apic][pin] =
727 ioapic_read_entry(apic, pin);
734 * Mask all IO APIC entries.
736 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
743 for (apic = 0; apic < nr_ioapics; apic++) {
744 if (!ioapic_entries[apic])
747 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
748 struct IO_APIC_route_entry entry;
750 entry = ioapic_entries[apic][pin];
753 ioapic_write_entry(apic, pin, entry);
760 * Restore IO APIC entries which was saved in ioapic_entries.
762 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
769 for (apic = 0; apic < nr_ioapics; apic++) {
770 if (!ioapic_entries[apic])
773 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
774 ioapic_write_entry(apic, pin,
775 ioapic_entries[apic][pin]);
780 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
784 for (apic = 0; apic < nr_ioapics; apic++)
785 kfree(ioapic_entries[apic]);
787 kfree(ioapic_entries);
791 * Find the IRQ entry number of a certain pin.
793 static int find_irq_entry(int apic, int pin, int type)
797 for (i = 0; i < mp_irq_entries; i++)
798 if (mp_irqs[i].irqtype == type &&
799 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
800 mp_irqs[i].dstapic == MP_APIC_ALL) &&
801 mp_irqs[i].dstirq == pin)
808 * Find the pin to which IRQ[irq] (ISA) is connected
810 static int __init find_isa_irq_pin(int irq, int type)
814 for (i = 0; i < mp_irq_entries; i++) {
815 int lbus = mp_irqs[i].srcbus;
817 if (test_bit(lbus, mp_bus_not_pci) &&
818 (mp_irqs[i].irqtype == type) &&
819 (mp_irqs[i].srcbusirq == irq))
821 return mp_irqs[i].dstirq;
826 static int __init find_isa_irq_apic(int irq, int type)
830 for (i = 0; i < mp_irq_entries; i++) {
831 int lbus = mp_irqs[i].srcbus;
833 if (test_bit(lbus, mp_bus_not_pci) &&
834 (mp_irqs[i].irqtype == type) &&
835 (mp_irqs[i].srcbusirq == irq))
838 if (i < mp_irq_entries) {
840 for(apic = 0; apic < nr_ioapics; apic++) {
841 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
849 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
851 * EISA Edge/Level control register, ELCR
853 static int EISA_ELCR(unsigned int irq)
855 if (irq < nr_legacy_irqs) {
856 unsigned int port = 0x4d0 + (irq >> 3);
857 return (inb(port) >> (irq & 7)) & 1;
859 apic_printk(APIC_VERBOSE, KERN_INFO
860 "Broken MPtable reports ISA irq %d\n", irq);
866 /* ISA interrupts are always polarity zero edge triggered,
867 * when listed as conforming in the MP table. */
869 #define default_ISA_trigger(idx) (0)
870 #define default_ISA_polarity(idx) (0)
872 /* EISA interrupts are always polarity zero and can be edge or level
873 * trigger depending on the ELCR value. If an interrupt is listed as
874 * EISA conforming in the MP table, that means its trigger type must
875 * be read in from the ELCR */
877 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
878 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
880 /* PCI interrupts are always polarity one level triggered,
881 * when listed as conforming in the MP table. */
883 #define default_PCI_trigger(idx) (1)
884 #define default_PCI_polarity(idx) (1)
886 /* MCA interrupts are always polarity zero level triggered,
887 * when listed as conforming in the MP table. */
889 #define default_MCA_trigger(idx) (1)
890 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
892 static int MPBIOS_polarity(int idx)
894 int bus = mp_irqs[idx].srcbus;
898 * Determine IRQ line polarity (high active or low active):
900 switch (mp_irqs[idx].irqflag & 3)
902 case 0: /* conforms, ie. bus-type dependent polarity */
903 if (test_bit(bus, mp_bus_not_pci))
904 polarity = default_ISA_polarity(idx);
906 polarity = default_PCI_polarity(idx);
908 case 1: /* high active */
913 case 2: /* reserved */
915 printk(KERN_WARNING "broken BIOS!!\n");
919 case 3: /* low active */
924 default: /* invalid */
926 printk(KERN_WARNING "broken BIOS!!\n");
934 static int MPBIOS_trigger(int idx)
936 int bus = mp_irqs[idx].srcbus;
940 * Determine IRQ trigger mode (edge or level sensitive):
942 switch ((mp_irqs[idx].irqflag>>2) & 3)
944 case 0: /* conforms, ie. bus-type dependent */
945 if (test_bit(bus, mp_bus_not_pci))
946 trigger = default_ISA_trigger(idx);
948 trigger = default_PCI_trigger(idx);
949 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
950 switch (mp_bus_id_to_type[bus]) {
951 case MP_BUS_ISA: /* ISA pin */
953 /* set before the switch */
956 case MP_BUS_EISA: /* EISA pin */
958 trigger = default_EISA_trigger(idx);
961 case MP_BUS_PCI: /* PCI pin */
963 /* set before the switch */
966 case MP_BUS_MCA: /* MCA pin */
968 trigger = default_MCA_trigger(idx);
973 printk(KERN_WARNING "broken BIOS!!\n");
985 case 2: /* reserved */
987 printk(KERN_WARNING "broken BIOS!!\n");
996 default: /* invalid */
998 printk(KERN_WARNING "broken BIOS!!\n");
1006 static inline int irq_polarity(int idx)
1008 return MPBIOS_polarity(idx);
1011 static inline int irq_trigger(int idx)
1013 return MPBIOS_trigger(idx);
1016 int (*ioapic_renumber_irq)(int ioapic, int irq);
1017 static int pin_2_irq(int idx, int apic, int pin)
1020 int bus = mp_irqs[idx].srcbus;
1023 * Debugging check, we are in big trouble if this message pops up!
1025 if (mp_irqs[idx].dstirq != pin)
1026 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1028 if (test_bit(bus, mp_bus_not_pci)) {
1029 irq = mp_irqs[idx].srcbusirq;
1032 * PCI IRQs are mapped in order
1036 irq += nr_ioapic_registers[i++];
1039 * For MPS mode, so far only needed by ES7000 platform
1041 if (ioapic_renumber_irq)
1042 irq = ioapic_renumber_irq(apic, irq);
1045 #ifdef CONFIG_X86_32
1047 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1049 if ((pin >= 16) && (pin <= 23)) {
1050 if (pirq_entries[pin-16] != -1) {
1051 if (!pirq_entries[pin-16]) {
1052 apic_printk(APIC_VERBOSE, KERN_DEBUG
1053 "disabling PIRQ%d\n", pin-16);
1055 irq = pirq_entries[pin-16];
1056 apic_printk(APIC_VERBOSE, KERN_DEBUG
1057 "using PIRQ%d -> IRQ %d\n",
1068 * Find a specific PCI IRQ entry.
1069 * Not an __init, possibly needed by modules
1071 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1072 struct io_apic_irq_attr *irq_attr)
1074 int apic, i, best_guess = -1;
1076 apic_printk(APIC_DEBUG,
1077 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1079 if (test_bit(bus, mp_bus_not_pci)) {
1080 apic_printk(APIC_VERBOSE,
1081 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1084 for (i = 0; i < mp_irq_entries; i++) {
1085 int lbus = mp_irqs[i].srcbus;
1087 for (apic = 0; apic < nr_ioapics; apic++)
1088 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1089 mp_irqs[i].dstapic == MP_APIC_ALL)
1092 if (!test_bit(lbus, mp_bus_not_pci) &&
1093 !mp_irqs[i].irqtype &&
1095 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1096 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1098 if (!(apic || IO_APIC_IRQ(irq)))
1101 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1102 set_io_apic_irq_attr(irq_attr, apic,
1109 * Use the first all-but-pin matching entry as a
1110 * best-guess fuzzy result for broken mptables.
1112 if (best_guess < 0) {
1113 set_io_apic_irq_attr(irq_attr, apic,
1123 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1125 void lock_vector_lock(void)
1127 /* Used to the online set of cpus does not change
1128 * during assign_irq_vector.
1130 raw_spin_lock(&vector_lock);
1133 void unlock_vector_lock(void)
1135 raw_spin_unlock(&vector_lock);
1139 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1142 * NOTE! The local APIC isn't very good at handling
1143 * multiple interrupts at the same interrupt level.
1144 * As the interrupt level is determined by taking the
1145 * vector number and shifting that right by 4, we
1146 * want to spread these out a bit so that they don't
1147 * all fall in the same interrupt level.
1149 * Also, we've got to be careful not to trash gate
1150 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1152 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1153 static int current_offset = VECTOR_OFFSET_START % 8;
1154 unsigned int old_vector;
1156 cpumask_var_t tmp_mask;
1158 if (cfg->move_in_progress)
1161 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1164 old_vector = cfg->vector;
1166 cpumask_and(tmp_mask, mask, cpu_online_mask);
1167 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1168 if (!cpumask_empty(tmp_mask)) {
1169 free_cpumask_var(tmp_mask);
1174 /* Only try and allocate irqs on cpus that are present */
1176 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1180 apic->vector_allocation_domain(cpu, tmp_mask);
1182 vector = current_vector;
1183 offset = current_offset;
1186 if (vector >= first_system_vector) {
1187 /* If out of vectors on large boxen, must share them. */
1188 offset = (offset + 1) % 8;
1189 vector = FIRST_EXTERNAL_VECTOR + offset;
1191 if (unlikely(current_vector == vector))
1194 if (test_bit(vector, used_vectors))
1197 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1198 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1201 current_vector = vector;
1202 current_offset = offset;
1204 cfg->move_in_progress = 1;
1205 cpumask_copy(cfg->old_domain, cfg->domain);
1207 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1208 per_cpu(vector_irq, new_cpu)[vector] = irq;
1209 cfg->vector = vector;
1210 cpumask_copy(cfg->domain, tmp_mask);
1214 free_cpumask_var(tmp_mask);
1218 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1221 unsigned long flags;
1223 raw_spin_lock_irqsave(&vector_lock, flags);
1224 err = __assign_irq_vector(irq, cfg, mask);
1225 raw_spin_unlock_irqrestore(&vector_lock, flags);
1229 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1233 BUG_ON(!cfg->vector);
1235 vector = cfg->vector;
1236 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1237 per_cpu(vector_irq, cpu)[vector] = -1;
1240 cpumask_clear(cfg->domain);
1242 if (likely(!cfg->move_in_progress))
1244 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1245 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1247 if (per_cpu(vector_irq, cpu)[vector] != irq)
1249 per_cpu(vector_irq, cpu)[vector] = -1;
1253 cfg->move_in_progress = 0;
1256 void __setup_vector_irq(int cpu)
1258 /* Initialize vector_irq on a new cpu */
1260 struct irq_cfg *cfg;
1261 struct irq_desc *desc;
1264 * vector_lock will make sure that we don't run into irq vector
1265 * assignments that might be happening on another cpu in parallel,
1266 * while we setup our initial vector to irq mappings.
1268 raw_spin_lock(&vector_lock);
1269 /* Mark the inuse vectors */
1270 for_each_irq_desc(irq, desc) {
1271 cfg = desc->chip_data;
1272 if (!cpumask_test_cpu(cpu, cfg->domain))
1274 vector = cfg->vector;
1275 per_cpu(vector_irq, cpu)[vector] = irq;
1277 /* Mark the free vectors */
1278 for (vector = 0; vector < NR_VECTORS; ++vector) {
1279 irq = per_cpu(vector_irq, cpu)[vector];
1284 if (!cpumask_test_cpu(cpu, cfg->domain))
1285 per_cpu(vector_irq, cpu)[vector] = -1;
1287 raw_spin_unlock(&vector_lock);
1290 static struct irq_chip ioapic_chip;
1291 static struct irq_chip ir_ioapic_chip;
1293 #define IOAPIC_AUTO -1
1294 #define IOAPIC_EDGE 0
1295 #define IOAPIC_LEVEL 1
1297 #ifdef CONFIG_X86_32
1298 static inline int IO_APIC_irq_trigger(int irq)
1302 for (apic = 0; apic < nr_ioapics; apic++) {
1303 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1304 idx = find_irq_entry(apic, pin, mp_INT);
1305 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1306 return irq_trigger(idx);
1310 * nonexistent IRQs are edge default
1315 static inline int IO_APIC_irq_trigger(int irq)
1321 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1324 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1325 trigger == IOAPIC_LEVEL)
1326 desc->status |= IRQ_LEVEL;
1328 desc->status &= ~IRQ_LEVEL;
1330 if (irq_remapped(irq)) {
1331 desc->status |= IRQ_MOVE_PCNTXT;
1333 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1337 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1338 handle_edge_irq, "edge");
1342 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1343 trigger == IOAPIC_LEVEL)
1344 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1348 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1349 handle_edge_irq, "edge");
1352 int setup_ioapic_entry(int apic_id, int irq,
1353 struct IO_APIC_route_entry *entry,
1354 unsigned int destination, int trigger,
1355 int polarity, int vector, int pin)
1358 * add it to the IO-APIC irq-routing table:
1360 memset(entry,0,sizeof(*entry));
1362 if (intr_remapping_enabled) {
1363 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1365 struct IR_IO_APIC_route_entry *ir_entry =
1366 (struct IR_IO_APIC_route_entry *) entry;
1370 panic("No mapping iommu for ioapic %d\n", apic_id);
1372 index = alloc_irte(iommu, irq, 1);
1374 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1376 memset(&irte, 0, sizeof(irte));
1379 irte.dst_mode = apic->irq_dest_mode;
1381 * Trigger mode in the IRTE will always be edge, and the
1382 * actual level or edge trigger will be setup in the IO-APIC
1383 * RTE. This will help simplify level triggered irq migration.
1384 * For more details, see the comments above explainig IO-APIC
1385 * irq migration in the presence of interrupt-remapping.
1387 irte.trigger_mode = 0;
1388 irte.dlvry_mode = apic->irq_delivery_mode;
1389 irte.vector = vector;
1390 irte.dest_id = IRTE_DEST(destination);
1392 /* Set source-id of interrupt request */
1393 set_ioapic_sid(&irte, apic_id);
1395 modify_irte(irq, &irte);
1397 ir_entry->index2 = (index >> 15) & 0x1;
1399 ir_entry->format = 1;
1400 ir_entry->index = (index & 0x7fff);
1402 * IO-APIC RTE will be configured with virtual vector.
1403 * irq handler will do the explicit EOI to the io-apic.
1405 ir_entry->vector = pin;
1407 entry->delivery_mode = apic->irq_delivery_mode;
1408 entry->dest_mode = apic->irq_dest_mode;
1409 entry->dest = destination;
1410 entry->vector = vector;
1413 entry->mask = 0; /* enable IRQ */
1414 entry->trigger = trigger;
1415 entry->polarity = polarity;
1417 /* Mask level triggered irqs.
1418 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1425 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1426 int trigger, int polarity)
1428 struct irq_cfg *cfg;
1429 struct IO_APIC_route_entry entry;
1432 if (!IO_APIC_IRQ(irq))
1435 cfg = desc->chip_data;
1438 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1439 * controllers like 8259. Now that IO-APIC can handle this irq, update
1442 if (irq < nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1443 apic->vector_allocation_domain(0, cfg->domain);
1445 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1448 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1450 apic_printk(APIC_VERBOSE,KERN_DEBUG
1451 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1452 "IRQ %d Mode:%i Active:%i)\n",
1453 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1454 irq, trigger, polarity);
1457 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1458 dest, trigger, polarity, cfg->vector, pin)) {
1459 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1460 mp_ioapics[apic_id].apicid, pin);
1461 __clear_irq_vector(irq, cfg);
1465 ioapic_register_intr(irq, desc, trigger);
1466 if (irq < nr_legacy_irqs)
1467 disable_8259A_irq(irq);
1469 ioapic_write_entry(apic_id, pin, entry);
1473 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1474 } mp_ioapic_routing[MAX_IO_APICS];
1476 static void __init setup_IO_APIC_irqs(void)
1478 int apic_id, pin, idx, irq;
1480 struct irq_desc *desc;
1481 struct irq_cfg *cfg;
1482 int node = cpu_to_node(boot_cpu_id);
1484 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1486 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1487 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1488 idx = find_irq_entry(apic_id, pin, mp_INT);
1492 apic_printk(APIC_VERBOSE,
1493 KERN_DEBUG " %d-%d",
1494 mp_ioapics[apic_id].apicid, pin);
1496 apic_printk(APIC_VERBOSE, " %d-%d",
1497 mp_ioapics[apic_id].apicid, pin);
1501 apic_printk(APIC_VERBOSE,
1502 " (apicid-pin) not connected\n");
1506 irq = pin_2_irq(idx, apic_id, pin);
1508 if ((apic_id > 0) && (irq > 16))
1512 * Skip the timer IRQ if there's a quirk handler
1513 * installed and if it returns 1:
1515 if (apic->multi_timer_check &&
1516 apic->multi_timer_check(apic_id, irq))
1519 desc = irq_to_desc_alloc_node(irq, node);
1521 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1524 cfg = desc->chip_data;
1525 add_pin_to_irq_node(cfg, node, apic_id, pin);
1527 * don't mark it in pin_programmed, so later acpi could
1528 * set it correctly when irq < 16
1530 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1531 irq_trigger(idx), irq_polarity(idx));
1535 apic_printk(APIC_VERBOSE,
1536 " (apicid-pin) not connected\n");
1540 * for the gsit that is not in first ioapic
1541 * but could not use acpi_register_gsi()
1542 * like some special sci in IBM x3330
1544 void setup_IO_APIC_irq_extra(u32 gsi)
1546 int apic_id = 0, pin, idx, irq;
1547 int node = cpu_to_node(boot_cpu_id);
1548 struct irq_desc *desc;
1549 struct irq_cfg *cfg;
1552 * Convert 'gsi' to 'ioapic.pin'.
1554 apic_id = mp_find_ioapic(gsi);
1558 pin = mp_find_ioapic_pin(apic_id, gsi);
1559 idx = find_irq_entry(apic_id, pin, mp_INT);
1563 irq = pin_2_irq(idx, apic_id, pin);
1564 #ifdef CONFIG_SPARSE_IRQ
1565 desc = irq_to_desc(irq);
1569 desc = irq_to_desc_alloc_node(irq, node);
1571 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1575 cfg = desc->chip_data;
1576 add_pin_to_irq_node(cfg, node, apic_id, pin);
1578 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1579 pr_debug("Pin %d-%d already programmed\n",
1580 mp_ioapics[apic_id].apicid, pin);
1583 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1585 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1586 irq_trigger(idx), irq_polarity(idx));
1590 * Set up the timer pin, possibly with the 8259A-master behind.
1592 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1595 struct IO_APIC_route_entry entry;
1597 if (intr_remapping_enabled)
1600 memset(&entry, 0, sizeof(entry));
1603 * We use logical delivery to get the timer IRQ
1606 entry.dest_mode = apic->irq_dest_mode;
1607 entry.mask = 0; /* don't mask IRQ for edge */
1608 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1609 entry.delivery_mode = apic->irq_delivery_mode;
1612 entry.vector = vector;
1615 * The timer IRQ doesn't have to know that behind the
1616 * scene we may have a 8259A-master in AEOI mode ...
1618 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1621 * Add it to the IO-APIC irq-routing table:
1623 ioapic_write_entry(apic_id, pin, entry);
1627 __apicdebuginit(void) print_IO_APIC(void)
1630 union IO_APIC_reg_00 reg_00;
1631 union IO_APIC_reg_01 reg_01;
1632 union IO_APIC_reg_02 reg_02;
1633 union IO_APIC_reg_03 reg_03;
1634 unsigned long flags;
1635 struct irq_cfg *cfg;
1636 struct irq_desc *desc;
1639 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1640 for (i = 0; i < nr_ioapics; i++)
1641 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1642 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1645 * We are a bit conservative about what we expect. We have to
1646 * know about every hardware change ASAP.
1648 printk(KERN_INFO "testing the IO APIC.......................\n");
1650 for (apic = 0; apic < nr_ioapics; apic++) {
1652 raw_spin_lock_irqsave(&ioapic_lock, flags);
1653 reg_00.raw = io_apic_read(apic, 0);
1654 reg_01.raw = io_apic_read(apic, 1);
1655 if (reg_01.bits.version >= 0x10)
1656 reg_02.raw = io_apic_read(apic, 2);
1657 if (reg_01.bits.version >= 0x20)
1658 reg_03.raw = io_apic_read(apic, 3);
1659 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1662 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1663 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1664 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1665 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1666 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1668 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1669 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1671 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1672 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1675 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1676 * but the value of reg_02 is read as the previous read register
1677 * value, so ignore it if reg_02 == reg_01.
1679 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1680 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1681 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1685 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1686 * or reg_03, but the value of reg_0[23] is read as the previous read
1687 * register value, so ignore it if reg_03 == reg_0[12].
1689 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1690 reg_03.raw != reg_01.raw) {
1691 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1692 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1695 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1697 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1698 " Stat Dmod Deli Vect:\n");
1700 for (i = 0; i <= reg_01.bits.entries; i++) {
1701 struct IO_APIC_route_entry entry;
1703 entry = ioapic_read_entry(apic, i);
1705 printk(KERN_DEBUG " %02x %03X ",
1710 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1715 entry.delivery_status,
1717 entry.delivery_mode,
1722 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1723 for_each_irq_desc(irq, desc) {
1724 struct irq_pin_list *entry;
1726 cfg = desc->chip_data;
1727 entry = cfg->irq_2_pin;
1730 printk(KERN_DEBUG "IRQ%d ", irq);
1731 for_each_irq_pin(entry, cfg->irq_2_pin)
1732 printk("-> %d:%d", entry->apic, entry->pin);
1736 printk(KERN_INFO ".................................... done.\n");
1741 __apicdebuginit(void) print_APIC_field(int base)
1747 for (i = 0; i < 8; i++)
1748 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1750 printk(KERN_CONT "\n");
1753 __apicdebuginit(void) print_local_APIC(void *dummy)
1755 unsigned int i, v, ver, maxlvt;
1758 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1759 smp_processor_id(), hard_smp_processor_id());
1760 v = apic_read(APIC_ID);
1761 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1762 v = apic_read(APIC_LVR);
1763 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1764 ver = GET_APIC_VERSION(v);
1765 maxlvt = lapic_get_maxlvt();
1767 v = apic_read(APIC_TASKPRI);
1768 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1770 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1771 if (!APIC_XAPIC(ver)) {
1772 v = apic_read(APIC_ARBPRI);
1773 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1774 v & APIC_ARBPRI_MASK);
1776 v = apic_read(APIC_PROCPRI);
1777 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1781 * Remote read supported only in the 82489DX and local APIC for
1782 * Pentium processors.
1784 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1785 v = apic_read(APIC_RRR);
1786 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1789 v = apic_read(APIC_LDR);
1790 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1791 if (!x2apic_enabled()) {
1792 v = apic_read(APIC_DFR);
1793 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1795 v = apic_read(APIC_SPIV);
1796 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1798 printk(KERN_DEBUG "... APIC ISR field:\n");
1799 print_APIC_field(APIC_ISR);
1800 printk(KERN_DEBUG "... APIC TMR field:\n");
1801 print_APIC_field(APIC_TMR);
1802 printk(KERN_DEBUG "... APIC IRR field:\n");
1803 print_APIC_field(APIC_IRR);
1805 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1806 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1807 apic_write(APIC_ESR, 0);
1809 v = apic_read(APIC_ESR);
1810 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1813 icr = apic_icr_read();
1814 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1815 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1817 v = apic_read(APIC_LVTT);
1818 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1820 if (maxlvt > 3) { /* PC is LVT#4. */
1821 v = apic_read(APIC_LVTPC);
1822 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1824 v = apic_read(APIC_LVT0);
1825 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1826 v = apic_read(APIC_LVT1);
1827 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1829 if (maxlvt > 2) { /* ERR is LVT#3. */
1830 v = apic_read(APIC_LVTERR);
1831 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1834 v = apic_read(APIC_TMICT);
1835 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1836 v = apic_read(APIC_TMCCT);
1837 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1838 v = apic_read(APIC_TDCR);
1839 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1841 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1842 v = apic_read(APIC_EFEAT);
1843 maxlvt = (v >> 16) & 0xff;
1844 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1845 v = apic_read(APIC_ECTRL);
1846 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1847 for (i = 0; i < maxlvt; i++) {
1848 v = apic_read(APIC_EILVTn(i));
1849 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1855 __apicdebuginit(void) print_local_APICs(int maxcpu)
1863 for_each_online_cpu(cpu) {
1866 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1871 __apicdebuginit(void) print_PIC(void)
1874 unsigned long flags;
1876 if (!nr_legacy_irqs)
1879 printk(KERN_DEBUG "\nprinting PIC contents\n");
1881 raw_spin_lock_irqsave(&i8259A_lock, flags);
1883 v = inb(0xa1) << 8 | inb(0x21);
1884 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1886 v = inb(0xa0) << 8 | inb(0x20);
1887 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1891 v = inb(0xa0) << 8 | inb(0x20);
1895 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1897 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1899 v = inb(0x4d1) << 8 | inb(0x4d0);
1900 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1903 static int __initdata show_lapic = 1;
1904 static __init int setup_show_lapic(char *arg)
1908 if (strcmp(arg, "all") == 0) {
1909 show_lapic = CONFIG_NR_CPUS;
1911 get_option(&arg, &num);
1918 __setup("show_lapic=", setup_show_lapic);
1920 __apicdebuginit(int) print_ICs(void)
1922 if (apic_verbosity == APIC_QUIET)
1927 /* don't print out if apic is not there */
1928 if (!cpu_has_apic && !apic_from_smp_config())
1931 print_local_APICs(show_lapic);
1937 fs_initcall(print_ICs);
1940 /* Where if anywhere is the i8259 connect in external int mode */
1941 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1943 void __init enable_IO_APIC(void)
1945 union IO_APIC_reg_01 reg_01;
1946 int i8259_apic, i8259_pin;
1948 unsigned long flags;
1951 * The number of IO-APIC IRQ registers (== #pins):
1953 for (apic = 0; apic < nr_ioapics; apic++) {
1954 raw_spin_lock_irqsave(&ioapic_lock, flags);
1955 reg_01.raw = io_apic_read(apic, 1);
1956 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1957 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1960 if (!nr_legacy_irqs)
1963 for(apic = 0; apic < nr_ioapics; apic++) {
1965 /* See if any of the pins is in ExtINT mode */
1966 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1967 struct IO_APIC_route_entry entry;
1968 entry = ioapic_read_entry(apic, pin);
1970 /* If the interrupt line is enabled and in ExtInt mode
1971 * I have found the pin where the i8259 is connected.
1973 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1974 ioapic_i8259.apic = apic;
1975 ioapic_i8259.pin = pin;
1981 /* Look to see what if the MP table has reported the ExtINT */
1982 /* If we could not find the appropriate pin by looking at the ioapic
1983 * the i8259 probably is not connected the ioapic but give the
1984 * mptable a chance anyway.
1986 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1987 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1988 /* Trust the MP table if nothing is setup in the hardware */
1989 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1990 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1991 ioapic_i8259.pin = i8259_pin;
1992 ioapic_i8259.apic = i8259_apic;
1994 /* Complain if the MP table and the hardware disagree */
1995 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1996 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1998 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2002 * Do not trust the IO-APIC being empty at bootup
2008 * Not an __init, needed by the reboot code
2010 void disable_IO_APIC(void)
2013 * Clear the IO-APIC before rebooting:
2017 if (!nr_legacy_irqs)
2021 * If the i8259 is routed through an IOAPIC
2022 * Put that IOAPIC in virtual wire mode
2023 * so legacy interrupts can be delivered.
2025 * With interrupt-remapping, for now we will use virtual wire A mode,
2026 * as virtual wire B is little complex (need to configure both
2027 * IOAPIC RTE aswell as interrupt-remapping table entry).
2028 * As this gets called during crash dump, keep this simple for now.
2030 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2031 struct IO_APIC_route_entry entry;
2033 memset(&entry, 0, sizeof(entry));
2034 entry.mask = 0; /* Enabled */
2035 entry.trigger = 0; /* Edge */
2037 entry.polarity = 0; /* High */
2038 entry.delivery_status = 0;
2039 entry.dest_mode = 0; /* Physical */
2040 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2042 entry.dest = read_apic_id();
2045 * Add it to the IO-APIC irq-routing table:
2047 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2051 * Use virtual wire A mode when interrupt remapping is enabled.
2053 if (cpu_has_apic || apic_from_smp_config())
2054 disconnect_bsp_APIC(!intr_remapping_enabled &&
2055 ioapic_i8259.pin != -1);
2058 #ifdef CONFIG_X86_32
2060 * function to set the IO-APIC physical IDs based on the
2061 * values stored in the MPC table.
2063 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2066 void __init setup_ioapic_ids_from_mpc(void)
2068 union IO_APIC_reg_00 reg_00;
2069 physid_mask_t phys_id_present_map;
2072 unsigned char old_id;
2073 unsigned long flags;
2078 * Don't check I/O APIC IDs for xAPIC systems. They have
2079 * no meaning without the serial APIC bus.
2081 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2082 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2085 * This is broken; anything with a real cpu count has to
2086 * circumvent this idiocy regardless.
2088 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2091 * Set the IOAPIC ID to the value stored in the MPC table.
2093 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2095 /* Read the register 0 value */
2096 raw_spin_lock_irqsave(&ioapic_lock, flags);
2097 reg_00.raw = io_apic_read(apic_id, 0);
2098 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2100 old_id = mp_ioapics[apic_id].apicid;
2102 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2103 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2104 apic_id, mp_ioapics[apic_id].apicid);
2105 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2107 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2111 * Sanity check, is the ID really free? Every APIC in a
2112 * system must have a unique ID or we get lots of nice
2113 * 'stuck on smp_invalidate_needed IPI wait' messages.
2115 if (apic->check_apicid_used(&phys_id_present_map,
2116 mp_ioapics[apic_id].apicid)) {
2117 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2118 apic_id, mp_ioapics[apic_id].apicid);
2119 for (i = 0; i < get_physical_broadcast(); i++)
2120 if (!physid_isset(i, phys_id_present_map))
2122 if (i >= get_physical_broadcast())
2123 panic("Max APIC ID exceeded!\n");
2124 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2126 physid_set(i, phys_id_present_map);
2127 mp_ioapics[apic_id].apicid = i;
2130 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2131 apic_printk(APIC_VERBOSE, "Setting %d in the "
2132 "phys_id_present_map\n",
2133 mp_ioapics[apic_id].apicid);
2134 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2139 * We need to adjust the IRQ routing table
2140 * if the ID changed.
2142 if (old_id != mp_ioapics[apic_id].apicid)
2143 for (i = 0; i < mp_irq_entries; i++)
2144 if (mp_irqs[i].dstapic == old_id)
2146 = mp_ioapics[apic_id].apicid;
2149 * Read the right value from the MPC table and
2150 * write it into the ID register.
2152 apic_printk(APIC_VERBOSE, KERN_INFO
2153 "...changing IO-APIC physical APIC ID to %d ...",
2154 mp_ioapics[apic_id].apicid);
2156 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2157 raw_spin_lock_irqsave(&ioapic_lock, flags);
2158 io_apic_write(apic_id, 0, reg_00.raw);
2159 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2164 raw_spin_lock_irqsave(&ioapic_lock, flags);
2165 reg_00.raw = io_apic_read(apic_id, 0);
2166 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2167 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2168 printk("could not set ID!\n");
2170 apic_printk(APIC_VERBOSE, " ok.\n");
2175 int no_timer_check __initdata;
2177 static int __init notimercheck(char *s)
2182 __setup("no_timer_check", notimercheck);
2185 * There is a nasty bug in some older SMP boards, their mptable lies
2186 * about the timer IRQ. We do the following to work around the situation:
2188 * - timer IRQ defaults to IO-APIC IRQ
2189 * - if this function detects that timer IRQs are defunct, then we fall
2190 * back to ISA timer IRQs
2192 static int __init timer_irq_works(void)
2194 unsigned long t1 = jiffies;
2195 unsigned long flags;
2200 local_save_flags(flags);
2202 /* Let ten ticks pass... */
2203 mdelay((10 * 1000) / HZ);
2204 local_irq_restore(flags);
2207 * Expect a few ticks at least, to be sure some possible
2208 * glue logic does not lock up after one or two first
2209 * ticks in a non-ExtINT mode. Also the local APIC
2210 * might have cached one ExtINT interrupt. Finally, at
2211 * least one tick may be lost due to delays.
2215 if (time_after(jiffies, t1 + 4))
2221 * In the SMP+IOAPIC case it might happen that there are an unspecified
2222 * number of pending IRQ events unhandled. These cases are very rare,
2223 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2224 * better to do it this way as thus we do not have to be aware of
2225 * 'pending' interrupts in the IRQ path, except at this point.
2228 * Edge triggered needs to resend any interrupt
2229 * that was delayed but this is now handled in the device
2234 * Starting up a edge-triggered IO-APIC interrupt is
2235 * nasty - we need to make sure that we get the edge.
2236 * If it is already asserted for some reason, we need
2237 * return 1 to indicate that is was pending.
2239 * This is not complete - we should be able to fake
2240 * an edge even if it isn't on the 8259A...
2243 static unsigned int startup_ioapic_irq(unsigned int irq)
2245 int was_pending = 0;
2246 unsigned long flags;
2247 struct irq_cfg *cfg;
2249 raw_spin_lock_irqsave(&ioapic_lock, flags);
2250 if (irq < nr_legacy_irqs) {
2251 disable_8259A_irq(irq);
2252 if (i8259A_irq_pending(irq))
2256 __unmask_IO_APIC_irq(cfg);
2257 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2262 static int ioapic_retrigger_irq(unsigned int irq)
2265 struct irq_cfg *cfg = irq_cfg(irq);
2266 unsigned long flags;
2268 raw_spin_lock_irqsave(&vector_lock, flags);
2269 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2270 raw_spin_unlock_irqrestore(&vector_lock, flags);
2276 * Level and edge triggered IO-APIC interrupts need different handling,
2277 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2278 * handled with the level-triggered descriptor, but that one has slightly
2279 * more overhead. Level-triggered interrupts cannot be handled with the
2280 * edge-triggered handler, without risking IRQ storms and other ugly
2285 void send_cleanup_vector(struct irq_cfg *cfg)
2287 cpumask_var_t cleanup_mask;
2289 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2291 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2292 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2294 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2295 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2296 free_cpumask_var(cleanup_mask);
2298 cfg->move_in_progress = 0;
2301 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2304 struct irq_pin_list *entry;
2305 u8 vector = cfg->vector;
2307 for_each_irq_pin(entry, cfg->irq_2_pin) {
2313 * With interrupt-remapping, destination information comes
2314 * from interrupt-remapping table entry.
2316 if (!irq_remapped(irq))
2317 io_apic_write(apic, 0x11 + pin*2, dest);
2318 reg = io_apic_read(apic, 0x10 + pin*2);
2319 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2321 io_apic_modify(apic, 0x10 + pin*2, reg);
2326 * Either sets desc->affinity to a valid value, and returns
2327 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2328 * leaves desc->affinity untouched.
2331 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2332 unsigned int *dest_id)
2334 struct irq_cfg *cfg;
2337 if (!cpumask_intersects(mask, cpu_online_mask))
2341 cfg = desc->chip_data;
2342 if (assign_irq_vector(irq, cfg, mask))
2345 cpumask_copy(desc->affinity, mask);
2347 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2352 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2354 struct irq_cfg *cfg;
2355 unsigned long flags;
2361 cfg = desc->chip_data;
2363 raw_spin_lock_irqsave(&ioapic_lock, flags);
2364 ret = set_desc_affinity(desc, mask, &dest);
2366 /* Only the high 8 bits are valid. */
2367 dest = SET_APIC_LOGICAL_ID(dest);
2368 __target_IO_APIC_irq(irq, dest, cfg);
2370 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2376 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2378 struct irq_desc *desc;
2380 desc = irq_to_desc(irq);
2382 return set_ioapic_affinity_irq_desc(desc, mask);
2385 #ifdef CONFIG_INTR_REMAP
2388 * Migrate the IO-APIC irq in the presence of intr-remapping.
2390 * For both level and edge triggered, irq migration is a simple atomic
2391 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2393 * For level triggered, we eliminate the io-apic RTE modification (with the
2394 * updated vector information), by using a virtual vector (io-apic pin number).
2395 * Real vector that is used for interrupting cpu will be coming from
2396 * the interrupt-remapping table entry.
2399 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2401 struct irq_cfg *cfg;
2407 if (!cpumask_intersects(mask, cpu_online_mask))
2411 if (get_irte(irq, &irte))
2414 cfg = desc->chip_data;
2415 if (assign_irq_vector(irq, cfg, mask))
2418 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2420 irte.vector = cfg->vector;
2421 irte.dest_id = IRTE_DEST(dest);
2424 * Modified the IRTE and flushes the Interrupt entry cache.
2426 modify_irte(irq, &irte);
2428 if (cfg->move_in_progress)
2429 send_cleanup_vector(cfg);
2431 cpumask_copy(desc->affinity, mask);
2437 * Migrates the IRQ destination in the process context.
2439 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2440 const struct cpumask *mask)
2442 return migrate_ioapic_irq_desc(desc, mask);
2444 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2445 const struct cpumask *mask)
2447 struct irq_desc *desc = irq_to_desc(irq);
2449 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2452 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2453 const struct cpumask *mask)
2459 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2461 unsigned vector, me;
2467 me = smp_processor_id();
2468 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2471 struct irq_desc *desc;
2472 struct irq_cfg *cfg;
2473 irq = __get_cpu_var(vector_irq)[vector];
2478 desc = irq_to_desc(irq);
2483 raw_spin_lock(&desc->lock);
2486 * Check if the irq migration is in progress. If so, we
2487 * haven't received the cleanup request yet for this irq.
2489 if (cfg->move_in_progress)
2492 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2495 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2497 * Check if the vector that needs to be cleanedup is
2498 * registered at the cpu's IRR. If so, then this is not
2499 * the best time to clean it up. Lets clean it up in the
2500 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2503 if (irr & (1 << (vector % 32))) {
2504 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2507 __get_cpu_var(vector_irq)[vector] = -1;
2509 raw_spin_unlock(&desc->lock);
2515 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2517 struct irq_desc *desc = *descp;
2518 struct irq_cfg *cfg = desc->chip_data;
2521 if (likely(!cfg->move_in_progress))
2524 me = smp_processor_id();
2526 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2527 send_cleanup_vector(cfg);
2530 static void irq_complete_move(struct irq_desc **descp)
2532 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2535 void irq_force_complete_move(int irq)
2537 struct irq_desc *desc = irq_to_desc(irq);
2538 struct irq_cfg *cfg = desc->chip_data;
2540 __irq_complete_move(&desc, cfg->vector);
2543 static inline void irq_complete_move(struct irq_desc **descp) {}
2546 static void ack_apic_edge(unsigned int irq)
2548 struct irq_desc *desc = irq_to_desc(irq);
2550 irq_complete_move(&desc);
2551 move_native_irq(irq);
2555 atomic_t irq_mis_count;
2558 * IO-APIC versions below 0x20 don't support EOI register.
2559 * For the record, here is the information about various versions:
2561 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2562 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2565 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2566 * version as 0x2. This is an error with documentation and these ICH chips
2567 * use io-apic's of version 0x20.
2569 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2570 * Otherwise, we simulate the EOI message manually by changing the trigger
2571 * mode to edge and then back to level, with RTE being masked during this.
2573 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2575 struct irq_pin_list *entry;
2577 for_each_irq_pin(entry, cfg->irq_2_pin) {
2578 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2580 * Intr-remapping uses pin number as the virtual vector
2581 * in the RTE. Actual vector is programmed in
2582 * intr-remapping table entry. Hence for the io-apic
2583 * EOI we use the pin number.
2585 if (irq_remapped(irq))
2586 io_apic_eoi(entry->apic, entry->pin);
2588 io_apic_eoi(entry->apic, cfg->vector);
2590 __mask_and_edge_IO_APIC_irq(entry);
2591 __unmask_and_level_IO_APIC_irq(entry);
2596 static void eoi_ioapic_irq(struct irq_desc *desc)
2598 struct irq_cfg *cfg;
2599 unsigned long flags;
2603 cfg = desc->chip_data;
2605 raw_spin_lock_irqsave(&ioapic_lock, flags);
2606 __eoi_ioapic_irq(irq, cfg);
2607 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2610 static void ack_apic_level(unsigned int irq)
2612 struct irq_desc *desc = irq_to_desc(irq);
2615 struct irq_cfg *cfg;
2616 int do_unmask_irq = 0;
2618 irq_complete_move(&desc);
2619 #ifdef CONFIG_GENERIC_PENDING_IRQ
2620 /* If we are moving the irq we need to mask it */
2621 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2623 mask_IO_APIC_irq_desc(desc);
2628 * It appears there is an erratum which affects at least version 0x11
2629 * of I/O APIC (that's the 82093AA and cores integrated into various
2630 * chipsets). Under certain conditions a level-triggered interrupt is
2631 * erroneously delivered as edge-triggered one but the respective IRR
2632 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2633 * message but it will never arrive and further interrupts are blocked
2634 * from the source. The exact reason is so far unknown, but the
2635 * phenomenon was observed when two consecutive interrupt requests
2636 * from a given source get delivered to the same CPU and the source is
2637 * temporarily disabled in between.
2639 * A workaround is to simulate an EOI message manually. We achieve it
2640 * by setting the trigger mode to edge and then to level when the edge
2641 * trigger mode gets detected in the TMR of a local APIC for a
2642 * level-triggered interrupt. We mask the source for the time of the
2643 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2644 * The idea is from Manfred Spraul. --macro
2646 * Also in the case when cpu goes offline, fixup_irqs() will forward
2647 * any unhandled interrupt on the offlined cpu to the new cpu
2648 * destination that is handling the corresponding interrupt. This
2649 * interrupt forwarding is done via IPI's. Hence, in this case also
2650 * level-triggered io-apic interrupt will be seen as an edge
2651 * interrupt in the IRR. And we can't rely on the cpu's EOI
2652 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2653 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2654 * supporting EOI register, we do an explicit EOI to clear the
2655 * remote IRR and on IO-APIC's which don't have an EOI register,
2656 * we use the above logic (mask+edge followed by unmask+level) from
2657 * Manfred Spraul to clear the remote IRR.
2659 cfg = desc->chip_data;
2661 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2664 * We must acknowledge the irq before we move it or the acknowledge will
2665 * not propagate properly.
2670 * Tail end of clearing remote IRR bit (either by delivering the EOI
2671 * message via io-apic EOI register write or simulating it using
2672 * mask+edge followed by unnask+level logic) manually when the
2673 * level triggered interrupt is seen as the edge triggered interrupt
2676 if (!(v & (1 << (i & 0x1f)))) {
2677 atomic_inc(&irq_mis_count);
2679 eoi_ioapic_irq(desc);
2682 /* Now we can move and renable the irq */
2683 if (unlikely(do_unmask_irq)) {
2684 /* Only migrate the irq if the ack has been received.
2686 * On rare occasions the broadcast level triggered ack gets
2687 * delayed going to ioapics, and if we reprogram the
2688 * vector while Remote IRR is still set the irq will never
2691 * To prevent this scenario we read the Remote IRR bit
2692 * of the ioapic. This has two effects.
2693 * - On any sane system the read of the ioapic will
2694 * flush writes (and acks) going to the ioapic from
2696 * - We get to see if the ACK has actually been delivered.
2698 * Based on failed experiments of reprogramming the
2699 * ioapic entry from outside of irq context starting
2700 * with masking the ioapic entry and then polling until
2701 * Remote IRR was clear before reprogramming the
2702 * ioapic I don't trust the Remote IRR bit to be
2703 * completey accurate.
2705 * However there appears to be no other way to plug
2706 * this race, so if the Remote IRR bit is not
2707 * accurate and is causing problems then it is a hardware bug
2708 * and you can go talk to the chipset vendor about it.
2710 cfg = desc->chip_data;
2711 if (!io_apic_level_ack_pending(cfg))
2712 move_masked_irq(irq);
2713 unmask_IO_APIC_irq_desc(desc);
2717 #ifdef CONFIG_INTR_REMAP
2718 static void ir_ack_apic_edge(unsigned int irq)
2723 static void ir_ack_apic_level(unsigned int irq)
2725 struct irq_desc *desc = irq_to_desc(irq);
2728 eoi_ioapic_irq(desc);
2730 #endif /* CONFIG_INTR_REMAP */
2732 static struct irq_chip ioapic_chip __read_mostly = {
2734 .startup = startup_ioapic_irq,
2735 .mask = mask_IO_APIC_irq,
2736 .unmask = unmask_IO_APIC_irq,
2737 .ack = ack_apic_edge,
2738 .eoi = ack_apic_level,
2740 .set_affinity = set_ioapic_affinity_irq,
2742 .retrigger = ioapic_retrigger_irq,
2745 static struct irq_chip ir_ioapic_chip __read_mostly = {
2746 .name = "IR-IO-APIC",
2747 .startup = startup_ioapic_irq,
2748 .mask = mask_IO_APIC_irq,
2749 .unmask = unmask_IO_APIC_irq,
2750 #ifdef CONFIG_INTR_REMAP
2751 .ack = ir_ack_apic_edge,
2752 .eoi = ir_ack_apic_level,
2754 .set_affinity = set_ir_ioapic_affinity_irq,
2757 .retrigger = ioapic_retrigger_irq,
2760 static inline void init_IO_APIC_traps(void)
2763 struct irq_desc *desc;
2764 struct irq_cfg *cfg;
2767 * NOTE! The local APIC isn't very good at handling
2768 * multiple interrupts at the same interrupt level.
2769 * As the interrupt level is determined by taking the
2770 * vector number and shifting that right by 4, we
2771 * want to spread these out a bit so that they don't
2772 * all fall in the same interrupt level.
2774 * Also, we've got to be careful not to trash gate
2775 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2777 for_each_irq_desc(irq, desc) {
2778 cfg = desc->chip_data;
2779 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2781 * Hmm.. We don't have an entry for this,
2782 * so default to an old-fashioned 8259
2783 * interrupt if we can..
2785 if (irq < nr_legacy_irqs)
2786 make_8259A_irq(irq);
2788 /* Strange. Oh, well.. */
2789 desc->chip = &no_irq_chip;
2795 * The local APIC irq-chip implementation:
2798 static void mask_lapic_irq(unsigned int irq)
2802 v = apic_read(APIC_LVT0);
2803 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2806 static void unmask_lapic_irq(unsigned int irq)
2810 v = apic_read(APIC_LVT0);
2811 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2814 static void ack_lapic_irq(unsigned int irq)
2819 static struct irq_chip lapic_chip __read_mostly = {
2820 .name = "local-APIC",
2821 .mask = mask_lapic_irq,
2822 .unmask = unmask_lapic_irq,
2823 .ack = ack_lapic_irq,
2826 static void lapic_register_intr(int irq, struct irq_desc *desc)
2828 desc->status &= ~IRQ_LEVEL;
2829 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2833 static void __init setup_nmi(void)
2836 * Dirty trick to enable the NMI watchdog ...
2837 * We put the 8259A master into AEOI mode and
2838 * unmask on all local APICs LVT0 as NMI.
2840 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2841 * is from Maciej W. Rozycki - so we do not have to EOI from
2842 * the NMI handler or the timer interrupt.
2844 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2846 enable_NMI_through_LVT0();
2848 apic_printk(APIC_VERBOSE, " done.\n");
2852 * This looks a bit hackish but it's about the only one way of sending
2853 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2854 * not support the ExtINT mode, unfortunately. We need to send these
2855 * cycles as some i82489DX-based boards have glue logic that keeps the
2856 * 8259A interrupt line asserted until INTA. --macro
2858 static inline void __init unlock_ExtINT_logic(void)
2861 struct IO_APIC_route_entry entry0, entry1;
2862 unsigned char save_control, save_freq_select;
2864 pin = find_isa_irq_pin(8, mp_INT);
2869 apic = find_isa_irq_apic(8, mp_INT);
2875 entry0 = ioapic_read_entry(apic, pin);
2876 clear_IO_APIC_pin(apic, pin);
2878 memset(&entry1, 0, sizeof(entry1));
2880 entry1.dest_mode = 0; /* physical delivery */
2881 entry1.mask = 0; /* unmask IRQ now */
2882 entry1.dest = hard_smp_processor_id();
2883 entry1.delivery_mode = dest_ExtINT;
2884 entry1.polarity = entry0.polarity;
2888 ioapic_write_entry(apic, pin, entry1);
2890 save_control = CMOS_READ(RTC_CONTROL);
2891 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2892 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2894 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2899 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2903 CMOS_WRITE(save_control, RTC_CONTROL);
2904 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2905 clear_IO_APIC_pin(apic, pin);
2907 ioapic_write_entry(apic, pin, entry0);
2910 static int disable_timer_pin_1 __initdata;
2911 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2912 static int __init disable_timer_pin_setup(char *arg)
2914 disable_timer_pin_1 = 1;
2917 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2919 int timer_through_8259 __initdata;
2922 * This code may look a bit paranoid, but it's supposed to cooperate with
2923 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2924 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2925 * fanatically on his truly buggy board.
2927 * FIXME: really need to revamp this for all platforms.
2929 static inline void __init check_timer(void)
2931 struct irq_desc *desc = irq_to_desc(0);
2932 struct irq_cfg *cfg = desc->chip_data;
2933 int node = cpu_to_node(boot_cpu_id);
2934 int apic1, pin1, apic2, pin2;
2935 unsigned long flags;
2938 local_irq_save(flags);
2941 * get/set the timer IRQ vector:
2943 disable_8259A_irq(0);
2944 assign_irq_vector(0, cfg, apic->target_cpus());
2947 * As IRQ0 is to be enabled in the 8259A, the virtual
2948 * wire has to be disabled in the local APIC. Also
2949 * timer interrupts need to be acknowledged manually in
2950 * the 8259A for the i82489DX when using the NMI
2951 * watchdog as that APIC treats NMIs as level-triggered.
2952 * The AEOI mode will finish them in the 8259A
2955 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2957 #ifdef CONFIG_X86_32
2961 ver = apic_read(APIC_LVR);
2962 ver = GET_APIC_VERSION(ver);
2963 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2967 pin1 = find_isa_irq_pin(0, mp_INT);
2968 apic1 = find_isa_irq_apic(0, mp_INT);
2969 pin2 = ioapic_i8259.pin;
2970 apic2 = ioapic_i8259.apic;
2972 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2973 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2974 cfg->vector, apic1, pin1, apic2, pin2);
2977 * Some BIOS writers are clueless and report the ExtINTA
2978 * I/O APIC input from the cascaded 8259A as the timer
2979 * interrupt input. So just in case, if only one pin
2980 * was found above, try it both directly and through the
2984 if (intr_remapping_enabled)
2985 panic("BIOS bug: timer not connected to IO-APIC");
2989 } else if (pin2 == -1) {
2996 * Ok, does IRQ0 through the IOAPIC work?
2999 add_pin_to_irq_node(cfg, node, apic1, pin1);
3000 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
3002 /* for edge trigger, setup_IO_APIC_irq already
3003 * leave it unmasked.
3004 * so only need to unmask if it is level-trigger
3005 * do we really have level trigger timer?
3008 idx = find_irq_entry(apic1, pin1, mp_INT);
3009 if (idx != -1 && irq_trigger(idx))
3010 unmask_IO_APIC_irq_desc(desc);
3012 if (timer_irq_works()) {
3013 if (nmi_watchdog == NMI_IO_APIC) {
3015 enable_8259A_irq(0);
3017 if (disable_timer_pin_1 > 0)
3018 clear_IO_APIC_pin(0, pin1);
3021 if (intr_remapping_enabled)
3022 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3023 local_irq_disable();
3024 clear_IO_APIC_pin(apic1, pin1);
3026 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3027 "8254 timer not connected to IO-APIC\n");
3029 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3030 "(IRQ0) through the 8259A ...\n");
3031 apic_printk(APIC_QUIET, KERN_INFO
3032 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3034 * legacy devices should be connected to IO APIC #0
3036 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3037 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3038 enable_8259A_irq(0);
3039 if (timer_irq_works()) {
3040 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3041 timer_through_8259 = 1;
3042 if (nmi_watchdog == NMI_IO_APIC) {
3043 disable_8259A_irq(0);
3045 enable_8259A_irq(0);
3050 * Cleanup, just in case ...
3052 local_irq_disable();
3053 disable_8259A_irq(0);
3054 clear_IO_APIC_pin(apic2, pin2);
3055 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3058 if (nmi_watchdog == NMI_IO_APIC) {
3059 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3060 "through the IO-APIC - disabling NMI Watchdog!\n");
3061 nmi_watchdog = NMI_NONE;
3063 #ifdef CONFIG_X86_32
3067 apic_printk(APIC_QUIET, KERN_INFO
3068 "...trying to set up timer as Virtual Wire IRQ...\n");
3070 lapic_register_intr(0, desc);
3071 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3072 enable_8259A_irq(0);
3074 if (timer_irq_works()) {
3075 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3078 local_irq_disable();
3079 disable_8259A_irq(0);
3080 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3081 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3083 apic_printk(APIC_QUIET, KERN_INFO
3084 "...trying to set up timer as ExtINT IRQ...\n");
3088 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3090 unlock_ExtINT_logic();
3092 if (timer_irq_works()) {
3093 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3096 local_irq_disable();
3097 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3098 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3099 "report. Then try booting with the 'noapic' option.\n");
3101 local_irq_restore(flags);
3105 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3106 * to devices. However there may be an I/O APIC pin available for
3107 * this interrupt regardless. The pin may be left unconnected, but
3108 * typically it will be reused as an ExtINT cascade interrupt for
3109 * the master 8259A. In the MPS case such a pin will normally be
3110 * reported as an ExtINT interrupt in the MP table. With ACPI
3111 * there is no provision for ExtINT interrupts, and in the absence
3112 * of an override it would be treated as an ordinary ISA I/O APIC
3113 * interrupt, that is edge-triggered and unmasked by default. We
3114 * used to do this, but it caused problems on some systems because
3115 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3116 * the same ExtINT cascade interrupt to drive the local APIC of the
3117 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3118 * the I/O APIC in all cases now. No actual device should request
3119 * it anyway. --macro
3121 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3123 void __init setup_IO_APIC(void)
3127 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3129 io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3131 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3133 * Set up IO-APIC IRQ routing.
3135 x86_init.mpparse.setup_ioapic_ids();
3138 setup_IO_APIC_irqs();
3139 init_IO_APIC_traps();
3145 * Called after all the initialization is done. If we didnt find any
3146 * APIC bugs then we can allow the modify fast path
3149 static int __init io_apic_bug_finalize(void)
3151 if (sis_apic_bug == -1)
3156 late_initcall(io_apic_bug_finalize);
3158 struct sysfs_ioapic_data {
3159 struct sys_device dev;
3160 struct IO_APIC_route_entry entry[0];
3162 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3164 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3166 struct IO_APIC_route_entry *entry;
3167 struct sysfs_ioapic_data *data;
3170 data = container_of(dev, struct sysfs_ioapic_data, dev);
3171 entry = data->entry;
3172 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3173 *entry = ioapic_read_entry(dev->id, i);
3178 static int ioapic_resume(struct sys_device *dev)
3180 struct IO_APIC_route_entry *entry;
3181 struct sysfs_ioapic_data *data;
3182 unsigned long flags;
3183 union IO_APIC_reg_00 reg_00;
3186 data = container_of(dev, struct sysfs_ioapic_data, dev);
3187 entry = data->entry;
3189 raw_spin_lock_irqsave(&ioapic_lock, flags);
3190 reg_00.raw = io_apic_read(dev->id, 0);
3191 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3192 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3193 io_apic_write(dev->id, 0, reg_00.raw);
3195 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3196 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3197 ioapic_write_entry(dev->id, i, entry[i]);
3202 static struct sysdev_class ioapic_sysdev_class = {
3204 .suspend = ioapic_suspend,
3205 .resume = ioapic_resume,
3208 static int __init ioapic_init_sysfs(void)
3210 struct sys_device * dev;
3213 error = sysdev_class_register(&ioapic_sysdev_class);
3217 for (i = 0; i < nr_ioapics; i++ ) {
3218 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3219 * sizeof(struct IO_APIC_route_entry);
3220 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3221 if (!mp_ioapic_data[i]) {
3222 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3225 dev = &mp_ioapic_data[i]->dev;
3227 dev->cls = &ioapic_sysdev_class;
3228 error = sysdev_register(dev);
3230 kfree(mp_ioapic_data[i]);
3231 mp_ioapic_data[i] = NULL;
3232 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3240 device_initcall(ioapic_init_sysfs);
3243 * Dynamic irq allocate and deallocation
3245 unsigned int create_irq_nr(unsigned int irq_want, int node)
3247 /* Allocate an unused irq */
3250 unsigned long flags;
3251 struct irq_cfg *cfg_new = NULL;
3252 struct irq_desc *desc_new = NULL;
3255 if (irq_want < nr_irqs_gsi)
3256 irq_want = nr_irqs_gsi;
3258 raw_spin_lock_irqsave(&vector_lock, flags);
3259 for (new = irq_want; new < nr_irqs; new++) {
3260 desc_new = irq_to_desc_alloc_node(new, node);
3262 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3265 cfg_new = desc_new->chip_data;
3267 if (cfg_new->vector != 0)
3270 desc_new = move_irq_desc(desc_new, node);
3271 cfg_new = desc_new->chip_data;
3273 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3277 raw_spin_unlock_irqrestore(&vector_lock, flags);
3280 dynamic_irq_init_keep_chip_data(irq);
3285 int create_irq(void)
3287 int node = cpu_to_node(boot_cpu_id);
3288 unsigned int irq_want;
3291 irq_want = nr_irqs_gsi;
3292 irq = create_irq_nr(irq_want, node);
3300 void destroy_irq(unsigned int irq)
3302 unsigned long flags;
3304 dynamic_irq_cleanup_keep_chip_data(irq);
3307 raw_spin_lock_irqsave(&vector_lock, flags);
3308 __clear_irq_vector(irq, get_irq_chip_data(irq));
3309 raw_spin_unlock_irqrestore(&vector_lock, flags);
3313 * MSI message composition
3315 #ifdef CONFIG_PCI_MSI
3316 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3317 struct msi_msg *msg, u8 hpet_id)
3319 struct irq_cfg *cfg;
3327 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3331 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3333 if (irq_remapped(irq)) {
3338 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3339 BUG_ON(ir_index == -1);
3341 memset (&irte, 0, sizeof(irte));
3344 irte.dst_mode = apic->irq_dest_mode;
3345 irte.trigger_mode = 0; /* edge */
3346 irte.dlvry_mode = apic->irq_delivery_mode;
3347 irte.vector = cfg->vector;
3348 irte.dest_id = IRTE_DEST(dest);
3350 /* Set source-id of interrupt request */
3352 set_msi_sid(&irte, pdev);
3354 set_hpet_sid(&irte, hpet_id);
3356 modify_irte(irq, &irte);
3358 msg->address_hi = MSI_ADDR_BASE_HI;
3359 msg->data = sub_handle;
3360 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3362 MSI_ADDR_IR_INDEX1(ir_index) |
3363 MSI_ADDR_IR_INDEX2(ir_index);
3365 if (x2apic_enabled())
3366 msg->address_hi = MSI_ADDR_BASE_HI |
3367 MSI_ADDR_EXT_DEST_ID(dest);
3369 msg->address_hi = MSI_ADDR_BASE_HI;
3373 ((apic->irq_dest_mode == 0) ?
3374 MSI_ADDR_DEST_MODE_PHYSICAL:
3375 MSI_ADDR_DEST_MODE_LOGICAL) |
3376 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3377 MSI_ADDR_REDIRECTION_CPU:
3378 MSI_ADDR_REDIRECTION_LOWPRI) |
3379 MSI_ADDR_DEST_ID(dest);
3382 MSI_DATA_TRIGGER_EDGE |
3383 MSI_DATA_LEVEL_ASSERT |
3384 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3385 MSI_DATA_DELIVERY_FIXED:
3386 MSI_DATA_DELIVERY_LOWPRI) |
3387 MSI_DATA_VECTOR(cfg->vector);
3393 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3395 struct irq_desc *desc = irq_to_desc(irq);
3396 struct irq_cfg *cfg;
3400 if (set_desc_affinity(desc, mask, &dest))
3403 cfg = desc->chip_data;
3405 read_msi_msg_desc(desc, &msg);
3407 msg.data &= ~MSI_DATA_VECTOR_MASK;
3408 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3409 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3410 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3412 write_msi_msg_desc(desc, &msg);
3416 #ifdef CONFIG_INTR_REMAP
3418 * Migrate the MSI irq to another cpumask. This migration is
3419 * done in the process context using interrupt-remapping hardware.
3422 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3424 struct irq_desc *desc = irq_to_desc(irq);
3425 struct irq_cfg *cfg = desc->chip_data;
3429 if (get_irte(irq, &irte))
3432 if (set_desc_affinity(desc, mask, &dest))
3435 irte.vector = cfg->vector;
3436 irte.dest_id = IRTE_DEST(dest);
3439 * atomically update the IRTE with the new destination and vector.
3441 modify_irte(irq, &irte);
3444 * After this point, all the interrupts will start arriving
3445 * at the new destination. So, time to cleanup the previous
3446 * vector allocation.
3448 if (cfg->move_in_progress)
3449 send_cleanup_vector(cfg);
3455 #endif /* CONFIG_SMP */
3458 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3459 * which implement the MSI or MSI-X Capability Structure.
3461 static struct irq_chip msi_chip = {
3463 .unmask = unmask_msi_irq,
3464 .mask = mask_msi_irq,
3465 .ack = ack_apic_edge,
3467 .set_affinity = set_msi_irq_affinity,
3469 .retrigger = ioapic_retrigger_irq,
3472 static struct irq_chip msi_ir_chip = {
3473 .name = "IR-PCI-MSI",
3474 .unmask = unmask_msi_irq,
3475 .mask = mask_msi_irq,
3476 #ifdef CONFIG_INTR_REMAP
3477 .ack = ir_ack_apic_edge,
3479 .set_affinity = ir_set_msi_irq_affinity,
3482 .retrigger = ioapic_retrigger_irq,
3486 * Map the PCI dev to the corresponding remapping hardware unit
3487 * and allocate 'nvec' consecutive interrupt-remapping table entries
3490 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3492 struct intel_iommu *iommu;
3495 iommu = map_dev_to_ir(dev);
3498 "Unable to map PCI %s to iommu\n", pci_name(dev));
3502 index = alloc_irte(iommu, irq, nvec);
3505 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3512 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3517 ret = msi_compose_msg(dev, irq, &msg, -1);
3521 set_irq_msi(irq, msidesc);
3522 write_msi_msg(irq, &msg);
3524 if (irq_remapped(irq)) {
3525 struct irq_desc *desc = irq_to_desc(irq);
3527 * irq migration in process context
3529 desc->status |= IRQ_MOVE_PCNTXT;
3530 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3532 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3534 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3539 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3542 int ret, sub_handle;
3543 struct msi_desc *msidesc;
3544 unsigned int irq_want;
3545 struct intel_iommu *iommu = NULL;
3549 /* x86 doesn't support multiple MSI yet */
3550 if (type == PCI_CAP_ID_MSI && nvec > 1)
3553 node = dev_to_node(&dev->dev);
3554 irq_want = nr_irqs_gsi;
3556 list_for_each_entry(msidesc, &dev->msi_list, list) {
3557 irq = create_irq_nr(irq_want, node);
3561 if (!intr_remapping_enabled)
3566 * allocate the consecutive block of IRTE's
3569 index = msi_alloc_irte(dev, irq, nvec);
3575 iommu = map_dev_to_ir(dev);
3581 * setup the mapping between the irq and the IRTE
3582 * base index, the sub_handle pointing to the
3583 * appropriate interrupt remap table entry.
3585 set_irte_irq(irq, iommu, index, sub_handle);
3588 ret = setup_msi_irq(dev, msidesc, irq);
3600 void arch_teardown_msi_irq(unsigned int irq)
3605 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3607 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3609 struct irq_desc *desc = irq_to_desc(irq);
3610 struct irq_cfg *cfg;
3614 if (set_desc_affinity(desc, mask, &dest))
3617 cfg = desc->chip_data;
3619 dmar_msi_read(irq, &msg);
3621 msg.data &= ~MSI_DATA_VECTOR_MASK;
3622 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3623 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3624 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3626 dmar_msi_write(irq, &msg);
3631 #endif /* CONFIG_SMP */
3633 static struct irq_chip dmar_msi_type = {
3635 .unmask = dmar_msi_unmask,
3636 .mask = dmar_msi_mask,
3637 .ack = ack_apic_edge,
3639 .set_affinity = dmar_msi_set_affinity,
3641 .retrigger = ioapic_retrigger_irq,
3644 int arch_setup_dmar_msi(unsigned int irq)
3649 ret = msi_compose_msg(NULL, irq, &msg, -1);
3652 dmar_msi_write(irq, &msg);
3653 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3659 #ifdef CONFIG_HPET_TIMER
3662 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3664 struct irq_desc *desc = irq_to_desc(irq);
3665 struct irq_cfg *cfg;
3669 if (set_desc_affinity(desc, mask, &dest))
3672 cfg = desc->chip_data;
3674 hpet_msi_read(irq, &msg);
3676 msg.data &= ~MSI_DATA_VECTOR_MASK;
3677 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3678 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3679 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3681 hpet_msi_write(irq, &msg);
3686 #endif /* CONFIG_SMP */
3688 static struct irq_chip ir_hpet_msi_type = {
3689 .name = "IR-HPET_MSI",
3690 .unmask = hpet_msi_unmask,
3691 .mask = hpet_msi_mask,
3692 #ifdef CONFIG_INTR_REMAP
3693 .ack = ir_ack_apic_edge,
3695 .set_affinity = ir_set_msi_irq_affinity,
3698 .retrigger = ioapic_retrigger_irq,
3701 static struct irq_chip hpet_msi_type = {
3703 .unmask = hpet_msi_unmask,
3704 .mask = hpet_msi_mask,
3705 .ack = ack_apic_edge,
3707 .set_affinity = hpet_msi_set_affinity,
3709 .retrigger = ioapic_retrigger_irq,
3712 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3716 struct irq_desc *desc = irq_to_desc(irq);
3718 if (intr_remapping_enabled) {
3719 struct intel_iommu *iommu = map_hpet_to_ir(id);
3725 index = alloc_irte(iommu, irq, 1);
3730 ret = msi_compose_msg(NULL, irq, &msg, id);
3734 hpet_msi_write(irq, &msg);
3735 desc->status |= IRQ_MOVE_PCNTXT;
3736 if (irq_remapped(irq))
3737 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3738 handle_edge_irq, "edge");
3740 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3741 handle_edge_irq, "edge");
3747 #endif /* CONFIG_PCI_MSI */
3749 * Hypertransport interrupt support
3751 #ifdef CONFIG_HT_IRQ
3755 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3757 struct ht_irq_msg msg;
3758 fetch_ht_irq_msg(irq, &msg);
3760 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3761 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3763 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3764 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3766 write_ht_irq_msg(irq, &msg);
3769 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3771 struct irq_desc *desc = irq_to_desc(irq);
3772 struct irq_cfg *cfg;
3775 if (set_desc_affinity(desc, mask, &dest))
3778 cfg = desc->chip_data;
3780 target_ht_irq(irq, dest, cfg->vector);
3787 static struct irq_chip ht_irq_chip = {
3789 .mask = mask_ht_irq,
3790 .unmask = unmask_ht_irq,
3791 .ack = ack_apic_edge,
3793 .set_affinity = set_ht_irq_affinity,
3795 .retrigger = ioapic_retrigger_irq,
3798 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3800 struct irq_cfg *cfg;
3807 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3809 struct ht_irq_msg msg;
3812 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3813 apic->target_cpus());
3815 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3819 HT_IRQ_LOW_DEST_ID(dest) |
3820 HT_IRQ_LOW_VECTOR(cfg->vector) |
3821 ((apic->irq_dest_mode == 0) ?
3822 HT_IRQ_LOW_DM_PHYSICAL :
3823 HT_IRQ_LOW_DM_LOGICAL) |
3824 HT_IRQ_LOW_RQEOI_EDGE |
3825 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3826 HT_IRQ_LOW_MT_FIXED :
3827 HT_IRQ_LOW_MT_ARBITRATED) |
3828 HT_IRQ_LOW_IRQ_MASKED;
3830 write_ht_irq_msg(irq, &msg);
3832 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3833 handle_edge_irq, "edge");
3835 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3839 #endif /* CONFIG_HT_IRQ */
3841 int __init io_apic_get_redir_entries (int ioapic)
3843 union IO_APIC_reg_01 reg_01;
3844 unsigned long flags;
3846 raw_spin_lock_irqsave(&ioapic_lock, flags);
3847 reg_01.raw = io_apic_read(ioapic, 1);
3848 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3850 return reg_01.bits.entries;
3853 void __init probe_nr_irqs_gsi(void)
3857 nr = acpi_probe_gsi();
3858 if (nr > nr_irqs_gsi) {
3861 /* for acpi=off or acpi is not compiled in */
3865 for (idx = 0; idx < nr_ioapics; idx++)
3866 nr += io_apic_get_redir_entries(idx) + 1;
3868 if (nr > nr_irqs_gsi)
3872 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3875 #ifdef CONFIG_SPARSE_IRQ
3876 int __init arch_probe_nr_irqs(void)
3880 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3881 nr_irqs = NR_VECTORS * nr_cpu_ids;
3883 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3884 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3886 * for MSI and HT dyn irq
3888 nr += nr_irqs_gsi * 16;
3897 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3898 struct io_apic_irq_attr *irq_attr)
3900 struct irq_desc *desc;
3901 struct irq_cfg *cfg;
3904 int trigger, polarity;
3906 ioapic = irq_attr->ioapic;
3907 if (!IO_APIC_IRQ(irq)) {
3908 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3914 node = dev_to_node(dev);
3916 node = cpu_to_node(boot_cpu_id);
3918 desc = irq_to_desc_alloc_node(irq, node);
3920 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3924 pin = irq_attr->ioapic_pin;
3925 trigger = irq_attr->trigger;
3926 polarity = irq_attr->polarity;
3929 * IRQs < 16 are already in the irq_2_pin[] map
3931 if (irq >= nr_legacy_irqs) {
3932 cfg = desc->chip_data;
3933 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3934 printk(KERN_INFO "can not add pin %d for irq %d\n",
3940 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3945 int io_apic_set_pci_routing(struct device *dev, int irq,
3946 struct io_apic_irq_attr *irq_attr)
3950 * Avoid pin reprogramming. PRTs typically include entries
3951 * with redundant pin->gsi mappings (but unique PCI devices);
3952 * we only program the IOAPIC on the first.
3954 ioapic = irq_attr->ioapic;
3955 pin = irq_attr->ioapic_pin;
3956 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3957 pr_debug("Pin %d-%d already programmed\n",
3958 mp_ioapics[ioapic].apicid, pin);
3961 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3963 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3966 u8 __init io_apic_unique_id(u8 id)
3968 #ifdef CONFIG_X86_32
3969 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3970 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3971 return io_apic_get_unique_id(nr_ioapics, id);
3976 DECLARE_BITMAP(used, 256);
3978 bitmap_zero(used, 256);
3979 for (i = 0; i < nr_ioapics; i++) {
3980 struct mpc_ioapic *ia = &mp_ioapics[i];
3981 __set_bit(ia->apicid, used);
3983 if (!test_bit(id, used))
3985 return find_first_zero_bit(used, 256);
3989 #ifdef CONFIG_X86_32
3990 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3992 union IO_APIC_reg_00 reg_00;
3993 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3995 unsigned long flags;
3999 * The P4 platform supports up to 256 APIC IDs on two separate APIC
4000 * buses (one for LAPICs, one for IOAPICs), where predecessors only
4001 * supports up to 16 on one shared APIC bus.
4003 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
4004 * advantage of new APIC bus architecture.
4007 if (physids_empty(apic_id_map))
4008 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
4010 raw_spin_lock_irqsave(&ioapic_lock, flags);
4011 reg_00.raw = io_apic_read(ioapic, 0);
4012 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4014 if (apic_id >= get_physical_broadcast()) {
4015 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
4016 "%d\n", ioapic, apic_id, reg_00.bits.ID);
4017 apic_id = reg_00.bits.ID;
4021 * Every APIC in a system must have a unique ID or we get lots of nice
4022 * 'stuck on smp_invalidate_needed IPI wait' messages.
4024 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
4026 for (i = 0; i < get_physical_broadcast(); i++) {
4027 if (!apic->check_apicid_used(&apic_id_map, i))
4031 if (i == get_physical_broadcast())
4032 panic("Max apic_id exceeded!\n");
4034 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
4035 "trying %d\n", ioapic, apic_id, i);
4040 apic->apicid_to_cpu_present(apic_id, &tmp);
4041 physids_or(apic_id_map, apic_id_map, tmp);
4043 if (reg_00.bits.ID != apic_id) {
4044 reg_00.bits.ID = apic_id;
4046 raw_spin_lock_irqsave(&ioapic_lock, flags);
4047 io_apic_write(ioapic, 0, reg_00.raw);
4048 reg_00.raw = io_apic_read(ioapic, 0);
4049 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4052 if (reg_00.bits.ID != apic_id) {
4053 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4058 apic_printk(APIC_VERBOSE, KERN_INFO
4059 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4065 int __init io_apic_get_version(int ioapic)
4067 union IO_APIC_reg_01 reg_01;
4068 unsigned long flags;
4070 raw_spin_lock_irqsave(&ioapic_lock, flags);
4071 reg_01.raw = io_apic_read(ioapic, 1);
4072 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4074 return reg_01.bits.version;
4077 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4081 if (skip_ioapic_setup)
4084 for (i = 0; i < mp_irq_entries; i++)
4085 if (mp_irqs[i].irqtype == mp_INT &&
4086 mp_irqs[i].srcbusirq == bus_irq)
4088 if (i >= mp_irq_entries)
4091 *trigger = irq_trigger(i);
4092 *polarity = irq_polarity(i);
4097 * This function currently is only a helper for the i386 smp boot process where
4098 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4099 * so mask in all cases should simply be apic->target_cpus()
4102 void __init setup_ioapic_dest(void)
4104 int pin, ioapic, irq, irq_entry;
4105 struct irq_desc *desc;
4106 const struct cpumask *mask;
4108 if (skip_ioapic_setup == 1)
4111 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
4112 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4113 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4114 if (irq_entry == -1)
4116 irq = pin_2_irq(irq_entry, ioapic, pin);
4118 if ((ioapic > 0) && (irq > 16))
4121 desc = irq_to_desc(irq);
4124 * Honour affinities which have been set in early boot
4127 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4128 mask = desc->affinity;
4130 mask = apic->target_cpus();
4132 if (intr_remapping_enabled)
4133 set_ir_ioapic_affinity_irq_desc(desc, mask);
4135 set_ioapic_affinity_irq_desc(desc, mask);
4141 #define IOAPIC_RESOURCE_NAME_SIZE 11
4143 static struct resource *ioapic_resources;
4145 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4148 struct resource *res;
4152 if (nr_ioapics <= 0)
4155 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4158 mem = alloc_bootmem(n);
4161 mem += sizeof(struct resource) * nr_ioapics;
4163 for (i = 0; i < nr_ioapics; i++) {
4165 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4166 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4167 mem += IOAPIC_RESOURCE_NAME_SIZE;
4170 ioapic_resources = res;
4175 void __init ioapic_init_mappings(void)
4177 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4178 struct resource *ioapic_res;
4181 ioapic_res = ioapic_setup_resources(nr_ioapics);
4182 for (i = 0; i < nr_ioapics; i++) {
4183 if (smp_found_config) {
4184 ioapic_phys = mp_ioapics[i].apicaddr;
4185 #ifdef CONFIG_X86_32
4188 "WARNING: bogus zero IO-APIC "
4189 "address found in MPTABLE, "
4190 "disabling IO/APIC support!\n");
4191 smp_found_config = 0;
4192 skip_ioapic_setup = 1;
4193 goto fake_ioapic_page;
4197 #ifdef CONFIG_X86_32
4200 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4201 ioapic_phys = __pa(ioapic_phys);
4203 set_fixmap_nocache(idx, ioapic_phys);
4204 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4205 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4209 ioapic_res->start = ioapic_phys;
4210 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4215 void __init ioapic_insert_resources(void)
4218 struct resource *r = ioapic_resources;
4223 "IO APIC resources couldn't be allocated.\n");
4227 for (i = 0; i < nr_ioapics; i++) {
4228 insert_resource(&iomem_resource, r);
4233 int mp_find_ioapic(int gsi)
4237 /* Find the IOAPIC that manages this GSI. */
4238 for (i = 0; i < nr_ioapics; i++) {
4239 if ((gsi >= mp_gsi_routing[i].gsi_base)
4240 && (gsi <= mp_gsi_routing[i].gsi_end))
4244 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4248 int mp_find_ioapic_pin(int ioapic, int gsi)
4250 if (WARN_ON(ioapic == -1))
4252 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4255 return gsi - mp_gsi_routing[ioapic].gsi_base;
4258 static int bad_ioapic(unsigned long address)
4260 if (nr_ioapics >= MAX_IO_APICS) {
4261 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4262 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4266 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4267 " found in table, skipping!\n");
4273 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4277 if (bad_ioapic(address))
4282 mp_ioapics[idx].type = MP_IOAPIC;
4283 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4284 mp_ioapics[idx].apicaddr = address;
4286 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4287 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4288 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4291 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4292 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4294 mp_gsi_routing[idx].gsi_base = gsi_base;
4295 mp_gsi_routing[idx].gsi_end = gsi_base +
4296 io_apic_get_redir_entries(idx);
4298 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4299 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4300 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4301 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);