2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* The one past the highest gsi number used */
94 /* MP IRQ source entries */
95 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
97 /* # of MP IRQ source entries */
101 static int nr_irqs_gsi = NR_IRQS_LEGACY;
103 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
104 int mp_bus_id_to_type[MAX_MP_BUSSES];
107 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
109 int skip_ioapic_setup;
111 void arch_disable_smp_support(void)
115 noioapicreroute = -1;
117 skip_ioapic_setup = 1;
120 static int __init parse_noapic(char *str)
122 /* disable IO-APIC */
123 arch_disable_smp_support();
126 early_param("noapic", parse_noapic);
128 struct irq_pin_list {
130 struct irq_pin_list *next;
133 static struct irq_pin_list *alloc_irq_pin_list(int node)
135 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
138 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
139 #ifdef CONFIG_SPARSE_IRQ
140 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
142 static struct irq_cfg irq_cfgx[NR_IRQS];
145 int __init arch_early_irq_init(void)
150 if (!legacy_pic->nr_legacy_irqs) {
156 count = ARRAY_SIZE(irq_cfgx);
157 node = cpu_to_node(0);
159 /* Make sure the legacy interrupts are marked in the bitmap */
160 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
162 for (i = 0; i < count; i++) {
163 set_irq_chip_data(i, &cfg[i]);
164 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
165 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
167 * For legacy IRQ's, start with assigning irq0 to irq15 to
168 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
170 if (i < legacy_pic->nr_legacy_irqs) {
171 cfg[i].vector = IRQ0_VECTOR + i;
172 cpumask_set_cpu(0, cfg[i].domain);
179 #ifdef CONFIG_SPARSE_IRQ
180 static struct irq_cfg *irq_cfg(unsigned int irq)
182 return get_irq_chip_data(irq);
185 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
189 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
192 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
194 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
198 free_cpumask_var(cfg->domain);
204 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
208 set_irq_chip_data(at, NULL);
209 free_cpumask_var(cfg->domain);
210 free_cpumask_var(cfg->old_domain);
216 struct irq_cfg *irq_cfg(unsigned int irq)
218 return irq < nr_irqs ? irq_cfgx + irq : NULL;
221 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
223 return irq_cfgx + irq;
226 static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { }
230 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
232 int res = irq_alloc_desc_at(at, node);
238 cfg = get_irq_chip_data(at);
243 cfg = alloc_irq_cfg(at, node);
245 set_irq_chip_data(at, cfg);
251 static int alloc_irq_from(unsigned int from, int node)
253 return irq_alloc_desc_from(from, node);
256 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
258 free_irq_cfg(at, cfg);
264 unsigned int unused[3];
266 unsigned int unused2[11];
270 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
272 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
273 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
276 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
278 struct io_apic __iomem *io_apic = io_apic_base(apic);
279 writel(vector, &io_apic->eoi);
282 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
284 struct io_apic __iomem *io_apic = io_apic_base(apic);
285 writel(reg, &io_apic->index);
286 return readl(&io_apic->data);
289 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
291 struct io_apic __iomem *io_apic = io_apic_base(apic);
292 writel(reg, &io_apic->index);
293 writel(value, &io_apic->data);
297 * Re-write a value: to be used for read-modify-write
298 * cycles where the read already set up the index register.
300 * Older SiS APIC requires we rewrite the index register
302 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
304 struct io_apic __iomem *io_apic = io_apic_base(apic);
307 writel(reg, &io_apic->index);
308 writel(value, &io_apic->data);
311 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
313 struct irq_pin_list *entry;
316 raw_spin_lock_irqsave(&ioapic_lock, flags);
317 for_each_irq_pin(entry, cfg->irq_2_pin) {
322 reg = io_apic_read(entry->apic, 0x10 + pin*2);
323 /* Is the remote IRR bit set? */
324 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
325 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
329 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
335 struct { u32 w1, w2; };
336 struct IO_APIC_route_entry entry;
339 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
341 union entry_union eu;
343 raw_spin_lock_irqsave(&ioapic_lock, flags);
344 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
345 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
346 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
351 * When we write a new IO APIC routing entry, we need to write the high
352 * word first! If the mask bit in the low word is clear, we will enable
353 * the interrupt, and we need to make sure the entry is fully populated
354 * before that happens.
357 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
359 union entry_union eu = {{0, 0}};
362 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
363 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
366 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
369 raw_spin_lock_irqsave(&ioapic_lock, flags);
370 __ioapic_write_entry(apic, pin, e);
371 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
375 * When we mask an IO APIC routing entry, we need to write the low
376 * word first, in order to set the mask bit before we change the
379 static void ioapic_mask_entry(int apic, int pin)
382 union entry_union eu = { .entry.mask = 1 };
384 raw_spin_lock_irqsave(&ioapic_lock, flags);
385 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
386 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
387 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
391 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
392 * shared ISA-space IRQs, so we have to support them. We are super
393 * fast in the common case, and fast for shared ISA-space IRQs.
396 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
398 struct irq_pin_list **last, *entry;
400 /* don't allow duplicates */
401 last = &cfg->irq_2_pin;
402 for_each_irq_pin(entry, cfg->irq_2_pin) {
403 if (entry->apic == apic && entry->pin == pin)
408 entry = alloc_irq_pin_list(node);
410 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
421 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
423 if (__add_pin_to_irq_node(cfg, node, apic, pin))
424 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
428 * Reroute an IRQ to a different pin.
430 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
431 int oldapic, int oldpin,
432 int newapic, int newpin)
434 struct irq_pin_list *entry;
436 for_each_irq_pin(entry, cfg->irq_2_pin) {
437 if (entry->apic == oldapic && entry->pin == oldpin) {
438 entry->apic = newapic;
440 /* every one is different, right? */
445 /* old apic/pin didn't exist, so just add new ones */
446 add_pin_to_irq_node(cfg, node, newapic, newpin);
449 static void __io_apic_modify_irq(struct irq_pin_list *entry,
450 int mask_and, int mask_or,
451 void (*final)(struct irq_pin_list *entry))
453 unsigned int reg, pin;
456 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
459 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
464 static void io_apic_modify_irq(struct irq_cfg *cfg,
465 int mask_and, int mask_or,
466 void (*final)(struct irq_pin_list *entry))
468 struct irq_pin_list *entry;
470 for_each_irq_pin(entry, cfg->irq_2_pin)
471 __io_apic_modify_irq(entry, mask_and, mask_or, final);
474 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
476 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
477 IO_APIC_REDIR_MASKED, NULL);
480 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
482 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
483 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
486 static void io_apic_sync(struct irq_pin_list *entry)
489 * Synchronize the IO-APIC and the CPU by doing
490 * a dummy read from the IO-APIC
492 struct io_apic __iomem *io_apic;
493 io_apic = io_apic_base(entry->apic);
494 readl(&io_apic->data);
497 static void mask_ioapic(struct irq_cfg *cfg)
501 raw_spin_lock_irqsave(&ioapic_lock, flags);
502 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
503 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
506 static void mask_ioapic_irq(struct irq_data *data)
508 mask_ioapic(data->chip_data);
511 static void __unmask_ioapic(struct irq_cfg *cfg)
513 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
516 static void unmask_ioapic(struct irq_cfg *cfg)
520 raw_spin_lock_irqsave(&ioapic_lock, flags);
521 __unmask_ioapic(cfg);
522 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
525 static void unmask_ioapic_irq(struct irq_data *data)
527 unmask_ioapic(data->chip_data);
530 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
532 struct IO_APIC_route_entry entry;
534 /* Check delivery_mode to be sure we're not clearing an SMI pin */
535 entry = ioapic_read_entry(apic, pin);
536 if (entry.delivery_mode == dest_SMI)
539 * Disable it in the IO-APIC irq-routing table:
541 ioapic_mask_entry(apic, pin);
544 static void clear_IO_APIC (void)
548 for (apic = 0; apic < nr_ioapics; apic++)
549 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
550 clear_IO_APIC_pin(apic, pin);
555 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
556 * specific CPU-side IRQs.
560 static int pirq_entries[MAX_PIRQS] = {
561 [0 ... MAX_PIRQS - 1] = -1
564 static int __init ioapic_pirq_setup(char *str)
567 int ints[MAX_PIRQS+1];
569 get_options(str, ARRAY_SIZE(ints), ints);
571 apic_printk(APIC_VERBOSE, KERN_INFO
572 "PIRQ redirection, working around broken MP-BIOS.\n");
574 if (ints[0] < MAX_PIRQS)
577 for (i = 0; i < max; i++) {
578 apic_printk(APIC_VERBOSE, KERN_DEBUG
579 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
581 * PIRQs are mapped upside down, usually.
583 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
588 __setup("pirq=", ioapic_pirq_setup);
589 #endif /* CONFIG_X86_32 */
591 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
594 struct IO_APIC_route_entry **ioapic_entries;
596 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
601 for (apic = 0; apic < nr_ioapics; apic++) {
602 ioapic_entries[apic] =
603 kzalloc(sizeof(struct IO_APIC_route_entry) *
604 nr_ioapic_registers[apic], GFP_KERNEL);
605 if (!ioapic_entries[apic])
609 return ioapic_entries;
613 kfree(ioapic_entries[apic]);
614 kfree(ioapic_entries);
620 * Saves all the IO-APIC RTE's
622 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
629 for (apic = 0; apic < nr_ioapics; apic++) {
630 if (!ioapic_entries[apic])
633 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
634 ioapic_entries[apic][pin] =
635 ioapic_read_entry(apic, pin);
642 * Mask all IO APIC entries.
644 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
651 for (apic = 0; apic < nr_ioapics; apic++) {
652 if (!ioapic_entries[apic])
655 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
656 struct IO_APIC_route_entry entry;
658 entry = ioapic_entries[apic][pin];
661 ioapic_write_entry(apic, pin, entry);
668 * Restore IO APIC entries which was saved in ioapic_entries.
670 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
677 for (apic = 0; apic < nr_ioapics; apic++) {
678 if (!ioapic_entries[apic])
681 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
682 ioapic_write_entry(apic, pin,
683 ioapic_entries[apic][pin]);
688 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
692 for (apic = 0; apic < nr_ioapics; apic++)
693 kfree(ioapic_entries[apic]);
695 kfree(ioapic_entries);
699 * Find the IRQ entry number of a certain pin.
701 static int find_irq_entry(int apic, int pin, int type)
705 for (i = 0; i < mp_irq_entries; i++)
706 if (mp_irqs[i].irqtype == type &&
707 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
708 mp_irqs[i].dstapic == MP_APIC_ALL) &&
709 mp_irqs[i].dstirq == pin)
716 * Find the pin to which IRQ[irq] (ISA) is connected
718 static int __init find_isa_irq_pin(int irq, int type)
722 for (i = 0; i < mp_irq_entries; i++) {
723 int lbus = mp_irqs[i].srcbus;
725 if (test_bit(lbus, mp_bus_not_pci) &&
726 (mp_irqs[i].irqtype == type) &&
727 (mp_irqs[i].srcbusirq == irq))
729 return mp_irqs[i].dstirq;
734 static int __init find_isa_irq_apic(int irq, int type)
738 for (i = 0; i < mp_irq_entries; i++) {
739 int lbus = mp_irqs[i].srcbus;
741 if (test_bit(lbus, mp_bus_not_pci) &&
742 (mp_irqs[i].irqtype == type) &&
743 (mp_irqs[i].srcbusirq == irq))
746 if (i < mp_irq_entries) {
748 for(apic = 0; apic < nr_ioapics; apic++) {
749 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
757 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
759 * EISA Edge/Level control register, ELCR
761 static int EISA_ELCR(unsigned int irq)
763 if (irq < legacy_pic->nr_legacy_irqs) {
764 unsigned int port = 0x4d0 + (irq >> 3);
765 return (inb(port) >> (irq & 7)) & 1;
767 apic_printk(APIC_VERBOSE, KERN_INFO
768 "Broken MPtable reports ISA irq %d\n", irq);
774 /* ISA interrupts are always polarity zero edge triggered,
775 * when listed as conforming in the MP table. */
777 #define default_ISA_trigger(idx) (0)
778 #define default_ISA_polarity(idx) (0)
780 /* EISA interrupts are always polarity zero and can be edge or level
781 * trigger depending on the ELCR value. If an interrupt is listed as
782 * EISA conforming in the MP table, that means its trigger type must
783 * be read in from the ELCR */
785 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
786 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
788 /* PCI interrupts are always polarity one level triggered,
789 * when listed as conforming in the MP table. */
791 #define default_PCI_trigger(idx) (1)
792 #define default_PCI_polarity(idx) (1)
794 /* MCA interrupts are always polarity zero level triggered,
795 * when listed as conforming in the MP table. */
797 #define default_MCA_trigger(idx) (1)
798 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
800 static int MPBIOS_polarity(int idx)
802 int bus = mp_irqs[idx].srcbus;
806 * Determine IRQ line polarity (high active or low active):
808 switch (mp_irqs[idx].irqflag & 3)
810 case 0: /* conforms, ie. bus-type dependent polarity */
811 if (test_bit(bus, mp_bus_not_pci))
812 polarity = default_ISA_polarity(idx);
814 polarity = default_PCI_polarity(idx);
816 case 1: /* high active */
821 case 2: /* reserved */
823 printk(KERN_WARNING "broken BIOS!!\n");
827 case 3: /* low active */
832 default: /* invalid */
834 printk(KERN_WARNING "broken BIOS!!\n");
842 static int MPBIOS_trigger(int idx)
844 int bus = mp_irqs[idx].srcbus;
848 * Determine IRQ trigger mode (edge or level sensitive):
850 switch ((mp_irqs[idx].irqflag>>2) & 3)
852 case 0: /* conforms, ie. bus-type dependent */
853 if (test_bit(bus, mp_bus_not_pci))
854 trigger = default_ISA_trigger(idx);
856 trigger = default_PCI_trigger(idx);
857 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
858 switch (mp_bus_id_to_type[bus]) {
859 case MP_BUS_ISA: /* ISA pin */
861 /* set before the switch */
864 case MP_BUS_EISA: /* EISA pin */
866 trigger = default_EISA_trigger(idx);
869 case MP_BUS_PCI: /* PCI pin */
871 /* set before the switch */
874 case MP_BUS_MCA: /* MCA pin */
876 trigger = default_MCA_trigger(idx);
881 printk(KERN_WARNING "broken BIOS!!\n");
893 case 2: /* reserved */
895 printk(KERN_WARNING "broken BIOS!!\n");
904 default: /* invalid */
906 printk(KERN_WARNING "broken BIOS!!\n");
914 static inline int irq_polarity(int idx)
916 return MPBIOS_polarity(idx);
919 static inline int irq_trigger(int idx)
921 return MPBIOS_trigger(idx);
924 static int pin_2_irq(int idx, int apic, int pin)
927 int bus = mp_irqs[idx].srcbus;
930 * Debugging check, we are in big trouble if this message pops up!
932 if (mp_irqs[idx].dstirq != pin)
933 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
935 if (test_bit(bus, mp_bus_not_pci)) {
936 irq = mp_irqs[idx].srcbusirq;
938 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
940 if (gsi >= NR_IRQS_LEGACY)
948 * PCI IRQ command line redirection. Yes, limits are hardcoded.
950 if ((pin >= 16) && (pin <= 23)) {
951 if (pirq_entries[pin-16] != -1) {
952 if (!pirq_entries[pin-16]) {
953 apic_printk(APIC_VERBOSE, KERN_DEBUG
954 "disabling PIRQ%d\n", pin-16);
956 irq = pirq_entries[pin-16];
957 apic_printk(APIC_VERBOSE, KERN_DEBUG
958 "using PIRQ%d -> IRQ %d\n",
969 * Find a specific PCI IRQ entry.
970 * Not an __init, possibly needed by modules
972 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
973 struct io_apic_irq_attr *irq_attr)
975 int apic, i, best_guess = -1;
977 apic_printk(APIC_DEBUG,
978 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
980 if (test_bit(bus, mp_bus_not_pci)) {
981 apic_printk(APIC_VERBOSE,
982 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
985 for (i = 0; i < mp_irq_entries; i++) {
986 int lbus = mp_irqs[i].srcbus;
988 for (apic = 0; apic < nr_ioapics; apic++)
989 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
990 mp_irqs[i].dstapic == MP_APIC_ALL)
993 if (!test_bit(lbus, mp_bus_not_pci) &&
994 !mp_irqs[i].irqtype &&
996 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
997 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
999 if (!(apic || IO_APIC_IRQ(irq)))
1002 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1003 set_io_apic_irq_attr(irq_attr, apic,
1010 * Use the first all-but-pin matching entry as a
1011 * best-guess fuzzy result for broken mptables.
1013 if (best_guess < 0) {
1014 set_io_apic_irq_attr(irq_attr, apic,
1024 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1026 void lock_vector_lock(void)
1028 /* Used to the online set of cpus does not change
1029 * during assign_irq_vector.
1031 raw_spin_lock(&vector_lock);
1034 void unlock_vector_lock(void)
1036 raw_spin_unlock(&vector_lock);
1040 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1043 * NOTE! The local APIC isn't very good at handling
1044 * multiple interrupts at the same interrupt level.
1045 * As the interrupt level is determined by taking the
1046 * vector number and shifting that right by 4, we
1047 * want to spread these out a bit so that they don't
1048 * all fall in the same interrupt level.
1050 * Also, we've got to be careful not to trash gate
1051 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1053 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1054 static int current_offset = VECTOR_OFFSET_START % 8;
1055 unsigned int old_vector;
1057 cpumask_var_t tmp_mask;
1059 if (cfg->move_in_progress)
1062 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1065 old_vector = cfg->vector;
1067 cpumask_and(tmp_mask, mask, cpu_online_mask);
1068 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1069 if (!cpumask_empty(tmp_mask)) {
1070 free_cpumask_var(tmp_mask);
1075 /* Only try and allocate irqs on cpus that are present */
1077 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1081 apic->vector_allocation_domain(cpu, tmp_mask);
1083 vector = current_vector;
1084 offset = current_offset;
1087 if (vector >= first_system_vector) {
1088 /* If out of vectors on large boxen, must share them. */
1089 offset = (offset + 1) % 8;
1090 vector = FIRST_EXTERNAL_VECTOR + offset;
1092 if (unlikely(current_vector == vector))
1095 if (test_bit(vector, used_vectors))
1098 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1099 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1102 current_vector = vector;
1103 current_offset = offset;
1105 cfg->move_in_progress = 1;
1106 cpumask_copy(cfg->old_domain, cfg->domain);
1108 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1109 per_cpu(vector_irq, new_cpu)[vector] = irq;
1110 cfg->vector = vector;
1111 cpumask_copy(cfg->domain, tmp_mask);
1115 free_cpumask_var(tmp_mask);
1119 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1122 unsigned long flags;
1124 raw_spin_lock_irqsave(&vector_lock, flags);
1125 err = __assign_irq_vector(irq, cfg, mask);
1126 raw_spin_unlock_irqrestore(&vector_lock, flags);
1130 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1134 BUG_ON(!cfg->vector);
1136 vector = cfg->vector;
1137 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1138 per_cpu(vector_irq, cpu)[vector] = -1;
1141 cpumask_clear(cfg->domain);
1143 if (likely(!cfg->move_in_progress))
1145 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1146 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1148 if (per_cpu(vector_irq, cpu)[vector] != irq)
1150 per_cpu(vector_irq, cpu)[vector] = -1;
1154 cfg->move_in_progress = 0;
1157 void __setup_vector_irq(int cpu)
1159 /* Initialize vector_irq on a new cpu */
1161 struct irq_cfg *cfg;
1164 * vector_lock will make sure that we don't run into irq vector
1165 * assignments that might be happening on another cpu in parallel,
1166 * while we setup our initial vector to irq mappings.
1168 raw_spin_lock(&vector_lock);
1169 /* Mark the inuse vectors */
1170 for_each_active_irq(irq) {
1171 cfg = get_irq_chip_data(irq);
1175 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1176 * will be part of the irq_cfg's domain.
1178 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1179 cpumask_set_cpu(cpu, cfg->domain);
1181 if (!cpumask_test_cpu(cpu, cfg->domain))
1183 vector = cfg->vector;
1184 per_cpu(vector_irq, cpu)[vector] = irq;
1186 /* Mark the free vectors */
1187 for (vector = 0; vector < NR_VECTORS; ++vector) {
1188 irq = per_cpu(vector_irq, cpu)[vector];
1193 if (!cpumask_test_cpu(cpu, cfg->domain))
1194 per_cpu(vector_irq, cpu)[vector] = -1;
1196 raw_spin_unlock(&vector_lock);
1199 static struct irq_chip ioapic_chip;
1200 static struct irq_chip ir_ioapic_chip;
1202 #define IOAPIC_AUTO -1
1203 #define IOAPIC_EDGE 0
1204 #define IOAPIC_LEVEL 1
1206 #ifdef CONFIG_X86_32
1207 static inline int IO_APIC_irq_trigger(int irq)
1211 for (apic = 0; apic < nr_ioapics; apic++) {
1212 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1213 idx = find_irq_entry(apic, pin, mp_INT);
1214 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1215 return irq_trigger(idx);
1219 * nonexistent IRQs are edge default
1224 static inline int IO_APIC_irq_trigger(int irq)
1230 static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
1233 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1234 trigger == IOAPIC_LEVEL)
1235 irq_set_status_flags(irq, IRQ_LEVEL);
1237 irq_clear_status_flags(irq, IRQ_LEVEL);
1239 if (irq_remapped(get_irq_chip_data(irq))) {
1240 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1242 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1246 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1247 handle_edge_irq, "edge");
1251 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1252 trigger == IOAPIC_LEVEL)
1253 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1257 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1258 handle_edge_irq, "edge");
1261 static int setup_ioapic_entry(int apic_id, int irq,
1262 struct IO_APIC_route_entry *entry,
1263 unsigned int destination, int trigger,
1264 int polarity, int vector, int pin)
1267 * add it to the IO-APIC irq-routing table:
1269 memset(entry,0,sizeof(*entry));
1271 if (intr_remapping_enabled) {
1272 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1274 struct IR_IO_APIC_route_entry *ir_entry =
1275 (struct IR_IO_APIC_route_entry *) entry;
1279 panic("No mapping iommu for ioapic %d\n", apic_id);
1281 index = alloc_irte(iommu, irq, 1);
1283 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1285 prepare_irte(&irte, vector, destination);
1287 /* Set source-id of interrupt request */
1288 set_ioapic_sid(&irte, apic_id);
1290 modify_irte(irq, &irte);
1292 ir_entry->index2 = (index >> 15) & 0x1;
1294 ir_entry->format = 1;
1295 ir_entry->index = (index & 0x7fff);
1297 * IO-APIC RTE will be configured with virtual vector.
1298 * irq handler will do the explicit EOI to the io-apic.
1300 ir_entry->vector = pin;
1302 entry->delivery_mode = apic->irq_delivery_mode;
1303 entry->dest_mode = apic->irq_dest_mode;
1304 entry->dest = destination;
1305 entry->vector = vector;
1308 entry->mask = 0; /* enable IRQ */
1309 entry->trigger = trigger;
1310 entry->polarity = polarity;
1312 /* Mask level triggered irqs.
1313 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1320 static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1321 struct irq_cfg *cfg, int trigger, int polarity)
1323 struct IO_APIC_route_entry entry;
1326 if (!IO_APIC_IRQ(irq))
1329 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1330 * controllers like 8259. Now that IO-APIC can handle this irq, update
1333 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1334 apic->vector_allocation_domain(0, cfg->domain);
1336 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1339 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1341 apic_printk(APIC_VERBOSE,KERN_DEBUG
1342 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1343 "IRQ %d Mode:%i Active:%i)\n",
1344 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1345 irq, trigger, polarity);
1348 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1349 dest, trigger, polarity, cfg->vector, pin)) {
1350 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1351 mp_ioapics[apic_id].apicid, pin);
1352 __clear_irq_vector(irq, cfg);
1356 ioapic_register_intr(irq, trigger);
1357 if (irq < legacy_pic->nr_legacy_irqs)
1358 legacy_pic->mask(irq);
1360 ioapic_write_entry(apic_id, pin, entry);
1364 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1365 } mp_ioapic_routing[MAX_IO_APICS];
1367 static void __init setup_IO_APIC_irqs(void)
1369 int apic_id, pin, idx, irq, notcon = 0;
1370 int node = cpu_to_node(0);
1371 struct irq_cfg *cfg;
1373 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1375 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1376 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1377 idx = find_irq_entry(apic_id, pin, mp_INT);
1381 apic_printk(APIC_VERBOSE,
1382 KERN_DEBUG " %d-%d",
1383 mp_ioapics[apic_id].apicid, pin);
1385 apic_printk(APIC_VERBOSE, " %d-%d",
1386 mp_ioapics[apic_id].apicid, pin);
1390 apic_printk(APIC_VERBOSE,
1391 " (apicid-pin) not connected\n");
1395 irq = pin_2_irq(idx, apic_id, pin);
1397 if ((apic_id > 0) && (irq > 16))
1401 * Skip the timer IRQ if there's a quirk handler
1402 * installed and if it returns 1:
1404 if (apic->multi_timer_check &&
1405 apic->multi_timer_check(apic_id, irq))
1408 cfg = alloc_irq_and_cfg_at(irq, node);
1412 add_pin_to_irq_node(cfg, node, apic_id, pin);
1414 * don't mark it in pin_programmed, so later acpi could
1415 * set it correctly when irq < 16
1417 setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx),
1422 apic_printk(APIC_VERBOSE,
1423 " (apicid-pin) not connected\n");
1427 * for the gsit that is not in first ioapic
1428 * but could not use acpi_register_gsi()
1429 * like some special sci in IBM x3330
1431 void setup_IO_APIC_irq_extra(u32 gsi)
1433 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
1434 struct irq_cfg *cfg;
1437 * Convert 'gsi' to 'ioapic.pin'.
1439 apic_id = mp_find_ioapic(gsi);
1443 pin = mp_find_ioapic_pin(apic_id, gsi);
1444 idx = find_irq_entry(apic_id, pin, mp_INT);
1448 irq = pin_2_irq(idx, apic_id, pin);
1450 /* Only handle the non legacy irqs on secondary ioapics */
1451 if (apic_id == 0 || irq < NR_IRQS_LEGACY)
1454 cfg = alloc_irq_and_cfg_at(irq, node);
1458 add_pin_to_irq_node(cfg, node, apic_id, pin);
1460 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1461 pr_debug("Pin %d-%d already programmed\n",
1462 mp_ioapics[apic_id].apicid, pin);
1465 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1467 setup_ioapic_irq(apic_id, pin, irq, cfg,
1468 irq_trigger(idx), irq_polarity(idx));
1472 * Set up the timer pin, possibly with the 8259A-master behind.
1474 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1477 struct IO_APIC_route_entry entry;
1479 if (intr_remapping_enabled)
1482 memset(&entry, 0, sizeof(entry));
1485 * We use logical delivery to get the timer IRQ
1488 entry.dest_mode = apic->irq_dest_mode;
1489 entry.mask = 0; /* don't mask IRQ for edge */
1490 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1491 entry.delivery_mode = apic->irq_delivery_mode;
1494 entry.vector = vector;
1497 * The timer IRQ doesn't have to know that behind the
1498 * scene we may have a 8259A-master in AEOI mode ...
1500 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1503 * Add it to the IO-APIC irq-routing table:
1505 ioapic_write_entry(apic_id, pin, entry);
1509 __apicdebuginit(void) print_IO_APIC(void)
1512 union IO_APIC_reg_00 reg_00;
1513 union IO_APIC_reg_01 reg_01;
1514 union IO_APIC_reg_02 reg_02;
1515 union IO_APIC_reg_03 reg_03;
1516 unsigned long flags;
1517 struct irq_cfg *cfg;
1520 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1521 for (i = 0; i < nr_ioapics; i++)
1522 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1523 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1526 * We are a bit conservative about what we expect. We have to
1527 * know about every hardware change ASAP.
1529 printk(KERN_INFO "testing the IO APIC.......................\n");
1531 for (apic = 0; apic < nr_ioapics; apic++) {
1533 raw_spin_lock_irqsave(&ioapic_lock, flags);
1534 reg_00.raw = io_apic_read(apic, 0);
1535 reg_01.raw = io_apic_read(apic, 1);
1536 if (reg_01.bits.version >= 0x10)
1537 reg_02.raw = io_apic_read(apic, 2);
1538 if (reg_01.bits.version >= 0x20)
1539 reg_03.raw = io_apic_read(apic, 3);
1540 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1543 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1544 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1545 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1546 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1547 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1549 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1550 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1552 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1553 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1556 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1557 * but the value of reg_02 is read as the previous read register
1558 * value, so ignore it if reg_02 == reg_01.
1560 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1561 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1562 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1566 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1567 * or reg_03, but the value of reg_0[23] is read as the previous read
1568 * register value, so ignore it if reg_03 == reg_0[12].
1570 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1571 reg_03.raw != reg_01.raw) {
1572 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1573 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1576 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1578 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1579 " Stat Dmod Deli Vect:\n");
1581 for (i = 0; i <= reg_01.bits.entries; i++) {
1582 struct IO_APIC_route_entry entry;
1584 entry = ioapic_read_entry(apic, i);
1586 printk(KERN_DEBUG " %02x %03X ",
1591 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1596 entry.delivery_status,
1598 entry.delivery_mode,
1603 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1604 for_each_active_irq(irq) {
1605 struct irq_pin_list *entry;
1607 cfg = get_irq_chip_data(irq);
1610 entry = cfg->irq_2_pin;
1613 printk(KERN_DEBUG "IRQ%d ", irq);
1614 for_each_irq_pin(entry, cfg->irq_2_pin)
1615 printk("-> %d:%d", entry->apic, entry->pin);
1619 printk(KERN_INFO ".................................... done.\n");
1624 __apicdebuginit(void) print_APIC_field(int base)
1630 for (i = 0; i < 8; i++)
1631 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1633 printk(KERN_CONT "\n");
1636 __apicdebuginit(void) print_local_APIC(void *dummy)
1638 unsigned int i, v, ver, maxlvt;
1641 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1642 smp_processor_id(), hard_smp_processor_id());
1643 v = apic_read(APIC_ID);
1644 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1645 v = apic_read(APIC_LVR);
1646 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1647 ver = GET_APIC_VERSION(v);
1648 maxlvt = lapic_get_maxlvt();
1650 v = apic_read(APIC_TASKPRI);
1651 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1653 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1654 if (!APIC_XAPIC(ver)) {
1655 v = apic_read(APIC_ARBPRI);
1656 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1657 v & APIC_ARBPRI_MASK);
1659 v = apic_read(APIC_PROCPRI);
1660 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1664 * Remote read supported only in the 82489DX and local APIC for
1665 * Pentium processors.
1667 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1668 v = apic_read(APIC_RRR);
1669 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1672 v = apic_read(APIC_LDR);
1673 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1674 if (!x2apic_enabled()) {
1675 v = apic_read(APIC_DFR);
1676 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1678 v = apic_read(APIC_SPIV);
1679 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1681 printk(KERN_DEBUG "... APIC ISR field:\n");
1682 print_APIC_field(APIC_ISR);
1683 printk(KERN_DEBUG "... APIC TMR field:\n");
1684 print_APIC_field(APIC_TMR);
1685 printk(KERN_DEBUG "... APIC IRR field:\n");
1686 print_APIC_field(APIC_IRR);
1688 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1689 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1690 apic_write(APIC_ESR, 0);
1692 v = apic_read(APIC_ESR);
1693 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1696 icr = apic_icr_read();
1697 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1698 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1700 v = apic_read(APIC_LVTT);
1701 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1703 if (maxlvt > 3) { /* PC is LVT#4. */
1704 v = apic_read(APIC_LVTPC);
1705 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1707 v = apic_read(APIC_LVT0);
1708 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1709 v = apic_read(APIC_LVT1);
1710 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1712 if (maxlvt > 2) { /* ERR is LVT#3. */
1713 v = apic_read(APIC_LVTERR);
1714 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1717 v = apic_read(APIC_TMICT);
1718 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1719 v = apic_read(APIC_TMCCT);
1720 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1721 v = apic_read(APIC_TDCR);
1722 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1724 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1725 v = apic_read(APIC_EFEAT);
1726 maxlvt = (v >> 16) & 0xff;
1727 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1728 v = apic_read(APIC_ECTRL);
1729 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1730 for (i = 0; i < maxlvt; i++) {
1731 v = apic_read(APIC_EILVTn(i));
1732 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1738 __apicdebuginit(void) print_local_APICs(int maxcpu)
1746 for_each_online_cpu(cpu) {
1749 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1754 __apicdebuginit(void) print_PIC(void)
1757 unsigned long flags;
1759 if (!legacy_pic->nr_legacy_irqs)
1762 printk(KERN_DEBUG "\nprinting PIC contents\n");
1764 raw_spin_lock_irqsave(&i8259A_lock, flags);
1766 v = inb(0xa1) << 8 | inb(0x21);
1767 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1769 v = inb(0xa0) << 8 | inb(0x20);
1770 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1774 v = inb(0xa0) << 8 | inb(0x20);
1778 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1780 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1782 v = inb(0x4d1) << 8 | inb(0x4d0);
1783 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1786 static int __initdata show_lapic = 1;
1787 static __init int setup_show_lapic(char *arg)
1791 if (strcmp(arg, "all") == 0) {
1792 show_lapic = CONFIG_NR_CPUS;
1794 get_option(&arg, &num);
1801 __setup("show_lapic=", setup_show_lapic);
1803 __apicdebuginit(int) print_ICs(void)
1805 if (apic_verbosity == APIC_QUIET)
1810 /* don't print out if apic is not there */
1811 if (!cpu_has_apic && !apic_from_smp_config())
1814 print_local_APICs(show_lapic);
1820 fs_initcall(print_ICs);
1823 /* Where if anywhere is the i8259 connect in external int mode */
1824 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1826 void __init enable_IO_APIC(void)
1828 int i8259_apic, i8259_pin;
1831 if (!legacy_pic->nr_legacy_irqs)
1834 for(apic = 0; apic < nr_ioapics; apic++) {
1836 /* See if any of the pins is in ExtINT mode */
1837 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1838 struct IO_APIC_route_entry entry;
1839 entry = ioapic_read_entry(apic, pin);
1841 /* If the interrupt line is enabled and in ExtInt mode
1842 * I have found the pin where the i8259 is connected.
1844 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1845 ioapic_i8259.apic = apic;
1846 ioapic_i8259.pin = pin;
1852 /* Look to see what if the MP table has reported the ExtINT */
1853 /* If we could not find the appropriate pin by looking at the ioapic
1854 * the i8259 probably is not connected the ioapic but give the
1855 * mptable a chance anyway.
1857 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1858 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1859 /* Trust the MP table if nothing is setup in the hardware */
1860 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1861 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1862 ioapic_i8259.pin = i8259_pin;
1863 ioapic_i8259.apic = i8259_apic;
1865 /* Complain if the MP table and the hardware disagree */
1866 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1867 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1869 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1873 * Do not trust the IO-APIC being empty at bootup
1879 * Not an __init, needed by the reboot code
1881 void disable_IO_APIC(void)
1884 * Clear the IO-APIC before rebooting:
1888 if (!legacy_pic->nr_legacy_irqs)
1892 * If the i8259 is routed through an IOAPIC
1893 * Put that IOAPIC in virtual wire mode
1894 * so legacy interrupts can be delivered.
1896 * With interrupt-remapping, for now we will use virtual wire A mode,
1897 * as virtual wire B is little complex (need to configure both
1898 * IOAPIC RTE aswell as interrupt-remapping table entry).
1899 * As this gets called during crash dump, keep this simple for now.
1901 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1902 struct IO_APIC_route_entry entry;
1904 memset(&entry, 0, sizeof(entry));
1905 entry.mask = 0; /* Enabled */
1906 entry.trigger = 0; /* Edge */
1908 entry.polarity = 0; /* High */
1909 entry.delivery_status = 0;
1910 entry.dest_mode = 0; /* Physical */
1911 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1913 entry.dest = read_apic_id();
1916 * Add it to the IO-APIC irq-routing table:
1918 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1922 * Use virtual wire A mode when interrupt remapping is enabled.
1924 if (cpu_has_apic || apic_from_smp_config())
1925 disconnect_bsp_APIC(!intr_remapping_enabled &&
1926 ioapic_i8259.pin != -1);
1929 #ifdef CONFIG_X86_32
1931 * function to set the IO-APIC physical IDs based on the
1932 * values stored in the MPC table.
1934 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1936 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1938 union IO_APIC_reg_00 reg_00;
1939 physid_mask_t phys_id_present_map;
1942 unsigned char old_id;
1943 unsigned long flags;
1946 * This is broken; anything with a real cpu count has to
1947 * circumvent this idiocy regardless.
1949 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1952 * Set the IOAPIC ID to the value stored in the MPC table.
1954 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1956 /* Read the register 0 value */
1957 raw_spin_lock_irqsave(&ioapic_lock, flags);
1958 reg_00.raw = io_apic_read(apic_id, 0);
1959 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1961 old_id = mp_ioapics[apic_id].apicid;
1963 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
1964 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1965 apic_id, mp_ioapics[apic_id].apicid);
1966 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1968 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
1972 * Sanity check, is the ID really free? Every APIC in a
1973 * system must have a unique ID or we get lots of nice
1974 * 'stuck on smp_invalidate_needed IPI wait' messages.
1976 if (apic->check_apicid_used(&phys_id_present_map,
1977 mp_ioapics[apic_id].apicid)) {
1978 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1979 apic_id, mp_ioapics[apic_id].apicid);
1980 for (i = 0; i < get_physical_broadcast(); i++)
1981 if (!physid_isset(i, phys_id_present_map))
1983 if (i >= get_physical_broadcast())
1984 panic("Max APIC ID exceeded!\n");
1985 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1987 physid_set(i, phys_id_present_map);
1988 mp_ioapics[apic_id].apicid = i;
1991 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
1992 apic_printk(APIC_VERBOSE, "Setting %d in the "
1993 "phys_id_present_map\n",
1994 mp_ioapics[apic_id].apicid);
1995 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1999 * We need to adjust the IRQ routing table
2000 * if the ID changed.
2002 if (old_id != mp_ioapics[apic_id].apicid)
2003 for (i = 0; i < mp_irq_entries; i++)
2004 if (mp_irqs[i].dstapic == old_id)
2006 = mp_ioapics[apic_id].apicid;
2009 * Read the right value from the MPC table and
2010 * write it into the ID register.
2012 apic_printk(APIC_VERBOSE, KERN_INFO
2013 "...changing IO-APIC physical APIC ID to %d ...",
2014 mp_ioapics[apic_id].apicid);
2016 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2017 raw_spin_lock_irqsave(&ioapic_lock, flags);
2018 io_apic_write(apic_id, 0, reg_00.raw);
2019 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2024 raw_spin_lock_irqsave(&ioapic_lock, flags);
2025 reg_00.raw = io_apic_read(apic_id, 0);
2026 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2027 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2028 printk("could not set ID!\n");
2030 apic_printk(APIC_VERBOSE, " ok.\n");
2034 void __init setup_ioapic_ids_from_mpc(void)
2040 * Don't check I/O APIC IDs for xAPIC systems. They have
2041 * no meaning without the serial APIC bus.
2043 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2044 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2046 setup_ioapic_ids_from_mpc_nocheck();
2050 int no_timer_check __initdata;
2052 static int __init notimercheck(char *s)
2057 __setup("no_timer_check", notimercheck);
2060 * There is a nasty bug in some older SMP boards, their mptable lies
2061 * about the timer IRQ. We do the following to work around the situation:
2063 * - timer IRQ defaults to IO-APIC IRQ
2064 * - if this function detects that timer IRQs are defunct, then we fall
2065 * back to ISA timer IRQs
2067 static int __init timer_irq_works(void)
2069 unsigned long t1 = jiffies;
2070 unsigned long flags;
2075 local_save_flags(flags);
2077 /* Let ten ticks pass... */
2078 mdelay((10 * 1000) / HZ);
2079 local_irq_restore(flags);
2082 * Expect a few ticks at least, to be sure some possible
2083 * glue logic does not lock up after one or two first
2084 * ticks in a non-ExtINT mode. Also the local APIC
2085 * might have cached one ExtINT interrupt. Finally, at
2086 * least one tick may be lost due to delays.
2090 if (time_after(jiffies, t1 + 4))
2096 * In the SMP+IOAPIC case it might happen that there are an unspecified
2097 * number of pending IRQ events unhandled. These cases are very rare,
2098 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2099 * better to do it this way as thus we do not have to be aware of
2100 * 'pending' interrupts in the IRQ path, except at this point.
2103 * Edge triggered needs to resend any interrupt
2104 * that was delayed but this is now handled in the device
2109 * Starting up a edge-triggered IO-APIC interrupt is
2110 * nasty - we need to make sure that we get the edge.
2111 * If it is already asserted for some reason, we need
2112 * return 1 to indicate that is was pending.
2114 * This is not complete - we should be able to fake
2115 * an edge even if it isn't on the 8259A...
2118 static unsigned int startup_ioapic_irq(struct irq_data *data)
2120 int was_pending = 0, irq = data->irq;
2121 unsigned long flags;
2123 raw_spin_lock_irqsave(&ioapic_lock, flags);
2124 if (irq < legacy_pic->nr_legacy_irqs) {
2125 legacy_pic->mask(irq);
2126 if (legacy_pic->irq_pending(irq))
2129 __unmask_ioapic(data->chip_data);
2130 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2135 static int ioapic_retrigger_irq(struct irq_data *data)
2137 struct irq_cfg *cfg = data->chip_data;
2138 unsigned long flags;
2140 raw_spin_lock_irqsave(&vector_lock, flags);
2141 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2142 raw_spin_unlock_irqrestore(&vector_lock, flags);
2148 * Level and edge triggered IO-APIC interrupts need different handling,
2149 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2150 * handled with the level-triggered descriptor, but that one has slightly
2151 * more overhead. Level-triggered interrupts cannot be handled with the
2152 * edge-triggered handler, without risking IRQ storms and other ugly
2157 void send_cleanup_vector(struct irq_cfg *cfg)
2159 cpumask_var_t cleanup_mask;
2161 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2163 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2164 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2166 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2167 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2168 free_cpumask_var(cleanup_mask);
2170 cfg->move_in_progress = 0;
2173 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2176 struct irq_pin_list *entry;
2177 u8 vector = cfg->vector;
2179 for_each_irq_pin(entry, cfg->irq_2_pin) {
2185 * With interrupt-remapping, destination information comes
2186 * from interrupt-remapping table entry.
2188 if (!irq_remapped(cfg))
2189 io_apic_write(apic, 0x11 + pin*2, dest);
2190 reg = io_apic_read(apic, 0x10 + pin*2);
2191 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2193 io_apic_modify(apic, 0x10 + pin*2, reg);
2198 * Either sets data->affinity to a valid value, and returns
2199 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2200 * leaves data->affinity untouched.
2202 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2203 unsigned int *dest_id)
2205 struct irq_cfg *cfg = data->chip_data;
2207 if (!cpumask_intersects(mask, cpu_online_mask))
2210 if (assign_irq_vector(data->irq, data->chip_data, mask))
2213 cpumask_copy(data->affinity, mask);
2215 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2220 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2223 unsigned int dest, irq = data->irq;
2224 unsigned long flags;
2227 raw_spin_lock_irqsave(&ioapic_lock, flags);
2228 ret = __ioapic_set_affinity(data, mask, &dest);
2230 /* Only the high 8 bits are valid. */
2231 dest = SET_APIC_LOGICAL_ID(dest);
2232 __target_IO_APIC_irq(irq, dest, data->chip_data);
2234 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2238 #ifdef CONFIG_INTR_REMAP
2241 * Migrate the IO-APIC irq in the presence of intr-remapping.
2243 * For both level and edge triggered, irq migration is a simple atomic
2244 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2246 * For level triggered, we eliminate the io-apic RTE modification (with the
2247 * updated vector information), by using a virtual vector (io-apic pin number).
2248 * Real vector that is used for interrupting cpu will be coming from
2249 * the interrupt-remapping table entry.
2252 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2255 struct irq_cfg *cfg = data->chip_data;
2256 unsigned int dest, irq = data->irq;
2259 if (!cpumask_intersects(mask, cpu_online_mask))
2262 if (get_irte(irq, &irte))
2265 if (assign_irq_vector(irq, cfg, mask))
2268 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2270 irte.vector = cfg->vector;
2271 irte.dest_id = IRTE_DEST(dest);
2274 * Modified the IRTE and flushes the Interrupt entry cache.
2276 modify_irte(irq, &irte);
2278 if (cfg->move_in_progress)
2279 send_cleanup_vector(cfg);
2281 cpumask_copy(data->affinity, mask);
2287 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2294 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2296 unsigned vector, me;
2302 me = smp_processor_id();
2303 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2306 struct irq_desc *desc;
2307 struct irq_cfg *cfg;
2308 irq = __get_cpu_var(vector_irq)[vector];
2313 desc = irq_to_desc(irq);
2318 raw_spin_lock(&desc->lock);
2321 * Check if the irq migration is in progress. If so, we
2322 * haven't received the cleanup request yet for this irq.
2324 if (cfg->move_in_progress)
2327 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2330 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2332 * Check if the vector that needs to be cleanedup is
2333 * registered at the cpu's IRR. If so, then this is not
2334 * the best time to clean it up. Lets clean it up in the
2335 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2338 if (irr & (1 << (vector % 32))) {
2339 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2342 __get_cpu_var(vector_irq)[vector] = -1;
2344 raw_spin_unlock(&desc->lock);
2350 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2354 if (likely(!cfg->move_in_progress))
2357 me = smp_processor_id();
2359 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2360 send_cleanup_vector(cfg);
2363 static void irq_complete_move(struct irq_cfg *cfg)
2365 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2368 void irq_force_complete_move(int irq)
2370 struct irq_cfg *cfg = get_irq_chip_data(irq);
2375 __irq_complete_move(cfg, cfg->vector);
2378 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2381 static void ack_apic_edge(struct irq_data *data)
2383 irq_complete_move(data->chip_data);
2384 move_native_irq(data->irq);
2388 atomic_t irq_mis_count;
2391 * IO-APIC versions below 0x20 don't support EOI register.
2392 * For the record, here is the information about various versions:
2394 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2395 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2398 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2399 * version as 0x2. This is an error with documentation and these ICH chips
2400 * use io-apic's of version 0x20.
2402 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2403 * Otherwise, we simulate the EOI message manually by changing the trigger
2404 * mode to edge and then back to level, with RTE being masked during this.
2406 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2408 struct irq_pin_list *entry;
2409 unsigned long flags;
2411 raw_spin_lock_irqsave(&ioapic_lock, flags);
2412 for_each_irq_pin(entry, cfg->irq_2_pin) {
2413 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2415 * Intr-remapping uses pin number as the virtual vector
2416 * in the RTE. Actual vector is programmed in
2417 * intr-remapping table entry. Hence for the io-apic
2418 * EOI we use the pin number.
2420 if (irq_remapped(cfg))
2421 io_apic_eoi(entry->apic, entry->pin);
2423 io_apic_eoi(entry->apic, cfg->vector);
2425 __mask_and_edge_IO_APIC_irq(entry);
2426 __unmask_and_level_IO_APIC_irq(entry);
2429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2432 static void ack_apic_level(struct irq_data *data)
2434 struct irq_cfg *cfg = data->chip_data;
2435 int i, do_unmask_irq = 0, irq = data->irq;
2438 irq_complete_move(cfg);
2439 #ifdef CONFIG_GENERIC_PENDING_IRQ
2440 /* If we are moving the irq we need to mask it */
2441 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2448 * It appears there is an erratum which affects at least version 0x11
2449 * of I/O APIC (that's the 82093AA and cores integrated into various
2450 * chipsets). Under certain conditions a level-triggered interrupt is
2451 * erroneously delivered as edge-triggered one but the respective IRR
2452 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2453 * message but it will never arrive and further interrupts are blocked
2454 * from the source. The exact reason is so far unknown, but the
2455 * phenomenon was observed when two consecutive interrupt requests
2456 * from a given source get delivered to the same CPU and the source is
2457 * temporarily disabled in between.
2459 * A workaround is to simulate an EOI message manually. We achieve it
2460 * by setting the trigger mode to edge and then to level when the edge
2461 * trigger mode gets detected in the TMR of a local APIC for a
2462 * level-triggered interrupt. We mask the source for the time of the
2463 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2464 * The idea is from Manfred Spraul. --macro
2466 * Also in the case when cpu goes offline, fixup_irqs() will forward
2467 * any unhandled interrupt on the offlined cpu to the new cpu
2468 * destination that is handling the corresponding interrupt. This
2469 * interrupt forwarding is done via IPI's. Hence, in this case also
2470 * level-triggered io-apic interrupt will be seen as an edge
2471 * interrupt in the IRR. And we can't rely on the cpu's EOI
2472 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2473 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2474 * supporting EOI register, we do an explicit EOI to clear the
2475 * remote IRR and on IO-APIC's which don't have an EOI register,
2476 * we use the above logic (mask+edge followed by unmask+level) from
2477 * Manfred Spraul to clear the remote IRR.
2480 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2483 * We must acknowledge the irq before we move it or the acknowledge will
2484 * not propagate properly.
2489 * Tail end of clearing remote IRR bit (either by delivering the EOI
2490 * message via io-apic EOI register write or simulating it using
2491 * mask+edge followed by unnask+level logic) manually when the
2492 * level triggered interrupt is seen as the edge triggered interrupt
2495 if (!(v & (1 << (i & 0x1f)))) {
2496 atomic_inc(&irq_mis_count);
2498 eoi_ioapic_irq(irq, cfg);
2501 /* Now we can move and renable the irq */
2502 if (unlikely(do_unmask_irq)) {
2503 /* Only migrate the irq if the ack has been received.
2505 * On rare occasions the broadcast level triggered ack gets
2506 * delayed going to ioapics, and if we reprogram the
2507 * vector while Remote IRR is still set the irq will never
2510 * To prevent this scenario we read the Remote IRR bit
2511 * of the ioapic. This has two effects.
2512 * - On any sane system the read of the ioapic will
2513 * flush writes (and acks) going to the ioapic from
2515 * - We get to see if the ACK has actually been delivered.
2517 * Based on failed experiments of reprogramming the
2518 * ioapic entry from outside of irq context starting
2519 * with masking the ioapic entry and then polling until
2520 * Remote IRR was clear before reprogramming the
2521 * ioapic I don't trust the Remote IRR bit to be
2522 * completey accurate.
2524 * However there appears to be no other way to plug
2525 * this race, so if the Remote IRR bit is not
2526 * accurate and is causing problems then it is a hardware bug
2527 * and you can go talk to the chipset vendor about it.
2529 if (!io_apic_level_ack_pending(cfg))
2530 move_masked_irq(irq);
2535 #ifdef CONFIG_INTR_REMAP
2536 static void ir_ack_apic_edge(struct irq_data *data)
2541 static void ir_ack_apic_level(struct irq_data *data)
2544 eoi_ioapic_irq(data->irq, data->chip_data);
2546 #endif /* CONFIG_INTR_REMAP */
2548 static struct irq_chip ioapic_chip __read_mostly = {
2550 .irq_startup = startup_ioapic_irq,
2551 .irq_mask = mask_ioapic_irq,
2552 .irq_unmask = unmask_ioapic_irq,
2553 .irq_ack = ack_apic_edge,
2554 .irq_eoi = ack_apic_level,
2556 .irq_set_affinity = ioapic_set_affinity,
2558 .irq_retrigger = ioapic_retrigger_irq,
2561 static struct irq_chip ir_ioapic_chip __read_mostly = {
2562 .name = "IR-IO-APIC",
2563 .irq_startup = startup_ioapic_irq,
2564 .irq_mask = mask_ioapic_irq,
2565 .irq_unmask = unmask_ioapic_irq,
2566 #ifdef CONFIG_INTR_REMAP
2567 .irq_ack = ir_ack_apic_edge,
2568 .irq_eoi = ir_ack_apic_level,
2570 .irq_set_affinity = ir_ioapic_set_affinity,
2573 .irq_retrigger = ioapic_retrigger_irq,
2576 static inline void init_IO_APIC_traps(void)
2578 struct irq_cfg *cfg;
2582 * NOTE! The local APIC isn't very good at handling
2583 * multiple interrupts at the same interrupt level.
2584 * As the interrupt level is determined by taking the
2585 * vector number and shifting that right by 4, we
2586 * want to spread these out a bit so that they don't
2587 * all fall in the same interrupt level.
2589 * Also, we've got to be careful not to trash gate
2590 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2592 for_each_active_irq(irq) {
2593 cfg = get_irq_chip_data(irq);
2594 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2596 * Hmm.. We don't have an entry for this,
2597 * so default to an old-fashioned 8259
2598 * interrupt if we can..
2600 if (irq < legacy_pic->nr_legacy_irqs)
2601 legacy_pic->make_irq(irq);
2603 /* Strange. Oh, well.. */
2604 set_irq_chip(irq, &no_irq_chip);
2610 * The local APIC irq-chip implementation:
2613 static void mask_lapic_irq(struct irq_data *data)
2617 v = apic_read(APIC_LVT0);
2618 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2621 static void unmask_lapic_irq(struct irq_data *data)
2625 v = apic_read(APIC_LVT0);
2626 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2629 static void ack_lapic_irq(struct irq_data *data)
2634 static struct irq_chip lapic_chip __read_mostly = {
2635 .name = "local-APIC",
2636 .irq_mask = mask_lapic_irq,
2637 .irq_unmask = unmask_lapic_irq,
2638 .irq_ack = ack_lapic_irq,
2641 static void lapic_register_intr(int irq)
2643 irq_clear_status_flags(irq, IRQ_LEVEL);
2644 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2649 * This looks a bit hackish but it's about the only one way of sending
2650 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2651 * not support the ExtINT mode, unfortunately. We need to send these
2652 * cycles as some i82489DX-based boards have glue logic that keeps the
2653 * 8259A interrupt line asserted until INTA. --macro
2655 static inline void __init unlock_ExtINT_logic(void)
2658 struct IO_APIC_route_entry entry0, entry1;
2659 unsigned char save_control, save_freq_select;
2661 pin = find_isa_irq_pin(8, mp_INT);
2666 apic = find_isa_irq_apic(8, mp_INT);
2672 entry0 = ioapic_read_entry(apic, pin);
2673 clear_IO_APIC_pin(apic, pin);
2675 memset(&entry1, 0, sizeof(entry1));
2677 entry1.dest_mode = 0; /* physical delivery */
2678 entry1.mask = 0; /* unmask IRQ now */
2679 entry1.dest = hard_smp_processor_id();
2680 entry1.delivery_mode = dest_ExtINT;
2681 entry1.polarity = entry0.polarity;
2685 ioapic_write_entry(apic, pin, entry1);
2687 save_control = CMOS_READ(RTC_CONTROL);
2688 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2689 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2691 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2696 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2700 CMOS_WRITE(save_control, RTC_CONTROL);
2701 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2702 clear_IO_APIC_pin(apic, pin);
2704 ioapic_write_entry(apic, pin, entry0);
2707 static int disable_timer_pin_1 __initdata;
2708 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2709 static int __init disable_timer_pin_setup(char *arg)
2711 disable_timer_pin_1 = 1;
2714 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2716 int timer_through_8259 __initdata;
2719 * This code may look a bit paranoid, but it's supposed to cooperate with
2720 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2721 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2722 * fanatically on his truly buggy board.
2724 * FIXME: really need to revamp this for all platforms.
2726 static inline void __init check_timer(void)
2728 struct irq_cfg *cfg = get_irq_chip_data(0);
2729 int node = cpu_to_node(0);
2730 int apic1, pin1, apic2, pin2;
2731 unsigned long flags;
2734 local_irq_save(flags);
2737 * get/set the timer IRQ vector:
2739 legacy_pic->mask(0);
2740 assign_irq_vector(0, cfg, apic->target_cpus());
2743 * As IRQ0 is to be enabled in the 8259A, the virtual
2744 * wire has to be disabled in the local APIC. Also
2745 * timer interrupts need to be acknowledged manually in
2746 * the 8259A for the i82489DX when using the NMI
2747 * watchdog as that APIC treats NMIs as level-triggered.
2748 * The AEOI mode will finish them in the 8259A
2751 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2752 legacy_pic->init(1);
2754 pin1 = find_isa_irq_pin(0, mp_INT);
2755 apic1 = find_isa_irq_apic(0, mp_INT);
2756 pin2 = ioapic_i8259.pin;
2757 apic2 = ioapic_i8259.apic;
2759 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2760 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2761 cfg->vector, apic1, pin1, apic2, pin2);
2764 * Some BIOS writers are clueless and report the ExtINTA
2765 * I/O APIC input from the cascaded 8259A as the timer
2766 * interrupt input. So just in case, if only one pin
2767 * was found above, try it both directly and through the
2771 if (intr_remapping_enabled)
2772 panic("BIOS bug: timer not connected to IO-APIC");
2776 } else if (pin2 == -1) {
2783 * Ok, does IRQ0 through the IOAPIC work?
2786 add_pin_to_irq_node(cfg, node, apic1, pin1);
2787 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2789 /* for edge trigger, setup_ioapic_irq already
2790 * leave it unmasked.
2791 * so only need to unmask if it is level-trigger
2792 * do we really have level trigger timer?
2795 idx = find_irq_entry(apic1, pin1, mp_INT);
2796 if (idx != -1 && irq_trigger(idx))
2799 if (timer_irq_works()) {
2800 if (disable_timer_pin_1 > 0)
2801 clear_IO_APIC_pin(0, pin1);
2804 if (intr_remapping_enabled)
2805 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2806 local_irq_disable();
2807 clear_IO_APIC_pin(apic1, pin1);
2809 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2810 "8254 timer not connected to IO-APIC\n");
2812 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2813 "(IRQ0) through the 8259A ...\n");
2814 apic_printk(APIC_QUIET, KERN_INFO
2815 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2817 * legacy devices should be connected to IO APIC #0
2819 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2820 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2821 legacy_pic->unmask(0);
2822 if (timer_irq_works()) {
2823 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2824 timer_through_8259 = 1;
2828 * Cleanup, just in case ...
2830 local_irq_disable();
2831 legacy_pic->mask(0);
2832 clear_IO_APIC_pin(apic2, pin2);
2833 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2836 apic_printk(APIC_QUIET, KERN_INFO
2837 "...trying to set up timer as Virtual Wire IRQ...\n");
2839 lapic_register_intr(0);
2840 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2841 legacy_pic->unmask(0);
2843 if (timer_irq_works()) {
2844 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2847 local_irq_disable();
2848 legacy_pic->mask(0);
2849 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2850 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2852 apic_printk(APIC_QUIET, KERN_INFO
2853 "...trying to set up timer as ExtINT IRQ...\n");
2855 legacy_pic->init(0);
2856 legacy_pic->make_irq(0);
2857 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2859 unlock_ExtINT_logic();
2861 if (timer_irq_works()) {
2862 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2865 local_irq_disable();
2866 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2867 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2868 "report. Then try booting with the 'noapic' option.\n");
2870 local_irq_restore(flags);
2874 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2875 * to devices. However there may be an I/O APIC pin available for
2876 * this interrupt regardless. The pin may be left unconnected, but
2877 * typically it will be reused as an ExtINT cascade interrupt for
2878 * the master 8259A. In the MPS case such a pin will normally be
2879 * reported as an ExtINT interrupt in the MP table. With ACPI
2880 * there is no provision for ExtINT interrupts, and in the absence
2881 * of an override it would be treated as an ordinary ISA I/O APIC
2882 * interrupt, that is edge-triggered and unmasked by default. We
2883 * used to do this, but it caused problems on some systems because
2884 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2885 * the same ExtINT cascade interrupt to drive the local APIC of the
2886 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2887 * the I/O APIC in all cases now. No actual device should request
2888 * it anyway. --macro
2890 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2892 void __init setup_IO_APIC(void)
2896 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2898 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2900 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2902 * Set up IO-APIC IRQ routing.
2904 x86_init.mpparse.setup_ioapic_ids();
2907 setup_IO_APIC_irqs();
2908 init_IO_APIC_traps();
2909 if (legacy_pic->nr_legacy_irqs)
2914 * Called after all the initialization is done. If we didnt find any
2915 * APIC bugs then we can allow the modify fast path
2918 static int __init io_apic_bug_finalize(void)
2920 if (sis_apic_bug == -1)
2925 late_initcall(io_apic_bug_finalize);
2927 struct sysfs_ioapic_data {
2928 struct sys_device dev;
2929 struct IO_APIC_route_entry entry[0];
2931 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2933 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2935 struct IO_APIC_route_entry *entry;
2936 struct sysfs_ioapic_data *data;
2939 data = container_of(dev, struct sysfs_ioapic_data, dev);
2940 entry = data->entry;
2941 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2942 *entry = ioapic_read_entry(dev->id, i);
2947 static int ioapic_resume(struct sys_device *dev)
2949 struct IO_APIC_route_entry *entry;
2950 struct sysfs_ioapic_data *data;
2951 unsigned long flags;
2952 union IO_APIC_reg_00 reg_00;
2955 data = container_of(dev, struct sysfs_ioapic_data, dev);
2956 entry = data->entry;
2958 raw_spin_lock_irqsave(&ioapic_lock, flags);
2959 reg_00.raw = io_apic_read(dev->id, 0);
2960 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
2961 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
2962 io_apic_write(dev->id, 0, reg_00.raw);
2964 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2965 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2966 ioapic_write_entry(dev->id, i, entry[i]);
2971 static struct sysdev_class ioapic_sysdev_class = {
2973 .suspend = ioapic_suspend,
2974 .resume = ioapic_resume,
2977 static int __init ioapic_init_sysfs(void)
2979 struct sys_device * dev;
2982 error = sysdev_class_register(&ioapic_sysdev_class);
2986 for (i = 0; i < nr_ioapics; i++ ) {
2987 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2988 * sizeof(struct IO_APIC_route_entry);
2989 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2990 if (!mp_ioapic_data[i]) {
2991 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2994 dev = &mp_ioapic_data[i]->dev;
2996 dev->cls = &ioapic_sysdev_class;
2997 error = sysdev_register(dev);
2999 kfree(mp_ioapic_data[i]);
3000 mp_ioapic_data[i] = NULL;
3001 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3009 device_initcall(ioapic_init_sysfs);
3012 * Dynamic irq allocate and deallocation
3014 unsigned int create_irq_nr(unsigned int from, int node)
3016 struct irq_cfg *cfg;
3017 unsigned long flags;
3018 unsigned int ret = 0;
3021 if (from < nr_irqs_gsi)
3024 irq = alloc_irq_from(from, node);
3027 cfg = alloc_irq_cfg(irq, node);
3029 free_irq_at(irq, NULL);
3033 raw_spin_lock_irqsave(&vector_lock, flags);
3034 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3036 raw_spin_unlock_irqrestore(&vector_lock, flags);
3039 set_irq_chip_data(irq, cfg);
3040 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3042 free_irq_at(irq, cfg);
3047 int create_irq(void)
3049 int node = cpu_to_node(0);
3050 unsigned int irq_want;
3053 irq_want = nr_irqs_gsi;
3054 irq = create_irq_nr(irq_want, node);
3062 void destroy_irq(unsigned int irq)
3064 struct irq_cfg *cfg = get_irq_chip_data(irq);
3065 unsigned long flags;
3067 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3069 if (irq_remapped(cfg))
3071 raw_spin_lock_irqsave(&vector_lock, flags);
3072 __clear_irq_vector(irq, cfg);
3073 raw_spin_unlock_irqrestore(&vector_lock, flags);
3074 free_irq_at(irq, cfg);
3078 * MSI message composition
3080 #ifdef CONFIG_PCI_MSI
3081 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3082 struct msi_msg *msg, u8 hpet_id)
3084 struct irq_cfg *cfg;
3092 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3096 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3098 if (irq_remapped(get_irq_chip_data(irq))) {
3103 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3104 BUG_ON(ir_index == -1);
3106 prepare_irte(&irte, cfg->vector, dest);
3108 /* Set source-id of interrupt request */
3110 set_msi_sid(&irte, pdev);
3112 set_hpet_sid(&irte, hpet_id);
3114 modify_irte(irq, &irte);
3116 msg->address_hi = MSI_ADDR_BASE_HI;
3117 msg->data = sub_handle;
3118 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3120 MSI_ADDR_IR_INDEX1(ir_index) |
3121 MSI_ADDR_IR_INDEX2(ir_index);
3123 if (x2apic_enabled())
3124 msg->address_hi = MSI_ADDR_BASE_HI |
3125 MSI_ADDR_EXT_DEST_ID(dest);
3127 msg->address_hi = MSI_ADDR_BASE_HI;
3131 ((apic->irq_dest_mode == 0) ?
3132 MSI_ADDR_DEST_MODE_PHYSICAL:
3133 MSI_ADDR_DEST_MODE_LOGICAL) |
3134 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3135 MSI_ADDR_REDIRECTION_CPU:
3136 MSI_ADDR_REDIRECTION_LOWPRI) |
3137 MSI_ADDR_DEST_ID(dest);
3140 MSI_DATA_TRIGGER_EDGE |
3141 MSI_DATA_LEVEL_ASSERT |
3142 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3143 MSI_DATA_DELIVERY_FIXED:
3144 MSI_DATA_DELIVERY_LOWPRI) |
3145 MSI_DATA_VECTOR(cfg->vector);
3152 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3154 struct irq_cfg *cfg = data->chip_data;
3158 if (__ioapic_set_affinity(data, mask, &dest))
3161 __get_cached_msi_msg(data->msi_desc, &msg);
3163 msg.data &= ~MSI_DATA_VECTOR_MASK;
3164 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3165 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3166 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3168 __write_msi_msg(data->msi_desc, &msg);
3172 #ifdef CONFIG_INTR_REMAP
3174 * Migrate the MSI irq to another cpumask. This migration is
3175 * done in the process context using interrupt-remapping hardware.
3178 ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3181 struct irq_cfg *cfg = data->chip_data;
3182 unsigned int dest, irq = data->irq;
3185 if (get_irte(irq, &irte))
3188 if (__ioapic_set_affinity(data, mask, &dest))
3191 irte.vector = cfg->vector;
3192 irte.dest_id = IRTE_DEST(dest);
3195 * atomically update the IRTE with the new destination and vector.
3197 modify_irte(irq, &irte);
3200 * After this point, all the interrupts will start arriving
3201 * at the new destination. So, time to cleanup the previous
3202 * vector allocation.
3204 if (cfg->move_in_progress)
3205 send_cleanup_vector(cfg);
3211 #endif /* CONFIG_SMP */
3214 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3215 * which implement the MSI or MSI-X Capability Structure.
3217 static struct irq_chip msi_chip = {
3219 .irq_unmask = unmask_msi_irq,
3220 .irq_mask = mask_msi_irq,
3221 .irq_ack = ack_apic_edge,
3223 .irq_set_affinity = msi_set_affinity,
3225 .irq_retrigger = ioapic_retrigger_irq,
3228 static struct irq_chip msi_ir_chip = {
3229 .name = "IR-PCI-MSI",
3230 .irq_unmask = unmask_msi_irq,
3231 .irq_mask = mask_msi_irq,
3232 #ifdef CONFIG_INTR_REMAP
3233 .irq_ack = ir_ack_apic_edge,
3235 .irq_set_affinity = ir_msi_set_affinity,
3238 .irq_retrigger = ioapic_retrigger_irq,
3242 * Map the PCI dev to the corresponding remapping hardware unit
3243 * and allocate 'nvec' consecutive interrupt-remapping table entries
3246 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3248 struct intel_iommu *iommu;
3251 iommu = map_dev_to_ir(dev);
3254 "Unable to map PCI %s to iommu\n", pci_name(dev));
3258 index = alloc_irte(iommu, irq, nvec);
3261 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3268 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3273 ret = msi_compose_msg(dev, irq, &msg, -1);
3277 set_irq_msi(irq, msidesc);
3278 write_msi_msg(irq, &msg);
3280 if (irq_remapped(get_irq_chip_data(irq))) {
3281 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3282 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3284 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3286 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3291 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3293 int node, ret, sub_handle, index = 0;
3294 unsigned int irq, irq_want;
3295 struct msi_desc *msidesc;
3296 struct intel_iommu *iommu = NULL;
3298 /* x86 doesn't support multiple MSI yet */
3299 if (type == PCI_CAP_ID_MSI && nvec > 1)
3302 node = dev_to_node(&dev->dev);
3303 irq_want = nr_irqs_gsi;
3305 list_for_each_entry(msidesc, &dev->msi_list, list) {
3306 irq = create_irq_nr(irq_want, node);
3310 if (!intr_remapping_enabled)
3315 * allocate the consecutive block of IRTE's
3318 index = msi_alloc_irte(dev, irq, nvec);
3324 iommu = map_dev_to_ir(dev);
3330 * setup the mapping between the irq and the IRTE
3331 * base index, the sub_handle pointing to the
3332 * appropriate interrupt remap table entry.
3334 set_irte_irq(irq, iommu, index, sub_handle);
3337 ret = setup_msi_irq(dev, msidesc, irq);
3349 void native_teardown_msi_irq(unsigned int irq)
3354 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3357 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3360 struct irq_cfg *cfg = data->chip_data;
3361 unsigned int dest, irq = data->irq;
3364 if (__ioapic_set_affinity(data, mask, &dest))
3367 dmar_msi_read(irq, &msg);
3369 msg.data &= ~MSI_DATA_VECTOR_MASK;
3370 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3371 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3372 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3373 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3375 dmar_msi_write(irq, &msg);
3380 #endif /* CONFIG_SMP */
3382 static struct irq_chip dmar_msi_type = {
3384 .irq_unmask = dmar_msi_unmask,
3385 .irq_mask = dmar_msi_mask,
3386 .irq_ack = ack_apic_edge,
3388 .irq_set_affinity = dmar_msi_set_affinity,
3390 .irq_retrigger = ioapic_retrigger_irq,
3393 int arch_setup_dmar_msi(unsigned int irq)
3398 ret = msi_compose_msg(NULL, irq, &msg, -1);
3401 dmar_msi_write(irq, &msg);
3402 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3408 #ifdef CONFIG_HPET_TIMER
3411 static int hpet_msi_set_affinity(struct irq_data *data,
3412 const struct cpumask *mask, bool force)
3414 struct irq_cfg *cfg = data->chip_data;
3418 if (__ioapic_set_affinity(data, mask, &dest))
3421 hpet_msi_read(data->handler_data, &msg);
3423 msg.data &= ~MSI_DATA_VECTOR_MASK;
3424 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3425 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3426 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3428 hpet_msi_write(data->handler_data, &msg);
3433 #endif /* CONFIG_SMP */
3435 static struct irq_chip ir_hpet_msi_type = {
3436 .name = "IR-HPET_MSI",
3437 .irq_unmask = hpet_msi_unmask,
3438 .irq_mask = hpet_msi_mask,
3439 #ifdef CONFIG_INTR_REMAP
3440 .irq_ack = ir_ack_apic_edge,
3442 .irq_set_affinity = ir_msi_set_affinity,
3445 .irq_retrigger = ioapic_retrigger_irq,
3448 static struct irq_chip hpet_msi_type = {
3450 .irq_unmask = hpet_msi_unmask,
3451 .irq_mask = hpet_msi_mask,
3452 .irq_ack = ack_apic_edge,
3454 .irq_set_affinity = hpet_msi_set_affinity,
3456 .irq_retrigger = ioapic_retrigger_irq,
3459 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3464 if (intr_remapping_enabled) {
3465 struct intel_iommu *iommu = map_hpet_to_ir(id);
3471 index = alloc_irte(iommu, irq, 1);
3476 ret = msi_compose_msg(NULL, irq, &msg, id);
3480 hpet_msi_write(get_irq_data(irq), &msg);
3481 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3482 if (irq_remapped(get_irq_chip_data(irq)))
3483 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3484 handle_edge_irq, "edge");
3486 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3487 handle_edge_irq, "edge");
3493 #endif /* CONFIG_PCI_MSI */
3495 * Hypertransport interrupt support
3497 #ifdef CONFIG_HT_IRQ
3501 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3503 struct ht_irq_msg msg;
3504 fetch_ht_irq_msg(irq, &msg);
3506 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3507 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3509 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3510 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3512 write_ht_irq_msg(irq, &msg);
3516 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3518 struct irq_cfg *cfg = data->chip_data;
3521 if (__ioapic_set_affinity(data, mask, &dest))
3524 target_ht_irq(data->irq, dest, cfg->vector);
3530 static struct irq_chip ht_irq_chip = {
3532 .irq_mask = mask_ht_irq,
3533 .irq_unmask = unmask_ht_irq,
3534 .irq_ack = ack_apic_edge,
3536 .irq_set_affinity = ht_set_affinity,
3538 .irq_retrigger = ioapic_retrigger_irq,
3541 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3543 struct irq_cfg *cfg;
3550 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3552 struct ht_irq_msg msg;
3555 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3556 apic->target_cpus());
3558 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3562 HT_IRQ_LOW_DEST_ID(dest) |
3563 HT_IRQ_LOW_VECTOR(cfg->vector) |
3564 ((apic->irq_dest_mode == 0) ?
3565 HT_IRQ_LOW_DM_PHYSICAL :
3566 HT_IRQ_LOW_DM_LOGICAL) |
3567 HT_IRQ_LOW_RQEOI_EDGE |
3568 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3569 HT_IRQ_LOW_MT_FIXED :
3570 HT_IRQ_LOW_MT_ARBITRATED) |
3571 HT_IRQ_LOW_IRQ_MASKED;
3573 write_ht_irq_msg(irq, &msg);
3575 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3576 handle_edge_irq, "edge");
3578 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3582 #endif /* CONFIG_HT_IRQ */
3584 int __init io_apic_get_redir_entries (int ioapic)
3586 union IO_APIC_reg_01 reg_01;
3587 unsigned long flags;
3589 raw_spin_lock_irqsave(&ioapic_lock, flags);
3590 reg_01.raw = io_apic_read(ioapic, 1);
3591 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3593 /* The register returns the maximum index redir index
3594 * supported, which is one less than the total number of redir
3597 return reg_01.bits.entries + 1;
3600 static void __init probe_nr_irqs_gsi(void)
3604 nr = gsi_top + NR_IRQS_LEGACY;
3605 if (nr > nr_irqs_gsi)
3608 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3611 int get_nr_irqs_gsi(void)
3616 #ifdef CONFIG_SPARSE_IRQ
3617 int __init arch_probe_nr_irqs(void)
3621 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3622 nr_irqs = NR_VECTORS * nr_cpu_ids;
3624 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3625 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3627 * for MSI and HT dyn irq
3629 nr += nr_irqs_gsi * 16;
3634 return NR_IRQS_LEGACY;
3638 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3639 struct io_apic_irq_attr *irq_attr)
3641 struct irq_cfg *cfg;
3644 int trigger, polarity;
3646 ioapic = irq_attr->ioapic;
3647 if (!IO_APIC_IRQ(irq)) {
3648 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3654 node = dev_to_node(dev);
3656 node = cpu_to_node(0);
3658 cfg = alloc_irq_and_cfg_at(irq, node);
3662 pin = irq_attr->ioapic_pin;
3663 trigger = irq_attr->trigger;
3664 polarity = irq_attr->polarity;
3667 * IRQs < 16 are already in the irq_2_pin[] map
3669 if (irq >= legacy_pic->nr_legacy_irqs) {
3670 if (__add_pin_to_irq_node(cfg, node, ioapic, pin)) {
3671 printk(KERN_INFO "can not add pin %d for irq %d\n",
3677 setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity);
3682 int io_apic_set_pci_routing(struct device *dev, int irq,
3683 struct io_apic_irq_attr *irq_attr)
3687 * Avoid pin reprogramming. PRTs typically include entries
3688 * with redundant pin->gsi mappings (but unique PCI devices);
3689 * we only program the IOAPIC on the first.
3691 ioapic = irq_attr->ioapic;
3692 pin = irq_attr->ioapic_pin;
3693 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3694 pr_debug("Pin %d-%d already programmed\n",
3695 mp_ioapics[ioapic].apicid, pin);
3698 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3700 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3703 u8 __init io_apic_unique_id(u8 id)
3705 #ifdef CONFIG_X86_32
3706 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3707 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3708 return io_apic_get_unique_id(nr_ioapics, id);
3713 DECLARE_BITMAP(used, 256);
3715 bitmap_zero(used, 256);
3716 for (i = 0; i < nr_ioapics; i++) {
3717 struct mpc_ioapic *ia = &mp_ioapics[i];
3718 __set_bit(ia->apicid, used);
3720 if (!test_bit(id, used))
3722 return find_first_zero_bit(used, 256);
3726 #ifdef CONFIG_X86_32
3727 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3729 union IO_APIC_reg_00 reg_00;
3730 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3732 unsigned long flags;
3736 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3737 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3738 * supports up to 16 on one shared APIC bus.
3740 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3741 * advantage of new APIC bus architecture.
3744 if (physids_empty(apic_id_map))
3745 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3747 raw_spin_lock_irqsave(&ioapic_lock, flags);
3748 reg_00.raw = io_apic_read(ioapic, 0);
3749 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3751 if (apic_id >= get_physical_broadcast()) {
3752 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3753 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3754 apic_id = reg_00.bits.ID;
3758 * Every APIC in a system must have a unique ID or we get lots of nice
3759 * 'stuck on smp_invalidate_needed IPI wait' messages.
3761 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3763 for (i = 0; i < get_physical_broadcast(); i++) {
3764 if (!apic->check_apicid_used(&apic_id_map, i))
3768 if (i == get_physical_broadcast())
3769 panic("Max apic_id exceeded!\n");
3771 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3772 "trying %d\n", ioapic, apic_id, i);
3777 apic->apicid_to_cpu_present(apic_id, &tmp);
3778 physids_or(apic_id_map, apic_id_map, tmp);
3780 if (reg_00.bits.ID != apic_id) {
3781 reg_00.bits.ID = apic_id;
3783 raw_spin_lock_irqsave(&ioapic_lock, flags);
3784 io_apic_write(ioapic, 0, reg_00.raw);
3785 reg_00.raw = io_apic_read(ioapic, 0);
3786 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3789 if (reg_00.bits.ID != apic_id) {
3790 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3795 apic_printk(APIC_VERBOSE, KERN_INFO
3796 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3802 int __init io_apic_get_version(int ioapic)
3804 union IO_APIC_reg_01 reg_01;
3805 unsigned long flags;
3807 raw_spin_lock_irqsave(&ioapic_lock, flags);
3808 reg_01.raw = io_apic_read(ioapic, 1);
3809 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3811 return reg_01.bits.version;
3814 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3816 int ioapic, pin, idx;
3818 if (skip_ioapic_setup)
3821 ioapic = mp_find_ioapic(gsi);
3825 pin = mp_find_ioapic_pin(ioapic, gsi);
3829 idx = find_irq_entry(ioapic, pin, mp_INT);
3833 *trigger = irq_trigger(idx);
3834 *polarity = irq_polarity(idx);
3839 * This function currently is only a helper for the i386 smp boot process where
3840 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3841 * so mask in all cases should simply be apic->target_cpus()
3844 void __init setup_ioapic_dest(void)
3846 int pin, ioapic, irq, irq_entry;
3847 struct irq_desc *desc;
3848 const struct cpumask *mask;
3850 if (skip_ioapic_setup == 1)
3853 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3854 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3855 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3856 if (irq_entry == -1)
3858 irq = pin_2_irq(irq_entry, ioapic, pin);
3860 if ((ioapic > 0) && (irq > 16))
3863 desc = irq_to_desc(irq);
3866 * Honour affinities which have been set in early boot
3869 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
3870 mask = desc->irq_data.affinity;
3872 mask = apic->target_cpus();
3874 if (intr_remapping_enabled)
3875 ir_ioapic_set_affinity(&desc->irq_data, mask, false);
3877 ioapic_set_affinity(&desc->irq_data, mask, false);
3883 #define IOAPIC_RESOURCE_NAME_SIZE 11
3885 static struct resource *ioapic_resources;
3887 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3890 struct resource *res;
3894 if (nr_ioapics <= 0)
3897 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3900 mem = alloc_bootmem(n);
3903 mem += sizeof(struct resource) * nr_ioapics;
3905 for (i = 0; i < nr_ioapics; i++) {
3907 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3908 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3909 mem += IOAPIC_RESOURCE_NAME_SIZE;
3912 ioapic_resources = res;
3917 void __init ioapic_and_gsi_init(void)
3919 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3920 struct resource *ioapic_res;
3923 ioapic_res = ioapic_setup_resources(nr_ioapics);
3924 for (i = 0; i < nr_ioapics; i++) {
3925 if (smp_found_config) {
3926 ioapic_phys = mp_ioapics[i].apicaddr;
3927 #ifdef CONFIG_X86_32
3930 "WARNING: bogus zero IO-APIC "
3931 "address found in MPTABLE, "
3932 "disabling IO/APIC support!\n");
3933 smp_found_config = 0;
3934 skip_ioapic_setup = 1;
3935 goto fake_ioapic_page;
3939 #ifdef CONFIG_X86_32
3942 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3943 ioapic_phys = __pa(ioapic_phys);
3945 set_fixmap_nocache(idx, ioapic_phys);
3946 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3947 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3951 ioapic_res->start = ioapic_phys;
3952 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3956 probe_nr_irqs_gsi();
3959 void __init ioapic_insert_resources(void)
3962 struct resource *r = ioapic_resources;
3967 "IO APIC resources couldn't be allocated.\n");
3971 for (i = 0; i < nr_ioapics; i++) {
3972 insert_resource(&iomem_resource, r);
3977 int mp_find_ioapic(u32 gsi)
3981 /* Find the IOAPIC that manages this GSI. */
3982 for (i = 0; i < nr_ioapics; i++) {
3983 if ((gsi >= mp_gsi_routing[i].gsi_base)
3984 && (gsi <= mp_gsi_routing[i].gsi_end))
3988 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3992 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3994 if (WARN_ON(ioapic == -1))
3996 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
3999 return gsi - mp_gsi_routing[ioapic].gsi_base;
4002 static int bad_ioapic(unsigned long address)
4004 if (nr_ioapics >= MAX_IO_APICS) {
4005 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4006 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4010 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4011 " found in table, skipping!\n");
4017 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4022 if (bad_ioapic(address))
4027 mp_ioapics[idx].type = MP_IOAPIC;
4028 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4029 mp_ioapics[idx].apicaddr = address;
4031 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4032 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4033 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4036 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4037 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4039 entries = io_apic_get_redir_entries(idx);
4040 mp_gsi_routing[idx].gsi_base = gsi_base;
4041 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
4044 * The number of IO-APIC IRQ registers (== #pins):
4046 nr_ioapic_registers[idx] = entries;
4048 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
4049 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
4051 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4052 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4053 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4054 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4059 /* Enable IOAPIC early just for system timer */
4060 void __init pre_init_apic_IRQ0(void)
4062 struct irq_cfg *cfg;
4064 printk(KERN_INFO "Early APIC setup for system timer0\n");
4066 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4067 &phys_cpu_present_map);
4069 /* Make sure the irq descriptor is set up */
4070 cfg = alloc_irq_and_cfg_at(0, 0);
4074 add_pin_to_irq_node(cfg, 0, 0, 0);
4075 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4077 setup_ioapic_irq(0, 0, 0, cfg, 0, 0);