2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
69 #define for_each_irq_pin(entry, head) \
70 for (entry = head; entry; entry = entry->next)
73 * Is the SiS APIC rmw bug present ?
74 * -1 = don't know, 0 = no, 1 = yes
76 int sis_apic_bug = -1;
78 static DEFINE_SPINLOCK(ioapic_lock);
79 static DEFINE_SPINLOCK(vector_lock);
82 * # of IRQ routing registers
84 int nr_ioapic_registers[MAX_IO_APICS];
86 /* I/O APIC entries */
87 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
90 /* IO APIC gsi routing info */
91 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
93 /* MP IRQ source entries */
94 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
96 /* # of MP IRQ source entries */
99 /* Number of legacy interrupts */
100 static int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY;
102 static int nr_irqs_gsi = NR_IRQS_LEGACY;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type[MAX_MP_BUSSES];
108 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
110 int skip_ioapic_setup;
112 void arch_disable_smp_support(void)
116 noioapicreroute = -1;
118 skip_ioapic_setup = 1;
121 static int __init parse_noapic(char *str)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic);
129 struct irq_pin_list {
131 struct irq_pin_list *next;
134 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
136 struct irq_pin_list *pin;
138 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
144 * This is performance-critical, we want to do it O(1)
146 * Most irqs are mapped 1:1 with pins.
149 struct irq_pin_list *irq_2_pin;
150 cpumask_var_t domain;
151 cpumask_var_t old_domain;
152 unsigned move_cleanup_count;
154 u8 move_in_progress : 1;
157 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
158 #ifdef CONFIG_SPARSE_IRQ
159 static struct irq_cfg irq_cfgx[] = {
161 static struct irq_cfg irq_cfgx[NR_IRQS] = {
163 [0] = { .vector = IRQ0_VECTOR, },
164 [1] = { .vector = IRQ1_VECTOR, },
165 [2] = { .vector = IRQ2_VECTOR, },
166 [3] = { .vector = IRQ3_VECTOR, },
167 [4] = { .vector = IRQ4_VECTOR, },
168 [5] = { .vector = IRQ5_VECTOR, },
169 [6] = { .vector = IRQ6_VECTOR, },
170 [7] = { .vector = IRQ7_VECTOR, },
171 [8] = { .vector = IRQ8_VECTOR, },
172 [9] = { .vector = IRQ9_VECTOR, },
173 [10] = { .vector = IRQ10_VECTOR, },
174 [11] = { .vector = IRQ11_VECTOR, },
175 [12] = { .vector = IRQ12_VECTOR, },
176 [13] = { .vector = IRQ13_VECTOR, },
177 [14] = { .vector = IRQ14_VECTOR, },
178 [15] = { .vector = IRQ15_VECTOR, },
181 void __init io_apic_disable_legacy(void)
187 int __init arch_early_irq_init(void)
190 struct irq_desc *desc;
196 count = ARRAY_SIZE(irq_cfgx);
197 node= cpu_to_node(boot_cpu_id);
199 for (i = 0; i < count; i++) {
200 desc = irq_to_desc(i);
201 desc->chip_data = &cfg[i];
202 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
203 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
204 if (i < nr_legacy_irqs)
205 cpumask_setall(cfg[i].domain);
211 #ifdef CONFIG_SPARSE_IRQ
212 static struct irq_cfg *irq_cfg(unsigned int irq)
214 struct irq_cfg *cfg = NULL;
215 struct irq_desc *desc;
217 desc = irq_to_desc(irq);
219 cfg = desc->chip_data;
224 static struct irq_cfg *get_one_free_irq_cfg(int node)
228 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
230 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
233 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
235 free_cpumask_var(cfg->domain);
239 cpumask_clear(cfg->domain);
240 cpumask_clear(cfg->old_domain);
247 int arch_init_chip_data(struct irq_desc *desc, int node)
251 cfg = desc->chip_data;
253 desc->chip_data = get_one_free_irq_cfg(node);
254 if (!desc->chip_data) {
255 printk(KERN_ERR "can not alloc irq_cfg\n");
263 /* for move_irq_desc */
265 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
267 struct irq_pin_list *old_entry, *head, *tail, *entry;
269 cfg->irq_2_pin = NULL;
270 old_entry = old_cfg->irq_2_pin;
274 entry = get_one_free_irq_2_pin(node);
278 entry->apic = old_entry->apic;
279 entry->pin = old_entry->pin;
282 old_entry = old_entry->next;
284 entry = get_one_free_irq_2_pin(node);
292 /* still use the old one */
295 entry->apic = old_entry->apic;
296 entry->pin = old_entry->pin;
299 old_entry = old_entry->next;
303 cfg->irq_2_pin = head;
306 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
308 struct irq_pin_list *entry, *next;
310 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
313 entry = old_cfg->irq_2_pin;
320 old_cfg->irq_2_pin = NULL;
323 void arch_init_copy_chip_data(struct irq_desc *old_desc,
324 struct irq_desc *desc, int node)
327 struct irq_cfg *old_cfg;
329 cfg = get_one_free_irq_cfg(node);
334 desc->chip_data = cfg;
336 old_cfg = old_desc->chip_data;
338 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
340 init_copy_irq_2_pin(old_cfg, cfg, node);
343 static void free_irq_cfg(struct irq_cfg *old_cfg)
348 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
350 struct irq_cfg *old_cfg, *cfg;
352 old_cfg = old_desc->chip_data;
353 cfg = desc->chip_data;
359 free_irq_2_pin(old_cfg, cfg);
360 free_irq_cfg(old_cfg);
361 old_desc->chip_data = NULL;
364 /* end for move_irq_desc */
367 static struct irq_cfg *irq_cfg(unsigned int irq)
369 return irq < nr_irqs ? irq_cfgx + irq : NULL;
376 unsigned int unused[3];
378 unsigned int unused2[11];
382 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
384 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
385 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
388 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
390 struct io_apic __iomem *io_apic = io_apic_base(apic);
391 writel(vector, &io_apic->eoi);
394 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
396 struct io_apic __iomem *io_apic = io_apic_base(apic);
397 writel(reg, &io_apic->index);
398 return readl(&io_apic->data);
401 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
403 struct io_apic __iomem *io_apic = io_apic_base(apic);
404 writel(reg, &io_apic->index);
405 writel(value, &io_apic->data);
409 * Re-write a value: to be used for read-modify-write
410 * cycles where the read already set up the index register.
412 * Older SiS APIC requires we rewrite the index register
414 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
416 struct io_apic __iomem *io_apic = io_apic_base(apic);
419 writel(reg, &io_apic->index);
420 writel(value, &io_apic->data);
423 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
425 struct irq_pin_list *entry;
428 spin_lock_irqsave(&ioapic_lock, flags);
429 for_each_irq_pin(entry, cfg->irq_2_pin) {
434 reg = io_apic_read(entry->apic, 0x10 + pin*2);
435 /* Is the remote IRR bit set? */
436 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
437 spin_unlock_irqrestore(&ioapic_lock, flags);
441 spin_unlock_irqrestore(&ioapic_lock, flags);
447 struct { u32 w1, w2; };
448 struct IO_APIC_route_entry entry;
451 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
453 union entry_union eu;
455 spin_lock_irqsave(&ioapic_lock, flags);
456 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
457 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
458 spin_unlock_irqrestore(&ioapic_lock, flags);
463 * When we write a new IO APIC routing entry, we need to write the high
464 * word first! If the mask bit in the low word is clear, we will enable
465 * the interrupt, and we need to make sure the entry is fully populated
466 * before that happens.
469 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
471 union entry_union eu = {{0, 0}};
474 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
475 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
478 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
481 spin_lock_irqsave(&ioapic_lock, flags);
482 __ioapic_write_entry(apic, pin, e);
483 spin_unlock_irqrestore(&ioapic_lock, flags);
487 * When we mask an IO APIC routing entry, we need to write the low
488 * word first, in order to set the mask bit before we change the
491 static void ioapic_mask_entry(int apic, int pin)
494 union entry_union eu = { .entry.mask = 1 };
496 spin_lock_irqsave(&ioapic_lock, flags);
497 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
498 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
499 spin_unlock_irqrestore(&ioapic_lock, flags);
503 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
504 * shared ISA-space IRQs, so we have to support them. We are super
505 * fast in the common case, and fast for shared ISA-space IRQs.
508 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
510 struct irq_pin_list **last, *entry;
512 /* don't allow duplicates */
513 last = &cfg->irq_2_pin;
514 for_each_irq_pin(entry, cfg->irq_2_pin) {
515 if (entry->apic == apic && entry->pin == pin)
520 entry = get_one_free_irq_2_pin(node);
522 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
533 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
535 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
536 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
540 * Reroute an IRQ to a different pin.
542 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
543 int oldapic, int oldpin,
544 int newapic, int newpin)
546 struct irq_pin_list *entry;
548 for_each_irq_pin(entry, cfg->irq_2_pin) {
549 if (entry->apic == oldapic && entry->pin == oldpin) {
550 entry->apic = newapic;
552 /* every one is different, right? */
557 /* old apic/pin didn't exist, so just add new ones */
558 add_pin_to_irq_node(cfg, node, newapic, newpin);
561 static void io_apic_modify_irq(struct irq_cfg *cfg,
562 int mask_and, int mask_or,
563 void (*final)(struct irq_pin_list *entry))
566 struct irq_pin_list *entry;
568 for_each_irq_pin(entry, cfg->irq_2_pin) {
571 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
574 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
580 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
582 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
585 static void io_apic_sync(struct irq_pin_list *entry)
588 * Synchronize the IO-APIC and the CPU by doing
589 * a dummy read from the IO-APIC
591 struct io_apic __iomem *io_apic;
592 io_apic = io_apic_base(entry->apic);
593 readl(&io_apic->data);
596 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
598 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
601 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
603 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
604 IO_APIC_REDIR_MASKED, NULL);
607 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
609 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
610 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
613 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
615 struct irq_cfg *cfg = desc->chip_data;
620 spin_lock_irqsave(&ioapic_lock, flags);
621 __mask_IO_APIC_irq(cfg);
622 spin_unlock_irqrestore(&ioapic_lock, flags);
625 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
627 struct irq_cfg *cfg = desc->chip_data;
630 spin_lock_irqsave(&ioapic_lock, flags);
631 __unmask_IO_APIC_irq(cfg);
632 spin_unlock_irqrestore(&ioapic_lock, flags);
635 static void mask_IO_APIC_irq(unsigned int irq)
637 struct irq_desc *desc = irq_to_desc(irq);
639 mask_IO_APIC_irq_desc(desc);
641 static void unmask_IO_APIC_irq(unsigned int irq)
643 struct irq_desc *desc = irq_to_desc(irq);
645 unmask_IO_APIC_irq_desc(desc);
648 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
650 struct IO_APIC_route_entry entry;
652 /* Check delivery_mode to be sure we're not clearing an SMI pin */
653 entry = ioapic_read_entry(apic, pin);
654 if (entry.delivery_mode == dest_SMI)
657 * Disable it in the IO-APIC irq-routing table:
659 ioapic_mask_entry(apic, pin);
662 static void clear_IO_APIC (void)
666 for (apic = 0; apic < nr_ioapics; apic++)
667 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
668 clear_IO_APIC_pin(apic, pin);
673 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
674 * specific CPU-side IRQs.
678 static int pirq_entries[MAX_PIRQS] = {
679 [0 ... MAX_PIRQS - 1] = -1
682 static int __init ioapic_pirq_setup(char *str)
685 int ints[MAX_PIRQS+1];
687 get_options(str, ARRAY_SIZE(ints), ints);
689 apic_printk(APIC_VERBOSE, KERN_INFO
690 "PIRQ redirection, working around broken MP-BIOS.\n");
692 if (ints[0] < MAX_PIRQS)
695 for (i = 0; i < max; i++) {
696 apic_printk(APIC_VERBOSE, KERN_DEBUG
697 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
699 * PIRQs are mapped upside down, usually.
701 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
706 __setup("pirq=", ioapic_pirq_setup);
707 #endif /* CONFIG_X86_32 */
709 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
712 struct IO_APIC_route_entry **ioapic_entries;
714 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
719 for (apic = 0; apic < nr_ioapics; apic++) {
720 ioapic_entries[apic] =
721 kzalloc(sizeof(struct IO_APIC_route_entry) *
722 nr_ioapic_registers[apic], GFP_ATOMIC);
723 if (!ioapic_entries[apic])
727 return ioapic_entries;
731 kfree(ioapic_entries[apic]);
732 kfree(ioapic_entries);
738 * Saves all the IO-APIC RTE's
740 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
747 for (apic = 0; apic < nr_ioapics; apic++) {
748 if (!ioapic_entries[apic])
751 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
752 ioapic_entries[apic][pin] =
753 ioapic_read_entry(apic, pin);
760 * Mask all IO APIC entries.
762 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
769 for (apic = 0; apic < nr_ioapics; apic++) {
770 if (!ioapic_entries[apic])
773 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
774 struct IO_APIC_route_entry entry;
776 entry = ioapic_entries[apic][pin];
779 ioapic_write_entry(apic, pin, entry);
786 * Restore IO APIC entries which was saved in ioapic_entries.
788 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
795 for (apic = 0; apic < nr_ioapics; apic++) {
796 if (!ioapic_entries[apic])
799 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
800 ioapic_write_entry(apic, pin,
801 ioapic_entries[apic][pin]);
806 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
810 for (apic = 0; apic < nr_ioapics; apic++)
811 kfree(ioapic_entries[apic]);
813 kfree(ioapic_entries);
817 * Find the IRQ entry number of a certain pin.
819 static int find_irq_entry(int apic, int pin, int type)
823 for (i = 0; i < mp_irq_entries; i++)
824 if (mp_irqs[i].irqtype == type &&
825 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
826 mp_irqs[i].dstapic == MP_APIC_ALL) &&
827 mp_irqs[i].dstirq == pin)
834 * Find the pin to which IRQ[irq] (ISA) is connected
836 static int __init find_isa_irq_pin(int irq, int type)
840 for (i = 0; i < mp_irq_entries; i++) {
841 int lbus = mp_irqs[i].srcbus;
843 if (test_bit(lbus, mp_bus_not_pci) &&
844 (mp_irqs[i].irqtype == type) &&
845 (mp_irqs[i].srcbusirq == irq))
847 return mp_irqs[i].dstirq;
852 static int __init find_isa_irq_apic(int irq, int type)
856 for (i = 0; i < mp_irq_entries; i++) {
857 int lbus = mp_irqs[i].srcbus;
859 if (test_bit(lbus, mp_bus_not_pci) &&
860 (mp_irqs[i].irqtype == type) &&
861 (mp_irqs[i].srcbusirq == irq))
864 if (i < mp_irq_entries) {
866 for(apic = 0; apic < nr_ioapics; apic++) {
867 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
875 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
877 * EISA Edge/Level control register, ELCR
879 static int EISA_ELCR(unsigned int irq)
881 if (irq < nr_legacy_irqs) {
882 unsigned int port = 0x4d0 + (irq >> 3);
883 return (inb(port) >> (irq & 7)) & 1;
885 apic_printk(APIC_VERBOSE, KERN_INFO
886 "Broken MPtable reports ISA irq %d\n", irq);
892 /* ISA interrupts are always polarity zero edge triggered,
893 * when listed as conforming in the MP table. */
895 #define default_ISA_trigger(idx) (0)
896 #define default_ISA_polarity(idx) (0)
898 /* EISA interrupts are always polarity zero and can be edge or level
899 * trigger depending on the ELCR value. If an interrupt is listed as
900 * EISA conforming in the MP table, that means its trigger type must
901 * be read in from the ELCR */
903 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
904 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
906 /* PCI interrupts are always polarity one level triggered,
907 * when listed as conforming in the MP table. */
909 #define default_PCI_trigger(idx) (1)
910 #define default_PCI_polarity(idx) (1)
912 /* MCA interrupts are always polarity zero level triggered,
913 * when listed as conforming in the MP table. */
915 #define default_MCA_trigger(idx) (1)
916 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
918 static int MPBIOS_polarity(int idx)
920 int bus = mp_irqs[idx].srcbus;
924 * Determine IRQ line polarity (high active or low active):
926 switch (mp_irqs[idx].irqflag & 3)
928 case 0: /* conforms, ie. bus-type dependent polarity */
929 if (test_bit(bus, mp_bus_not_pci))
930 polarity = default_ISA_polarity(idx);
932 polarity = default_PCI_polarity(idx);
934 case 1: /* high active */
939 case 2: /* reserved */
941 printk(KERN_WARNING "broken BIOS!!\n");
945 case 3: /* low active */
950 default: /* invalid */
952 printk(KERN_WARNING "broken BIOS!!\n");
960 static int MPBIOS_trigger(int idx)
962 int bus = mp_irqs[idx].srcbus;
966 * Determine IRQ trigger mode (edge or level sensitive):
968 switch ((mp_irqs[idx].irqflag>>2) & 3)
970 case 0: /* conforms, ie. bus-type dependent */
971 if (test_bit(bus, mp_bus_not_pci))
972 trigger = default_ISA_trigger(idx);
974 trigger = default_PCI_trigger(idx);
975 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
976 switch (mp_bus_id_to_type[bus]) {
977 case MP_BUS_ISA: /* ISA pin */
979 /* set before the switch */
982 case MP_BUS_EISA: /* EISA pin */
984 trigger = default_EISA_trigger(idx);
987 case MP_BUS_PCI: /* PCI pin */
989 /* set before the switch */
992 case MP_BUS_MCA: /* MCA pin */
994 trigger = default_MCA_trigger(idx);
999 printk(KERN_WARNING "broken BIOS!!\n");
1011 case 2: /* reserved */
1013 printk(KERN_WARNING "broken BIOS!!\n");
1022 default: /* invalid */
1024 printk(KERN_WARNING "broken BIOS!!\n");
1032 static inline int irq_polarity(int idx)
1034 return MPBIOS_polarity(idx);
1037 static inline int irq_trigger(int idx)
1039 return MPBIOS_trigger(idx);
1042 int (*ioapic_renumber_irq)(int ioapic, int irq);
1043 static int pin_2_irq(int idx, int apic, int pin)
1046 int bus = mp_irqs[idx].srcbus;
1049 * Debugging check, we are in big trouble if this message pops up!
1051 if (mp_irqs[idx].dstirq != pin)
1052 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1054 if (test_bit(bus, mp_bus_not_pci)) {
1055 irq = mp_irqs[idx].srcbusirq;
1058 * PCI IRQs are mapped in order
1062 irq += nr_ioapic_registers[i++];
1065 * For MPS mode, so far only needed by ES7000 platform
1067 if (ioapic_renumber_irq)
1068 irq = ioapic_renumber_irq(apic, irq);
1071 #ifdef CONFIG_X86_32
1073 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1075 if ((pin >= 16) && (pin <= 23)) {
1076 if (pirq_entries[pin-16] != -1) {
1077 if (!pirq_entries[pin-16]) {
1078 apic_printk(APIC_VERBOSE, KERN_DEBUG
1079 "disabling PIRQ%d\n", pin-16);
1081 irq = pirq_entries[pin-16];
1082 apic_printk(APIC_VERBOSE, KERN_DEBUG
1083 "using PIRQ%d -> IRQ %d\n",
1094 * Find a specific PCI IRQ entry.
1095 * Not an __init, possibly needed by modules
1097 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1098 struct io_apic_irq_attr *irq_attr)
1100 int apic, i, best_guess = -1;
1102 apic_printk(APIC_DEBUG,
1103 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1105 if (test_bit(bus, mp_bus_not_pci)) {
1106 apic_printk(APIC_VERBOSE,
1107 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1110 for (i = 0; i < mp_irq_entries; i++) {
1111 int lbus = mp_irqs[i].srcbus;
1113 for (apic = 0; apic < nr_ioapics; apic++)
1114 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1115 mp_irqs[i].dstapic == MP_APIC_ALL)
1118 if (!test_bit(lbus, mp_bus_not_pci) &&
1119 !mp_irqs[i].irqtype &&
1121 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1122 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1124 if (!(apic || IO_APIC_IRQ(irq)))
1127 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1128 set_io_apic_irq_attr(irq_attr, apic,
1135 * Use the first all-but-pin matching entry as a
1136 * best-guess fuzzy result for broken mptables.
1138 if (best_guess < 0) {
1139 set_io_apic_irq_attr(irq_attr, apic,
1149 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1151 void lock_vector_lock(void)
1153 /* Used to the online set of cpus does not change
1154 * during assign_irq_vector.
1156 spin_lock(&vector_lock);
1159 void unlock_vector_lock(void)
1161 spin_unlock(&vector_lock);
1165 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1168 * NOTE! The local APIC isn't very good at handling
1169 * multiple interrupts at the same interrupt level.
1170 * As the interrupt level is determined by taking the
1171 * vector number and shifting that right by 4, we
1172 * want to spread these out a bit so that they don't
1173 * all fall in the same interrupt level.
1175 * Also, we've got to be careful not to trash gate
1176 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1178 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1179 unsigned int old_vector;
1181 cpumask_var_t tmp_mask;
1183 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1186 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1189 old_vector = cfg->vector;
1191 cpumask_and(tmp_mask, mask, cpu_online_mask);
1192 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1193 if (!cpumask_empty(tmp_mask)) {
1194 free_cpumask_var(tmp_mask);
1199 /* Only try and allocate irqs on cpus that are present */
1201 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1205 apic->vector_allocation_domain(cpu, tmp_mask);
1207 vector = current_vector;
1208 offset = current_offset;
1211 if (vector >= first_system_vector) {
1212 /* If out of vectors on large boxen, must share them. */
1213 offset = (offset + 1) % 8;
1214 vector = FIRST_DEVICE_VECTOR + offset;
1216 if (unlikely(current_vector == vector))
1219 if (test_bit(vector, used_vectors))
1222 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1223 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1226 current_vector = vector;
1227 current_offset = offset;
1229 cfg->move_in_progress = 1;
1230 cpumask_copy(cfg->old_domain, cfg->domain);
1232 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1233 per_cpu(vector_irq, new_cpu)[vector] = irq;
1234 cfg->vector = vector;
1235 cpumask_copy(cfg->domain, tmp_mask);
1239 free_cpumask_var(tmp_mask);
1244 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1247 unsigned long flags;
1249 spin_lock_irqsave(&vector_lock, flags);
1250 err = __assign_irq_vector(irq, cfg, mask);
1251 spin_unlock_irqrestore(&vector_lock, flags);
1255 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1259 BUG_ON(!cfg->vector);
1261 vector = cfg->vector;
1262 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1263 per_cpu(vector_irq, cpu)[vector] = -1;
1266 cpumask_clear(cfg->domain);
1268 if (likely(!cfg->move_in_progress))
1270 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1271 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1273 if (per_cpu(vector_irq, cpu)[vector] != irq)
1275 per_cpu(vector_irq, cpu)[vector] = -1;
1279 cfg->move_in_progress = 0;
1282 void __setup_vector_irq(int cpu)
1284 /* Initialize vector_irq on a new cpu */
1285 /* This function must be called with vector_lock held */
1287 struct irq_cfg *cfg;
1288 struct irq_desc *desc;
1290 /* Mark the inuse vectors */
1291 for_each_irq_desc(irq, desc) {
1292 cfg = desc->chip_data;
1293 if (!cpumask_test_cpu(cpu, cfg->domain))
1295 vector = cfg->vector;
1296 per_cpu(vector_irq, cpu)[vector] = irq;
1298 /* Mark the free vectors */
1299 for (vector = 0; vector < NR_VECTORS; ++vector) {
1300 irq = per_cpu(vector_irq, cpu)[vector];
1305 if (!cpumask_test_cpu(cpu, cfg->domain))
1306 per_cpu(vector_irq, cpu)[vector] = -1;
1310 static struct irq_chip ioapic_chip;
1311 static struct irq_chip ir_ioapic_chip;
1313 #define IOAPIC_AUTO -1
1314 #define IOAPIC_EDGE 0
1315 #define IOAPIC_LEVEL 1
1317 #ifdef CONFIG_X86_32
1318 static inline int IO_APIC_irq_trigger(int irq)
1322 for (apic = 0; apic < nr_ioapics; apic++) {
1323 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1324 idx = find_irq_entry(apic, pin, mp_INT);
1325 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1326 return irq_trigger(idx);
1330 * nonexistent IRQs are edge default
1335 static inline int IO_APIC_irq_trigger(int irq)
1341 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1344 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1345 trigger == IOAPIC_LEVEL)
1346 desc->status |= IRQ_LEVEL;
1348 desc->status &= ~IRQ_LEVEL;
1350 if (irq_remapped(irq)) {
1351 desc->status |= IRQ_MOVE_PCNTXT;
1353 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1357 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1358 handle_edge_irq, "edge");
1362 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1363 trigger == IOAPIC_LEVEL)
1364 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1368 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1369 handle_edge_irq, "edge");
1372 int setup_ioapic_entry(int apic_id, int irq,
1373 struct IO_APIC_route_entry *entry,
1374 unsigned int destination, int trigger,
1375 int polarity, int vector, int pin)
1378 * add it to the IO-APIC irq-routing table:
1380 memset(entry,0,sizeof(*entry));
1382 if (intr_remapping_enabled) {
1383 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1385 struct IR_IO_APIC_route_entry *ir_entry =
1386 (struct IR_IO_APIC_route_entry *) entry;
1390 panic("No mapping iommu for ioapic %d\n", apic_id);
1392 index = alloc_irte(iommu, irq, 1);
1394 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1396 memset(&irte, 0, sizeof(irte));
1399 irte.dst_mode = apic->irq_dest_mode;
1401 * Trigger mode in the IRTE will always be edge, and the
1402 * actual level or edge trigger will be setup in the IO-APIC
1403 * RTE. This will help simplify level triggered irq migration.
1404 * For more details, see the comments above explainig IO-APIC
1405 * irq migration in the presence of interrupt-remapping.
1407 irte.trigger_mode = 0;
1408 irte.dlvry_mode = apic->irq_delivery_mode;
1409 irte.vector = vector;
1410 irte.dest_id = IRTE_DEST(destination);
1412 /* Set source-id of interrupt request */
1413 set_ioapic_sid(&irte, apic_id);
1415 modify_irte(irq, &irte);
1417 ir_entry->index2 = (index >> 15) & 0x1;
1419 ir_entry->format = 1;
1420 ir_entry->index = (index & 0x7fff);
1422 * IO-APIC RTE will be configured with virtual vector.
1423 * irq handler will do the explicit EOI to the io-apic.
1425 ir_entry->vector = pin;
1427 entry->delivery_mode = apic->irq_delivery_mode;
1428 entry->dest_mode = apic->irq_dest_mode;
1429 entry->dest = destination;
1430 entry->vector = vector;
1433 entry->mask = 0; /* enable IRQ */
1434 entry->trigger = trigger;
1435 entry->polarity = polarity;
1437 /* Mask level triggered irqs.
1438 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1445 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1446 int trigger, int polarity)
1448 struct irq_cfg *cfg;
1449 struct IO_APIC_route_entry entry;
1452 if (!IO_APIC_IRQ(irq))
1455 cfg = desc->chip_data;
1457 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1460 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1462 apic_printk(APIC_VERBOSE,KERN_DEBUG
1463 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1464 "IRQ %d Mode:%i Active:%i)\n",
1465 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1466 irq, trigger, polarity);
1469 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1470 dest, trigger, polarity, cfg->vector, pin)) {
1471 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1472 mp_ioapics[apic_id].apicid, pin);
1473 __clear_irq_vector(irq, cfg);
1477 ioapic_register_intr(irq, desc, trigger);
1478 if (irq < nr_legacy_irqs)
1479 disable_8259A_irq(irq);
1481 ioapic_write_entry(apic_id, pin, entry);
1485 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1486 } mp_ioapic_routing[MAX_IO_APICS];
1488 static void __init setup_IO_APIC_irqs(void)
1490 int apic_id = 0, pin, idx, irq;
1492 struct irq_desc *desc;
1493 struct irq_cfg *cfg;
1494 int node = cpu_to_node(boot_cpu_id);
1496 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1499 if (!acpi_disabled && acpi_ioapic) {
1500 apic_id = mp_find_ioapic(0);
1506 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1507 idx = find_irq_entry(apic_id, pin, mp_INT);
1511 apic_printk(APIC_VERBOSE,
1512 KERN_DEBUG " %d-%d",
1513 mp_ioapics[apic_id].apicid, pin);
1515 apic_printk(APIC_VERBOSE, " %d-%d",
1516 mp_ioapics[apic_id].apicid, pin);
1520 apic_printk(APIC_VERBOSE,
1521 " (apicid-pin) not connected\n");
1525 irq = pin_2_irq(idx, apic_id, pin);
1528 * Skip the timer IRQ if there's a quirk handler
1529 * installed and if it returns 1:
1531 if (apic->multi_timer_check &&
1532 apic->multi_timer_check(apic_id, irq))
1535 desc = irq_to_desc_alloc_node(irq, node);
1537 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1540 cfg = desc->chip_data;
1541 add_pin_to_irq_node(cfg, node, apic_id, pin);
1543 * don't mark it in pin_programmed, so later acpi could
1544 * set it correctly when irq < 16
1546 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1547 irq_trigger(idx), irq_polarity(idx));
1551 apic_printk(APIC_VERBOSE,
1552 " (apicid-pin) not connected\n");
1556 * Set up the timer pin, possibly with the 8259A-master behind.
1558 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1561 struct IO_APIC_route_entry entry;
1563 if (intr_remapping_enabled)
1566 memset(&entry, 0, sizeof(entry));
1569 * We use logical delivery to get the timer IRQ
1572 entry.dest_mode = apic->irq_dest_mode;
1573 entry.mask = 0; /* don't mask IRQ for edge */
1574 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1575 entry.delivery_mode = apic->irq_delivery_mode;
1578 entry.vector = vector;
1581 * The timer IRQ doesn't have to know that behind the
1582 * scene we may have a 8259A-master in AEOI mode ...
1584 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1587 * Add it to the IO-APIC irq-routing table:
1589 ioapic_write_entry(apic_id, pin, entry);
1593 __apicdebuginit(void) print_IO_APIC(void)
1596 union IO_APIC_reg_00 reg_00;
1597 union IO_APIC_reg_01 reg_01;
1598 union IO_APIC_reg_02 reg_02;
1599 union IO_APIC_reg_03 reg_03;
1600 unsigned long flags;
1601 struct irq_cfg *cfg;
1602 struct irq_desc *desc;
1605 if (apic_verbosity == APIC_QUIET)
1608 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1609 for (i = 0; i < nr_ioapics; i++)
1610 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1611 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1614 * We are a bit conservative about what we expect. We have to
1615 * know about every hardware change ASAP.
1617 printk(KERN_INFO "testing the IO APIC.......................\n");
1619 for (apic = 0; apic < nr_ioapics; apic++) {
1621 spin_lock_irqsave(&ioapic_lock, flags);
1622 reg_00.raw = io_apic_read(apic, 0);
1623 reg_01.raw = io_apic_read(apic, 1);
1624 if (reg_01.bits.version >= 0x10)
1625 reg_02.raw = io_apic_read(apic, 2);
1626 if (reg_01.bits.version >= 0x20)
1627 reg_03.raw = io_apic_read(apic, 3);
1628 spin_unlock_irqrestore(&ioapic_lock, flags);
1631 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1632 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1633 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1634 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1635 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1637 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1638 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1640 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1641 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1644 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1645 * but the value of reg_02 is read as the previous read register
1646 * value, so ignore it if reg_02 == reg_01.
1648 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1649 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1650 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1654 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1655 * or reg_03, but the value of reg_0[23] is read as the previous read
1656 * register value, so ignore it if reg_03 == reg_0[12].
1658 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1659 reg_03.raw != reg_01.raw) {
1660 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1661 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1664 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1666 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1667 " Stat Dmod Deli Vect: \n");
1669 for (i = 0; i <= reg_01.bits.entries; i++) {
1670 struct IO_APIC_route_entry entry;
1672 entry = ioapic_read_entry(apic, i);
1674 printk(KERN_DEBUG " %02x %03X ",
1679 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1684 entry.delivery_status,
1686 entry.delivery_mode,
1691 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1692 for_each_irq_desc(irq, desc) {
1693 struct irq_pin_list *entry;
1695 cfg = desc->chip_data;
1696 entry = cfg->irq_2_pin;
1699 printk(KERN_DEBUG "IRQ%d ", irq);
1700 for_each_irq_pin(entry, cfg->irq_2_pin)
1701 printk("-> %d:%d", entry->apic, entry->pin);
1705 printk(KERN_INFO ".................................... done.\n");
1710 __apicdebuginit(void) print_APIC_field(int base)
1714 if (apic_verbosity == APIC_QUIET)
1719 for (i = 0; i < 8; i++)
1720 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1722 printk(KERN_CONT "\n");
1725 __apicdebuginit(void) print_local_APIC(void *dummy)
1727 unsigned int i, v, ver, maxlvt;
1730 if (apic_verbosity == APIC_QUIET)
1733 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1734 smp_processor_id(), hard_smp_processor_id());
1735 v = apic_read(APIC_ID);
1736 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1737 v = apic_read(APIC_LVR);
1738 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1739 ver = GET_APIC_VERSION(v);
1740 maxlvt = lapic_get_maxlvt();
1742 v = apic_read(APIC_TASKPRI);
1743 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1745 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1746 if (!APIC_XAPIC(ver)) {
1747 v = apic_read(APIC_ARBPRI);
1748 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1749 v & APIC_ARBPRI_MASK);
1751 v = apic_read(APIC_PROCPRI);
1752 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1756 * Remote read supported only in the 82489DX and local APIC for
1757 * Pentium processors.
1759 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1760 v = apic_read(APIC_RRR);
1761 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1764 v = apic_read(APIC_LDR);
1765 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1766 if (!x2apic_enabled()) {
1767 v = apic_read(APIC_DFR);
1768 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1770 v = apic_read(APIC_SPIV);
1771 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1773 printk(KERN_DEBUG "... APIC ISR field:\n");
1774 print_APIC_field(APIC_ISR);
1775 printk(KERN_DEBUG "... APIC TMR field:\n");
1776 print_APIC_field(APIC_TMR);
1777 printk(KERN_DEBUG "... APIC IRR field:\n");
1778 print_APIC_field(APIC_IRR);
1780 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1781 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1782 apic_write(APIC_ESR, 0);
1784 v = apic_read(APIC_ESR);
1785 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1788 icr = apic_icr_read();
1789 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1790 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1792 v = apic_read(APIC_LVTT);
1793 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1795 if (maxlvt > 3) { /* PC is LVT#4. */
1796 v = apic_read(APIC_LVTPC);
1797 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1799 v = apic_read(APIC_LVT0);
1800 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1801 v = apic_read(APIC_LVT1);
1802 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1804 if (maxlvt > 2) { /* ERR is LVT#3. */
1805 v = apic_read(APIC_LVTERR);
1806 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1809 v = apic_read(APIC_TMICT);
1810 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1811 v = apic_read(APIC_TMCCT);
1812 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1813 v = apic_read(APIC_TDCR);
1814 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1816 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1817 v = apic_read(APIC_EFEAT);
1818 maxlvt = (v >> 16) & 0xff;
1819 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1820 v = apic_read(APIC_ECTRL);
1821 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1822 for (i = 0; i < maxlvt; i++) {
1823 v = apic_read(APIC_EILVTn(i));
1824 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1830 __apicdebuginit(void) print_all_local_APICs(void)
1835 for_each_online_cpu(cpu)
1836 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1840 __apicdebuginit(void) print_PIC(void)
1843 unsigned long flags;
1845 if (apic_verbosity == APIC_QUIET || !nr_legacy_irqs)
1848 printk(KERN_DEBUG "\nprinting PIC contents\n");
1850 spin_lock_irqsave(&i8259A_lock, flags);
1852 v = inb(0xa1) << 8 | inb(0x21);
1853 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1855 v = inb(0xa0) << 8 | inb(0x20);
1856 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1860 v = inb(0xa0) << 8 | inb(0x20);
1864 spin_unlock_irqrestore(&i8259A_lock, flags);
1866 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1868 v = inb(0x4d1) << 8 | inb(0x4d0);
1869 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1872 __apicdebuginit(int) print_all_ICs(void)
1876 /* don't print out if apic is not there */
1877 if (!cpu_has_apic && !apic_from_smp_config())
1880 print_all_local_APICs();
1886 fs_initcall(print_all_ICs);
1889 /* Where if anywhere is the i8259 connect in external int mode */
1890 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1892 void __init enable_IO_APIC(void)
1894 union IO_APIC_reg_01 reg_01;
1895 int i8259_apic, i8259_pin;
1897 unsigned long flags;
1900 * The number of IO-APIC IRQ registers (== #pins):
1902 for (apic = 0; apic < nr_ioapics; apic++) {
1903 spin_lock_irqsave(&ioapic_lock, flags);
1904 reg_01.raw = io_apic_read(apic, 1);
1905 spin_unlock_irqrestore(&ioapic_lock, flags);
1906 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1909 if (!nr_legacy_irqs)
1912 for(apic = 0; apic < nr_ioapics; apic++) {
1914 /* See if any of the pins is in ExtINT mode */
1915 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1916 struct IO_APIC_route_entry entry;
1917 entry = ioapic_read_entry(apic, pin);
1919 /* If the interrupt line is enabled and in ExtInt mode
1920 * I have found the pin where the i8259 is connected.
1922 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1923 ioapic_i8259.apic = apic;
1924 ioapic_i8259.pin = pin;
1930 /* Look to see what if the MP table has reported the ExtINT */
1931 /* If we could not find the appropriate pin by looking at the ioapic
1932 * the i8259 probably is not connected the ioapic but give the
1933 * mptable a chance anyway.
1935 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1936 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1937 /* Trust the MP table if nothing is setup in the hardware */
1938 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1939 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1940 ioapic_i8259.pin = i8259_pin;
1941 ioapic_i8259.apic = i8259_apic;
1943 /* Complain if the MP table and the hardware disagree */
1944 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1945 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1947 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1951 * Do not trust the IO-APIC being empty at bootup
1957 * Not an __init, needed by the reboot code
1959 void disable_IO_APIC(void)
1962 * Clear the IO-APIC before rebooting:
1966 if (!nr_legacy_irqs)
1970 * If the i8259 is routed through an IOAPIC
1971 * Put that IOAPIC in virtual wire mode
1972 * so legacy interrupts can be delivered.
1974 * With interrupt-remapping, for now we will use virtual wire A mode,
1975 * as virtual wire B is little complex (need to configure both
1976 * IOAPIC RTE aswell as interrupt-remapping table entry).
1977 * As this gets called during crash dump, keep this simple for now.
1979 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1980 struct IO_APIC_route_entry entry;
1982 memset(&entry, 0, sizeof(entry));
1983 entry.mask = 0; /* Enabled */
1984 entry.trigger = 0; /* Edge */
1986 entry.polarity = 0; /* High */
1987 entry.delivery_status = 0;
1988 entry.dest_mode = 0; /* Physical */
1989 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1991 entry.dest = read_apic_id();
1994 * Add it to the IO-APIC irq-routing table:
1996 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2000 * Use virtual wire A mode when interrupt remapping is enabled.
2002 if (cpu_has_apic || apic_from_smp_config())
2003 disconnect_bsp_APIC(!intr_remapping_enabled &&
2004 ioapic_i8259.pin != -1);
2007 #ifdef CONFIG_X86_32
2009 * function to set the IO-APIC physical IDs based on the
2010 * values stored in the MPC table.
2012 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2015 void __init setup_ioapic_ids_from_mpc(void)
2017 union IO_APIC_reg_00 reg_00;
2018 physid_mask_t phys_id_present_map;
2021 unsigned char old_id;
2022 unsigned long flags;
2027 * Don't check I/O APIC IDs for xAPIC systems. They have
2028 * no meaning without the serial APIC bus.
2030 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2031 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2034 * This is broken; anything with a real cpu count has to
2035 * circumvent this idiocy regardless.
2037 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2040 * Set the IOAPIC ID to the value stored in the MPC table.
2042 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2044 /* Read the register 0 value */
2045 spin_lock_irqsave(&ioapic_lock, flags);
2046 reg_00.raw = io_apic_read(apic_id, 0);
2047 spin_unlock_irqrestore(&ioapic_lock, flags);
2049 old_id = mp_ioapics[apic_id].apicid;
2051 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2052 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2053 apic_id, mp_ioapics[apic_id].apicid);
2054 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2056 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2060 * Sanity check, is the ID really free? Every APIC in a
2061 * system must have a unique ID or we get lots of nice
2062 * 'stuck on smp_invalidate_needed IPI wait' messages.
2064 if (apic->check_apicid_used(phys_id_present_map,
2065 mp_ioapics[apic_id].apicid)) {
2066 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2067 apic_id, mp_ioapics[apic_id].apicid);
2068 for (i = 0; i < get_physical_broadcast(); i++)
2069 if (!physid_isset(i, phys_id_present_map))
2071 if (i >= get_physical_broadcast())
2072 panic("Max APIC ID exceeded!\n");
2073 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2075 physid_set(i, phys_id_present_map);
2076 mp_ioapics[apic_id].apicid = i;
2079 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2080 apic_printk(APIC_VERBOSE, "Setting %d in the "
2081 "phys_id_present_map\n",
2082 mp_ioapics[apic_id].apicid);
2083 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2088 * We need to adjust the IRQ routing table
2089 * if the ID changed.
2091 if (old_id != mp_ioapics[apic_id].apicid)
2092 for (i = 0; i < mp_irq_entries; i++)
2093 if (mp_irqs[i].dstapic == old_id)
2095 = mp_ioapics[apic_id].apicid;
2098 * Read the right value from the MPC table and
2099 * write it into the ID register.
2101 apic_printk(APIC_VERBOSE, KERN_INFO
2102 "...changing IO-APIC physical APIC ID to %d ...",
2103 mp_ioapics[apic_id].apicid);
2105 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2106 spin_lock_irqsave(&ioapic_lock, flags);
2107 io_apic_write(apic_id, 0, reg_00.raw);
2108 spin_unlock_irqrestore(&ioapic_lock, flags);
2113 spin_lock_irqsave(&ioapic_lock, flags);
2114 reg_00.raw = io_apic_read(apic_id, 0);
2115 spin_unlock_irqrestore(&ioapic_lock, flags);
2116 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2117 printk("could not set ID!\n");
2119 apic_printk(APIC_VERBOSE, " ok.\n");
2124 int no_timer_check __initdata;
2126 static int __init notimercheck(char *s)
2131 __setup("no_timer_check", notimercheck);
2134 * There is a nasty bug in some older SMP boards, their mptable lies
2135 * about the timer IRQ. We do the following to work around the situation:
2137 * - timer IRQ defaults to IO-APIC IRQ
2138 * - if this function detects that timer IRQs are defunct, then we fall
2139 * back to ISA timer IRQs
2141 static int __init timer_irq_works(void)
2143 unsigned long t1 = jiffies;
2144 unsigned long flags;
2149 local_save_flags(flags);
2151 /* Let ten ticks pass... */
2152 mdelay((10 * 1000) / HZ);
2153 local_irq_restore(flags);
2156 * Expect a few ticks at least, to be sure some possible
2157 * glue logic does not lock up after one or two first
2158 * ticks in a non-ExtINT mode. Also the local APIC
2159 * might have cached one ExtINT interrupt. Finally, at
2160 * least one tick may be lost due to delays.
2164 if (time_after(jiffies, t1 + 4))
2170 * In the SMP+IOAPIC case it might happen that there are an unspecified
2171 * number of pending IRQ events unhandled. These cases are very rare,
2172 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2173 * better to do it this way as thus we do not have to be aware of
2174 * 'pending' interrupts in the IRQ path, except at this point.
2177 * Edge triggered needs to resend any interrupt
2178 * that was delayed but this is now handled in the device
2183 * Starting up a edge-triggered IO-APIC interrupt is
2184 * nasty - we need to make sure that we get the edge.
2185 * If it is already asserted for some reason, we need
2186 * return 1 to indicate that is was pending.
2188 * This is not complete - we should be able to fake
2189 * an edge even if it isn't on the 8259A...
2192 static unsigned int startup_ioapic_irq(unsigned int irq)
2194 int was_pending = 0;
2195 unsigned long flags;
2196 struct irq_cfg *cfg;
2198 spin_lock_irqsave(&ioapic_lock, flags);
2199 if (irq < nr_legacy_irqs) {
2200 disable_8259A_irq(irq);
2201 if (i8259A_irq_pending(irq))
2205 __unmask_IO_APIC_irq(cfg);
2206 spin_unlock_irqrestore(&ioapic_lock, flags);
2211 static int ioapic_retrigger_irq(unsigned int irq)
2214 struct irq_cfg *cfg = irq_cfg(irq);
2215 unsigned long flags;
2217 spin_lock_irqsave(&vector_lock, flags);
2218 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2219 spin_unlock_irqrestore(&vector_lock, flags);
2225 * Level and edge triggered IO-APIC interrupts need different handling,
2226 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2227 * handled with the level-triggered descriptor, but that one has slightly
2228 * more overhead. Level-triggered interrupts cannot be handled with the
2229 * edge-triggered handler, without risking IRQ storms and other ugly
2234 static void send_cleanup_vector(struct irq_cfg *cfg)
2236 cpumask_var_t cleanup_mask;
2238 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2240 cfg->move_cleanup_count = 0;
2241 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2242 cfg->move_cleanup_count++;
2243 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2244 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2246 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2247 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2248 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2249 free_cpumask_var(cleanup_mask);
2251 cfg->move_in_progress = 0;
2254 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2257 struct irq_pin_list *entry;
2258 u8 vector = cfg->vector;
2260 for_each_irq_pin(entry, cfg->irq_2_pin) {
2266 * With interrupt-remapping, destination information comes
2267 * from interrupt-remapping table entry.
2269 if (!irq_remapped(irq))
2270 io_apic_write(apic, 0x11 + pin*2, dest);
2271 reg = io_apic_read(apic, 0x10 + pin*2);
2272 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2274 io_apic_modify(apic, 0x10 + pin*2, reg);
2279 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2282 * Either sets desc->affinity to a valid value, and returns
2283 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2284 * leaves desc->affinity untouched.
2287 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2289 struct irq_cfg *cfg;
2292 if (!cpumask_intersects(mask, cpu_online_mask))
2296 cfg = desc->chip_data;
2297 if (assign_irq_vector(irq, cfg, mask))
2300 cpumask_copy(desc->affinity, mask);
2302 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2306 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2308 struct irq_cfg *cfg;
2309 unsigned long flags;
2315 cfg = desc->chip_data;
2317 spin_lock_irqsave(&ioapic_lock, flags);
2318 dest = set_desc_affinity(desc, mask);
2319 if (dest != BAD_APICID) {
2320 /* Only the high 8 bits are valid. */
2321 dest = SET_APIC_LOGICAL_ID(dest);
2322 __target_IO_APIC_irq(irq, dest, cfg);
2325 spin_unlock_irqrestore(&ioapic_lock, flags);
2331 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2333 struct irq_desc *desc;
2335 desc = irq_to_desc(irq);
2337 return set_ioapic_affinity_irq_desc(desc, mask);
2340 #ifdef CONFIG_INTR_REMAP
2343 * Migrate the IO-APIC irq in the presence of intr-remapping.
2345 * For both level and edge triggered, irq migration is a simple atomic
2346 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2348 * For level triggered, we eliminate the io-apic RTE modification (with the
2349 * updated vector information), by using a virtual vector (io-apic pin number).
2350 * Real vector that is used for interrupting cpu will be coming from
2351 * the interrupt-remapping table entry.
2354 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2356 struct irq_cfg *cfg;
2362 if (!cpumask_intersects(mask, cpu_online_mask))
2366 if (get_irte(irq, &irte))
2369 cfg = desc->chip_data;
2370 if (assign_irq_vector(irq, cfg, mask))
2373 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2375 irte.vector = cfg->vector;
2376 irte.dest_id = IRTE_DEST(dest);
2379 * Modified the IRTE and flushes the Interrupt entry cache.
2381 modify_irte(irq, &irte);
2383 if (cfg->move_in_progress)
2384 send_cleanup_vector(cfg);
2386 cpumask_copy(desc->affinity, mask);
2392 * Migrates the IRQ destination in the process context.
2394 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2395 const struct cpumask *mask)
2397 return migrate_ioapic_irq_desc(desc, mask);
2399 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2400 const struct cpumask *mask)
2402 struct irq_desc *desc = irq_to_desc(irq);
2404 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2407 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2408 const struct cpumask *mask)
2414 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2416 unsigned vector, me;
2422 me = smp_processor_id();
2423 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2426 struct irq_desc *desc;
2427 struct irq_cfg *cfg;
2428 irq = __get_cpu_var(vector_irq)[vector];
2433 desc = irq_to_desc(irq);
2438 spin_lock(&desc->lock);
2439 if (!cfg->move_cleanup_count)
2442 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2445 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2447 * Check if the vector that needs to be cleanedup is
2448 * registered at the cpu's IRR. If so, then this is not
2449 * the best time to clean it up. Lets clean it up in the
2450 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2453 if (irr & (1 << (vector % 32))) {
2454 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2457 __get_cpu_var(vector_irq)[vector] = -1;
2458 cfg->move_cleanup_count--;
2460 spin_unlock(&desc->lock);
2466 static void irq_complete_move(struct irq_desc **descp)
2468 struct irq_desc *desc = *descp;
2469 struct irq_cfg *cfg = desc->chip_data;
2470 unsigned vector, me;
2472 if (likely(!cfg->move_in_progress))
2475 vector = ~get_irq_regs()->orig_ax;
2476 me = smp_processor_id();
2478 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2479 send_cleanup_vector(cfg);
2482 static inline void irq_complete_move(struct irq_desc **descp) {}
2485 static void ack_apic_edge(unsigned int irq)
2487 struct irq_desc *desc = irq_to_desc(irq);
2489 irq_complete_move(&desc);
2490 move_native_irq(irq);
2494 atomic_t irq_mis_count;
2496 static void ack_apic_level(unsigned int irq)
2498 struct irq_desc *desc = irq_to_desc(irq);
2501 struct irq_cfg *cfg;
2502 int do_unmask_irq = 0;
2504 irq_complete_move(&desc);
2505 #ifdef CONFIG_GENERIC_PENDING_IRQ
2506 /* If we are moving the irq we need to mask it */
2507 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2509 mask_IO_APIC_irq_desc(desc);
2514 * It appears there is an erratum which affects at least version 0x11
2515 * of I/O APIC (that's the 82093AA and cores integrated into various
2516 * chipsets). Under certain conditions a level-triggered interrupt is
2517 * erroneously delivered as edge-triggered one but the respective IRR
2518 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2519 * message but it will never arrive and further interrupts are blocked
2520 * from the source. The exact reason is so far unknown, but the
2521 * phenomenon was observed when two consecutive interrupt requests
2522 * from a given source get delivered to the same CPU and the source is
2523 * temporarily disabled in between.
2525 * A workaround is to simulate an EOI message manually. We achieve it
2526 * by setting the trigger mode to edge and then to level when the edge
2527 * trigger mode gets detected in the TMR of a local APIC for a
2528 * level-triggered interrupt. We mask the source for the time of the
2529 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2530 * The idea is from Manfred Spraul. --macro
2532 cfg = desc->chip_data;
2534 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2537 * We must acknowledge the irq before we move it or the acknowledge will
2538 * not propagate properly.
2542 /* Now we can move and renable the irq */
2543 if (unlikely(do_unmask_irq)) {
2544 /* Only migrate the irq if the ack has been received.
2546 * On rare occasions the broadcast level triggered ack gets
2547 * delayed going to ioapics, and if we reprogram the
2548 * vector while Remote IRR is still set the irq will never
2551 * To prevent this scenario we read the Remote IRR bit
2552 * of the ioapic. This has two effects.
2553 * - On any sane system the read of the ioapic will
2554 * flush writes (and acks) going to the ioapic from
2556 * - We get to see if the ACK has actually been delivered.
2558 * Based on failed experiments of reprogramming the
2559 * ioapic entry from outside of irq context starting
2560 * with masking the ioapic entry and then polling until
2561 * Remote IRR was clear before reprogramming the
2562 * ioapic I don't trust the Remote IRR bit to be
2563 * completey accurate.
2565 * However there appears to be no other way to plug
2566 * this race, so if the Remote IRR bit is not
2567 * accurate and is causing problems then it is a hardware bug
2568 * and you can go talk to the chipset vendor about it.
2570 cfg = desc->chip_data;
2571 if (!io_apic_level_ack_pending(cfg))
2572 move_masked_irq(irq);
2573 unmask_IO_APIC_irq_desc(desc);
2576 /* Tail end of version 0x11 I/O APIC bug workaround */
2577 if (!(v & (1 << (i & 0x1f)))) {
2578 atomic_inc(&irq_mis_count);
2579 spin_lock(&ioapic_lock);
2580 __mask_and_edge_IO_APIC_irq(cfg);
2581 __unmask_and_level_IO_APIC_irq(cfg);
2582 spin_unlock(&ioapic_lock);
2586 #ifdef CONFIG_INTR_REMAP
2587 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2589 struct irq_pin_list *entry;
2591 for_each_irq_pin(entry, cfg->irq_2_pin)
2592 io_apic_eoi(entry->apic, entry->pin);
2596 eoi_ioapic_irq(struct irq_desc *desc)
2598 struct irq_cfg *cfg;
2599 unsigned long flags;
2603 cfg = desc->chip_data;
2605 spin_lock_irqsave(&ioapic_lock, flags);
2606 __eoi_ioapic_irq(irq, cfg);
2607 spin_unlock_irqrestore(&ioapic_lock, flags);
2610 static void ir_ack_apic_edge(unsigned int irq)
2615 static void ir_ack_apic_level(unsigned int irq)
2617 struct irq_desc *desc = irq_to_desc(irq);
2620 eoi_ioapic_irq(desc);
2622 #endif /* CONFIG_INTR_REMAP */
2624 static struct irq_chip ioapic_chip __read_mostly = {
2626 .startup = startup_ioapic_irq,
2627 .mask = mask_IO_APIC_irq,
2628 .unmask = unmask_IO_APIC_irq,
2629 .ack = ack_apic_edge,
2630 .eoi = ack_apic_level,
2632 .set_affinity = set_ioapic_affinity_irq,
2634 .retrigger = ioapic_retrigger_irq,
2637 static struct irq_chip ir_ioapic_chip __read_mostly = {
2638 .name = "IR-IO-APIC",
2639 .startup = startup_ioapic_irq,
2640 .mask = mask_IO_APIC_irq,
2641 .unmask = unmask_IO_APIC_irq,
2642 #ifdef CONFIG_INTR_REMAP
2643 .ack = ir_ack_apic_edge,
2644 .eoi = ir_ack_apic_level,
2646 .set_affinity = set_ir_ioapic_affinity_irq,
2649 .retrigger = ioapic_retrigger_irq,
2652 static inline void init_IO_APIC_traps(void)
2655 struct irq_desc *desc;
2656 struct irq_cfg *cfg;
2659 * NOTE! The local APIC isn't very good at handling
2660 * multiple interrupts at the same interrupt level.
2661 * As the interrupt level is determined by taking the
2662 * vector number and shifting that right by 4, we
2663 * want to spread these out a bit so that they don't
2664 * all fall in the same interrupt level.
2666 * Also, we've got to be careful not to trash gate
2667 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2669 for_each_irq_desc(irq, desc) {
2670 cfg = desc->chip_data;
2671 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2673 * Hmm.. We don't have an entry for this,
2674 * so default to an old-fashioned 8259
2675 * interrupt if we can..
2677 if (irq < nr_legacy_irqs)
2678 make_8259A_irq(irq);
2680 /* Strange. Oh, well.. */
2681 desc->chip = &no_irq_chip;
2687 * The local APIC irq-chip implementation:
2690 static void mask_lapic_irq(unsigned int irq)
2694 v = apic_read(APIC_LVT0);
2695 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2698 static void unmask_lapic_irq(unsigned int irq)
2702 v = apic_read(APIC_LVT0);
2703 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2706 static void ack_lapic_irq(unsigned int irq)
2711 static struct irq_chip lapic_chip __read_mostly = {
2712 .name = "local-APIC",
2713 .mask = mask_lapic_irq,
2714 .unmask = unmask_lapic_irq,
2715 .ack = ack_lapic_irq,
2718 static void lapic_register_intr(int irq, struct irq_desc *desc)
2720 desc->status &= ~IRQ_LEVEL;
2721 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2725 static void __init setup_nmi(void)
2728 * Dirty trick to enable the NMI watchdog ...
2729 * We put the 8259A master into AEOI mode and
2730 * unmask on all local APICs LVT0 as NMI.
2732 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2733 * is from Maciej W. Rozycki - so we do not have to EOI from
2734 * the NMI handler or the timer interrupt.
2736 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2738 enable_NMI_through_LVT0();
2740 apic_printk(APIC_VERBOSE, " done.\n");
2744 * This looks a bit hackish but it's about the only one way of sending
2745 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2746 * not support the ExtINT mode, unfortunately. We need to send these
2747 * cycles as some i82489DX-based boards have glue logic that keeps the
2748 * 8259A interrupt line asserted until INTA. --macro
2750 static inline void __init unlock_ExtINT_logic(void)
2753 struct IO_APIC_route_entry entry0, entry1;
2754 unsigned char save_control, save_freq_select;
2756 pin = find_isa_irq_pin(8, mp_INT);
2761 apic = find_isa_irq_apic(8, mp_INT);
2767 entry0 = ioapic_read_entry(apic, pin);
2768 clear_IO_APIC_pin(apic, pin);
2770 memset(&entry1, 0, sizeof(entry1));
2772 entry1.dest_mode = 0; /* physical delivery */
2773 entry1.mask = 0; /* unmask IRQ now */
2774 entry1.dest = hard_smp_processor_id();
2775 entry1.delivery_mode = dest_ExtINT;
2776 entry1.polarity = entry0.polarity;
2780 ioapic_write_entry(apic, pin, entry1);
2782 save_control = CMOS_READ(RTC_CONTROL);
2783 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2784 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2786 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2791 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2795 CMOS_WRITE(save_control, RTC_CONTROL);
2796 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2797 clear_IO_APIC_pin(apic, pin);
2799 ioapic_write_entry(apic, pin, entry0);
2802 static int disable_timer_pin_1 __initdata;
2803 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2804 static int __init disable_timer_pin_setup(char *arg)
2806 disable_timer_pin_1 = 1;
2809 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2811 int timer_through_8259 __initdata;
2814 * This code may look a bit paranoid, but it's supposed to cooperate with
2815 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2816 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2817 * fanatically on his truly buggy board.
2819 * FIXME: really need to revamp this for all platforms.
2821 static inline void __init check_timer(void)
2823 struct irq_desc *desc = irq_to_desc(0);
2824 struct irq_cfg *cfg = desc->chip_data;
2825 int node = cpu_to_node(boot_cpu_id);
2826 int apic1, pin1, apic2, pin2;
2827 unsigned long flags;
2830 local_irq_save(flags);
2833 * get/set the timer IRQ vector:
2835 disable_8259A_irq(0);
2836 assign_irq_vector(0, cfg, apic->target_cpus());
2839 * As IRQ0 is to be enabled in the 8259A, the virtual
2840 * wire has to be disabled in the local APIC. Also
2841 * timer interrupts need to be acknowledged manually in
2842 * the 8259A for the i82489DX when using the NMI
2843 * watchdog as that APIC treats NMIs as level-triggered.
2844 * The AEOI mode will finish them in the 8259A
2847 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2849 #ifdef CONFIG_X86_32
2853 ver = apic_read(APIC_LVR);
2854 ver = GET_APIC_VERSION(ver);
2855 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2859 pin1 = find_isa_irq_pin(0, mp_INT);
2860 apic1 = find_isa_irq_apic(0, mp_INT);
2861 pin2 = ioapic_i8259.pin;
2862 apic2 = ioapic_i8259.apic;
2864 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2865 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2866 cfg->vector, apic1, pin1, apic2, pin2);
2869 * Some BIOS writers are clueless and report the ExtINTA
2870 * I/O APIC input from the cascaded 8259A as the timer
2871 * interrupt input. So just in case, if only one pin
2872 * was found above, try it both directly and through the
2876 if (intr_remapping_enabled)
2877 panic("BIOS bug: timer not connected to IO-APIC");
2881 } else if (pin2 == -1) {
2888 * Ok, does IRQ0 through the IOAPIC work?
2891 add_pin_to_irq_node(cfg, node, apic1, pin1);
2892 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2894 /* for edge trigger, setup_IO_APIC_irq already
2895 * leave it unmasked.
2896 * so only need to unmask if it is level-trigger
2897 * do we really have level trigger timer?
2900 idx = find_irq_entry(apic1, pin1, mp_INT);
2901 if (idx != -1 && irq_trigger(idx))
2902 unmask_IO_APIC_irq_desc(desc);
2904 if (timer_irq_works()) {
2905 if (nmi_watchdog == NMI_IO_APIC) {
2907 enable_8259A_irq(0);
2909 if (disable_timer_pin_1 > 0)
2910 clear_IO_APIC_pin(0, pin1);
2913 if (intr_remapping_enabled)
2914 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2915 local_irq_disable();
2916 clear_IO_APIC_pin(apic1, pin1);
2918 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2919 "8254 timer not connected to IO-APIC\n");
2921 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2922 "(IRQ0) through the 8259A ...\n");
2923 apic_printk(APIC_QUIET, KERN_INFO
2924 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2926 * legacy devices should be connected to IO APIC #0
2928 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2929 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2930 enable_8259A_irq(0);
2931 if (timer_irq_works()) {
2932 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2933 timer_through_8259 = 1;
2934 if (nmi_watchdog == NMI_IO_APIC) {
2935 disable_8259A_irq(0);
2937 enable_8259A_irq(0);
2942 * Cleanup, just in case ...
2944 local_irq_disable();
2945 disable_8259A_irq(0);
2946 clear_IO_APIC_pin(apic2, pin2);
2947 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2950 if (nmi_watchdog == NMI_IO_APIC) {
2951 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2952 "through the IO-APIC - disabling NMI Watchdog!\n");
2953 nmi_watchdog = NMI_NONE;
2955 #ifdef CONFIG_X86_32
2959 apic_printk(APIC_QUIET, KERN_INFO
2960 "...trying to set up timer as Virtual Wire IRQ...\n");
2962 lapic_register_intr(0, desc);
2963 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2964 enable_8259A_irq(0);
2966 if (timer_irq_works()) {
2967 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2970 local_irq_disable();
2971 disable_8259A_irq(0);
2972 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2973 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2975 apic_printk(APIC_QUIET, KERN_INFO
2976 "...trying to set up timer as ExtINT IRQ...\n");
2980 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2982 unlock_ExtINT_logic();
2984 if (timer_irq_works()) {
2985 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2988 local_irq_disable();
2989 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2990 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2991 "report. Then try booting with the 'noapic' option.\n");
2993 local_irq_restore(flags);
2997 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2998 * to devices. However there may be an I/O APIC pin available for
2999 * this interrupt regardless. The pin may be left unconnected, but
3000 * typically it will be reused as an ExtINT cascade interrupt for
3001 * the master 8259A. In the MPS case such a pin will normally be
3002 * reported as an ExtINT interrupt in the MP table. With ACPI
3003 * there is no provision for ExtINT interrupts, and in the absence
3004 * of an override it would be treated as an ordinary ISA I/O APIC
3005 * interrupt, that is edge-triggered and unmasked by default. We
3006 * used to do this, but it caused problems on some systems because
3007 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3008 * the same ExtINT cascade interrupt to drive the local APIC of the
3009 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3010 * the I/O APIC in all cases now. No actual device should request
3011 * it anyway. --macro
3013 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3015 void __init setup_IO_APIC(void)
3019 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3021 io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3023 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3025 * Set up IO-APIC IRQ routing.
3027 x86_init.mpparse.setup_ioapic_ids();
3030 setup_IO_APIC_irqs();
3031 init_IO_APIC_traps();
3037 * Called after all the initialization is done. If we didnt find any
3038 * APIC bugs then we can allow the modify fast path
3041 static int __init io_apic_bug_finalize(void)
3043 if (sis_apic_bug == -1)
3048 late_initcall(io_apic_bug_finalize);
3050 struct sysfs_ioapic_data {
3051 struct sys_device dev;
3052 struct IO_APIC_route_entry entry[0];
3054 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3056 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3058 struct IO_APIC_route_entry *entry;
3059 struct sysfs_ioapic_data *data;
3062 data = container_of(dev, struct sysfs_ioapic_data, dev);
3063 entry = data->entry;
3064 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3065 *entry = ioapic_read_entry(dev->id, i);
3070 static int ioapic_resume(struct sys_device *dev)
3072 struct IO_APIC_route_entry *entry;
3073 struct sysfs_ioapic_data *data;
3074 unsigned long flags;
3075 union IO_APIC_reg_00 reg_00;
3078 data = container_of(dev, struct sysfs_ioapic_data, dev);
3079 entry = data->entry;
3081 spin_lock_irqsave(&ioapic_lock, flags);
3082 reg_00.raw = io_apic_read(dev->id, 0);
3083 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3084 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3085 io_apic_write(dev->id, 0, reg_00.raw);
3087 spin_unlock_irqrestore(&ioapic_lock, flags);
3088 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3089 ioapic_write_entry(dev->id, i, entry[i]);
3094 static struct sysdev_class ioapic_sysdev_class = {
3096 .suspend = ioapic_suspend,
3097 .resume = ioapic_resume,
3100 static int __init ioapic_init_sysfs(void)
3102 struct sys_device * dev;
3105 error = sysdev_class_register(&ioapic_sysdev_class);
3109 for (i = 0; i < nr_ioapics; i++ ) {
3110 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3111 * sizeof(struct IO_APIC_route_entry);
3112 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3113 if (!mp_ioapic_data[i]) {
3114 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3117 dev = &mp_ioapic_data[i]->dev;
3119 dev->cls = &ioapic_sysdev_class;
3120 error = sysdev_register(dev);
3122 kfree(mp_ioapic_data[i]);
3123 mp_ioapic_data[i] = NULL;
3124 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3132 device_initcall(ioapic_init_sysfs);
3135 * Dynamic irq allocate and deallocation
3137 unsigned int create_irq_nr(unsigned int irq_want, int node)
3139 /* Allocate an unused irq */
3142 unsigned long flags;
3143 struct irq_cfg *cfg_new = NULL;
3144 struct irq_desc *desc_new = NULL;
3147 if (irq_want < nr_irqs_gsi)
3148 irq_want = nr_irqs_gsi;
3150 spin_lock_irqsave(&vector_lock, flags);
3151 for (new = irq_want; new < nr_irqs; new++) {
3152 desc_new = irq_to_desc_alloc_node(new, node);
3154 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3157 cfg_new = desc_new->chip_data;
3159 if (cfg_new->vector != 0)
3162 desc_new = move_irq_desc(desc_new, node);
3164 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3168 spin_unlock_irqrestore(&vector_lock, flags);
3171 dynamic_irq_init(irq);
3172 /* restore it, in case dynamic_irq_init clear it */
3174 desc_new->chip_data = cfg_new;
3179 int create_irq(void)
3181 int node = cpu_to_node(boot_cpu_id);
3182 unsigned int irq_want;
3185 irq_want = nr_irqs_gsi;
3186 irq = create_irq_nr(irq_want, node);
3194 void destroy_irq(unsigned int irq)
3196 unsigned long flags;
3197 struct irq_cfg *cfg;
3198 struct irq_desc *desc;
3200 /* store it, in case dynamic_irq_cleanup clear it */
3201 desc = irq_to_desc(irq);
3202 cfg = desc->chip_data;
3203 dynamic_irq_cleanup(irq);
3204 /* connect back irq_cfg */
3205 desc->chip_data = cfg;
3208 spin_lock_irqsave(&vector_lock, flags);
3209 __clear_irq_vector(irq, cfg);
3210 spin_unlock_irqrestore(&vector_lock, flags);
3214 * MSI message composition
3216 #ifdef CONFIG_PCI_MSI
3217 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3219 struct irq_cfg *cfg;
3227 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3231 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3233 if (irq_remapped(irq)) {
3238 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3239 BUG_ON(ir_index == -1);
3241 memset (&irte, 0, sizeof(irte));
3244 irte.dst_mode = apic->irq_dest_mode;
3245 irte.trigger_mode = 0; /* edge */
3246 irte.dlvry_mode = apic->irq_delivery_mode;
3247 irte.vector = cfg->vector;
3248 irte.dest_id = IRTE_DEST(dest);
3250 /* Set source-id of interrupt request */
3251 set_msi_sid(&irte, pdev);
3253 modify_irte(irq, &irte);
3255 msg->address_hi = MSI_ADDR_BASE_HI;
3256 msg->data = sub_handle;
3257 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3259 MSI_ADDR_IR_INDEX1(ir_index) |
3260 MSI_ADDR_IR_INDEX2(ir_index);
3262 if (x2apic_enabled())
3263 msg->address_hi = MSI_ADDR_BASE_HI |
3264 MSI_ADDR_EXT_DEST_ID(dest);
3266 msg->address_hi = MSI_ADDR_BASE_HI;
3270 ((apic->irq_dest_mode == 0) ?
3271 MSI_ADDR_DEST_MODE_PHYSICAL:
3272 MSI_ADDR_DEST_MODE_LOGICAL) |
3273 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3274 MSI_ADDR_REDIRECTION_CPU:
3275 MSI_ADDR_REDIRECTION_LOWPRI) |
3276 MSI_ADDR_DEST_ID(dest);
3279 MSI_DATA_TRIGGER_EDGE |
3280 MSI_DATA_LEVEL_ASSERT |
3281 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3282 MSI_DATA_DELIVERY_FIXED:
3283 MSI_DATA_DELIVERY_LOWPRI) |
3284 MSI_DATA_VECTOR(cfg->vector);
3290 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3292 struct irq_desc *desc = irq_to_desc(irq);
3293 struct irq_cfg *cfg;
3297 dest = set_desc_affinity(desc, mask);
3298 if (dest == BAD_APICID)
3301 cfg = desc->chip_data;
3303 read_msi_msg_desc(desc, &msg);
3305 msg.data &= ~MSI_DATA_VECTOR_MASK;
3306 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3307 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3308 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3310 write_msi_msg_desc(desc, &msg);
3314 #ifdef CONFIG_INTR_REMAP
3316 * Migrate the MSI irq to another cpumask. This migration is
3317 * done in the process context using interrupt-remapping hardware.
3320 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3322 struct irq_desc *desc = irq_to_desc(irq);
3323 struct irq_cfg *cfg = desc->chip_data;
3327 if (get_irte(irq, &irte))
3330 dest = set_desc_affinity(desc, mask);
3331 if (dest == BAD_APICID)
3334 irte.vector = cfg->vector;
3335 irte.dest_id = IRTE_DEST(dest);
3338 * atomically update the IRTE with the new destination and vector.
3340 modify_irte(irq, &irte);
3343 * After this point, all the interrupts will start arriving
3344 * at the new destination. So, time to cleanup the previous
3345 * vector allocation.
3347 if (cfg->move_in_progress)
3348 send_cleanup_vector(cfg);
3354 #endif /* CONFIG_SMP */
3357 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3358 * which implement the MSI or MSI-X Capability Structure.
3360 static struct irq_chip msi_chip = {
3362 .unmask = unmask_msi_irq,
3363 .mask = mask_msi_irq,
3364 .ack = ack_apic_edge,
3366 .set_affinity = set_msi_irq_affinity,
3368 .retrigger = ioapic_retrigger_irq,
3371 static struct irq_chip msi_ir_chip = {
3372 .name = "IR-PCI-MSI",
3373 .unmask = unmask_msi_irq,
3374 .mask = mask_msi_irq,
3375 #ifdef CONFIG_INTR_REMAP
3376 .ack = ir_ack_apic_edge,
3378 .set_affinity = ir_set_msi_irq_affinity,
3381 .retrigger = ioapic_retrigger_irq,
3385 * Map the PCI dev to the corresponding remapping hardware unit
3386 * and allocate 'nvec' consecutive interrupt-remapping table entries
3389 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3391 struct intel_iommu *iommu;
3394 iommu = map_dev_to_ir(dev);
3397 "Unable to map PCI %s to iommu\n", pci_name(dev));
3401 index = alloc_irte(iommu, irq, nvec);
3404 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3411 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3416 ret = msi_compose_msg(dev, irq, &msg);
3420 set_irq_msi(irq, msidesc);
3421 write_msi_msg(irq, &msg);
3423 if (irq_remapped(irq)) {
3424 struct irq_desc *desc = irq_to_desc(irq);
3426 * irq migration in process context
3428 desc->status |= IRQ_MOVE_PCNTXT;
3429 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3431 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3433 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3438 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3441 int ret, sub_handle;
3442 struct msi_desc *msidesc;
3443 unsigned int irq_want;
3444 struct intel_iommu *iommu = NULL;
3448 /* x86 doesn't support multiple MSI yet */
3449 if (type == PCI_CAP_ID_MSI && nvec > 1)
3452 node = dev_to_node(&dev->dev);
3453 irq_want = nr_irqs_gsi;
3455 list_for_each_entry(msidesc, &dev->msi_list, list) {
3456 irq = create_irq_nr(irq_want, node);
3460 if (!intr_remapping_enabled)
3465 * allocate the consecutive block of IRTE's
3468 index = msi_alloc_irte(dev, irq, nvec);
3474 iommu = map_dev_to_ir(dev);
3480 * setup the mapping between the irq and the IRTE
3481 * base index, the sub_handle pointing to the
3482 * appropriate interrupt remap table entry.
3484 set_irte_irq(irq, iommu, index, sub_handle);
3487 ret = setup_msi_irq(dev, msidesc, irq);
3499 void arch_teardown_msi_irq(unsigned int irq)
3504 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3506 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3508 struct irq_desc *desc = irq_to_desc(irq);
3509 struct irq_cfg *cfg;
3513 dest = set_desc_affinity(desc, mask);
3514 if (dest == BAD_APICID)
3517 cfg = desc->chip_data;
3519 dmar_msi_read(irq, &msg);
3521 msg.data &= ~MSI_DATA_VECTOR_MASK;
3522 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3523 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3524 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3526 dmar_msi_write(irq, &msg);
3531 #endif /* CONFIG_SMP */
3533 static struct irq_chip dmar_msi_type = {
3535 .unmask = dmar_msi_unmask,
3536 .mask = dmar_msi_mask,
3537 .ack = ack_apic_edge,
3539 .set_affinity = dmar_msi_set_affinity,
3541 .retrigger = ioapic_retrigger_irq,
3544 int arch_setup_dmar_msi(unsigned int irq)
3549 ret = msi_compose_msg(NULL, irq, &msg);
3552 dmar_msi_write(irq, &msg);
3553 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3559 #ifdef CONFIG_HPET_TIMER
3562 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3564 struct irq_desc *desc = irq_to_desc(irq);
3565 struct irq_cfg *cfg;
3569 dest = set_desc_affinity(desc, mask);
3570 if (dest == BAD_APICID)
3573 cfg = desc->chip_data;
3575 hpet_msi_read(irq, &msg);
3577 msg.data &= ~MSI_DATA_VECTOR_MASK;
3578 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3579 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3580 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3582 hpet_msi_write(irq, &msg);
3587 #endif /* CONFIG_SMP */
3589 static struct irq_chip hpet_msi_type = {
3591 .unmask = hpet_msi_unmask,
3592 .mask = hpet_msi_mask,
3593 .ack = ack_apic_edge,
3595 .set_affinity = hpet_msi_set_affinity,
3597 .retrigger = ioapic_retrigger_irq,
3600 int arch_setup_hpet_msi(unsigned int irq)
3604 struct irq_desc *desc = irq_to_desc(irq);
3606 ret = msi_compose_msg(NULL, irq, &msg);
3610 hpet_msi_write(irq, &msg);
3611 desc->status |= IRQ_MOVE_PCNTXT;
3612 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3619 #endif /* CONFIG_PCI_MSI */
3621 * Hypertransport interrupt support
3623 #ifdef CONFIG_HT_IRQ
3627 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3629 struct ht_irq_msg msg;
3630 fetch_ht_irq_msg(irq, &msg);
3632 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3633 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3635 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3636 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3638 write_ht_irq_msg(irq, &msg);
3641 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3643 struct irq_desc *desc = irq_to_desc(irq);
3644 struct irq_cfg *cfg;
3647 dest = set_desc_affinity(desc, mask);
3648 if (dest == BAD_APICID)
3651 cfg = desc->chip_data;
3653 target_ht_irq(irq, dest, cfg->vector);
3660 static struct irq_chip ht_irq_chip = {
3662 .mask = mask_ht_irq,
3663 .unmask = unmask_ht_irq,
3664 .ack = ack_apic_edge,
3666 .set_affinity = set_ht_irq_affinity,
3668 .retrigger = ioapic_retrigger_irq,
3671 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3673 struct irq_cfg *cfg;
3680 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3682 struct ht_irq_msg msg;
3685 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3686 apic->target_cpus());
3688 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3692 HT_IRQ_LOW_DEST_ID(dest) |
3693 HT_IRQ_LOW_VECTOR(cfg->vector) |
3694 ((apic->irq_dest_mode == 0) ?
3695 HT_IRQ_LOW_DM_PHYSICAL :
3696 HT_IRQ_LOW_DM_LOGICAL) |
3697 HT_IRQ_LOW_RQEOI_EDGE |
3698 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3699 HT_IRQ_LOW_MT_FIXED :
3700 HT_IRQ_LOW_MT_ARBITRATED) |
3701 HT_IRQ_LOW_IRQ_MASKED;
3703 write_ht_irq_msg(irq, &msg);
3705 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3706 handle_edge_irq, "edge");
3708 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3712 #endif /* CONFIG_HT_IRQ */
3714 #ifdef CONFIG_X86_UV
3716 * Re-target the irq to the specified CPU and enable the specified MMR located
3717 * on the specified blade to allow the sending of MSIs to the specified CPU.
3719 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3720 unsigned long mmr_offset)
3722 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3723 struct irq_cfg *cfg;
3725 unsigned long mmr_value;
3726 struct uv_IO_APIC_route_entry *entry;
3727 unsigned long flags;
3730 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3734 err = assign_irq_vector(irq, cfg, eligible_cpu);
3738 spin_lock_irqsave(&vector_lock, flags);
3739 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3741 spin_unlock_irqrestore(&vector_lock, flags);
3744 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3745 entry->vector = cfg->vector;
3746 entry->delivery_mode = apic->irq_delivery_mode;
3747 entry->dest_mode = apic->irq_dest_mode;
3748 entry->polarity = 0;
3751 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3753 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3754 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3756 if (cfg->move_in_progress)
3757 send_cleanup_vector(cfg);
3763 * Disable the specified MMR located on the specified blade so that MSIs are
3764 * longer allowed to be sent.
3766 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3768 unsigned long mmr_value;
3769 struct uv_IO_APIC_route_entry *entry;
3772 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3775 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3778 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3779 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3781 #endif /* CONFIG_X86_64 */
3783 int __init io_apic_get_redir_entries (int ioapic)
3785 union IO_APIC_reg_01 reg_01;
3786 unsigned long flags;
3788 spin_lock_irqsave(&ioapic_lock, flags);
3789 reg_01.raw = io_apic_read(ioapic, 1);
3790 spin_unlock_irqrestore(&ioapic_lock, flags);
3792 return reg_01.bits.entries;
3795 void __init probe_nr_irqs_gsi(void)
3799 nr = acpi_probe_gsi();
3800 if (nr > nr_irqs_gsi) {
3803 /* for acpi=off or acpi is not compiled in */
3807 for (idx = 0; idx < nr_ioapics; idx++)
3808 nr += io_apic_get_redir_entries(idx) + 1;
3810 if (nr > nr_irqs_gsi)
3814 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3817 #ifdef CONFIG_SPARSE_IRQ
3818 int __init arch_probe_nr_irqs(void)
3822 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3823 nr_irqs = NR_VECTORS * nr_cpu_ids;
3825 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3826 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3828 * for MSI and HT dyn irq
3830 nr += nr_irqs_gsi * 16;
3839 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3840 struct io_apic_irq_attr *irq_attr)
3842 struct irq_desc *desc;
3843 struct irq_cfg *cfg;
3846 int trigger, polarity;
3848 ioapic = irq_attr->ioapic;
3849 if (!IO_APIC_IRQ(irq)) {
3850 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3856 node = dev_to_node(dev);
3858 node = cpu_to_node(boot_cpu_id);
3860 desc = irq_to_desc_alloc_node(irq, node);
3862 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3866 pin = irq_attr->ioapic_pin;
3867 trigger = irq_attr->trigger;
3868 polarity = irq_attr->polarity;
3871 * IRQs < 16 are already in the irq_2_pin[] map
3873 if (irq >= nr_legacy_irqs) {
3874 cfg = desc->chip_data;
3875 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3876 printk(KERN_INFO "can not add pin %d for irq %d\n",
3882 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3887 int io_apic_set_pci_routing(struct device *dev, int irq,
3888 struct io_apic_irq_attr *irq_attr)
3892 * Avoid pin reprogramming. PRTs typically include entries
3893 * with redundant pin->gsi mappings (but unique PCI devices);
3894 * we only program the IOAPIC on the first.
3896 ioapic = irq_attr->ioapic;
3897 pin = irq_attr->ioapic_pin;
3898 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3899 pr_debug("Pin %d-%d already programmed\n",
3900 mp_ioapics[ioapic].apicid, pin);
3903 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3905 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3908 u8 __init io_apic_unique_id(u8 id)
3910 #ifdef CONFIG_X86_32
3911 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3912 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3913 return io_apic_get_unique_id(nr_ioapics, id);
3918 DECLARE_BITMAP(used, 256);
3920 bitmap_zero(used, 256);
3921 for (i = 0; i < nr_ioapics; i++) {
3922 struct mpc_ioapic *ia = &mp_ioapics[i];
3923 __set_bit(ia->apicid, used);
3925 if (!test_bit(id, used))
3927 return find_first_zero_bit(used, 256);
3931 #ifdef CONFIG_X86_32
3932 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3934 union IO_APIC_reg_00 reg_00;
3935 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3937 unsigned long flags;
3941 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3942 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3943 * supports up to 16 on one shared APIC bus.
3945 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3946 * advantage of new APIC bus architecture.
3949 if (physids_empty(apic_id_map))
3950 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3952 spin_lock_irqsave(&ioapic_lock, flags);
3953 reg_00.raw = io_apic_read(ioapic, 0);
3954 spin_unlock_irqrestore(&ioapic_lock, flags);
3956 if (apic_id >= get_physical_broadcast()) {
3957 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3958 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3959 apic_id = reg_00.bits.ID;
3963 * Every APIC in a system must have a unique ID or we get lots of nice
3964 * 'stuck on smp_invalidate_needed IPI wait' messages.
3966 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3968 for (i = 0; i < get_physical_broadcast(); i++) {
3969 if (!apic->check_apicid_used(apic_id_map, i))
3973 if (i == get_physical_broadcast())
3974 panic("Max apic_id exceeded!\n");
3976 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3977 "trying %d\n", ioapic, apic_id, i);
3982 tmp = apic->apicid_to_cpu_present(apic_id);
3983 physids_or(apic_id_map, apic_id_map, tmp);
3985 if (reg_00.bits.ID != apic_id) {
3986 reg_00.bits.ID = apic_id;
3988 spin_lock_irqsave(&ioapic_lock, flags);
3989 io_apic_write(ioapic, 0, reg_00.raw);
3990 reg_00.raw = io_apic_read(ioapic, 0);
3991 spin_unlock_irqrestore(&ioapic_lock, flags);
3994 if (reg_00.bits.ID != apic_id) {
3995 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4000 apic_printk(APIC_VERBOSE, KERN_INFO
4001 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4007 int __init io_apic_get_version(int ioapic)
4009 union IO_APIC_reg_01 reg_01;
4010 unsigned long flags;
4012 spin_lock_irqsave(&ioapic_lock, flags);
4013 reg_01.raw = io_apic_read(ioapic, 1);
4014 spin_unlock_irqrestore(&ioapic_lock, flags);
4016 return reg_01.bits.version;
4019 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4023 if (skip_ioapic_setup)
4026 for (i = 0; i < mp_irq_entries; i++)
4027 if (mp_irqs[i].irqtype == mp_INT &&
4028 mp_irqs[i].srcbusirq == bus_irq)
4030 if (i >= mp_irq_entries)
4033 *trigger = irq_trigger(i);
4034 *polarity = irq_polarity(i);
4039 * This function currently is only a helper for the i386 smp boot process where
4040 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4041 * so mask in all cases should simply be apic->target_cpus()
4044 void __init setup_ioapic_dest(void)
4046 int pin, ioapic = 0, irq, irq_entry;
4047 struct irq_desc *desc;
4048 const struct cpumask *mask;
4050 if (skip_ioapic_setup == 1)
4054 if (!acpi_disabled && acpi_ioapic) {
4055 ioapic = mp_find_ioapic(0);
4061 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4062 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4063 if (irq_entry == -1)
4065 irq = pin_2_irq(irq_entry, ioapic, pin);
4067 desc = irq_to_desc(irq);
4070 * Honour affinities which have been set in early boot
4073 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4074 mask = desc->affinity;
4076 mask = apic->target_cpus();
4078 if (intr_remapping_enabled)
4079 set_ir_ioapic_affinity_irq_desc(desc, mask);
4081 set_ioapic_affinity_irq_desc(desc, mask);
4087 #define IOAPIC_RESOURCE_NAME_SIZE 11
4089 static struct resource *ioapic_resources;
4091 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4094 struct resource *res;
4098 if (nr_ioapics <= 0)
4101 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4104 mem = alloc_bootmem(n);
4107 mem += sizeof(struct resource) * nr_ioapics;
4109 for (i = 0; i < nr_ioapics; i++) {
4111 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4112 sprintf(mem, "IOAPIC %u", i);
4113 mem += IOAPIC_RESOURCE_NAME_SIZE;
4116 ioapic_resources = res;
4121 void __init ioapic_init_mappings(void)
4123 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4124 struct resource *ioapic_res;
4127 ioapic_res = ioapic_setup_resources(nr_ioapics);
4128 for (i = 0; i < nr_ioapics; i++) {
4129 if (smp_found_config) {
4130 ioapic_phys = mp_ioapics[i].apicaddr;
4131 #ifdef CONFIG_X86_32
4134 "WARNING: bogus zero IO-APIC "
4135 "address found in MPTABLE, "
4136 "disabling IO/APIC support!\n");
4137 smp_found_config = 0;
4138 skip_ioapic_setup = 1;
4139 goto fake_ioapic_page;
4143 #ifdef CONFIG_X86_32
4146 ioapic_phys = (unsigned long)
4147 alloc_bootmem_pages(PAGE_SIZE);
4148 ioapic_phys = __pa(ioapic_phys);
4150 set_fixmap_nocache(idx, ioapic_phys);
4151 apic_printk(APIC_VERBOSE,
4152 "mapped IOAPIC to %08lx (%08lx)\n",
4153 __fix_to_virt(idx), ioapic_phys);
4156 ioapic_res->start = ioapic_phys;
4157 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4162 void __init ioapic_insert_resources(void)
4165 struct resource *r = ioapic_resources;
4170 "IO APIC resources couldn't be allocated.\n");
4174 for (i = 0; i < nr_ioapics; i++) {
4175 insert_resource(&iomem_resource, r);
4180 int mp_find_ioapic(int gsi)
4184 /* Find the IOAPIC that manages this GSI. */
4185 for (i = 0; i < nr_ioapics; i++) {
4186 if ((gsi >= mp_gsi_routing[i].gsi_base)
4187 && (gsi <= mp_gsi_routing[i].gsi_end))
4191 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4195 int mp_find_ioapic_pin(int ioapic, int gsi)
4197 if (WARN_ON(ioapic == -1))
4199 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4202 return gsi - mp_gsi_routing[ioapic].gsi_base;
4205 static int bad_ioapic(unsigned long address)
4207 if (nr_ioapics >= MAX_IO_APICS) {
4208 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4209 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4213 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4214 " found in table, skipping!\n");
4220 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4224 if (bad_ioapic(address))
4229 mp_ioapics[idx].type = MP_IOAPIC;
4230 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4231 mp_ioapics[idx].apicaddr = address;
4233 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4234 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4235 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4238 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4239 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4241 mp_gsi_routing[idx].gsi_base = gsi_base;
4242 mp_gsi_routing[idx].gsi_end = gsi_base +
4243 io_apic_get_redir_entries(idx);
4245 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4246 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4247 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4248 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);