2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
71 static void __init __ioapic_init_mappings(void);
73 static unsigned int __io_apic_read (unsigned int apic, unsigned int reg);
74 static void __io_apic_write (unsigned int apic, unsigned int reg, unsigned int val);
75 static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
77 static struct io_apic_ops io_apic_ops = {
78 .init = __ioapic_init_mappings,
79 .read = __io_apic_read,
80 .write = __io_apic_write,
81 .modify = __io_apic_modify,
84 void __init set_io_apic_ops(const struct io_apic_ops *ops)
90 * Is the SiS APIC rmw bug present ?
91 * -1 = don't know, 0 = no, 1 = yes
93 int sis_apic_bug = -1;
95 static DEFINE_RAW_SPINLOCK(ioapic_lock);
96 static DEFINE_RAW_SPINLOCK(vector_lock);
98 static struct ioapic {
100 * # of IRQ routing registers
104 * Saved state during suspend/resume, or while enabling intr-remap.
106 struct IO_APIC_route_entry *saved_registers;
107 /* I/O APIC config */
108 struct mpc_ioapic mp_config;
109 /* IO APIC gsi routing info */
110 struct mp_ioapic_gsi gsi_config;
111 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
112 } ioapics[MAX_IO_APICS];
114 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
116 int mpc_ioapic_id(int ioapic_idx)
118 return ioapics[ioapic_idx].mp_config.apicid;
121 unsigned int mpc_ioapic_addr(int ioapic_idx)
123 return ioapics[ioapic_idx].mp_config.apicaddr;
126 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
128 return &ioapics[ioapic_idx].gsi_config;
133 /* The one past the highest gsi number used */
136 /* MP IRQ source entries */
137 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
139 /* # of MP IRQ source entries */
143 static int nr_irqs_gsi = NR_IRQS_LEGACY;
145 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
146 int mp_bus_id_to_type[MAX_MP_BUSSES];
149 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
151 int skip_ioapic_setup;
154 * disable_ioapic_support() - disables ioapic support at runtime
156 void disable_ioapic_support(void)
160 noioapicreroute = -1;
162 skip_ioapic_setup = 1;
165 static int __init parse_noapic(char *str)
167 /* disable IO-APIC */
168 disable_ioapic_support();
171 early_param("noapic", parse_noapic);
173 static int io_apic_setup_irq_pin(unsigned int irq, int node,
174 struct io_apic_irq_attr *attr);
176 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
177 void mp_save_irq(struct mpc_intsrc *m)
181 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
182 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
183 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
184 m->srcbusirq, m->dstapic, m->dstirq);
186 for (i = 0; i < mp_irq_entries; i++) {
187 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
191 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
192 if (++mp_irq_entries == MAX_IRQ_SOURCES)
193 panic("Max # of irq sources exceeded!!\n");
196 struct irq_pin_list {
198 struct irq_pin_list *next;
201 static struct irq_pin_list *alloc_irq_pin_list(int node)
203 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
207 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
208 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
210 int __init arch_early_irq_init(void)
215 if (!legacy_pic->nr_legacy_irqs)
218 for (i = 0; i < nr_ioapics; i++) {
219 ioapics[i].saved_registers =
220 kzalloc(sizeof(struct IO_APIC_route_entry) *
221 ioapics[i].nr_registers, GFP_KERNEL);
222 if (!ioapics[i].saved_registers)
223 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
227 count = ARRAY_SIZE(irq_cfgx);
228 node = cpu_to_node(0);
230 /* Make sure the legacy interrupts are marked in the bitmap */
231 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
233 for (i = 0; i < count; i++) {
234 irq_set_chip_data(i, &cfg[i]);
235 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
236 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
238 * For legacy IRQ's, start with assigning irq0 to irq15 to
239 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
241 if (i < legacy_pic->nr_legacy_irqs) {
242 cfg[i].vector = IRQ0_VECTOR + i;
243 cpumask_set_cpu(0, cfg[i].domain);
250 static struct irq_cfg *irq_cfg(unsigned int irq)
252 return irq_get_chip_data(irq);
255 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
259 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
262 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
264 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
268 free_cpumask_var(cfg->domain);
274 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
278 irq_set_chip_data(at, NULL);
279 free_cpumask_var(cfg->domain);
280 free_cpumask_var(cfg->old_domain);
284 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
286 int res = irq_alloc_desc_at(at, node);
292 cfg = irq_get_chip_data(at);
297 cfg = alloc_irq_cfg(at, node);
299 irq_set_chip_data(at, cfg);
305 static int alloc_irq_from(unsigned int from, int node)
307 return irq_alloc_desc_from(from, node);
310 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
312 free_irq_cfg(at, cfg);
316 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
318 return io_apic_ops.read(apic, reg);
321 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
323 io_apic_ops.write(apic, reg, value);
326 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
328 io_apic_ops.modify(apic, reg, value);
334 unsigned int unused[3];
336 unsigned int unused2[11];
340 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
342 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
343 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
346 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
348 struct io_apic __iomem *io_apic = io_apic_base(apic);
349 writel(vector, &io_apic->eoi);
352 static unsigned int __io_apic_read(unsigned int apic, unsigned int reg)
354 struct io_apic __iomem *io_apic = io_apic_base(apic);
355 writel(reg, &io_apic->index);
356 return readl(&io_apic->data);
359 static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
361 struct io_apic __iomem *io_apic = io_apic_base(apic);
363 writel(reg, &io_apic->index);
364 writel(value, &io_apic->data);
368 * Re-write a value: to be used for read-modify-write
369 * cycles where the read already set up the index register.
371 * Older SiS APIC requires we rewrite the index register
373 static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
375 struct io_apic __iomem *io_apic = io_apic_base(apic);
378 writel(reg, &io_apic->index);
379 writel(value, &io_apic->data);
382 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
384 struct irq_pin_list *entry;
387 raw_spin_lock_irqsave(&ioapic_lock, flags);
388 for_each_irq_pin(entry, cfg->irq_2_pin) {
393 reg = io_apic_read(entry->apic, 0x10 + pin*2);
394 /* Is the remote IRR bit set? */
395 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
396 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
400 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
406 struct { u32 w1, w2; };
407 struct IO_APIC_route_entry entry;
410 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
412 union entry_union eu;
414 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
415 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
420 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
422 union entry_union eu;
425 raw_spin_lock_irqsave(&ioapic_lock, flags);
426 eu.entry = __ioapic_read_entry(apic, pin);
427 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
433 * When we write a new IO APIC routing entry, we need to write the high
434 * word first! If the mask bit in the low word is clear, we will enable
435 * the interrupt, and we need to make sure the entry is fully populated
436 * before that happens.
438 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
440 union entry_union eu = {{0, 0}};
443 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
444 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
447 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
451 raw_spin_lock_irqsave(&ioapic_lock, flags);
452 __ioapic_write_entry(apic, pin, e);
453 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
457 * When we mask an IO APIC routing entry, we need to write the low
458 * word first, in order to set the mask bit before we change the
461 static void ioapic_mask_entry(int apic, int pin)
464 union entry_union eu = { .entry.mask = 1 };
466 raw_spin_lock_irqsave(&ioapic_lock, flags);
467 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
468 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
469 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
473 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
474 * shared ISA-space IRQs, so we have to support them. We are super
475 * fast in the common case, and fast for shared ISA-space IRQs.
477 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
479 struct irq_pin_list **last, *entry;
481 /* don't allow duplicates */
482 last = &cfg->irq_2_pin;
483 for_each_irq_pin(entry, cfg->irq_2_pin) {
484 if (entry->apic == apic && entry->pin == pin)
489 entry = alloc_irq_pin_list(node);
491 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
502 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
504 if (__add_pin_to_irq_node(cfg, node, apic, pin))
505 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
509 * Reroute an IRQ to a different pin.
511 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
512 int oldapic, int oldpin,
513 int newapic, int newpin)
515 struct irq_pin_list *entry;
517 for_each_irq_pin(entry, cfg->irq_2_pin) {
518 if (entry->apic == oldapic && entry->pin == oldpin) {
519 entry->apic = newapic;
521 /* every one is different, right? */
526 /* old apic/pin didn't exist, so just add new ones */
527 add_pin_to_irq_node(cfg, node, newapic, newpin);
530 static void __io_apic_modify_irq(struct irq_pin_list *entry,
531 int mask_and, int mask_or,
532 void (*final)(struct irq_pin_list *entry))
534 unsigned int reg, pin;
537 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
540 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
545 static void io_apic_modify_irq(struct irq_cfg *cfg,
546 int mask_and, int mask_or,
547 void (*final)(struct irq_pin_list *entry))
549 struct irq_pin_list *entry;
551 for_each_irq_pin(entry, cfg->irq_2_pin)
552 __io_apic_modify_irq(entry, mask_and, mask_or, final);
555 static void io_apic_sync(struct irq_pin_list *entry)
558 * Synchronize the IO-APIC and the CPU by doing
559 * a dummy read from the IO-APIC
561 struct io_apic __iomem *io_apic;
563 io_apic = io_apic_base(entry->apic);
564 readl(&io_apic->data);
567 static void mask_ioapic(struct irq_cfg *cfg)
571 raw_spin_lock_irqsave(&ioapic_lock, flags);
572 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
573 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
576 static void mask_ioapic_irq(struct irq_data *data)
578 mask_ioapic(data->chip_data);
581 static void __unmask_ioapic(struct irq_cfg *cfg)
583 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
586 static void unmask_ioapic(struct irq_cfg *cfg)
590 raw_spin_lock_irqsave(&ioapic_lock, flags);
591 __unmask_ioapic(cfg);
592 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
595 static void unmask_ioapic_irq(struct irq_data *data)
597 unmask_ioapic(data->chip_data);
601 * IO-APIC versions below 0x20 don't support EOI register.
602 * For the record, here is the information about various versions:
604 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
605 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
608 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
609 * version as 0x2. This is an error with documentation and these ICH chips
610 * use io-apic's of version 0x20.
612 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
613 * Otherwise, we simulate the EOI message manually by changing the trigger
614 * mode to edge and then back to level, with RTE being masked during this.
616 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
618 if (mpc_ioapic_ver(apic) >= 0x20) {
620 * Intr-remapping uses pin number as the virtual vector
621 * in the RTE. Actual vector is programmed in
622 * intr-remapping table entry. Hence for the io-apic
623 * EOI we use the pin number.
625 if (cfg && irq_remapped(cfg))
626 io_apic_eoi(apic, pin);
628 io_apic_eoi(apic, vector);
630 struct IO_APIC_route_entry entry, entry1;
632 entry = entry1 = __ioapic_read_entry(apic, pin);
635 * Mask the entry and change the trigger mode to edge.
638 entry1.trigger = IOAPIC_EDGE;
640 __ioapic_write_entry(apic, pin, entry1);
643 * Restore the previous level triggered entry.
645 __ioapic_write_entry(apic, pin, entry);
649 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
651 struct irq_pin_list *entry;
654 raw_spin_lock_irqsave(&ioapic_lock, flags);
655 for_each_irq_pin(entry, cfg->irq_2_pin)
656 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
657 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
660 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
662 struct IO_APIC_route_entry entry;
664 /* Check delivery_mode to be sure we're not clearing an SMI pin */
665 entry = ioapic_read_entry(apic, pin);
666 if (entry.delivery_mode == dest_SMI)
670 * Make sure the entry is masked and re-read the contents to check
671 * if it is a level triggered pin and if the remote-IRR is set.
675 ioapic_write_entry(apic, pin, entry);
676 entry = ioapic_read_entry(apic, pin);
683 * Make sure the trigger mode is set to level. Explicit EOI
684 * doesn't clear the remote-IRR if the trigger mode is not
687 if (!entry.trigger) {
688 entry.trigger = IOAPIC_LEVEL;
689 ioapic_write_entry(apic, pin, entry);
692 raw_spin_lock_irqsave(&ioapic_lock, flags);
693 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
694 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
698 * Clear the rest of the bits in the IO-APIC RTE except for the mask
701 ioapic_mask_entry(apic, pin);
702 entry = ioapic_read_entry(apic, pin);
704 printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
705 mpc_ioapic_id(apic), pin);
708 static void clear_IO_APIC (void)
712 for (apic = 0; apic < nr_ioapics; apic++)
713 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
714 clear_IO_APIC_pin(apic, pin);
719 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
720 * specific CPU-side IRQs.
724 static int pirq_entries[MAX_PIRQS] = {
725 [0 ... MAX_PIRQS - 1] = -1
728 static int __init ioapic_pirq_setup(char *str)
731 int ints[MAX_PIRQS+1];
733 get_options(str, ARRAY_SIZE(ints), ints);
735 apic_printk(APIC_VERBOSE, KERN_INFO
736 "PIRQ redirection, working around broken MP-BIOS.\n");
738 if (ints[0] < MAX_PIRQS)
741 for (i = 0; i < max; i++) {
742 apic_printk(APIC_VERBOSE, KERN_DEBUG
743 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
745 * PIRQs are mapped upside down, usually.
747 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
752 __setup("pirq=", ioapic_pirq_setup);
753 #endif /* CONFIG_X86_32 */
756 * Saves all the IO-APIC RTE's
758 int save_ioapic_entries(void)
763 for (apic = 0; apic < nr_ioapics; apic++) {
764 if (!ioapics[apic].saved_registers) {
769 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
770 ioapics[apic].saved_registers[pin] =
771 ioapic_read_entry(apic, pin);
778 * Mask all IO APIC entries.
780 void mask_ioapic_entries(void)
784 for (apic = 0; apic < nr_ioapics; apic++) {
785 if (!ioapics[apic].saved_registers)
788 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
789 struct IO_APIC_route_entry entry;
791 entry = ioapics[apic].saved_registers[pin];
794 ioapic_write_entry(apic, pin, entry);
801 * Restore IO APIC entries which was saved in the ioapic structure.
803 int restore_ioapic_entries(void)
807 for (apic = 0; apic < nr_ioapics; apic++) {
808 if (!ioapics[apic].saved_registers)
811 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
812 ioapic_write_entry(apic, pin,
813 ioapics[apic].saved_registers[pin]);
819 * Find the IRQ entry number of a certain pin.
821 static int find_irq_entry(int ioapic_idx, int pin, int type)
825 for (i = 0; i < mp_irq_entries; i++)
826 if (mp_irqs[i].irqtype == type &&
827 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
828 mp_irqs[i].dstapic == MP_APIC_ALL) &&
829 mp_irqs[i].dstirq == pin)
836 * Find the pin to which IRQ[irq] (ISA) is connected
838 static int __init find_isa_irq_pin(int irq, int type)
842 for (i = 0; i < mp_irq_entries; i++) {
843 int lbus = mp_irqs[i].srcbus;
845 if (test_bit(lbus, mp_bus_not_pci) &&
846 (mp_irqs[i].irqtype == type) &&
847 (mp_irqs[i].srcbusirq == irq))
849 return mp_irqs[i].dstirq;
854 static int __init find_isa_irq_apic(int irq, int type)
858 for (i = 0; i < mp_irq_entries; i++) {
859 int lbus = mp_irqs[i].srcbus;
861 if (test_bit(lbus, mp_bus_not_pci) &&
862 (mp_irqs[i].irqtype == type) &&
863 (mp_irqs[i].srcbusirq == irq))
867 if (i < mp_irq_entries) {
870 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
871 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
878 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
880 * EISA Edge/Level control register, ELCR
882 static int EISA_ELCR(unsigned int irq)
884 if (irq < legacy_pic->nr_legacy_irqs) {
885 unsigned int port = 0x4d0 + (irq >> 3);
886 return (inb(port) >> (irq & 7)) & 1;
888 apic_printk(APIC_VERBOSE, KERN_INFO
889 "Broken MPtable reports ISA irq %d\n", irq);
895 /* ISA interrupts are always polarity zero edge triggered,
896 * when listed as conforming in the MP table. */
898 #define default_ISA_trigger(idx) (0)
899 #define default_ISA_polarity(idx) (0)
901 /* EISA interrupts are always polarity zero and can be edge or level
902 * trigger depending on the ELCR value. If an interrupt is listed as
903 * EISA conforming in the MP table, that means its trigger type must
904 * be read in from the ELCR */
906 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
907 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
909 /* PCI interrupts are always polarity one level triggered,
910 * when listed as conforming in the MP table. */
912 #define default_PCI_trigger(idx) (1)
913 #define default_PCI_polarity(idx) (1)
915 /* MCA interrupts are always polarity zero level triggered,
916 * when listed as conforming in the MP table. */
918 #define default_MCA_trigger(idx) (1)
919 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
921 static int irq_polarity(int idx)
923 int bus = mp_irqs[idx].srcbus;
927 * Determine IRQ line polarity (high active or low active):
929 switch (mp_irqs[idx].irqflag & 3)
931 case 0: /* conforms, ie. bus-type dependent polarity */
932 if (test_bit(bus, mp_bus_not_pci))
933 polarity = default_ISA_polarity(idx);
935 polarity = default_PCI_polarity(idx);
937 case 1: /* high active */
942 case 2: /* reserved */
944 printk(KERN_WARNING "broken BIOS!!\n");
948 case 3: /* low active */
953 default: /* invalid */
955 printk(KERN_WARNING "broken BIOS!!\n");
963 static int irq_trigger(int idx)
965 int bus = mp_irqs[idx].srcbus;
969 * Determine IRQ trigger mode (edge or level sensitive):
971 switch ((mp_irqs[idx].irqflag>>2) & 3)
973 case 0: /* conforms, ie. bus-type dependent */
974 if (test_bit(bus, mp_bus_not_pci))
975 trigger = default_ISA_trigger(idx);
977 trigger = default_PCI_trigger(idx);
978 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
979 switch (mp_bus_id_to_type[bus]) {
980 case MP_BUS_ISA: /* ISA pin */
982 /* set before the switch */
985 case MP_BUS_EISA: /* EISA pin */
987 trigger = default_EISA_trigger(idx);
990 case MP_BUS_PCI: /* PCI pin */
992 /* set before the switch */
995 case MP_BUS_MCA: /* MCA pin */
997 trigger = default_MCA_trigger(idx);
1002 printk(KERN_WARNING "broken BIOS!!\n");
1014 case 2: /* reserved */
1016 printk(KERN_WARNING "broken BIOS!!\n");
1025 default: /* invalid */
1027 printk(KERN_WARNING "broken BIOS!!\n");
1035 static int pin_2_irq(int idx, int apic, int pin)
1038 int bus = mp_irqs[idx].srcbus;
1039 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
1042 * Debugging check, we are in big trouble if this message pops up!
1044 if (mp_irqs[idx].dstirq != pin)
1045 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1047 if (test_bit(bus, mp_bus_not_pci)) {
1048 irq = mp_irqs[idx].srcbusirq;
1050 u32 gsi = gsi_cfg->gsi_base + pin;
1052 if (gsi >= NR_IRQS_LEGACY)
1055 irq = gsi_top + gsi;
1058 #ifdef CONFIG_X86_32
1060 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1062 if ((pin >= 16) && (pin <= 23)) {
1063 if (pirq_entries[pin-16] != -1) {
1064 if (!pirq_entries[pin-16]) {
1065 apic_printk(APIC_VERBOSE, KERN_DEBUG
1066 "disabling PIRQ%d\n", pin-16);
1068 irq = pirq_entries[pin-16];
1069 apic_printk(APIC_VERBOSE, KERN_DEBUG
1070 "using PIRQ%d -> IRQ %d\n",
1081 * Find a specific PCI IRQ entry.
1082 * Not an __init, possibly needed by modules
1084 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1085 struct io_apic_irq_attr *irq_attr)
1087 int ioapic_idx, i, best_guess = -1;
1089 apic_printk(APIC_DEBUG,
1090 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1092 if (test_bit(bus, mp_bus_not_pci)) {
1093 apic_printk(APIC_VERBOSE,
1094 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1097 for (i = 0; i < mp_irq_entries; i++) {
1098 int lbus = mp_irqs[i].srcbus;
1100 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1101 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1102 mp_irqs[i].dstapic == MP_APIC_ALL)
1105 if (!test_bit(lbus, mp_bus_not_pci) &&
1106 !mp_irqs[i].irqtype &&
1108 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1109 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1111 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1114 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1115 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1122 * Use the first all-but-pin matching entry as a
1123 * best-guess fuzzy result for broken mptables.
1125 if (best_guess < 0) {
1126 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1136 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1138 void lock_vector_lock(void)
1140 /* Used to the online set of cpus does not change
1141 * during assign_irq_vector.
1143 raw_spin_lock(&vector_lock);
1146 void unlock_vector_lock(void)
1148 raw_spin_unlock(&vector_lock);
1152 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1155 * NOTE! The local APIC isn't very good at handling
1156 * multiple interrupts at the same interrupt level.
1157 * As the interrupt level is determined by taking the
1158 * vector number and shifting that right by 4, we
1159 * want to spread these out a bit so that they don't
1160 * all fall in the same interrupt level.
1162 * Also, we've got to be careful not to trash gate
1163 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1165 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1166 static int current_offset = VECTOR_OFFSET_START % 8;
1167 unsigned int old_vector;
1169 cpumask_var_t tmp_mask;
1171 if (cfg->move_in_progress)
1174 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1177 old_vector = cfg->vector;
1179 cpumask_and(tmp_mask, mask, cpu_online_mask);
1180 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1181 if (!cpumask_empty(tmp_mask)) {
1182 free_cpumask_var(tmp_mask);
1187 /* Only try and allocate irqs on cpus that are present */
1189 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1193 apic->vector_allocation_domain(cpu, tmp_mask);
1195 vector = current_vector;
1196 offset = current_offset;
1199 if (vector >= first_system_vector) {
1200 /* If out of vectors on large boxen, must share them. */
1201 offset = (offset + 1) % 8;
1202 vector = FIRST_EXTERNAL_VECTOR + offset;
1204 if (unlikely(current_vector == vector))
1207 if (test_bit(vector, used_vectors))
1210 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1211 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1214 current_vector = vector;
1215 current_offset = offset;
1217 cfg->move_in_progress = 1;
1218 cpumask_copy(cfg->old_domain, cfg->domain);
1220 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1221 per_cpu(vector_irq, new_cpu)[vector] = irq;
1222 cfg->vector = vector;
1223 cpumask_copy(cfg->domain, tmp_mask);
1227 free_cpumask_var(tmp_mask);
1231 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1234 unsigned long flags;
1236 raw_spin_lock_irqsave(&vector_lock, flags);
1237 err = __assign_irq_vector(irq, cfg, mask);
1238 raw_spin_unlock_irqrestore(&vector_lock, flags);
1242 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1246 BUG_ON(!cfg->vector);
1248 vector = cfg->vector;
1249 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1250 per_cpu(vector_irq, cpu)[vector] = -1;
1253 cpumask_clear(cfg->domain);
1255 if (likely(!cfg->move_in_progress))
1257 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1258 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1260 if (per_cpu(vector_irq, cpu)[vector] != irq)
1262 per_cpu(vector_irq, cpu)[vector] = -1;
1266 cfg->move_in_progress = 0;
1269 void __setup_vector_irq(int cpu)
1271 /* Initialize vector_irq on a new cpu */
1273 struct irq_cfg *cfg;
1276 * vector_lock will make sure that we don't run into irq vector
1277 * assignments that might be happening on another cpu in parallel,
1278 * while we setup our initial vector to irq mappings.
1280 raw_spin_lock(&vector_lock);
1281 /* Mark the inuse vectors */
1282 for_each_active_irq(irq) {
1283 cfg = irq_get_chip_data(irq);
1287 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1288 * will be part of the irq_cfg's domain.
1290 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1291 cpumask_set_cpu(cpu, cfg->domain);
1293 if (!cpumask_test_cpu(cpu, cfg->domain))
1295 vector = cfg->vector;
1296 per_cpu(vector_irq, cpu)[vector] = irq;
1298 /* Mark the free vectors */
1299 for (vector = 0; vector < NR_VECTORS; ++vector) {
1300 irq = per_cpu(vector_irq, cpu)[vector];
1305 if (!cpumask_test_cpu(cpu, cfg->domain))
1306 per_cpu(vector_irq, cpu)[vector] = -1;
1308 raw_spin_unlock(&vector_lock);
1311 static struct irq_chip ioapic_chip;
1313 #ifdef CONFIG_X86_32
1314 static inline int IO_APIC_irq_trigger(int irq)
1318 for (apic = 0; apic < nr_ioapics; apic++) {
1319 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1320 idx = find_irq_entry(apic, pin, mp_INT);
1321 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1322 return irq_trigger(idx);
1326 * nonexistent IRQs are edge default
1331 static inline int IO_APIC_irq_trigger(int irq)
1337 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1338 unsigned long trigger)
1340 struct irq_chip *chip = &ioapic_chip;
1341 irq_flow_handler_t hdl;
1344 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1345 trigger == IOAPIC_LEVEL) {
1346 irq_set_status_flags(irq, IRQ_LEVEL);
1349 irq_clear_status_flags(irq, IRQ_LEVEL);
1353 if (irq_remapped(cfg)) {
1354 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1355 irq_remap_modify_chip_defaults(chip);
1356 fasteoi = trigger != 0;
1359 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1360 irq_set_chip_and_handler_name(irq, chip, hdl,
1361 fasteoi ? "fasteoi" : "edge");
1365 static int setup_ir_ioapic_entry(int irq,
1366 struct IR_IO_APIC_route_entry *entry,
1367 unsigned int destination, int vector,
1368 struct io_apic_irq_attr *attr)
1372 int ioapic_id = mpc_ioapic_id(attr->ioapic);
1373 struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
1376 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
1380 index = alloc_irte(iommu, irq, 1);
1382 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
1386 prepare_irte(&irte, vector, destination);
1388 /* Set source-id of interrupt request */
1389 set_ioapic_sid(&irte, ioapic_id);
1391 modify_irte(irq, &irte);
1393 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1394 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1395 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1396 "Avail:%X Vector:%02X Dest:%08X "
1397 "SID:%04X SQ:%X SVT:%X)\n",
1398 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
1399 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1400 irte.avail, irte.vector, irte.dest_id,
1401 irte.sid, irte.sq, irte.svt);
1403 memset(entry, 0, sizeof(*entry));
1405 entry->index2 = (index >> 15) & 0x1;
1408 entry->index = (index & 0x7fff);
1410 * IO-APIC RTE will be configured with virtual vector.
1411 * irq handler will do the explicit EOI to the io-apic.
1413 entry->vector = attr->ioapic_pin;
1414 entry->mask = 0; /* enable IRQ */
1415 entry->trigger = attr->trigger;
1416 entry->polarity = attr->polarity;
1418 /* Mask level triggered irqs.
1419 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1427 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1428 unsigned int destination, int vector,
1429 struct io_apic_irq_attr *attr)
1431 if (intr_remapping_enabled)
1432 return setup_ir_ioapic_entry(irq,
1433 (struct IR_IO_APIC_route_entry *)entry,
1434 destination, vector, attr);
1436 memset(entry, 0, sizeof(*entry));
1438 entry->delivery_mode = apic->irq_delivery_mode;
1439 entry->dest_mode = apic->irq_dest_mode;
1440 entry->dest = destination;
1441 entry->vector = vector;
1442 entry->mask = 0; /* enable IRQ */
1443 entry->trigger = attr->trigger;
1444 entry->polarity = attr->polarity;
1447 * Mask level triggered irqs.
1448 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1456 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1457 struct io_apic_irq_attr *attr)
1459 struct IO_APIC_route_entry entry;
1462 if (!IO_APIC_IRQ(irq))
1465 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1466 * controllers like 8259. Now that IO-APIC can handle this irq, update
1469 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1470 apic->vector_allocation_domain(0, cfg->domain);
1472 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1475 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1477 apic_printk(APIC_VERBOSE,KERN_DEBUG
1478 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1479 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1480 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1481 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1483 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1484 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1485 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1486 __clear_irq_vector(irq, cfg);
1491 ioapic_register_intr(irq, cfg, attr->trigger);
1492 if (irq < legacy_pic->nr_legacy_irqs)
1493 legacy_pic->mask(irq);
1495 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1498 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1503 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1504 mpc_ioapic_id(ioapic_idx), pin);
1508 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1510 int idx, node = cpu_to_node(0);
1511 struct io_apic_irq_attr attr;
1512 unsigned int pin, irq;
1514 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1515 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1516 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1519 irq = pin_2_irq(idx, ioapic_idx, pin);
1521 if ((ioapic_idx > 0) && (irq > 16))
1525 * Skip the timer IRQ if there's a quirk handler
1526 * installed and if it returns 1:
1528 if (apic->multi_timer_check &&
1529 apic->multi_timer_check(ioapic_idx, irq))
1532 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1535 io_apic_setup_irq_pin(irq, node, &attr);
1539 static void __init setup_IO_APIC_irqs(void)
1541 unsigned int ioapic_idx;
1543 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1545 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1546 __io_apic_setup_irqs(ioapic_idx);
1550 * for the gsit that is not in first ioapic
1551 * but could not use acpi_register_gsi()
1552 * like some special sci in IBM x3330
1554 void setup_IO_APIC_irq_extra(u32 gsi)
1556 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1557 struct io_apic_irq_attr attr;
1560 * Convert 'gsi' to 'ioapic.pin'.
1562 ioapic_idx = mp_find_ioapic(gsi);
1566 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1567 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1571 irq = pin_2_irq(idx, ioapic_idx, pin);
1573 /* Only handle the non legacy irqs on secondary ioapics */
1574 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1577 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1580 io_apic_setup_irq_pin_once(irq, node, &attr);
1584 * Set up the timer pin, possibly with the 8259A-master behind.
1586 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1587 unsigned int pin, int vector)
1589 struct IO_APIC_route_entry entry;
1591 if (intr_remapping_enabled)
1594 memset(&entry, 0, sizeof(entry));
1597 * We use logical delivery to get the timer IRQ
1600 entry.dest_mode = apic->irq_dest_mode;
1601 entry.mask = 0; /* don't mask IRQ for edge */
1602 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1603 entry.delivery_mode = apic->irq_delivery_mode;
1606 entry.vector = vector;
1609 * The timer IRQ doesn't have to know that behind the
1610 * scene we may have a 8259A-master in AEOI mode ...
1612 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1616 * Add it to the IO-APIC irq-routing table:
1618 ioapic_write_entry(ioapic_idx, pin, entry);
1621 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1624 union IO_APIC_reg_00 reg_00;
1625 union IO_APIC_reg_01 reg_01;
1626 union IO_APIC_reg_02 reg_02;
1627 union IO_APIC_reg_03 reg_03;
1628 unsigned long flags;
1630 raw_spin_lock_irqsave(&ioapic_lock, flags);
1631 reg_00.raw = io_apic_read(ioapic_idx, 0);
1632 reg_01.raw = io_apic_read(ioapic_idx, 1);
1633 if (reg_01.bits.version >= 0x10)
1634 reg_02.raw = io_apic_read(ioapic_idx, 2);
1635 if (reg_01.bits.version >= 0x20)
1636 reg_03.raw = io_apic_read(ioapic_idx, 3);
1637 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1640 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1641 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1642 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1643 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1644 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1646 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1647 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1648 reg_01.bits.entries);
1650 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1651 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1652 reg_01.bits.version);
1655 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1656 * but the value of reg_02 is read as the previous read register
1657 * value, so ignore it if reg_02 == reg_01.
1659 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1660 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1661 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1665 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1666 * or reg_03, but the value of reg_0[23] is read as the previous read
1667 * register value, so ignore it if reg_03 == reg_0[12].
1669 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1670 reg_03.raw != reg_01.raw) {
1671 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1672 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1675 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1677 if (intr_remapping_enabled) {
1678 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1679 " Pol Stat Indx2 Zero Vect:\n");
1681 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1682 " Stat Dmod Deli Vect:\n");
1685 for (i = 0; i <= reg_01.bits.entries; i++) {
1686 if (intr_remapping_enabled) {
1687 struct IO_APIC_route_entry entry;
1688 struct IR_IO_APIC_route_entry *ir_entry;
1690 entry = ioapic_read_entry(ioapic_idx, i);
1691 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1692 printk(KERN_DEBUG " %02x %04X ",
1696 printk("%1d %1d %1d %1d %1d "
1697 "%1d %1d %X %02X\n",
1703 ir_entry->delivery_status,
1709 struct IO_APIC_route_entry entry;
1711 entry = ioapic_read_entry(ioapic_idx, i);
1712 printk(KERN_DEBUG " %02x %02X ",
1716 printk("%1d %1d %1d %1d %1d "
1722 entry.delivery_status,
1724 entry.delivery_mode,
1731 __apicdebuginit(void) print_IO_APICs(void)
1734 struct irq_cfg *cfg;
1736 struct irq_chip *chip;
1738 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1739 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1740 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1741 mpc_ioapic_id(ioapic_idx),
1742 ioapics[ioapic_idx].nr_registers);
1745 * We are a bit conservative about what we expect. We have to
1746 * know about every hardware change ASAP.
1748 printk(KERN_INFO "testing the IO APIC.......................\n");
1750 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1751 print_IO_APIC(ioapic_idx);
1753 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1754 for_each_active_irq(irq) {
1755 struct irq_pin_list *entry;
1757 chip = irq_get_chip(irq);
1758 if (chip != &ioapic_chip)
1761 cfg = irq_get_chip_data(irq);
1764 entry = cfg->irq_2_pin;
1767 printk(KERN_DEBUG "IRQ%d ", irq);
1768 for_each_irq_pin(entry, cfg->irq_2_pin)
1769 printk("-> %d:%d", entry->apic, entry->pin);
1773 printk(KERN_INFO ".................................... done.\n");
1776 __apicdebuginit(void) print_APIC_field(int base)
1782 for (i = 0; i < 8; i++)
1783 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1785 printk(KERN_CONT "\n");
1788 __apicdebuginit(void) print_local_APIC(void *dummy)
1790 unsigned int i, v, ver, maxlvt;
1793 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1794 smp_processor_id(), hard_smp_processor_id());
1795 v = apic_read(APIC_ID);
1796 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1797 v = apic_read(APIC_LVR);
1798 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1799 ver = GET_APIC_VERSION(v);
1800 maxlvt = lapic_get_maxlvt();
1802 v = apic_read(APIC_TASKPRI);
1803 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1805 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1806 if (!APIC_XAPIC(ver)) {
1807 v = apic_read(APIC_ARBPRI);
1808 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1809 v & APIC_ARBPRI_MASK);
1811 v = apic_read(APIC_PROCPRI);
1812 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1816 * Remote read supported only in the 82489DX and local APIC for
1817 * Pentium processors.
1819 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1820 v = apic_read(APIC_RRR);
1821 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1824 v = apic_read(APIC_LDR);
1825 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1826 if (!x2apic_enabled()) {
1827 v = apic_read(APIC_DFR);
1828 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1830 v = apic_read(APIC_SPIV);
1831 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1833 printk(KERN_DEBUG "... APIC ISR field:\n");
1834 print_APIC_field(APIC_ISR);
1835 printk(KERN_DEBUG "... APIC TMR field:\n");
1836 print_APIC_field(APIC_TMR);
1837 printk(KERN_DEBUG "... APIC IRR field:\n");
1838 print_APIC_field(APIC_IRR);
1840 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1841 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1842 apic_write(APIC_ESR, 0);
1844 v = apic_read(APIC_ESR);
1845 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1848 icr = apic_icr_read();
1849 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1850 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1852 v = apic_read(APIC_LVTT);
1853 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1855 if (maxlvt > 3) { /* PC is LVT#4. */
1856 v = apic_read(APIC_LVTPC);
1857 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1859 v = apic_read(APIC_LVT0);
1860 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1861 v = apic_read(APIC_LVT1);
1862 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1864 if (maxlvt > 2) { /* ERR is LVT#3. */
1865 v = apic_read(APIC_LVTERR);
1866 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1869 v = apic_read(APIC_TMICT);
1870 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1871 v = apic_read(APIC_TMCCT);
1872 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1873 v = apic_read(APIC_TDCR);
1874 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1876 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1877 v = apic_read(APIC_EFEAT);
1878 maxlvt = (v >> 16) & 0xff;
1879 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1880 v = apic_read(APIC_ECTRL);
1881 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1882 for (i = 0; i < maxlvt; i++) {
1883 v = apic_read(APIC_EILVTn(i));
1884 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1890 __apicdebuginit(void) print_local_APICs(int maxcpu)
1898 for_each_online_cpu(cpu) {
1901 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1906 __apicdebuginit(void) print_PIC(void)
1909 unsigned long flags;
1911 if (!legacy_pic->nr_legacy_irqs)
1914 printk(KERN_DEBUG "\nprinting PIC contents\n");
1916 raw_spin_lock_irqsave(&i8259A_lock, flags);
1918 v = inb(0xa1) << 8 | inb(0x21);
1919 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1921 v = inb(0xa0) << 8 | inb(0x20);
1922 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1926 v = inb(0xa0) << 8 | inb(0x20);
1930 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1932 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1934 v = inb(0x4d1) << 8 | inb(0x4d0);
1935 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1938 static int __initdata show_lapic = 1;
1939 static __init int setup_show_lapic(char *arg)
1943 if (strcmp(arg, "all") == 0) {
1944 show_lapic = CONFIG_NR_CPUS;
1946 get_option(&arg, &num);
1953 __setup("show_lapic=", setup_show_lapic);
1955 __apicdebuginit(int) print_ICs(void)
1957 if (apic_verbosity == APIC_QUIET)
1962 /* don't print out if apic is not there */
1963 if (!cpu_has_apic && !apic_from_smp_config())
1966 print_local_APICs(show_lapic);
1972 late_initcall(print_ICs);
1975 /* Where if anywhere is the i8259 connect in external int mode */
1976 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1978 void __init enable_IO_APIC(void)
1980 int i8259_apic, i8259_pin;
1983 if (!legacy_pic->nr_legacy_irqs)
1986 for(apic = 0; apic < nr_ioapics; apic++) {
1988 /* See if any of the pins is in ExtINT mode */
1989 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1990 struct IO_APIC_route_entry entry;
1991 entry = ioapic_read_entry(apic, pin);
1993 /* If the interrupt line is enabled and in ExtInt mode
1994 * I have found the pin where the i8259 is connected.
1996 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1997 ioapic_i8259.apic = apic;
1998 ioapic_i8259.pin = pin;
2004 /* Look to see what if the MP table has reported the ExtINT */
2005 /* If we could not find the appropriate pin by looking at the ioapic
2006 * the i8259 probably is not connected the ioapic but give the
2007 * mptable a chance anyway.
2009 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2010 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2011 /* Trust the MP table if nothing is setup in the hardware */
2012 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2013 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2014 ioapic_i8259.pin = i8259_pin;
2015 ioapic_i8259.apic = i8259_apic;
2017 /* Complain if the MP table and the hardware disagree */
2018 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2019 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2021 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2025 * Do not trust the IO-APIC being empty at bootup
2031 * Not an __init, needed by the reboot code
2033 void disable_IO_APIC(void)
2036 * Clear the IO-APIC before rebooting:
2040 if (!legacy_pic->nr_legacy_irqs)
2044 * If the i8259 is routed through an IOAPIC
2045 * Put that IOAPIC in virtual wire mode
2046 * so legacy interrupts can be delivered.
2048 * With interrupt-remapping, for now we will use virtual wire A mode,
2049 * as virtual wire B is little complex (need to configure both
2050 * IOAPIC RTE as well as interrupt-remapping table entry).
2051 * As this gets called during crash dump, keep this simple for now.
2053 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2054 struct IO_APIC_route_entry entry;
2056 memset(&entry, 0, sizeof(entry));
2057 entry.mask = 0; /* Enabled */
2058 entry.trigger = 0; /* Edge */
2060 entry.polarity = 0; /* High */
2061 entry.delivery_status = 0;
2062 entry.dest_mode = 0; /* Physical */
2063 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2065 entry.dest = read_apic_id();
2068 * Add it to the IO-APIC irq-routing table:
2070 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2074 * Use virtual wire A mode when interrupt remapping is enabled.
2076 if (cpu_has_apic || apic_from_smp_config())
2077 disconnect_bsp_APIC(!intr_remapping_enabled &&
2078 ioapic_i8259.pin != -1);
2081 #ifdef CONFIG_X86_32
2083 * function to set the IO-APIC physical IDs based on the
2084 * values stored in the MPC table.
2086 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2088 void __init setup_ioapic_ids_from_mpc_nocheck(void)
2090 union IO_APIC_reg_00 reg_00;
2091 physid_mask_t phys_id_present_map;
2094 unsigned char old_id;
2095 unsigned long flags;
2098 * This is broken; anything with a real cpu count has to
2099 * circumvent this idiocy regardless.
2101 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2104 * Set the IOAPIC ID to the value stored in the MPC table.
2106 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
2107 /* Read the register 0 value */
2108 raw_spin_lock_irqsave(&ioapic_lock, flags);
2109 reg_00.raw = io_apic_read(ioapic_idx, 0);
2110 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2112 old_id = mpc_ioapic_id(ioapic_idx);
2114 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2115 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2116 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2117 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2119 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2123 * Sanity check, is the ID really free? Every APIC in a
2124 * system must have a unique ID or we get lots of nice
2125 * 'stuck on smp_invalidate_needed IPI wait' messages.
2127 if (apic->check_apicid_used(&phys_id_present_map,
2128 mpc_ioapic_id(ioapic_idx))) {
2129 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2130 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2131 for (i = 0; i < get_physical_broadcast(); i++)
2132 if (!physid_isset(i, phys_id_present_map))
2134 if (i >= get_physical_broadcast())
2135 panic("Max APIC ID exceeded!\n");
2136 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2138 physid_set(i, phys_id_present_map);
2139 ioapics[ioapic_idx].mp_config.apicid = i;
2142 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2144 apic_printk(APIC_VERBOSE, "Setting %d in the "
2145 "phys_id_present_map\n",
2146 mpc_ioapic_id(ioapic_idx));
2147 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2151 * We need to adjust the IRQ routing table
2152 * if the ID changed.
2154 if (old_id != mpc_ioapic_id(ioapic_idx))
2155 for (i = 0; i < mp_irq_entries; i++)
2156 if (mp_irqs[i].dstapic == old_id)
2158 = mpc_ioapic_id(ioapic_idx);
2161 * Update the ID register according to the right value
2162 * from the MPC table if they are different.
2164 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2167 apic_printk(APIC_VERBOSE, KERN_INFO
2168 "...changing IO-APIC physical APIC ID to %d ...",
2169 mpc_ioapic_id(ioapic_idx));
2171 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2172 raw_spin_lock_irqsave(&ioapic_lock, flags);
2173 io_apic_write(ioapic_idx, 0, reg_00.raw);
2174 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2179 raw_spin_lock_irqsave(&ioapic_lock, flags);
2180 reg_00.raw = io_apic_read(ioapic_idx, 0);
2181 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2182 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2183 printk("could not set ID!\n");
2185 apic_printk(APIC_VERBOSE, " ok.\n");
2189 void __init setup_ioapic_ids_from_mpc(void)
2195 * Don't check I/O APIC IDs for xAPIC systems. They have
2196 * no meaning without the serial APIC bus.
2198 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2199 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2201 setup_ioapic_ids_from_mpc_nocheck();
2205 int no_timer_check __initdata;
2207 static int __init notimercheck(char *s)
2212 __setup("no_timer_check", notimercheck);
2215 * There is a nasty bug in some older SMP boards, their mptable lies
2216 * about the timer IRQ. We do the following to work around the situation:
2218 * - timer IRQ defaults to IO-APIC IRQ
2219 * - if this function detects that timer IRQs are defunct, then we fall
2220 * back to ISA timer IRQs
2222 static int __init timer_irq_works(void)
2224 unsigned long t1 = jiffies;
2225 unsigned long flags;
2230 local_save_flags(flags);
2232 /* Let ten ticks pass... */
2233 mdelay((10 * 1000) / HZ);
2234 local_irq_restore(flags);
2237 * Expect a few ticks at least, to be sure some possible
2238 * glue logic does not lock up after one or two first
2239 * ticks in a non-ExtINT mode. Also the local APIC
2240 * might have cached one ExtINT interrupt. Finally, at
2241 * least one tick may be lost due to delays.
2245 if (time_after(jiffies, t1 + 4))
2251 * In the SMP+IOAPIC case it might happen that there are an unspecified
2252 * number of pending IRQ events unhandled. These cases are very rare,
2253 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2254 * better to do it this way as thus we do not have to be aware of
2255 * 'pending' interrupts in the IRQ path, except at this point.
2258 * Edge triggered needs to resend any interrupt
2259 * that was delayed but this is now handled in the device
2264 * Starting up a edge-triggered IO-APIC interrupt is
2265 * nasty - we need to make sure that we get the edge.
2266 * If it is already asserted for some reason, we need
2267 * return 1 to indicate that is was pending.
2269 * This is not complete - we should be able to fake
2270 * an edge even if it isn't on the 8259A...
2273 static unsigned int startup_ioapic_irq(struct irq_data *data)
2275 int was_pending = 0, irq = data->irq;
2276 unsigned long flags;
2278 raw_spin_lock_irqsave(&ioapic_lock, flags);
2279 if (irq < legacy_pic->nr_legacy_irqs) {
2280 legacy_pic->mask(irq);
2281 if (legacy_pic->irq_pending(irq))
2284 __unmask_ioapic(data->chip_data);
2285 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2290 static int ioapic_retrigger_irq(struct irq_data *data)
2292 struct irq_cfg *cfg = data->chip_data;
2293 unsigned long flags;
2295 raw_spin_lock_irqsave(&vector_lock, flags);
2296 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2297 raw_spin_unlock_irqrestore(&vector_lock, flags);
2303 * Level and edge triggered IO-APIC interrupts need different handling,
2304 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2305 * handled with the level-triggered descriptor, but that one has slightly
2306 * more overhead. Level-triggered interrupts cannot be handled with the
2307 * edge-triggered handler, without risking IRQ storms and other ugly
2312 void send_cleanup_vector(struct irq_cfg *cfg)
2314 cpumask_var_t cleanup_mask;
2316 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2318 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2319 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2321 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2322 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2323 free_cpumask_var(cleanup_mask);
2325 cfg->move_in_progress = 0;
2328 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2331 struct irq_pin_list *entry;
2332 u8 vector = cfg->vector;
2334 for_each_irq_pin(entry, cfg->irq_2_pin) {
2340 * With interrupt-remapping, destination information comes
2341 * from interrupt-remapping table entry.
2343 if (!irq_remapped(cfg))
2344 io_apic_write(apic, 0x11 + pin*2, dest);
2345 reg = io_apic_read(apic, 0x10 + pin*2);
2346 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2348 io_apic_modify(apic, 0x10 + pin*2, reg);
2353 * Either sets data->affinity to a valid value, and returns
2354 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2355 * leaves data->affinity untouched.
2357 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2358 unsigned int *dest_id)
2360 struct irq_cfg *cfg = data->chip_data;
2362 if (!cpumask_intersects(mask, cpu_online_mask))
2365 if (assign_irq_vector(data->irq, data->chip_data, mask))
2368 cpumask_copy(data->affinity, mask);
2370 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2375 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2378 unsigned int dest, irq = data->irq;
2379 unsigned long flags;
2382 raw_spin_lock_irqsave(&ioapic_lock, flags);
2383 ret = __ioapic_set_affinity(data, mask, &dest);
2385 /* Only the high 8 bits are valid. */
2386 dest = SET_APIC_LOGICAL_ID(dest);
2387 __target_IO_APIC_irq(irq, dest, data->chip_data);
2389 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2393 #ifdef CONFIG_IRQ_REMAP
2396 * Migrate the IO-APIC irq in the presence of intr-remapping.
2398 * For both level and edge triggered, irq migration is a simple atomic
2399 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2401 * For level triggered, we eliminate the io-apic RTE modification (with the
2402 * updated vector information), by using a virtual vector (io-apic pin number).
2403 * Real vector that is used for interrupting cpu will be coming from
2404 * the interrupt-remapping table entry.
2406 * As the migration is a simple atomic update of IRTE, the same mechanism
2407 * is used to migrate MSI irq's in the presence of interrupt-remapping.
2410 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2413 struct irq_cfg *cfg = data->chip_data;
2414 unsigned int dest, irq = data->irq;
2417 if (!cpumask_intersects(mask, cpu_online_mask))
2420 if (get_irte(irq, &irte))
2423 if (assign_irq_vector(irq, cfg, mask))
2426 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2428 irte.vector = cfg->vector;
2429 irte.dest_id = IRTE_DEST(dest);
2432 * Atomically updates the IRTE with the new destination, vector
2433 * and flushes the interrupt entry cache.
2435 modify_irte(irq, &irte);
2438 * After this point, all the interrupts will start arriving
2439 * at the new destination. So, time to cleanup the previous
2440 * vector allocation.
2442 if (cfg->move_in_progress)
2443 send_cleanup_vector(cfg);
2445 cpumask_copy(data->affinity, mask);
2451 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2458 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2460 unsigned vector, me;
2466 me = smp_processor_id();
2467 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2470 struct irq_desc *desc;
2471 struct irq_cfg *cfg;
2472 irq = __this_cpu_read(vector_irq[vector]);
2477 desc = irq_to_desc(irq);
2482 raw_spin_lock(&desc->lock);
2485 * Check if the irq migration is in progress. If so, we
2486 * haven't received the cleanup request yet for this irq.
2488 if (cfg->move_in_progress)
2491 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2494 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2496 * Check if the vector that needs to be cleanedup is
2497 * registered at the cpu's IRR. If so, then this is not
2498 * the best time to clean it up. Lets clean it up in the
2499 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2502 if (irr & (1 << (vector % 32))) {
2503 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2506 __this_cpu_write(vector_irq[vector], -1);
2508 raw_spin_unlock(&desc->lock);
2514 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2518 if (likely(!cfg->move_in_progress))
2521 me = smp_processor_id();
2523 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2524 send_cleanup_vector(cfg);
2527 static void irq_complete_move(struct irq_cfg *cfg)
2529 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2532 void irq_force_complete_move(int irq)
2534 struct irq_cfg *cfg = irq_get_chip_data(irq);
2539 __irq_complete_move(cfg, cfg->vector);
2542 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2545 static void ack_apic_edge(struct irq_data *data)
2547 irq_complete_move(data->chip_data);
2552 atomic_t irq_mis_count;
2554 #ifdef CONFIG_GENERIC_PENDING_IRQ
2555 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2557 /* If we are moving the irq we need to mask it */
2558 if (unlikely(irqd_is_setaffinity_pending(data))) {
2565 static inline void ioapic_irqd_unmask(struct irq_data *data,
2566 struct irq_cfg *cfg, bool masked)
2568 if (unlikely(masked)) {
2569 /* Only migrate the irq if the ack has been received.
2571 * On rare occasions the broadcast level triggered ack gets
2572 * delayed going to ioapics, and if we reprogram the
2573 * vector while Remote IRR is still set the irq will never
2576 * To prevent this scenario we read the Remote IRR bit
2577 * of the ioapic. This has two effects.
2578 * - On any sane system the read of the ioapic will
2579 * flush writes (and acks) going to the ioapic from
2581 * - We get to see if the ACK has actually been delivered.
2583 * Based on failed experiments of reprogramming the
2584 * ioapic entry from outside of irq context starting
2585 * with masking the ioapic entry and then polling until
2586 * Remote IRR was clear before reprogramming the
2587 * ioapic I don't trust the Remote IRR bit to be
2588 * completey accurate.
2590 * However there appears to be no other way to plug
2591 * this race, so if the Remote IRR bit is not
2592 * accurate and is causing problems then it is a hardware bug
2593 * and you can go talk to the chipset vendor about it.
2595 if (!io_apic_level_ack_pending(cfg))
2596 irq_move_masked_irq(data);
2601 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2605 static inline void ioapic_irqd_unmask(struct irq_data *data,
2606 struct irq_cfg *cfg, bool masked)
2611 static void ack_apic_level(struct irq_data *data)
2613 struct irq_cfg *cfg = data->chip_data;
2614 int i, irq = data->irq;
2618 irq_complete_move(cfg);
2619 masked = ioapic_irqd_mask(data, cfg);
2622 * It appears there is an erratum which affects at least version 0x11
2623 * of I/O APIC (that's the 82093AA and cores integrated into various
2624 * chipsets). Under certain conditions a level-triggered interrupt is
2625 * erroneously delivered as edge-triggered one but the respective IRR
2626 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2627 * message but it will never arrive and further interrupts are blocked
2628 * from the source. The exact reason is so far unknown, but the
2629 * phenomenon was observed when two consecutive interrupt requests
2630 * from a given source get delivered to the same CPU and the source is
2631 * temporarily disabled in between.
2633 * A workaround is to simulate an EOI message manually. We achieve it
2634 * by setting the trigger mode to edge and then to level when the edge
2635 * trigger mode gets detected in the TMR of a local APIC for a
2636 * level-triggered interrupt. We mask the source for the time of the
2637 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2638 * The idea is from Manfred Spraul. --macro
2640 * Also in the case when cpu goes offline, fixup_irqs() will forward
2641 * any unhandled interrupt on the offlined cpu to the new cpu
2642 * destination that is handling the corresponding interrupt. This
2643 * interrupt forwarding is done via IPI's. Hence, in this case also
2644 * level-triggered io-apic interrupt will be seen as an edge
2645 * interrupt in the IRR. And we can't rely on the cpu's EOI
2646 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2647 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2648 * supporting EOI register, we do an explicit EOI to clear the
2649 * remote IRR and on IO-APIC's which don't have an EOI register,
2650 * we use the above logic (mask+edge followed by unmask+level) from
2651 * Manfred Spraul to clear the remote IRR.
2654 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2657 * We must acknowledge the irq before we move it or the acknowledge will
2658 * not propagate properly.
2663 * Tail end of clearing remote IRR bit (either by delivering the EOI
2664 * message via io-apic EOI register write or simulating it using
2665 * mask+edge followed by unnask+level logic) manually when the
2666 * level triggered interrupt is seen as the edge triggered interrupt
2669 if (!(v & (1 << (i & 0x1f)))) {
2670 atomic_inc(&irq_mis_count);
2672 eoi_ioapic_irq(irq, cfg);
2675 ioapic_irqd_unmask(data, cfg, masked);
2678 #ifdef CONFIG_IRQ_REMAP
2679 static void ir_ack_apic_edge(struct irq_data *data)
2684 static void ir_ack_apic_level(struct irq_data *data)
2687 eoi_ioapic_irq(data->irq, data->chip_data);
2690 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2692 seq_printf(p, " IR-%s", data->chip->name);
2695 static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2697 chip->irq_print_chip = ir_print_prefix;
2698 chip->irq_ack = ir_ack_apic_edge;
2699 chip->irq_eoi = ir_ack_apic_level;
2702 chip->irq_set_affinity = ir_ioapic_set_affinity;
2705 #endif /* CONFIG_IRQ_REMAP */
2707 static struct irq_chip ioapic_chip __read_mostly = {
2709 .irq_startup = startup_ioapic_irq,
2710 .irq_mask = mask_ioapic_irq,
2711 .irq_unmask = unmask_ioapic_irq,
2712 .irq_ack = ack_apic_edge,
2713 .irq_eoi = ack_apic_level,
2715 .irq_set_affinity = ioapic_set_affinity,
2717 .irq_retrigger = ioapic_retrigger_irq,
2720 static inline void init_IO_APIC_traps(void)
2722 struct irq_cfg *cfg;
2726 * NOTE! The local APIC isn't very good at handling
2727 * multiple interrupts at the same interrupt level.
2728 * As the interrupt level is determined by taking the
2729 * vector number and shifting that right by 4, we
2730 * want to spread these out a bit so that they don't
2731 * all fall in the same interrupt level.
2733 * Also, we've got to be careful not to trash gate
2734 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2736 for_each_active_irq(irq) {
2737 cfg = irq_get_chip_data(irq);
2738 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2740 * Hmm.. We don't have an entry for this,
2741 * so default to an old-fashioned 8259
2742 * interrupt if we can..
2744 if (irq < legacy_pic->nr_legacy_irqs)
2745 legacy_pic->make_irq(irq);
2747 /* Strange. Oh, well.. */
2748 irq_set_chip(irq, &no_irq_chip);
2754 * The local APIC irq-chip implementation:
2757 static void mask_lapic_irq(struct irq_data *data)
2761 v = apic_read(APIC_LVT0);
2762 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2765 static void unmask_lapic_irq(struct irq_data *data)
2769 v = apic_read(APIC_LVT0);
2770 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2773 static void ack_lapic_irq(struct irq_data *data)
2778 static struct irq_chip lapic_chip __read_mostly = {
2779 .name = "local-APIC",
2780 .irq_mask = mask_lapic_irq,
2781 .irq_unmask = unmask_lapic_irq,
2782 .irq_ack = ack_lapic_irq,
2785 static void lapic_register_intr(int irq)
2787 irq_clear_status_flags(irq, IRQ_LEVEL);
2788 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2793 * This looks a bit hackish but it's about the only one way of sending
2794 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2795 * not support the ExtINT mode, unfortunately. We need to send these
2796 * cycles as some i82489DX-based boards have glue logic that keeps the
2797 * 8259A interrupt line asserted until INTA. --macro
2799 static inline void __init unlock_ExtINT_logic(void)
2802 struct IO_APIC_route_entry entry0, entry1;
2803 unsigned char save_control, save_freq_select;
2805 pin = find_isa_irq_pin(8, mp_INT);
2810 apic = find_isa_irq_apic(8, mp_INT);
2816 entry0 = ioapic_read_entry(apic, pin);
2817 clear_IO_APIC_pin(apic, pin);
2819 memset(&entry1, 0, sizeof(entry1));
2821 entry1.dest_mode = 0; /* physical delivery */
2822 entry1.mask = 0; /* unmask IRQ now */
2823 entry1.dest = hard_smp_processor_id();
2824 entry1.delivery_mode = dest_ExtINT;
2825 entry1.polarity = entry0.polarity;
2829 ioapic_write_entry(apic, pin, entry1);
2831 save_control = CMOS_READ(RTC_CONTROL);
2832 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2833 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2835 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2840 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2844 CMOS_WRITE(save_control, RTC_CONTROL);
2845 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2846 clear_IO_APIC_pin(apic, pin);
2848 ioapic_write_entry(apic, pin, entry0);
2851 static int disable_timer_pin_1 __initdata;
2852 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2853 static int __init disable_timer_pin_setup(char *arg)
2855 disable_timer_pin_1 = 1;
2858 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2860 int timer_through_8259 __initdata;
2863 * This code may look a bit paranoid, but it's supposed to cooperate with
2864 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2865 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2866 * fanatically on his truly buggy board.
2868 * FIXME: really need to revamp this for all platforms.
2870 static inline void __init check_timer(void)
2872 struct irq_cfg *cfg = irq_get_chip_data(0);
2873 int node = cpu_to_node(0);
2874 int apic1, pin1, apic2, pin2;
2875 unsigned long flags;
2878 local_irq_save(flags);
2881 * get/set the timer IRQ vector:
2883 legacy_pic->mask(0);
2884 assign_irq_vector(0, cfg, apic->target_cpus());
2887 * As IRQ0 is to be enabled in the 8259A, the virtual
2888 * wire has to be disabled in the local APIC. Also
2889 * timer interrupts need to be acknowledged manually in
2890 * the 8259A for the i82489DX when using the NMI
2891 * watchdog as that APIC treats NMIs as level-triggered.
2892 * The AEOI mode will finish them in the 8259A
2895 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2896 legacy_pic->init(1);
2898 pin1 = find_isa_irq_pin(0, mp_INT);
2899 apic1 = find_isa_irq_apic(0, mp_INT);
2900 pin2 = ioapic_i8259.pin;
2901 apic2 = ioapic_i8259.apic;
2903 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2904 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2905 cfg->vector, apic1, pin1, apic2, pin2);
2908 * Some BIOS writers are clueless and report the ExtINTA
2909 * I/O APIC input from the cascaded 8259A as the timer
2910 * interrupt input. So just in case, if only one pin
2911 * was found above, try it both directly and through the
2915 if (intr_remapping_enabled)
2916 panic("BIOS bug: timer not connected to IO-APIC");
2920 } else if (pin2 == -1) {
2927 * Ok, does IRQ0 through the IOAPIC work?
2930 add_pin_to_irq_node(cfg, node, apic1, pin1);
2931 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2933 /* for edge trigger, setup_ioapic_irq already
2934 * leave it unmasked.
2935 * so only need to unmask if it is level-trigger
2936 * do we really have level trigger timer?
2939 idx = find_irq_entry(apic1, pin1, mp_INT);
2940 if (idx != -1 && irq_trigger(idx))
2943 if (timer_irq_works()) {
2944 if (disable_timer_pin_1 > 0)
2945 clear_IO_APIC_pin(0, pin1);
2948 if (intr_remapping_enabled)
2949 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2950 local_irq_disable();
2951 clear_IO_APIC_pin(apic1, pin1);
2953 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2954 "8254 timer not connected to IO-APIC\n");
2956 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2957 "(IRQ0) through the 8259A ...\n");
2958 apic_printk(APIC_QUIET, KERN_INFO
2959 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2961 * legacy devices should be connected to IO APIC #0
2963 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2964 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2965 legacy_pic->unmask(0);
2966 if (timer_irq_works()) {
2967 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2968 timer_through_8259 = 1;
2972 * Cleanup, just in case ...
2974 local_irq_disable();
2975 legacy_pic->mask(0);
2976 clear_IO_APIC_pin(apic2, pin2);
2977 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2980 apic_printk(APIC_QUIET, KERN_INFO
2981 "...trying to set up timer as Virtual Wire IRQ...\n");
2983 lapic_register_intr(0);
2984 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2985 legacy_pic->unmask(0);
2987 if (timer_irq_works()) {
2988 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2991 local_irq_disable();
2992 legacy_pic->mask(0);
2993 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2994 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2996 apic_printk(APIC_QUIET, KERN_INFO
2997 "...trying to set up timer as ExtINT IRQ...\n");
2999 legacy_pic->init(0);
3000 legacy_pic->make_irq(0);
3001 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3003 unlock_ExtINT_logic();
3005 if (timer_irq_works()) {
3006 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3009 local_irq_disable();
3010 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3011 if (x2apic_preenabled)
3012 apic_printk(APIC_QUIET, KERN_INFO
3013 "Perhaps problem with the pre-enabled x2apic mode\n"
3014 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
3015 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3016 "report. Then try booting with the 'noapic' option.\n");
3018 local_irq_restore(flags);
3022 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3023 * to devices. However there may be an I/O APIC pin available for
3024 * this interrupt regardless. The pin may be left unconnected, but
3025 * typically it will be reused as an ExtINT cascade interrupt for
3026 * the master 8259A. In the MPS case such a pin will normally be
3027 * reported as an ExtINT interrupt in the MP table. With ACPI
3028 * there is no provision for ExtINT interrupts, and in the absence
3029 * of an override it would be treated as an ordinary ISA I/O APIC
3030 * interrupt, that is edge-triggered and unmasked by default. We
3031 * used to do this, but it caused problems on some systems because
3032 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3033 * the same ExtINT cascade interrupt to drive the local APIC of the
3034 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3035 * the I/O APIC in all cases now. No actual device should request
3036 * it anyway. --macro
3038 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3040 void __init setup_IO_APIC(void)
3044 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3046 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3048 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3050 * Set up IO-APIC IRQ routing.
3052 x86_init.mpparse.setup_ioapic_ids();
3055 setup_IO_APIC_irqs();
3056 init_IO_APIC_traps();
3057 if (legacy_pic->nr_legacy_irqs)
3062 * Called after all the initialization is done. If we didn't find any
3063 * APIC bugs then we can allow the modify fast path
3066 static int __init io_apic_bug_finalize(void)
3068 if (sis_apic_bug == -1)
3073 late_initcall(io_apic_bug_finalize);
3075 static void resume_ioapic_id(int ioapic_idx)
3077 unsigned long flags;
3078 union IO_APIC_reg_00 reg_00;
3080 raw_spin_lock_irqsave(&ioapic_lock, flags);
3081 reg_00.raw = io_apic_read(ioapic_idx, 0);
3082 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
3083 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
3084 io_apic_write(ioapic_idx, 0, reg_00.raw);
3086 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3089 static void ioapic_resume(void)
3093 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
3094 resume_ioapic_id(ioapic_idx);
3096 restore_ioapic_entries();
3099 static struct syscore_ops ioapic_syscore_ops = {
3100 .suspend = save_ioapic_entries,
3101 .resume = ioapic_resume,
3104 static int __init ioapic_init_ops(void)
3106 register_syscore_ops(&ioapic_syscore_ops);
3111 device_initcall(ioapic_init_ops);
3114 * Dynamic irq allocate and deallocation
3116 unsigned int create_irq_nr(unsigned int from, int node)
3118 struct irq_cfg *cfg;
3119 unsigned long flags;
3120 unsigned int ret = 0;
3123 if (from < nr_irqs_gsi)
3126 irq = alloc_irq_from(from, node);
3129 cfg = alloc_irq_cfg(irq, node);
3131 free_irq_at(irq, NULL);
3135 raw_spin_lock_irqsave(&vector_lock, flags);
3136 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3138 raw_spin_unlock_irqrestore(&vector_lock, flags);
3141 irq_set_chip_data(irq, cfg);
3142 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3144 free_irq_at(irq, cfg);
3149 int create_irq(void)
3151 int node = cpu_to_node(0);
3152 unsigned int irq_want;
3155 irq_want = nr_irqs_gsi;
3156 irq = create_irq_nr(irq_want, node);
3164 void destroy_irq(unsigned int irq)
3166 struct irq_cfg *cfg = irq_get_chip_data(irq);
3167 unsigned long flags;
3169 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3171 if (irq_remapped(cfg))
3173 raw_spin_lock_irqsave(&vector_lock, flags);
3174 __clear_irq_vector(irq, cfg);
3175 raw_spin_unlock_irqrestore(&vector_lock, flags);
3176 free_irq_at(irq, cfg);
3180 * MSI message composition
3182 #ifdef CONFIG_PCI_MSI
3183 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3184 struct msi_msg *msg, u8 hpet_id)
3186 struct irq_cfg *cfg;
3194 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3198 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3200 if (irq_remapped(cfg)) {
3205 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3206 BUG_ON(ir_index == -1);
3208 prepare_irte(&irte, cfg->vector, dest);
3210 /* Set source-id of interrupt request */
3212 set_msi_sid(&irte, pdev);
3214 set_hpet_sid(&irte, hpet_id);
3216 modify_irte(irq, &irte);
3218 msg->address_hi = MSI_ADDR_BASE_HI;
3219 msg->data = sub_handle;
3220 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3222 MSI_ADDR_IR_INDEX1(ir_index) |
3223 MSI_ADDR_IR_INDEX2(ir_index);
3225 if (x2apic_enabled())
3226 msg->address_hi = MSI_ADDR_BASE_HI |
3227 MSI_ADDR_EXT_DEST_ID(dest);
3229 msg->address_hi = MSI_ADDR_BASE_HI;
3233 ((apic->irq_dest_mode == 0) ?
3234 MSI_ADDR_DEST_MODE_PHYSICAL:
3235 MSI_ADDR_DEST_MODE_LOGICAL) |
3236 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3237 MSI_ADDR_REDIRECTION_CPU:
3238 MSI_ADDR_REDIRECTION_LOWPRI) |
3239 MSI_ADDR_DEST_ID(dest);
3242 MSI_DATA_TRIGGER_EDGE |
3243 MSI_DATA_LEVEL_ASSERT |
3244 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3245 MSI_DATA_DELIVERY_FIXED:
3246 MSI_DATA_DELIVERY_LOWPRI) |
3247 MSI_DATA_VECTOR(cfg->vector);
3254 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3256 struct irq_cfg *cfg = data->chip_data;
3260 if (__ioapic_set_affinity(data, mask, &dest))
3263 __get_cached_msi_msg(data->msi_desc, &msg);
3265 msg.data &= ~MSI_DATA_VECTOR_MASK;
3266 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3267 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3268 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3270 __write_msi_msg(data->msi_desc, &msg);
3274 #endif /* CONFIG_SMP */
3277 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3278 * which implement the MSI or MSI-X Capability Structure.
3280 static struct irq_chip msi_chip = {
3282 .irq_unmask = unmask_msi_irq,
3283 .irq_mask = mask_msi_irq,
3284 .irq_ack = ack_apic_edge,
3286 .irq_set_affinity = msi_set_affinity,
3288 .irq_retrigger = ioapic_retrigger_irq,
3292 * Map the PCI dev to the corresponding remapping hardware unit
3293 * and allocate 'nvec' consecutive interrupt-remapping table entries
3296 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3298 struct intel_iommu *iommu;
3301 iommu = map_dev_to_ir(dev);
3304 "Unable to map PCI %s to iommu\n", pci_name(dev));
3308 index = alloc_irte(iommu, irq, nvec);
3311 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3318 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3320 struct irq_chip *chip = &msi_chip;
3324 ret = msi_compose_msg(dev, irq, &msg, -1);
3328 irq_set_msi_desc(irq, msidesc);
3329 write_msi_msg(irq, &msg);
3331 if (irq_remapped(irq_get_chip_data(irq))) {
3332 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3333 irq_remap_modify_chip_defaults(chip);
3336 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3338 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3343 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3345 int node, ret, sub_handle, index = 0;
3346 unsigned int irq, irq_want;
3347 struct msi_desc *msidesc;
3348 struct intel_iommu *iommu = NULL;
3350 /* x86 doesn't support multiple MSI yet */
3351 if (type == PCI_CAP_ID_MSI && nvec > 1)
3354 node = dev_to_node(&dev->dev);
3355 irq_want = nr_irqs_gsi;
3357 list_for_each_entry(msidesc, &dev->msi_list, list) {
3358 irq = create_irq_nr(irq_want, node);
3362 if (!intr_remapping_enabled)
3367 * allocate the consecutive block of IRTE's
3370 index = msi_alloc_irte(dev, irq, nvec);
3376 iommu = map_dev_to_ir(dev);
3382 * setup the mapping between the irq and the IRTE
3383 * base index, the sub_handle pointing to the
3384 * appropriate interrupt remap table entry.
3386 set_irte_irq(irq, iommu, index, sub_handle);
3389 ret = setup_msi_irq(dev, msidesc, irq);
3401 void native_teardown_msi_irq(unsigned int irq)
3406 #ifdef CONFIG_DMAR_TABLE
3409 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3412 struct irq_cfg *cfg = data->chip_data;
3413 unsigned int dest, irq = data->irq;
3416 if (__ioapic_set_affinity(data, mask, &dest))
3419 dmar_msi_read(irq, &msg);
3421 msg.data &= ~MSI_DATA_VECTOR_MASK;
3422 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3423 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3424 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3425 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3427 dmar_msi_write(irq, &msg);
3432 #endif /* CONFIG_SMP */
3434 static struct irq_chip dmar_msi_type = {
3436 .irq_unmask = dmar_msi_unmask,
3437 .irq_mask = dmar_msi_mask,
3438 .irq_ack = ack_apic_edge,
3440 .irq_set_affinity = dmar_msi_set_affinity,
3442 .irq_retrigger = ioapic_retrigger_irq,
3445 int arch_setup_dmar_msi(unsigned int irq)
3450 ret = msi_compose_msg(NULL, irq, &msg, -1);
3453 dmar_msi_write(irq, &msg);
3454 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3460 #ifdef CONFIG_HPET_TIMER
3463 static int hpet_msi_set_affinity(struct irq_data *data,
3464 const struct cpumask *mask, bool force)
3466 struct irq_cfg *cfg = data->chip_data;
3470 if (__ioapic_set_affinity(data, mask, &dest))
3473 hpet_msi_read(data->handler_data, &msg);
3475 msg.data &= ~MSI_DATA_VECTOR_MASK;
3476 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3477 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3478 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3480 hpet_msi_write(data->handler_data, &msg);
3485 #endif /* CONFIG_SMP */
3487 static struct irq_chip hpet_msi_type = {
3489 .irq_unmask = hpet_msi_unmask,
3490 .irq_mask = hpet_msi_mask,
3491 .irq_ack = ack_apic_edge,
3493 .irq_set_affinity = hpet_msi_set_affinity,
3495 .irq_retrigger = ioapic_retrigger_irq,
3498 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3500 struct irq_chip *chip = &hpet_msi_type;
3504 if (intr_remapping_enabled) {
3505 struct intel_iommu *iommu = map_hpet_to_ir(id);
3511 index = alloc_irte(iommu, irq, 1);
3516 ret = msi_compose_msg(NULL, irq, &msg, id);
3520 hpet_msi_write(irq_get_handler_data(irq), &msg);
3521 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3522 if (irq_remapped(irq_get_chip_data(irq)))
3523 irq_remap_modify_chip_defaults(chip);
3525 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3530 #endif /* CONFIG_PCI_MSI */
3532 * Hypertransport interrupt support
3534 #ifdef CONFIG_HT_IRQ
3538 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3540 struct ht_irq_msg msg;
3541 fetch_ht_irq_msg(irq, &msg);
3543 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3544 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3546 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3547 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3549 write_ht_irq_msg(irq, &msg);
3553 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3555 struct irq_cfg *cfg = data->chip_data;
3558 if (__ioapic_set_affinity(data, mask, &dest))
3561 target_ht_irq(data->irq, dest, cfg->vector);
3567 static struct irq_chip ht_irq_chip = {
3569 .irq_mask = mask_ht_irq,
3570 .irq_unmask = unmask_ht_irq,
3571 .irq_ack = ack_apic_edge,
3573 .irq_set_affinity = ht_set_affinity,
3575 .irq_retrigger = ioapic_retrigger_irq,
3578 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3580 struct irq_cfg *cfg;
3587 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3589 struct ht_irq_msg msg;
3592 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3593 apic->target_cpus());
3595 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3599 HT_IRQ_LOW_DEST_ID(dest) |
3600 HT_IRQ_LOW_VECTOR(cfg->vector) |
3601 ((apic->irq_dest_mode == 0) ?
3602 HT_IRQ_LOW_DM_PHYSICAL :
3603 HT_IRQ_LOW_DM_LOGICAL) |
3604 HT_IRQ_LOW_RQEOI_EDGE |
3605 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3606 HT_IRQ_LOW_MT_FIXED :
3607 HT_IRQ_LOW_MT_ARBITRATED) |
3608 HT_IRQ_LOW_IRQ_MASKED;
3610 write_ht_irq_msg(irq, &msg);
3612 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3613 handle_edge_irq, "edge");
3615 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3619 #endif /* CONFIG_HT_IRQ */
3622 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3624 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3629 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3631 setup_ioapic_irq(irq, cfg, attr);
3635 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3636 struct io_apic_irq_attr *attr)
3638 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3641 /* Avoid redundant programming */
3642 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3643 pr_debug("Pin %d-%d already programmed\n",
3644 mpc_ioapic_id(ioapic_idx), pin);
3647 ret = io_apic_setup_irq_pin(irq, node, attr);
3649 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3653 static int __init io_apic_get_redir_entries(int ioapic)
3655 union IO_APIC_reg_01 reg_01;
3656 unsigned long flags;
3658 raw_spin_lock_irqsave(&ioapic_lock, flags);
3659 reg_01.raw = io_apic_read(ioapic, 1);
3660 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3662 /* The register returns the maximum index redir index
3663 * supported, which is one less than the total number of redir
3666 return reg_01.bits.entries + 1;
3669 static void __init probe_nr_irqs_gsi(void)
3673 nr = gsi_top + NR_IRQS_LEGACY;
3674 if (nr > nr_irqs_gsi)
3677 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3680 int get_nr_irqs_gsi(void)
3685 int __init arch_probe_nr_irqs(void)
3689 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3690 nr_irqs = NR_VECTORS * nr_cpu_ids;
3692 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3693 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3695 * for MSI and HT dyn irq
3697 nr += nr_irqs_gsi * 16;
3702 return NR_IRQS_LEGACY;
3705 int io_apic_set_pci_routing(struct device *dev, int irq,
3706 struct io_apic_irq_attr *irq_attr)
3710 if (!IO_APIC_IRQ(irq)) {
3711 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3716 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3718 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3721 #ifdef CONFIG_X86_32
3722 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3724 union IO_APIC_reg_00 reg_00;
3725 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3727 unsigned long flags;
3731 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3732 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3733 * supports up to 16 on one shared APIC bus.
3735 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3736 * advantage of new APIC bus architecture.
3739 if (physids_empty(apic_id_map))
3740 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3742 raw_spin_lock_irqsave(&ioapic_lock, flags);
3743 reg_00.raw = io_apic_read(ioapic, 0);
3744 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3746 if (apic_id >= get_physical_broadcast()) {
3747 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3748 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3749 apic_id = reg_00.bits.ID;
3753 * Every APIC in a system must have a unique ID or we get lots of nice
3754 * 'stuck on smp_invalidate_needed IPI wait' messages.
3756 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3758 for (i = 0; i < get_physical_broadcast(); i++) {
3759 if (!apic->check_apicid_used(&apic_id_map, i))
3763 if (i == get_physical_broadcast())
3764 panic("Max apic_id exceeded!\n");
3766 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3767 "trying %d\n", ioapic, apic_id, i);
3772 apic->apicid_to_cpu_present(apic_id, &tmp);
3773 physids_or(apic_id_map, apic_id_map, tmp);
3775 if (reg_00.bits.ID != apic_id) {
3776 reg_00.bits.ID = apic_id;
3778 raw_spin_lock_irqsave(&ioapic_lock, flags);
3779 io_apic_write(ioapic, 0, reg_00.raw);
3780 reg_00.raw = io_apic_read(ioapic, 0);
3781 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3784 if (reg_00.bits.ID != apic_id) {
3785 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3790 apic_printk(APIC_VERBOSE, KERN_INFO
3791 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3796 static u8 __init io_apic_unique_id(u8 id)
3798 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3799 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3800 return io_apic_get_unique_id(nr_ioapics, id);
3805 static u8 __init io_apic_unique_id(u8 id)
3808 DECLARE_BITMAP(used, 256);
3810 bitmap_zero(used, 256);
3811 for (i = 0; i < nr_ioapics; i++) {
3812 __set_bit(mpc_ioapic_id(i), used);
3814 if (!test_bit(id, used))
3816 return find_first_zero_bit(used, 256);
3820 static int __init io_apic_get_version(int ioapic)
3822 union IO_APIC_reg_01 reg_01;
3823 unsigned long flags;
3825 raw_spin_lock_irqsave(&ioapic_lock, flags);
3826 reg_01.raw = io_apic_read(ioapic, 1);
3827 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3829 return reg_01.bits.version;
3832 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3834 int ioapic, pin, idx;
3836 if (skip_ioapic_setup)
3839 ioapic = mp_find_ioapic(gsi);
3843 pin = mp_find_ioapic_pin(ioapic, gsi);
3847 idx = find_irq_entry(ioapic, pin, mp_INT);
3851 *trigger = irq_trigger(idx);
3852 *polarity = irq_polarity(idx);
3857 * This function currently is only a helper for the i386 smp boot process where
3858 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3859 * so mask in all cases should simply be apic->target_cpus()
3862 void __init setup_ioapic_dest(void)
3864 int pin, ioapic, irq, irq_entry;
3865 const struct cpumask *mask;
3866 struct irq_data *idata;
3868 if (skip_ioapic_setup == 1)
3871 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3872 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3873 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3874 if (irq_entry == -1)
3876 irq = pin_2_irq(irq_entry, ioapic, pin);
3878 if ((ioapic > 0) && (irq > 16))
3881 idata = irq_get_irq_data(irq);
3884 * Honour affinities which have been set in early boot
3886 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3887 mask = idata->affinity;
3889 mask = apic->target_cpus();
3891 if (intr_remapping_enabled)
3892 ir_ioapic_set_affinity(idata, mask, false);
3894 ioapic_set_affinity(idata, mask, false);
3900 #define IOAPIC_RESOURCE_NAME_SIZE 11
3902 static struct resource *ioapic_resources;
3904 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3907 struct resource *res;
3911 if (nr_ioapics <= 0)
3914 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3917 mem = alloc_bootmem(n);
3920 mem += sizeof(struct resource) * nr_ioapics;
3922 for (i = 0; i < nr_ioapics; i++) {
3924 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3925 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3926 mem += IOAPIC_RESOURCE_NAME_SIZE;
3929 ioapic_resources = res;
3934 void __init ioapic_and_gsi_init(void)
3939 static void __init __ioapic_init_mappings(void)
3941 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3942 struct resource *ioapic_res;
3945 ioapic_res = ioapic_setup_resources(nr_ioapics);
3946 for (i = 0; i < nr_ioapics; i++) {
3947 if (smp_found_config) {
3948 ioapic_phys = mpc_ioapic_addr(i);
3949 #ifdef CONFIG_X86_32
3952 "WARNING: bogus zero IO-APIC "
3953 "address found in MPTABLE, "
3954 "disabling IO/APIC support!\n");
3955 smp_found_config = 0;
3956 skip_ioapic_setup = 1;
3957 goto fake_ioapic_page;
3961 #ifdef CONFIG_X86_32
3964 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3965 ioapic_phys = __pa(ioapic_phys);
3967 set_fixmap_nocache(idx, ioapic_phys);
3968 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3969 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3973 ioapic_res->start = ioapic_phys;
3974 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3978 probe_nr_irqs_gsi();
3981 void __init ioapic_insert_resources(void)
3984 struct resource *r = ioapic_resources;
3989 "IO APIC resources couldn't be allocated.\n");
3993 for (i = 0; i < nr_ioapics; i++) {
3994 insert_resource(&iomem_resource, r);
3999 int mp_find_ioapic(u32 gsi)
4003 if (nr_ioapics == 0)
4006 /* Find the IOAPIC that manages this GSI. */
4007 for (i = 0; i < nr_ioapics; i++) {
4008 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
4009 if ((gsi >= gsi_cfg->gsi_base)
4010 && (gsi <= gsi_cfg->gsi_end))
4014 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4018 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4020 struct mp_ioapic_gsi *gsi_cfg;
4022 if (WARN_ON(ioapic == -1))
4025 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
4026 if (WARN_ON(gsi > gsi_cfg->gsi_end))
4029 return gsi - gsi_cfg->gsi_base;
4032 static __init int bad_ioapic(unsigned long address)
4034 if (nr_ioapics >= MAX_IO_APICS) {
4035 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
4036 MAX_IO_APICS, nr_ioapics);
4040 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
4046 static __init int bad_ioapic_register(int idx)
4048 union IO_APIC_reg_00 reg_00;
4049 union IO_APIC_reg_01 reg_01;
4050 union IO_APIC_reg_02 reg_02;
4052 reg_00.raw = io_apic_read(idx, 0);
4053 reg_01.raw = io_apic_read(idx, 1);
4054 reg_02.raw = io_apic_read(idx, 2);
4056 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
4057 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
4058 mpc_ioapic_addr(idx));
4065 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4069 struct mp_ioapic_gsi *gsi_cfg;
4071 if (bad_ioapic(address))
4076 ioapics[idx].mp_config.type = MP_IOAPIC;
4077 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
4078 ioapics[idx].mp_config.apicaddr = address;
4080 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4082 if (bad_ioapic_register(idx)) {
4083 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
4087 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
4088 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
4091 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4092 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4094 entries = io_apic_get_redir_entries(idx);
4095 gsi_cfg = mp_ioapic_gsi_routing(idx);
4096 gsi_cfg->gsi_base = gsi_base;
4097 gsi_cfg->gsi_end = gsi_base + entries - 1;
4100 * The number of IO-APIC IRQ registers (== #pins):
4102 ioapics[idx].nr_registers = entries;
4104 if (gsi_cfg->gsi_end >= gsi_top)
4105 gsi_top = gsi_cfg->gsi_end + 1;
4107 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
4108 idx, mpc_ioapic_id(idx),
4109 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
4110 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
4115 /* Enable IOAPIC early just for system timer */
4116 void __init pre_init_apic_IRQ0(void)
4118 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4120 printk(KERN_INFO "Early APIC setup for system timer0\n");
4122 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4123 &phys_cpu_present_map);
4127 io_apic_setup_irq_pin(0, 0, &attr);
4128 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,