2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
71 static void __init __ioapic_init_mappings(void);
73 static unsigned int __io_apic_read (unsigned int apic, unsigned int reg);
74 static void __io_apic_write (unsigned int apic, unsigned int reg, unsigned int val);
75 static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
77 static struct io_apic_ops io_apic_ops = {
78 .init = __ioapic_init_mappings,
79 .read = __io_apic_read,
80 .write = __io_apic_write,
81 .modify = __io_apic_modify,
84 void __init set_io_apic_ops(const struct io_apic_ops *ops)
89 #ifdef CONFIG_IRQ_REMAP
90 static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
91 static inline bool irq_remapped(struct irq_cfg *cfg)
93 return cfg->irq_2_iommu.iommu != NULL;
96 static inline bool irq_remapped(struct irq_cfg *cfg)
100 static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
106 * Is the SiS APIC rmw bug present ?
107 * -1 = don't know, 0 = no, 1 = yes
109 int sis_apic_bug = -1;
111 static DEFINE_RAW_SPINLOCK(ioapic_lock);
112 static DEFINE_RAW_SPINLOCK(vector_lock);
114 static struct ioapic {
116 * # of IRQ routing registers
120 * Saved state during suspend/resume, or while enabling intr-remap.
122 struct IO_APIC_route_entry *saved_registers;
123 /* I/O APIC config */
124 struct mpc_ioapic mp_config;
125 /* IO APIC gsi routing info */
126 struct mp_ioapic_gsi gsi_config;
127 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
128 } ioapics[MAX_IO_APICS];
130 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
132 int mpc_ioapic_id(int ioapic_idx)
134 return ioapics[ioapic_idx].mp_config.apicid;
137 unsigned int mpc_ioapic_addr(int ioapic_idx)
139 return ioapics[ioapic_idx].mp_config.apicaddr;
142 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
144 return &ioapics[ioapic_idx].gsi_config;
149 /* The one past the highest gsi number used */
152 /* MP IRQ source entries */
153 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
155 /* # of MP IRQ source entries */
159 static int nr_irqs_gsi = NR_IRQS_LEGACY;
161 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
162 int mp_bus_id_to_type[MAX_MP_BUSSES];
165 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
167 int skip_ioapic_setup;
170 * disable_ioapic_support() - disables ioapic support at runtime
172 void disable_ioapic_support(void)
176 noioapicreroute = -1;
178 skip_ioapic_setup = 1;
181 static int __init parse_noapic(char *str)
183 /* disable IO-APIC */
184 disable_ioapic_support();
187 early_param("noapic", parse_noapic);
189 static int io_apic_setup_irq_pin(unsigned int irq, int node,
190 struct io_apic_irq_attr *attr);
192 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
193 void mp_save_irq(struct mpc_intsrc *m)
197 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
198 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
199 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
200 m->srcbusirq, m->dstapic, m->dstirq);
202 for (i = 0; i < mp_irq_entries; i++) {
203 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
207 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
208 if (++mp_irq_entries == MAX_IRQ_SOURCES)
209 panic("Max # of irq sources exceeded!!\n");
212 struct irq_pin_list {
214 struct irq_pin_list *next;
217 static struct irq_pin_list *alloc_irq_pin_list(int node)
219 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
223 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
224 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
226 int __init arch_early_irq_init(void)
231 if (!legacy_pic->nr_legacy_irqs)
234 for (i = 0; i < nr_ioapics; i++) {
235 ioapics[i].saved_registers =
236 kzalloc(sizeof(struct IO_APIC_route_entry) *
237 ioapics[i].nr_registers, GFP_KERNEL);
238 if (!ioapics[i].saved_registers)
239 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
243 count = ARRAY_SIZE(irq_cfgx);
244 node = cpu_to_node(0);
246 /* Make sure the legacy interrupts are marked in the bitmap */
247 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
249 for (i = 0; i < count; i++) {
250 irq_set_chip_data(i, &cfg[i]);
251 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
252 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
254 * For legacy IRQ's, start with assigning irq0 to irq15 to
255 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
257 if (i < legacy_pic->nr_legacy_irqs) {
258 cfg[i].vector = IRQ0_VECTOR + i;
259 cpumask_set_cpu(0, cfg[i].domain);
266 static struct irq_cfg *irq_cfg(unsigned int irq)
268 return irq_get_chip_data(irq);
271 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
275 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
278 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
280 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
284 free_cpumask_var(cfg->domain);
290 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
294 irq_set_chip_data(at, NULL);
295 free_cpumask_var(cfg->domain);
296 free_cpumask_var(cfg->old_domain);
300 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
302 int res = irq_alloc_desc_at(at, node);
308 cfg = irq_get_chip_data(at);
313 cfg = alloc_irq_cfg(at, node);
315 irq_set_chip_data(at, cfg);
321 static int alloc_irq_from(unsigned int from, int node)
323 return irq_alloc_desc_from(from, node);
326 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
328 free_irq_cfg(at, cfg);
332 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
334 return io_apic_ops.read(apic, reg);
337 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
339 io_apic_ops.write(apic, reg, value);
342 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
344 io_apic_ops.modify(apic, reg, value);
350 unsigned int unused[3];
352 unsigned int unused2[11];
356 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
358 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
359 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
362 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
364 struct io_apic __iomem *io_apic = io_apic_base(apic);
365 writel(vector, &io_apic->eoi);
368 static unsigned int __io_apic_read(unsigned int apic, unsigned int reg)
370 struct io_apic __iomem *io_apic = io_apic_base(apic);
371 writel(reg, &io_apic->index);
372 return readl(&io_apic->data);
375 static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
377 struct io_apic __iomem *io_apic = io_apic_base(apic);
379 writel(reg, &io_apic->index);
380 writel(value, &io_apic->data);
384 * Re-write a value: to be used for read-modify-write
385 * cycles where the read already set up the index register.
387 * Older SiS APIC requires we rewrite the index register
389 static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
391 struct io_apic __iomem *io_apic = io_apic_base(apic);
394 writel(reg, &io_apic->index);
395 writel(value, &io_apic->data);
398 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
400 struct irq_pin_list *entry;
403 raw_spin_lock_irqsave(&ioapic_lock, flags);
404 for_each_irq_pin(entry, cfg->irq_2_pin) {
409 reg = io_apic_read(entry->apic, 0x10 + pin*2);
410 /* Is the remote IRR bit set? */
411 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
412 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
416 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
422 struct { u32 w1, w2; };
423 struct IO_APIC_route_entry entry;
426 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
428 union entry_union eu;
430 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
431 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
436 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
438 union entry_union eu;
441 raw_spin_lock_irqsave(&ioapic_lock, flags);
442 eu.entry = __ioapic_read_entry(apic, pin);
443 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
449 * When we write a new IO APIC routing entry, we need to write the high
450 * word first! If the mask bit in the low word is clear, we will enable
451 * the interrupt, and we need to make sure the entry is fully populated
452 * before that happens.
454 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
456 union entry_union eu = {{0, 0}};
459 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
460 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
463 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
467 raw_spin_lock_irqsave(&ioapic_lock, flags);
468 __ioapic_write_entry(apic, pin, e);
469 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
473 * When we mask an IO APIC routing entry, we need to write the low
474 * word first, in order to set the mask bit before we change the
477 static void ioapic_mask_entry(int apic, int pin)
480 union entry_union eu = { .entry.mask = 1 };
482 raw_spin_lock_irqsave(&ioapic_lock, flags);
483 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
484 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
485 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
489 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
490 * shared ISA-space IRQs, so we have to support them. We are super
491 * fast in the common case, and fast for shared ISA-space IRQs.
493 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
495 struct irq_pin_list **last, *entry;
497 /* don't allow duplicates */
498 last = &cfg->irq_2_pin;
499 for_each_irq_pin(entry, cfg->irq_2_pin) {
500 if (entry->apic == apic && entry->pin == pin)
505 entry = alloc_irq_pin_list(node);
507 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
518 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
520 if (__add_pin_to_irq_node(cfg, node, apic, pin))
521 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
525 * Reroute an IRQ to a different pin.
527 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
528 int oldapic, int oldpin,
529 int newapic, int newpin)
531 struct irq_pin_list *entry;
533 for_each_irq_pin(entry, cfg->irq_2_pin) {
534 if (entry->apic == oldapic && entry->pin == oldpin) {
535 entry->apic = newapic;
537 /* every one is different, right? */
542 /* old apic/pin didn't exist, so just add new ones */
543 add_pin_to_irq_node(cfg, node, newapic, newpin);
546 static void __io_apic_modify_irq(struct irq_pin_list *entry,
547 int mask_and, int mask_or,
548 void (*final)(struct irq_pin_list *entry))
550 unsigned int reg, pin;
553 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
556 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
561 static void io_apic_modify_irq(struct irq_cfg *cfg,
562 int mask_and, int mask_or,
563 void (*final)(struct irq_pin_list *entry))
565 struct irq_pin_list *entry;
567 for_each_irq_pin(entry, cfg->irq_2_pin)
568 __io_apic_modify_irq(entry, mask_and, mask_or, final);
571 static void io_apic_sync(struct irq_pin_list *entry)
574 * Synchronize the IO-APIC and the CPU by doing
575 * a dummy read from the IO-APIC
577 struct io_apic __iomem *io_apic;
579 io_apic = io_apic_base(entry->apic);
580 readl(&io_apic->data);
583 static void mask_ioapic(struct irq_cfg *cfg)
587 raw_spin_lock_irqsave(&ioapic_lock, flags);
588 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
589 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
592 static void mask_ioapic_irq(struct irq_data *data)
594 mask_ioapic(data->chip_data);
597 static void __unmask_ioapic(struct irq_cfg *cfg)
599 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
602 static void unmask_ioapic(struct irq_cfg *cfg)
606 raw_spin_lock_irqsave(&ioapic_lock, flags);
607 __unmask_ioapic(cfg);
608 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
611 static void unmask_ioapic_irq(struct irq_data *data)
613 unmask_ioapic(data->chip_data);
617 * IO-APIC versions below 0x20 don't support EOI register.
618 * For the record, here is the information about various versions:
620 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
621 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
624 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
625 * version as 0x2. This is an error with documentation and these ICH chips
626 * use io-apic's of version 0x20.
628 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
629 * Otherwise, we simulate the EOI message manually by changing the trigger
630 * mode to edge and then back to level, with RTE being masked during this.
632 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
634 if (mpc_ioapic_ver(apic) >= 0x20) {
636 * Intr-remapping uses pin number as the virtual vector
637 * in the RTE. Actual vector is programmed in
638 * intr-remapping table entry. Hence for the io-apic
639 * EOI we use the pin number.
641 if (cfg && irq_remapped(cfg))
642 io_apic_eoi(apic, pin);
644 io_apic_eoi(apic, vector);
646 struct IO_APIC_route_entry entry, entry1;
648 entry = entry1 = __ioapic_read_entry(apic, pin);
651 * Mask the entry and change the trigger mode to edge.
654 entry1.trigger = IOAPIC_EDGE;
656 __ioapic_write_entry(apic, pin, entry1);
659 * Restore the previous level triggered entry.
661 __ioapic_write_entry(apic, pin, entry);
665 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
667 struct irq_pin_list *entry;
670 raw_spin_lock_irqsave(&ioapic_lock, flags);
671 for_each_irq_pin(entry, cfg->irq_2_pin)
672 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
673 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
676 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
678 struct IO_APIC_route_entry entry;
680 /* Check delivery_mode to be sure we're not clearing an SMI pin */
681 entry = ioapic_read_entry(apic, pin);
682 if (entry.delivery_mode == dest_SMI)
686 * Make sure the entry is masked and re-read the contents to check
687 * if it is a level triggered pin and if the remote-IRR is set.
691 ioapic_write_entry(apic, pin, entry);
692 entry = ioapic_read_entry(apic, pin);
699 * Make sure the trigger mode is set to level. Explicit EOI
700 * doesn't clear the remote-IRR if the trigger mode is not
703 if (!entry.trigger) {
704 entry.trigger = IOAPIC_LEVEL;
705 ioapic_write_entry(apic, pin, entry);
708 raw_spin_lock_irqsave(&ioapic_lock, flags);
709 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
710 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
714 * Clear the rest of the bits in the IO-APIC RTE except for the mask
717 ioapic_mask_entry(apic, pin);
718 entry = ioapic_read_entry(apic, pin);
720 printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
721 mpc_ioapic_id(apic), pin);
724 static void clear_IO_APIC (void)
728 for (apic = 0; apic < nr_ioapics; apic++)
729 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
730 clear_IO_APIC_pin(apic, pin);
735 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
736 * specific CPU-side IRQs.
740 static int pirq_entries[MAX_PIRQS] = {
741 [0 ... MAX_PIRQS - 1] = -1
744 static int __init ioapic_pirq_setup(char *str)
747 int ints[MAX_PIRQS+1];
749 get_options(str, ARRAY_SIZE(ints), ints);
751 apic_printk(APIC_VERBOSE, KERN_INFO
752 "PIRQ redirection, working around broken MP-BIOS.\n");
754 if (ints[0] < MAX_PIRQS)
757 for (i = 0; i < max; i++) {
758 apic_printk(APIC_VERBOSE, KERN_DEBUG
759 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
761 * PIRQs are mapped upside down, usually.
763 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
768 __setup("pirq=", ioapic_pirq_setup);
769 #endif /* CONFIG_X86_32 */
772 * Saves all the IO-APIC RTE's
774 int save_ioapic_entries(void)
779 for (apic = 0; apic < nr_ioapics; apic++) {
780 if (!ioapics[apic].saved_registers) {
785 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
786 ioapics[apic].saved_registers[pin] =
787 ioapic_read_entry(apic, pin);
794 * Mask all IO APIC entries.
796 void mask_ioapic_entries(void)
800 for (apic = 0; apic < nr_ioapics; apic++) {
801 if (!ioapics[apic].saved_registers)
804 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
805 struct IO_APIC_route_entry entry;
807 entry = ioapics[apic].saved_registers[pin];
810 ioapic_write_entry(apic, pin, entry);
817 * Restore IO APIC entries which was saved in the ioapic structure.
819 int restore_ioapic_entries(void)
823 for (apic = 0; apic < nr_ioapics; apic++) {
824 if (!ioapics[apic].saved_registers)
827 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
828 ioapic_write_entry(apic, pin,
829 ioapics[apic].saved_registers[pin]);
835 * Find the IRQ entry number of a certain pin.
837 static int find_irq_entry(int ioapic_idx, int pin, int type)
841 for (i = 0; i < mp_irq_entries; i++)
842 if (mp_irqs[i].irqtype == type &&
843 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
844 mp_irqs[i].dstapic == MP_APIC_ALL) &&
845 mp_irqs[i].dstirq == pin)
852 * Find the pin to which IRQ[irq] (ISA) is connected
854 static int __init find_isa_irq_pin(int irq, int type)
858 for (i = 0; i < mp_irq_entries; i++) {
859 int lbus = mp_irqs[i].srcbus;
861 if (test_bit(lbus, mp_bus_not_pci) &&
862 (mp_irqs[i].irqtype == type) &&
863 (mp_irqs[i].srcbusirq == irq))
865 return mp_irqs[i].dstirq;
870 static int __init find_isa_irq_apic(int irq, int type)
874 for (i = 0; i < mp_irq_entries; i++) {
875 int lbus = mp_irqs[i].srcbus;
877 if (test_bit(lbus, mp_bus_not_pci) &&
878 (mp_irqs[i].irqtype == type) &&
879 (mp_irqs[i].srcbusirq == irq))
883 if (i < mp_irq_entries) {
886 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
887 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
894 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
896 * EISA Edge/Level control register, ELCR
898 static int EISA_ELCR(unsigned int irq)
900 if (irq < legacy_pic->nr_legacy_irqs) {
901 unsigned int port = 0x4d0 + (irq >> 3);
902 return (inb(port) >> (irq & 7)) & 1;
904 apic_printk(APIC_VERBOSE, KERN_INFO
905 "Broken MPtable reports ISA irq %d\n", irq);
911 /* ISA interrupts are always polarity zero edge triggered,
912 * when listed as conforming in the MP table. */
914 #define default_ISA_trigger(idx) (0)
915 #define default_ISA_polarity(idx) (0)
917 /* EISA interrupts are always polarity zero and can be edge or level
918 * trigger depending on the ELCR value. If an interrupt is listed as
919 * EISA conforming in the MP table, that means its trigger type must
920 * be read in from the ELCR */
922 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
923 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
925 /* PCI interrupts are always polarity one level triggered,
926 * when listed as conforming in the MP table. */
928 #define default_PCI_trigger(idx) (1)
929 #define default_PCI_polarity(idx) (1)
931 /* MCA interrupts are always polarity zero level triggered,
932 * when listed as conforming in the MP table. */
934 #define default_MCA_trigger(idx) (1)
935 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
937 static int irq_polarity(int idx)
939 int bus = mp_irqs[idx].srcbus;
943 * Determine IRQ line polarity (high active or low active):
945 switch (mp_irqs[idx].irqflag & 3)
947 case 0: /* conforms, ie. bus-type dependent polarity */
948 if (test_bit(bus, mp_bus_not_pci))
949 polarity = default_ISA_polarity(idx);
951 polarity = default_PCI_polarity(idx);
953 case 1: /* high active */
958 case 2: /* reserved */
960 printk(KERN_WARNING "broken BIOS!!\n");
964 case 3: /* low active */
969 default: /* invalid */
971 printk(KERN_WARNING "broken BIOS!!\n");
979 static int irq_trigger(int idx)
981 int bus = mp_irqs[idx].srcbus;
985 * Determine IRQ trigger mode (edge or level sensitive):
987 switch ((mp_irqs[idx].irqflag>>2) & 3)
989 case 0: /* conforms, ie. bus-type dependent */
990 if (test_bit(bus, mp_bus_not_pci))
991 trigger = default_ISA_trigger(idx);
993 trigger = default_PCI_trigger(idx);
994 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
995 switch (mp_bus_id_to_type[bus]) {
996 case MP_BUS_ISA: /* ISA pin */
998 /* set before the switch */
1001 case MP_BUS_EISA: /* EISA pin */
1003 trigger = default_EISA_trigger(idx);
1006 case MP_BUS_PCI: /* PCI pin */
1008 /* set before the switch */
1011 case MP_BUS_MCA: /* MCA pin */
1013 trigger = default_MCA_trigger(idx);
1018 printk(KERN_WARNING "broken BIOS!!\n");
1030 case 2: /* reserved */
1032 printk(KERN_WARNING "broken BIOS!!\n");
1041 default: /* invalid */
1043 printk(KERN_WARNING "broken BIOS!!\n");
1051 static int pin_2_irq(int idx, int apic, int pin)
1054 int bus = mp_irqs[idx].srcbus;
1055 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
1058 * Debugging check, we are in big trouble if this message pops up!
1060 if (mp_irqs[idx].dstirq != pin)
1061 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1063 if (test_bit(bus, mp_bus_not_pci)) {
1064 irq = mp_irqs[idx].srcbusirq;
1066 u32 gsi = gsi_cfg->gsi_base + pin;
1068 if (gsi >= NR_IRQS_LEGACY)
1071 irq = gsi_top + gsi;
1074 #ifdef CONFIG_X86_32
1076 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1078 if ((pin >= 16) && (pin <= 23)) {
1079 if (pirq_entries[pin-16] != -1) {
1080 if (!pirq_entries[pin-16]) {
1081 apic_printk(APIC_VERBOSE, KERN_DEBUG
1082 "disabling PIRQ%d\n", pin-16);
1084 irq = pirq_entries[pin-16];
1085 apic_printk(APIC_VERBOSE, KERN_DEBUG
1086 "using PIRQ%d -> IRQ %d\n",
1097 * Find a specific PCI IRQ entry.
1098 * Not an __init, possibly needed by modules
1100 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1101 struct io_apic_irq_attr *irq_attr)
1103 int ioapic_idx, i, best_guess = -1;
1105 apic_printk(APIC_DEBUG,
1106 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1108 if (test_bit(bus, mp_bus_not_pci)) {
1109 apic_printk(APIC_VERBOSE,
1110 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1113 for (i = 0; i < mp_irq_entries; i++) {
1114 int lbus = mp_irqs[i].srcbus;
1116 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1117 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1118 mp_irqs[i].dstapic == MP_APIC_ALL)
1121 if (!test_bit(lbus, mp_bus_not_pci) &&
1122 !mp_irqs[i].irqtype &&
1124 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1125 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1127 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1130 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1131 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1138 * Use the first all-but-pin matching entry as a
1139 * best-guess fuzzy result for broken mptables.
1141 if (best_guess < 0) {
1142 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1152 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1154 void lock_vector_lock(void)
1156 /* Used to the online set of cpus does not change
1157 * during assign_irq_vector.
1159 raw_spin_lock(&vector_lock);
1162 void unlock_vector_lock(void)
1164 raw_spin_unlock(&vector_lock);
1168 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1171 * NOTE! The local APIC isn't very good at handling
1172 * multiple interrupts at the same interrupt level.
1173 * As the interrupt level is determined by taking the
1174 * vector number and shifting that right by 4, we
1175 * want to spread these out a bit so that they don't
1176 * all fall in the same interrupt level.
1178 * Also, we've got to be careful not to trash gate
1179 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1181 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1182 static int current_offset = VECTOR_OFFSET_START % 8;
1183 unsigned int old_vector;
1185 cpumask_var_t tmp_mask;
1187 if (cfg->move_in_progress)
1190 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1193 old_vector = cfg->vector;
1195 cpumask_and(tmp_mask, mask, cpu_online_mask);
1196 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1197 if (!cpumask_empty(tmp_mask)) {
1198 free_cpumask_var(tmp_mask);
1203 /* Only try and allocate irqs on cpus that are present */
1205 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1209 apic->vector_allocation_domain(cpu, tmp_mask);
1211 vector = current_vector;
1212 offset = current_offset;
1215 if (vector >= first_system_vector) {
1216 /* If out of vectors on large boxen, must share them. */
1217 offset = (offset + 1) % 8;
1218 vector = FIRST_EXTERNAL_VECTOR + offset;
1220 if (unlikely(current_vector == vector))
1223 if (test_bit(vector, used_vectors))
1226 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1227 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1230 current_vector = vector;
1231 current_offset = offset;
1233 cfg->move_in_progress = 1;
1234 cpumask_copy(cfg->old_domain, cfg->domain);
1236 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1237 per_cpu(vector_irq, new_cpu)[vector] = irq;
1238 cfg->vector = vector;
1239 cpumask_copy(cfg->domain, tmp_mask);
1243 free_cpumask_var(tmp_mask);
1247 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1250 unsigned long flags;
1252 raw_spin_lock_irqsave(&vector_lock, flags);
1253 err = __assign_irq_vector(irq, cfg, mask);
1254 raw_spin_unlock_irqrestore(&vector_lock, flags);
1258 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1262 BUG_ON(!cfg->vector);
1264 vector = cfg->vector;
1265 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1266 per_cpu(vector_irq, cpu)[vector] = -1;
1269 cpumask_clear(cfg->domain);
1271 if (likely(!cfg->move_in_progress))
1273 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1274 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1276 if (per_cpu(vector_irq, cpu)[vector] != irq)
1278 per_cpu(vector_irq, cpu)[vector] = -1;
1282 cfg->move_in_progress = 0;
1285 void __setup_vector_irq(int cpu)
1287 /* Initialize vector_irq on a new cpu */
1289 struct irq_cfg *cfg;
1292 * vector_lock will make sure that we don't run into irq vector
1293 * assignments that might be happening on another cpu in parallel,
1294 * while we setup our initial vector to irq mappings.
1296 raw_spin_lock(&vector_lock);
1297 /* Mark the inuse vectors */
1298 for_each_active_irq(irq) {
1299 cfg = irq_get_chip_data(irq);
1303 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1304 * will be part of the irq_cfg's domain.
1306 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1307 cpumask_set_cpu(cpu, cfg->domain);
1309 if (!cpumask_test_cpu(cpu, cfg->domain))
1311 vector = cfg->vector;
1312 per_cpu(vector_irq, cpu)[vector] = irq;
1314 /* Mark the free vectors */
1315 for (vector = 0; vector < NR_VECTORS; ++vector) {
1316 irq = per_cpu(vector_irq, cpu)[vector];
1321 if (!cpumask_test_cpu(cpu, cfg->domain))
1322 per_cpu(vector_irq, cpu)[vector] = -1;
1324 raw_spin_unlock(&vector_lock);
1327 static struct irq_chip ioapic_chip;
1329 #ifdef CONFIG_X86_32
1330 static inline int IO_APIC_irq_trigger(int irq)
1334 for (apic = 0; apic < nr_ioapics; apic++) {
1335 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1336 idx = find_irq_entry(apic, pin, mp_INT);
1337 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1338 return irq_trigger(idx);
1342 * nonexistent IRQs are edge default
1347 static inline int IO_APIC_irq_trigger(int irq)
1353 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1354 unsigned long trigger)
1356 struct irq_chip *chip = &ioapic_chip;
1357 irq_flow_handler_t hdl;
1360 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1361 trigger == IOAPIC_LEVEL) {
1362 irq_set_status_flags(irq, IRQ_LEVEL);
1365 irq_clear_status_flags(irq, IRQ_LEVEL);
1369 if (irq_remapped(cfg)) {
1370 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1371 irq_remap_modify_chip_defaults(chip);
1372 fasteoi = trigger != 0;
1375 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1376 irq_set_chip_and_handler_name(irq, chip, hdl,
1377 fasteoi ? "fasteoi" : "edge");
1380 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1381 unsigned int destination, int vector,
1382 struct io_apic_irq_attr *attr)
1384 if (irq_remapping_enabled)
1385 return setup_ioapic_remapped_entry(irq, entry, destination,
1388 memset(entry, 0, sizeof(*entry));
1390 entry->delivery_mode = apic->irq_delivery_mode;
1391 entry->dest_mode = apic->irq_dest_mode;
1392 entry->dest = destination;
1393 entry->vector = vector;
1394 entry->mask = 0; /* enable IRQ */
1395 entry->trigger = attr->trigger;
1396 entry->polarity = attr->polarity;
1399 * Mask level triggered irqs.
1400 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1408 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1409 struct io_apic_irq_attr *attr)
1411 struct IO_APIC_route_entry entry;
1414 if (!IO_APIC_IRQ(irq))
1417 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1418 * controllers like 8259. Now that IO-APIC can handle this irq, update
1421 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1422 apic->vector_allocation_domain(0, cfg->domain);
1424 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1427 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1429 apic_printk(APIC_VERBOSE,KERN_DEBUG
1430 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1431 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1432 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1433 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1435 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1436 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1437 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1438 __clear_irq_vector(irq, cfg);
1443 ioapic_register_intr(irq, cfg, attr->trigger);
1444 if (irq < legacy_pic->nr_legacy_irqs)
1445 legacy_pic->mask(irq);
1447 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1450 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1455 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1456 mpc_ioapic_id(ioapic_idx), pin);
1460 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1462 int idx, node = cpu_to_node(0);
1463 struct io_apic_irq_attr attr;
1464 unsigned int pin, irq;
1466 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1467 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1468 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1471 irq = pin_2_irq(idx, ioapic_idx, pin);
1473 if ((ioapic_idx > 0) && (irq > 16))
1477 * Skip the timer IRQ if there's a quirk handler
1478 * installed and if it returns 1:
1480 if (apic->multi_timer_check &&
1481 apic->multi_timer_check(ioapic_idx, irq))
1484 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1487 io_apic_setup_irq_pin(irq, node, &attr);
1491 static void __init setup_IO_APIC_irqs(void)
1493 unsigned int ioapic_idx;
1495 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1497 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1498 __io_apic_setup_irqs(ioapic_idx);
1502 * for the gsit that is not in first ioapic
1503 * but could not use acpi_register_gsi()
1504 * like some special sci in IBM x3330
1506 void setup_IO_APIC_irq_extra(u32 gsi)
1508 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1509 struct io_apic_irq_attr attr;
1512 * Convert 'gsi' to 'ioapic.pin'.
1514 ioapic_idx = mp_find_ioapic(gsi);
1518 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1519 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1523 irq = pin_2_irq(idx, ioapic_idx, pin);
1525 /* Only handle the non legacy irqs on secondary ioapics */
1526 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1529 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1532 io_apic_setup_irq_pin_once(irq, node, &attr);
1536 * Set up the timer pin, possibly with the 8259A-master behind.
1538 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1539 unsigned int pin, int vector)
1541 struct IO_APIC_route_entry entry;
1543 if (irq_remapping_enabled)
1546 memset(&entry, 0, sizeof(entry));
1549 * We use logical delivery to get the timer IRQ
1552 entry.dest_mode = apic->irq_dest_mode;
1553 entry.mask = 0; /* don't mask IRQ for edge */
1554 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1555 entry.delivery_mode = apic->irq_delivery_mode;
1558 entry.vector = vector;
1561 * The timer IRQ doesn't have to know that behind the
1562 * scene we may have a 8259A-master in AEOI mode ...
1564 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1568 * Add it to the IO-APIC irq-routing table:
1570 ioapic_write_entry(ioapic_idx, pin, entry);
1573 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1576 union IO_APIC_reg_00 reg_00;
1577 union IO_APIC_reg_01 reg_01;
1578 union IO_APIC_reg_02 reg_02;
1579 union IO_APIC_reg_03 reg_03;
1580 unsigned long flags;
1582 raw_spin_lock_irqsave(&ioapic_lock, flags);
1583 reg_00.raw = io_apic_read(ioapic_idx, 0);
1584 reg_01.raw = io_apic_read(ioapic_idx, 1);
1585 if (reg_01.bits.version >= 0x10)
1586 reg_02.raw = io_apic_read(ioapic_idx, 2);
1587 if (reg_01.bits.version >= 0x20)
1588 reg_03.raw = io_apic_read(ioapic_idx, 3);
1589 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1592 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1593 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1594 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1595 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1596 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1598 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1599 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1600 reg_01.bits.entries);
1602 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1603 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1604 reg_01.bits.version);
1607 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1608 * but the value of reg_02 is read as the previous read register
1609 * value, so ignore it if reg_02 == reg_01.
1611 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1612 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1613 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1617 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1618 * or reg_03, but the value of reg_0[23] is read as the previous read
1619 * register value, so ignore it if reg_03 == reg_0[12].
1621 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1622 reg_03.raw != reg_01.raw) {
1623 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1624 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1627 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1629 if (irq_remapping_enabled) {
1630 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1631 " Pol Stat Indx2 Zero Vect:\n");
1633 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1634 " Stat Dmod Deli Vect:\n");
1637 for (i = 0; i <= reg_01.bits.entries; i++) {
1638 if (irq_remapping_enabled) {
1639 struct IO_APIC_route_entry entry;
1640 struct IR_IO_APIC_route_entry *ir_entry;
1642 entry = ioapic_read_entry(ioapic_idx, i);
1643 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1644 printk(KERN_DEBUG " %02x %04X ",
1648 printk("%1d %1d %1d %1d %1d "
1649 "%1d %1d %X %02X\n",
1655 ir_entry->delivery_status,
1661 struct IO_APIC_route_entry entry;
1663 entry = ioapic_read_entry(ioapic_idx, i);
1664 printk(KERN_DEBUG " %02x %02X ",
1668 printk("%1d %1d %1d %1d %1d "
1674 entry.delivery_status,
1676 entry.delivery_mode,
1683 __apicdebuginit(void) print_IO_APICs(void)
1686 struct irq_cfg *cfg;
1688 struct irq_chip *chip;
1690 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1691 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1692 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1693 mpc_ioapic_id(ioapic_idx),
1694 ioapics[ioapic_idx].nr_registers);
1697 * We are a bit conservative about what we expect. We have to
1698 * know about every hardware change ASAP.
1700 printk(KERN_INFO "testing the IO APIC.......................\n");
1702 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1703 print_IO_APIC(ioapic_idx);
1705 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1706 for_each_active_irq(irq) {
1707 struct irq_pin_list *entry;
1709 chip = irq_get_chip(irq);
1710 if (chip != &ioapic_chip)
1713 cfg = irq_get_chip_data(irq);
1716 entry = cfg->irq_2_pin;
1719 printk(KERN_DEBUG "IRQ%d ", irq);
1720 for_each_irq_pin(entry, cfg->irq_2_pin)
1721 printk("-> %d:%d", entry->apic, entry->pin);
1725 printk(KERN_INFO ".................................... done.\n");
1728 __apicdebuginit(void) print_APIC_field(int base)
1734 for (i = 0; i < 8; i++)
1735 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1737 printk(KERN_CONT "\n");
1740 __apicdebuginit(void) print_local_APIC(void *dummy)
1742 unsigned int i, v, ver, maxlvt;
1745 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1746 smp_processor_id(), hard_smp_processor_id());
1747 v = apic_read(APIC_ID);
1748 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1749 v = apic_read(APIC_LVR);
1750 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1751 ver = GET_APIC_VERSION(v);
1752 maxlvt = lapic_get_maxlvt();
1754 v = apic_read(APIC_TASKPRI);
1755 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1757 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1758 if (!APIC_XAPIC(ver)) {
1759 v = apic_read(APIC_ARBPRI);
1760 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1761 v & APIC_ARBPRI_MASK);
1763 v = apic_read(APIC_PROCPRI);
1764 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1768 * Remote read supported only in the 82489DX and local APIC for
1769 * Pentium processors.
1771 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1772 v = apic_read(APIC_RRR);
1773 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1776 v = apic_read(APIC_LDR);
1777 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1778 if (!x2apic_enabled()) {
1779 v = apic_read(APIC_DFR);
1780 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1782 v = apic_read(APIC_SPIV);
1783 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1785 printk(KERN_DEBUG "... APIC ISR field:\n");
1786 print_APIC_field(APIC_ISR);
1787 printk(KERN_DEBUG "... APIC TMR field:\n");
1788 print_APIC_field(APIC_TMR);
1789 printk(KERN_DEBUG "... APIC IRR field:\n");
1790 print_APIC_field(APIC_IRR);
1792 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1793 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1794 apic_write(APIC_ESR, 0);
1796 v = apic_read(APIC_ESR);
1797 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1800 icr = apic_icr_read();
1801 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1802 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1804 v = apic_read(APIC_LVTT);
1805 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1807 if (maxlvt > 3) { /* PC is LVT#4. */
1808 v = apic_read(APIC_LVTPC);
1809 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1811 v = apic_read(APIC_LVT0);
1812 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1813 v = apic_read(APIC_LVT1);
1814 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1816 if (maxlvt > 2) { /* ERR is LVT#3. */
1817 v = apic_read(APIC_LVTERR);
1818 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1821 v = apic_read(APIC_TMICT);
1822 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1823 v = apic_read(APIC_TMCCT);
1824 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1825 v = apic_read(APIC_TDCR);
1826 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1828 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1829 v = apic_read(APIC_EFEAT);
1830 maxlvt = (v >> 16) & 0xff;
1831 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1832 v = apic_read(APIC_ECTRL);
1833 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1834 for (i = 0; i < maxlvt; i++) {
1835 v = apic_read(APIC_EILVTn(i));
1836 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1842 __apicdebuginit(void) print_local_APICs(int maxcpu)
1850 for_each_online_cpu(cpu) {
1853 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1858 __apicdebuginit(void) print_PIC(void)
1861 unsigned long flags;
1863 if (!legacy_pic->nr_legacy_irqs)
1866 printk(KERN_DEBUG "\nprinting PIC contents\n");
1868 raw_spin_lock_irqsave(&i8259A_lock, flags);
1870 v = inb(0xa1) << 8 | inb(0x21);
1871 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1873 v = inb(0xa0) << 8 | inb(0x20);
1874 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1878 v = inb(0xa0) << 8 | inb(0x20);
1882 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1884 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1886 v = inb(0x4d1) << 8 | inb(0x4d0);
1887 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1890 static int __initdata show_lapic = 1;
1891 static __init int setup_show_lapic(char *arg)
1895 if (strcmp(arg, "all") == 0) {
1896 show_lapic = CONFIG_NR_CPUS;
1898 get_option(&arg, &num);
1905 __setup("show_lapic=", setup_show_lapic);
1907 __apicdebuginit(int) print_ICs(void)
1909 if (apic_verbosity == APIC_QUIET)
1914 /* don't print out if apic is not there */
1915 if (!cpu_has_apic && !apic_from_smp_config())
1918 print_local_APICs(show_lapic);
1924 late_initcall(print_ICs);
1927 /* Where if anywhere is the i8259 connect in external int mode */
1928 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1930 void __init enable_IO_APIC(void)
1932 int i8259_apic, i8259_pin;
1935 if (!legacy_pic->nr_legacy_irqs)
1938 for(apic = 0; apic < nr_ioapics; apic++) {
1940 /* See if any of the pins is in ExtINT mode */
1941 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1942 struct IO_APIC_route_entry entry;
1943 entry = ioapic_read_entry(apic, pin);
1945 /* If the interrupt line is enabled and in ExtInt mode
1946 * I have found the pin where the i8259 is connected.
1948 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1949 ioapic_i8259.apic = apic;
1950 ioapic_i8259.pin = pin;
1956 /* Look to see what if the MP table has reported the ExtINT */
1957 /* If we could not find the appropriate pin by looking at the ioapic
1958 * the i8259 probably is not connected the ioapic but give the
1959 * mptable a chance anyway.
1961 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1962 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1963 /* Trust the MP table if nothing is setup in the hardware */
1964 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1965 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1966 ioapic_i8259.pin = i8259_pin;
1967 ioapic_i8259.apic = i8259_apic;
1969 /* Complain if the MP table and the hardware disagree */
1970 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1971 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1973 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1977 * Do not trust the IO-APIC being empty at bootup
1983 * Not an __init, needed by the reboot code
1985 void disable_IO_APIC(void)
1988 * Clear the IO-APIC before rebooting:
1992 if (!legacy_pic->nr_legacy_irqs)
1996 * If the i8259 is routed through an IOAPIC
1997 * Put that IOAPIC in virtual wire mode
1998 * so legacy interrupts can be delivered.
2000 * With interrupt-remapping, for now we will use virtual wire A mode,
2001 * as virtual wire B is little complex (need to configure both
2002 * IOAPIC RTE as well as interrupt-remapping table entry).
2003 * As this gets called during crash dump, keep this simple for now.
2005 if (ioapic_i8259.pin != -1 && !irq_remapping_enabled) {
2006 struct IO_APIC_route_entry entry;
2008 memset(&entry, 0, sizeof(entry));
2009 entry.mask = 0; /* Enabled */
2010 entry.trigger = 0; /* Edge */
2012 entry.polarity = 0; /* High */
2013 entry.delivery_status = 0;
2014 entry.dest_mode = 0; /* Physical */
2015 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2017 entry.dest = read_apic_id();
2020 * Add it to the IO-APIC irq-routing table:
2022 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2026 * Use virtual wire A mode when interrupt remapping is enabled.
2028 if (cpu_has_apic || apic_from_smp_config())
2029 disconnect_bsp_APIC(!irq_remapping_enabled &&
2030 ioapic_i8259.pin != -1);
2033 #ifdef CONFIG_X86_32
2035 * function to set the IO-APIC physical IDs based on the
2036 * values stored in the MPC table.
2038 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2040 void __init setup_ioapic_ids_from_mpc_nocheck(void)
2042 union IO_APIC_reg_00 reg_00;
2043 physid_mask_t phys_id_present_map;
2046 unsigned char old_id;
2047 unsigned long flags;
2050 * This is broken; anything with a real cpu count has to
2051 * circumvent this idiocy regardless.
2053 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2056 * Set the IOAPIC ID to the value stored in the MPC table.
2058 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
2059 /* Read the register 0 value */
2060 raw_spin_lock_irqsave(&ioapic_lock, flags);
2061 reg_00.raw = io_apic_read(ioapic_idx, 0);
2062 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2064 old_id = mpc_ioapic_id(ioapic_idx);
2066 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2067 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2068 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2069 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2071 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2075 * Sanity check, is the ID really free? Every APIC in a
2076 * system must have a unique ID or we get lots of nice
2077 * 'stuck on smp_invalidate_needed IPI wait' messages.
2079 if (apic->check_apicid_used(&phys_id_present_map,
2080 mpc_ioapic_id(ioapic_idx))) {
2081 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2082 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2083 for (i = 0; i < get_physical_broadcast(); i++)
2084 if (!physid_isset(i, phys_id_present_map))
2086 if (i >= get_physical_broadcast())
2087 panic("Max APIC ID exceeded!\n");
2088 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2090 physid_set(i, phys_id_present_map);
2091 ioapics[ioapic_idx].mp_config.apicid = i;
2094 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2096 apic_printk(APIC_VERBOSE, "Setting %d in the "
2097 "phys_id_present_map\n",
2098 mpc_ioapic_id(ioapic_idx));
2099 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2103 * We need to adjust the IRQ routing table
2104 * if the ID changed.
2106 if (old_id != mpc_ioapic_id(ioapic_idx))
2107 for (i = 0; i < mp_irq_entries; i++)
2108 if (mp_irqs[i].dstapic == old_id)
2110 = mpc_ioapic_id(ioapic_idx);
2113 * Update the ID register according to the right value
2114 * from the MPC table if they are different.
2116 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2119 apic_printk(APIC_VERBOSE, KERN_INFO
2120 "...changing IO-APIC physical APIC ID to %d ...",
2121 mpc_ioapic_id(ioapic_idx));
2123 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2124 raw_spin_lock_irqsave(&ioapic_lock, flags);
2125 io_apic_write(ioapic_idx, 0, reg_00.raw);
2126 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2131 raw_spin_lock_irqsave(&ioapic_lock, flags);
2132 reg_00.raw = io_apic_read(ioapic_idx, 0);
2133 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2134 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2135 printk("could not set ID!\n");
2137 apic_printk(APIC_VERBOSE, " ok.\n");
2141 void __init setup_ioapic_ids_from_mpc(void)
2147 * Don't check I/O APIC IDs for xAPIC systems. They have
2148 * no meaning without the serial APIC bus.
2150 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2151 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2153 setup_ioapic_ids_from_mpc_nocheck();
2157 int no_timer_check __initdata;
2159 static int __init notimercheck(char *s)
2164 __setup("no_timer_check", notimercheck);
2167 * There is a nasty bug in some older SMP boards, their mptable lies
2168 * about the timer IRQ. We do the following to work around the situation:
2170 * - timer IRQ defaults to IO-APIC IRQ
2171 * - if this function detects that timer IRQs are defunct, then we fall
2172 * back to ISA timer IRQs
2174 static int __init timer_irq_works(void)
2176 unsigned long t1 = jiffies;
2177 unsigned long flags;
2182 local_save_flags(flags);
2184 /* Let ten ticks pass... */
2185 mdelay((10 * 1000) / HZ);
2186 local_irq_restore(flags);
2189 * Expect a few ticks at least, to be sure some possible
2190 * glue logic does not lock up after one or two first
2191 * ticks in a non-ExtINT mode. Also the local APIC
2192 * might have cached one ExtINT interrupt. Finally, at
2193 * least one tick may be lost due to delays.
2197 if (time_after(jiffies, t1 + 4))
2203 * In the SMP+IOAPIC case it might happen that there are an unspecified
2204 * number of pending IRQ events unhandled. These cases are very rare,
2205 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2206 * better to do it this way as thus we do not have to be aware of
2207 * 'pending' interrupts in the IRQ path, except at this point.
2210 * Edge triggered needs to resend any interrupt
2211 * that was delayed but this is now handled in the device
2216 * Starting up a edge-triggered IO-APIC interrupt is
2217 * nasty - we need to make sure that we get the edge.
2218 * If it is already asserted for some reason, we need
2219 * return 1 to indicate that is was pending.
2221 * This is not complete - we should be able to fake
2222 * an edge even if it isn't on the 8259A...
2225 static unsigned int startup_ioapic_irq(struct irq_data *data)
2227 int was_pending = 0, irq = data->irq;
2228 unsigned long flags;
2230 raw_spin_lock_irqsave(&ioapic_lock, flags);
2231 if (irq < legacy_pic->nr_legacy_irqs) {
2232 legacy_pic->mask(irq);
2233 if (legacy_pic->irq_pending(irq))
2236 __unmask_ioapic(data->chip_data);
2237 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2242 static int ioapic_retrigger_irq(struct irq_data *data)
2244 struct irq_cfg *cfg = data->chip_data;
2245 unsigned long flags;
2247 raw_spin_lock_irqsave(&vector_lock, flags);
2248 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2249 raw_spin_unlock_irqrestore(&vector_lock, flags);
2255 * Level and edge triggered IO-APIC interrupts need different handling,
2256 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2257 * handled with the level-triggered descriptor, but that one has slightly
2258 * more overhead. Level-triggered interrupts cannot be handled with the
2259 * edge-triggered handler, without risking IRQ storms and other ugly
2264 void send_cleanup_vector(struct irq_cfg *cfg)
2266 cpumask_var_t cleanup_mask;
2268 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2270 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2271 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2273 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2274 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2275 free_cpumask_var(cleanup_mask);
2277 cfg->move_in_progress = 0;
2280 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2283 struct irq_pin_list *entry;
2284 u8 vector = cfg->vector;
2286 for_each_irq_pin(entry, cfg->irq_2_pin) {
2292 * With interrupt-remapping, destination information comes
2293 * from interrupt-remapping table entry.
2295 if (!irq_remapped(cfg))
2296 io_apic_write(apic, 0x11 + pin*2, dest);
2297 reg = io_apic_read(apic, 0x10 + pin*2);
2298 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2300 io_apic_modify(apic, 0x10 + pin*2, reg);
2305 * Either sets data->affinity to a valid value, and returns
2306 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2307 * leaves data->affinity untouched.
2309 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2310 unsigned int *dest_id)
2312 struct irq_cfg *cfg = data->chip_data;
2314 if (!cpumask_intersects(mask, cpu_online_mask))
2317 if (assign_irq_vector(data->irq, data->chip_data, mask))
2320 cpumask_copy(data->affinity, mask);
2322 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2327 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2330 unsigned int dest, irq = data->irq;
2331 unsigned long flags;
2334 raw_spin_lock_irqsave(&ioapic_lock, flags);
2335 ret = __ioapic_set_affinity(data, mask, &dest);
2337 /* Only the high 8 bits are valid. */
2338 dest = SET_APIC_LOGICAL_ID(dest);
2339 __target_IO_APIC_irq(irq, dest, data->chip_data);
2341 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2345 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2347 unsigned vector, me;
2353 me = smp_processor_id();
2354 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2357 struct irq_desc *desc;
2358 struct irq_cfg *cfg;
2359 irq = __this_cpu_read(vector_irq[vector]);
2364 desc = irq_to_desc(irq);
2369 raw_spin_lock(&desc->lock);
2372 * Check if the irq migration is in progress. If so, we
2373 * haven't received the cleanup request yet for this irq.
2375 if (cfg->move_in_progress)
2378 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2381 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2383 * Check if the vector that needs to be cleanedup is
2384 * registered at the cpu's IRR. If so, then this is not
2385 * the best time to clean it up. Lets clean it up in the
2386 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2389 if (irr & (1 << (vector % 32))) {
2390 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2393 __this_cpu_write(vector_irq[vector], -1);
2395 raw_spin_unlock(&desc->lock);
2401 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2405 if (likely(!cfg->move_in_progress))
2408 me = smp_processor_id();
2410 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2411 send_cleanup_vector(cfg);
2414 static void irq_complete_move(struct irq_cfg *cfg)
2416 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2419 void irq_force_complete_move(int irq)
2421 struct irq_cfg *cfg = irq_get_chip_data(irq);
2426 __irq_complete_move(cfg, cfg->vector);
2429 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2432 static void ack_apic_edge(struct irq_data *data)
2434 irq_complete_move(data->chip_data);
2439 atomic_t irq_mis_count;
2441 #ifdef CONFIG_GENERIC_PENDING_IRQ
2442 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2444 /* If we are moving the irq we need to mask it */
2445 if (unlikely(irqd_is_setaffinity_pending(data))) {
2452 static inline void ioapic_irqd_unmask(struct irq_data *data,
2453 struct irq_cfg *cfg, bool masked)
2455 if (unlikely(masked)) {
2456 /* Only migrate the irq if the ack has been received.
2458 * On rare occasions the broadcast level triggered ack gets
2459 * delayed going to ioapics, and if we reprogram the
2460 * vector while Remote IRR is still set the irq will never
2463 * To prevent this scenario we read the Remote IRR bit
2464 * of the ioapic. This has two effects.
2465 * - On any sane system the read of the ioapic will
2466 * flush writes (and acks) going to the ioapic from
2468 * - We get to see if the ACK has actually been delivered.
2470 * Based on failed experiments of reprogramming the
2471 * ioapic entry from outside of irq context starting
2472 * with masking the ioapic entry and then polling until
2473 * Remote IRR was clear before reprogramming the
2474 * ioapic I don't trust the Remote IRR bit to be
2475 * completey accurate.
2477 * However there appears to be no other way to plug
2478 * this race, so if the Remote IRR bit is not
2479 * accurate and is causing problems then it is a hardware bug
2480 * and you can go talk to the chipset vendor about it.
2482 if (!io_apic_level_ack_pending(cfg))
2483 irq_move_masked_irq(data);
2488 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2492 static inline void ioapic_irqd_unmask(struct irq_data *data,
2493 struct irq_cfg *cfg, bool masked)
2498 static void ack_apic_level(struct irq_data *data)
2500 struct irq_cfg *cfg = data->chip_data;
2501 int i, irq = data->irq;
2505 irq_complete_move(cfg);
2506 masked = ioapic_irqd_mask(data, cfg);
2509 * It appears there is an erratum which affects at least version 0x11
2510 * of I/O APIC (that's the 82093AA and cores integrated into various
2511 * chipsets). Under certain conditions a level-triggered interrupt is
2512 * erroneously delivered as edge-triggered one but the respective IRR
2513 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2514 * message but it will never arrive and further interrupts are blocked
2515 * from the source. The exact reason is so far unknown, but the
2516 * phenomenon was observed when two consecutive interrupt requests
2517 * from a given source get delivered to the same CPU and the source is
2518 * temporarily disabled in between.
2520 * A workaround is to simulate an EOI message manually. We achieve it
2521 * by setting the trigger mode to edge and then to level when the edge
2522 * trigger mode gets detected in the TMR of a local APIC for a
2523 * level-triggered interrupt. We mask the source for the time of the
2524 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2525 * The idea is from Manfred Spraul. --macro
2527 * Also in the case when cpu goes offline, fixup_irqs() will forward
2528 * any unhandled interrupt on the offlined cpu to the new cpu
2529 * destination that is handling the corresponding interrupt. This
2530 * interrupt forwarding is done via IPI's. Hence, in this case also
2531 * level-triggered io-apic interrupt will be seen as an edge
2532 * interrupt in the IRR. And we can't rely on the cpu's EOI
2533 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2534 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2535 * supporting EOI register, we do an explicit EOI to clear the
2536 * remote IRR and on IO-APIC's which don't have an EOI register,
2537 * we use the above logic (mask+edge followed by unmask+level) from
2538 * Manfred Spraul to clear the remote IRR.
2541 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2544 * We must acknowledge the irq before we move it or the acknowledge will
2545 * not propagate properly.
2550 * Tail end of clearing remote IRR bit (either by delivering the EOI
2551 * message via io-apic EOI register write or simulating it using
2552 * mask+edge followed by unnask+level logic) manually when the
2553 * level triggered interrupt is seen as the edge triggered interrupt
2556 if (!(v & (1 << (i & 0x1f)))) {
2557 atomic_inc(&irq_mis_count);
2559 eoi_ioapic_irq(irq, cfg);
2562 ioapic_irqd_unmask(data, cfg, masked);
2565 #ifdef CONFIG_IRQ_REMAP
2566 static void ir_ack_apic_edge(struct irq_data *data)
2571 static void ir_ack_apic_level(struct irq_data *data)
2574 eoi_ioapic_irq(data->irq, data->chip_data);
2577 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2579 seq_printf(p, " IR-%s", data->chip->name);
2582 static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2584 chip->irq_print_chip = ir_print_prefix;
2585 chip->irq_ack = ir_ack_apic_edge;
2586 chip->irq_eoi = ir_ack_apic_level;
2589 chip->irq_set_affinity = set_remapped_irq_affinity;
2592 #endif /* CONFIG_IRQ_REMAP */
2594 static struct irq_chip ioapic_chip __read_mostly = {
2596 .irq_startup = startup_ioapic_irq,
2597 .irq_mask = mask_ioapic_irq,
2598 .irq_unmask = unmask_ioapic_irq,
2599 .irq_ack = ack_apic_edge,
2600 .irq_eoi = ack_apic_level,
2602 .irq_set_affinity = ioapic_set_affinity,
2604 .irq_retrigger = ioapic_retrigger_irq,
2607 static inline void init_IO_APIC_traps(void)
2609 struct irq_cfg *cfg;
2613 * NOTE! The local APIC isn't very good at handling
2614 * multiple interrupts at the same interrupt level.
2615 * As the interrupt level is determined by taking the
2616 * vector number and shifting that right by 4, we
2617 * want to spread these out a bit so that they don't
2618 * all fall in the same interrupt level.
2620 * Also, we've got to be careful not to trash gate
2621 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2623 for_each_active_irq(irq) {
2624 cfg = irq_get_chip_data(irq);
2625 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2627 * Hmm.. We don't have an entry for this,
2628 * so default to an old-fashioned 8259
2629 * interrupt if we can..
2631 if (irq < legacy_pic->nr_legacy_irqs)
2632 legacy_pic->make_irq(irq);
2634 /* Strange. Oh, well.. */
2635 irq_set_chip(irq, &no_irq_chip);
2641 * The local APIC irq-chip implementation:
2644 static void mask_lapic_irq(struct irq_data *data)
2648 v = apic_read(APIC_LVT0);
2649 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2652 static void unmask_lapic_irq(struct irq_data *data)
2656 v = apic_read(APIC_LVT0);
2657 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2660 static void ack_lapic_irq(struct irq_data *data)
2665 static struct irq_chip lapic_chip __read_mostly = {
2666 .name = "local-APIC",
2667 .irq_mask = mask_lapic_irq,
2668 .irq_unmask = unmask_lapic_irq,
2669 .irq_ack = ack_lapic_irq,
2672 static void lapic_register_intr(int irq)
2674 irq_clear_status_flags(irq, IRQ_LEVEL);
2675 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2680 * This looks a bit hackish but it's about the only one way of sending
2681 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2682 * not support the ExtINT mode, unfortunately. We need to send these
2683 * cycles as some i82489DX-based boards have glue logic that keeps the
2684 * 8259A interrupt line asserted until INTA. --macro
2686 static inline void __init unlock_ExtINT_logic(void)
2689 struct IO_APIC_route_entry entry0, entry1;
2690 unsigned char save_control, save_freq_select;
2692 pin = find_isa_irq_pin(8, mp_INT);
2697 apic = find_isa_irq_apic(8, mp_INT);
2703 entry0 = ioapic_read_entry(apic, pin);
2704 clear_IO_APIC_pin(apic, pin);
2706 memset(&entry1, 0, sizeof(entry1));
2708 entry1.dest_mode = 0; /* physical delivery */
2709 entry1.mask = 0; /* unmask IRQ now */
2710 entry1.dest = hard_smp_processor_id();
2711 entry1.delivery_mode = dest_ExtINT;
2712 entry1.polarity = entry0.polarity;
2716 ioapic_write_entry(apic, pin, entry1);
2718 save_control = CMOS_READ(RTC_CONTROL);
2719 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2720 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2722 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2727 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2731 CMOS_WRITE(save_control, RTC_CONTROL);
2732 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2733 clear_IO_APIC_pin(apic, pin);
2735 ioapic_write_entry(apic, pin, entry0);
2738 static int disable_timer_pin_1 __initdata;
2739 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2740 static int __init disable_timer_pin_setup(char *arg)
2742 disable_timer_pin_1 = 1;
2745 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2747 int timer_through_8259 __initdata;
2750 * This code may look a bit paranoid, but it's supposed to cooperate with
2751 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2752 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2753 * fanatically on his truly buggy board.
2755 * FIXME: really need to revamp this for all platforms.
2757 static inline void __init check_timer(void)
2759 struct irq_cfg *cfg = irq_get_chip_data(0);
2760 int node = cpu_to_node(0);
2761 int apic1, pin1, apic2, pin2;
2762 unsigned long flags;
2765 local_irq_save(flags);
2768 * get/set the timer IRQ vector:
2770 legacy_pic->mask(0);
2771 assign_irq_vector(0, cfg, apic->target_cpus());
2774 * As IRQ0 is to be enabled in the 8259A, the virtual
2775 * wire has to be disabled in the local APIC. Also
2776 * timer interrupts need to be acknowledged manually in
2777 * the 8259A for the i82489DX when using the NMI
2778 * watchdog as that APIC treats NMIs as level-triggered.
2779 * The AEOI mode will finish them in the 8259A
2782 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2783 legacy_pic->init(1);
2785 pin1 = find_isa_irq_pin(0, mp_INT);
2786 apic1 = find_isa_irq_apic(0, mp_INT);
2787 pin2 = ioapic_i8259.pin;
2788 apic2 = ioapic_i8259.apic;
2790 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2791 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2792 cfg->vector, apic1, pin1, apic2, pin2);
2795 * Some BIOS writers are clueless and report the ExtINTA
2796 * I/O APIC input from the cascaded 8259A as the timer
2797 * interrupt input. So just in case, if only one pin
2798 * was found above, try it both directly and through the
2802 if (irq_remapping_enabled)
2803 panic("BIOS bug: timer not connected to IO-APIC");
2807 } else if (pin2 == -1) {
2814 * Ok, does IRQ0 through the IOAPIC work?
2817 add_pin_to_irq_node(cfg, node, apic1, pin1);
2818 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2820 /* for edge trigger, setup_ioapic_irq already
2821 * leave it unmasked.
2822 * so only need to unmask if it is level-trigger
2823 * do we really have level trigger timer?
2826 idx = find_irq_entry(apic1, pin1, mp_INT);
2827 if (idx != -1 && irq_trigger(idx))
2830 if (timer_irq_works()) {
2831 if (disable_timer_pin_1 > 0)
2832 clear_IO_APIC_pin(0, pin1);
2835 if (irq_remapping_enabled)
2836 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2837 local_irq_disable();
2838 clear_IO_APIC_pin(apic1, pin1);
2840 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2841 "8254 timer not connected to IO-APIC\n");
2843 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2844 "(IRQ0) through the 8259A ...\n");
2845 apic_printk(APIC_QUIET, KERN_INFO
2846 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2848 * legacy devices should be connected to IO APIC #0
2850 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2851 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2852 legacy_pic->unmask(0);
2853 if (timer_irq_works()) {
2854 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2855 timer_through_8259 = 1;
2859 * Cleanup, just in case ...
2861 local_irq_disable();
2862 legacy_pic->mask(0);
2863 clear_IO_APIC_pin(apic2, pin2);
2864 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2867 apic_printk(APIC_QUIET, KERN_INFO
2868 "...trying to set up timer as Virtual Wire IRQ...\n");
2870 lapic_register_intr(0);
2871 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2872 legacy_pic->unmask(0);
2874 if (timer_irq_works()) {
2875 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2878 local_irq_disable();
2879 legacy_pic->mask(0);
2880 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2881 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2883 apic_printk(APIC_QUIET, KERN_INFO
2884 "...trying to set up timer as ExtINT IRQ...\n");
2886 legacy_pic->init(0);
2887 legacy_pic->make_irq(0);
2888 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2890 unlock_ExtINT_logic();
2892 if (timer_irq_works()) {
2893 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2896 local_irq_disable();
2897 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2898 if (x2apic_preenabled)
2899 apic_printk(APIC_QUIET, KERN_INFO
2900 "Perhaps problem with the pre-enabled x2apic mode\n"
2901 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2902 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2903 "report. Then try booting with the 'noapic' option.\n");
2905 local_irq_restore(flags);
2909 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2910 * to devices. However there may be an I/O APIC pin available for
2911 * this interrupt regardless. The pin may be left unconnected, but
2912 * typically it will be reused as an ExtINT cascade interrupt for
2913 * the master 8259A. In the MPS case such a pin will normally be
2914 * reported as an ExtINT interrupt in the MP table. With ACPI
2915 * there is no provision for ExtINT interrupts, and in the absence
2916 * of an override it would be treated as an ordinary ISA I/O APIC
2917 * interrupt, that is edge-triggered and unmasked by default. We
2918 * used to do this, but it caused problems on some systems because
2919 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2920 * the same ExtINT cascade interrupt to drive the local APIC of the
2921 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2922 * the I/O APIC in all cases now. No actual device should request
2923 * it anyway. --macro
2925 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2927 void __init setup_IO_APIC(void)
2931 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2933 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2935 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2937 * Set up IO-APIC IRQ routing.
2939 x86_init.mpparse.setup_ioapic_ids();
2942 setup_IO_APIC_irqs();
2943 init_IO_APIC_traps();
2944 if (legacy_pic->nr_legacy_irqs)
2949 * Called after all the initialization is done. If we didn't find any
2950 * APIC bugs then we can allow the modify fast path
2953 static int __init io_apic_bug_finalize(void)
2955 if (sis_apic_bug == -1)
2960 late_initcall(io_apic_bug_finalize);
2962 static void resume_ioapic_id(int ioapic_idx)
2964 unsigned long flags;
2965 union IO_APIC_reg_00 reg_00;
2967 raw_spin_lock_irqsave(&ioapic_lock, flags);
2968 reg_00.raw = io_apic_read(ioapic_idx, 0);
2969 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2970 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2971 io_apic_write(ioapic_idx, 0, reg_00.raw);
2973 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2976 static void ioapic_resume(void)
2980 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
2981 resume_ioapic_id(ioapic_idx);
2983 restore_ioapic_entries();
2986 static struct syscore_ops ioapic_syscore_ops = {
2987 .suspend = save_ioapic_entries,
2988 .resume = ioapic_resume,
2991 static int __init ioapic_init_ops(void)
2993 register_syscore_ops(&ioapic_syscore_ops);
2998 device_initcall(ioapic_init_ops);
3001 * Dynamic irq allocate and deallocation
3003 unsigned int create_irq_nr(unsigned int from, int node)
3005 struct irq_cfg *cfg;
3006 unsigned long flags;
3007 unsigned int ret = 0;
3010 if (from < nr_irqs_gsi)
3013 irq = alloc_irq_from(from, node);
3016 cfg = alloc_irq_cfg(irq, node);
3018 free_irq_at(irq, NULL);
3022 raw_spin_lock_irqsave(&vector_lock, flags);
3023 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3025 raw_spin_unlock_irqrestore(&vector_lock, flags);
3028 irq_set_chip_data(irq, cfg);
3029 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3031 free_irq_at(irq, cfg);
3036 int create_irq(void)
3038 int node = cpu_to_node(0);
3039 unsigned int irq_want;
3042 irq_want = nr_irqs_gsi;
3043 irq = create_irq_nr(irq_want, node);
3051 void destroy_irq(unsigned int irq)
3053 struct irq_cfg *cfg = irq_get_chip_data(irq);
3054 unsigned long flags;
3056 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3058 if (irq_remapped(cfg))
3059 free_remapped_irq(irq);
3060 raw_spin_lock_irqsave(&vector_lock, flags);
3061 __clear_irq_vector(irq, cfg);
3062 raw_spin_unlock_irqrestore(&vector_lock, flags);
3063 free_irq_at(irq, cfg);
3067 * MSI message composition
3069 #ifdef CONFIG_PCI_MSI
3070 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3071 struct msi_msg *msg, u8 hpet_id)
3073 struct irq_cfg *cfg;
3081 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3085 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3087 if (irq_remapped(cfg)) {
3088 compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
3092 if (x2apic_enabled())
3093 msg->address_hi = MSI_ADDR_BASE_HI |
3094 MSI_ADDR_EXT_DEST_ID(dest);
3096 msg->address_hi = MSI_ADDR_BASE_HI;
3100 ((apic->irq_dest_mode == 0) ?
3101 MSI_ADDR_DEST_MODE_PHYSICAL:
3102 MSI_ADDR_DEST_MODE_LOGICAL) |
3103 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3104 MSI_ADDR_REDIRECTION_CPU:
3105 MSI_ADDR_REDIRECTION_LOWPRI) |
3106 MSI_ADDR_DEST_ID(dest);
3109 MSI_DATA_TRIGGER_EDGE |
3110 MSI_DATA_LEVEL_ASSERT |
3111 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3112 MSI_DATA_DELIVERY_FIXED:
3113 MSI_DATA_DELIVERY_LOWPRI) |
3114 MSI_DATA_VECTOR(cfg->vector);
3121 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3123 struct irq_cfg *cfg = data->chip_data;
3127 if (__ioapic_set_affinity(data, mask, &dest))
3130 __get_cached_msi_msg(data->msi_desc, &msg);
3132 msg.data &= ~MSI_DATA_VECTOR_MASK;
3133 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3134 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3135 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3137 __write_msi_msg(data->msi_desc, &msg);
3141 #endif /* CONFIG_SMP */
3144 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3145 * which implement the MSI or MSI-X Capability Structure.
3147 static struct irq_chip msi_chip = {
3149 .irq_unmask = unmask_msi_irq,
3150 .irq_mask = mask_msi_irq,
3151 .irq_ack = ack_apic_edge,
3153 .irq_set_affinity = msi_set_affinity,
3155 .irq_retrigger = ioapic_retrigger_irq,
3158 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3160 struct irq_chip *chip = &msi_chip;
3164 ret = msi_compose_msg(dev, irq, &msg, -1);
3168 irq_set_msi_desc(irq, msidesc);
3169 write_msi_msg(irq, &msg);
3171 if (irq_remapped(irq_get_chip_data(irq))) {
3172 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3173 irq_remap_modify_chip_defaults(chip);
3176 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3178 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3183 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3185 int node, ret, sub_handle, index = 0;
3186 unsigned int irq, irq_want;
3187 struct msi_desc *msidesc;
3189 /* x86 doesn't support multiple MSI yet */
3190 if (type == PCI_CAP_ID_MSI && nvec > 1)
3193 node = dev_to_node(&dev->dev);
3194 irq_want = nr_irqs_gsi;
3196 list_for_each_entry(msidesc, &dev->msi_list, list) {
3197 irq = create_irq_nr(irq_want, node);
3201 if (!irq_remapping_enabled)
3206 * allocate the consecutive block of IRTE's
3209 index = msi_alloc_remapped_irq(dev, irq, nvec);
3215 ret = msi_setup_remapped_irq(dev, irq, index,
3221 ret = setup_msi_irq(dev, msidesc, irq);
3233 void native_teardown_msi_irq(unsigned int irq)
3238 #ifdef CONFIG_DMAR_TABLE
3241 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3244 struct irq_cfg *cfg = data->chip_data;
3245 unsigned int dest, irq = data->irq;
3248 if (__ioapic_set_affinity(data, mask, &dest))
3251 dmar_msi_read(irq, &msg);
3253 msg.data &= ~MSI_DATA_VECTOR_MASK;
3254 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3255 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3256 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3257 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3259 dmar_msi_write(irq, &msg);
3264 #endif /* CONFIG_SMP */
3266 static struct irq_chip dmar_msi_type = {
3268 .irq_unmask = dmar_msi_unmask,
3269 .irq_mask = dmar_msi_mask,
3270 .irq_ack = ack_apic_edge,
3272 .irq_set_affinity = dmar_msi_set_affinity,
3274 .irq_retrigger = ioapic_retrigger_irq,
3277 int arch_setup_dmar_msi(unsigned int irq)
3282 ret = msi_compose_msg(NULL, irq, &msg, -1);
3285 dmar_msi_write(irq, &msg);
3286 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3292 #ifdef CONFIG_HPET_TIMER
3295 static int hpet_msi_set_affinity(struct irq_data *data,
3296 const struct cpumask *mask, bool force)
3298 struct irq_cfg *cfg = data->chip_data;
3302 if (__ioapic_set_affinity(data, mask, &dest))
3305 hpet_msi_read(data->handler_data, &msg);
3307 msg.data &= ~MSI_DATA_VECTOR_MASK;
3308 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3309 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3310 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3312 hpet_msi_write(data->handler_data, &msg);
3317 #endif /* CONFIG_SMP */
3319 static struct irq_chip hpet_msi_type = {
3321 .irq_unmask = hpet_msi_unmask,
3322 .irq_mask = hpet_msi_mask,
3323 .irq_ack = ack_apic_edge,
3325 .irq_set_affinity = hpet_msi_set_affinity,
3327 .irq_retrigger = ioapic_retrigger_irq,
3330 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3332 struct irq_chip *chip = &hpet_msi_type;
3336 if (irq_remapping_enabled) {
3337 if (!setup_hpet_msi_remapped(irq, id))
3341 ret = msi_compose_msg(NULL, irq, &msg, id);
3345 hpet_msi_write(irq_get_handler_data(irq), &msg);
3346 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3347 if (irq_remapped(irq_get_chip_data(irq)))
3348 irq_remap_modify_chip_defaults(chip);
3350 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3355 #endif /* CONFIG_PCI_MSI */
3357 * Hypertransport interrupt support
3359 #ifdef CONFIG_HT_IRQ
3363 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3365 struct ht_irq_msg msg;
3366 fetch_ht_irq_msg(irq, &msg);
3368 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3369 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3371 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3372 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3374 write_ht_irq_msg(irq, &msg);
3378 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3380 struct irq_cfg *cfg = data->chip_data;
3383 if (__ioapic_set_affinity(data, mask, &dest))
3386 target_ht_irq(data->irq, dest, cfg->vector);
3392 static struct irq_chip ht_irq_chip = {
3394 .irq_mask = mask_ht_irq,
3395 .irq_unmask = unmask_ht_irq,
3396 .irq_ack = ack_apic_edge,
3398 .irq_set_affinity = ht_set_affinity,
3400 .irq_retrigger = ioapic_retrigger_irq,
3403 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3405 struct irq_cfg *cfg;
3412 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3414 struct ht_irq_msg msg;
3417 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3418 apic->target_cpus());
3420 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3424 HT_IRQ_LOW_DEST_ID(dest) |
3425 HT_IRQ_LOW_VECTOR(cfg->vector) |
3426 ((apic->irq_dest_mode == 0) ?
3427 HT_IRQ_LOW_DM_PHYSICAL :
3428 HT_IRQ_LOW_DM_LOGICAL) |
3429 HT_IRQ_LOW_RQEOI_EDGE |
3430 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3431 HT_IRQ_LOW_MT_FIXED :
3432 HT_IRQ_LOW_MT_ARBITRATED) |
3433 HT_IRQ_LOW_IRQ_MASKED;
3435 write_ht_irq_msg(irq, &msg);
3437 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3438 handle_edge_irq, "edge");
3440 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3444 #endif /* CONFIG_HT_IRQ */
3447 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3449 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3454 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3456 setup_ioapic_irq(irq, cfg, attr);
3460 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3461 struct io_apic_irq_attr *attr)
3463 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3466 /* Avoid redundant programming */
3467 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3468 pr_debug("Pin %d-%d already programmed\n",
3469 mpc_ioapic_id(ioapic_idx), pin);
3472 ret = io_apic_setup_irq_pin(irq, node, attr);
3474 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3478 static int __init io_apic_get_redir_entries(int ioapic)
3480 union IO_APIC_reg_01 reg_01;
3481 unsigned long flags;
3483 raw_spin_lock_irqsave(&ioapic_lock, flags);
3484 reg_01.raw = io_apic_read(ioapic, 1);
3485 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3487 /* The register returns the maximum index redir index
3488 * supported, which is one less than the total number of redir
3491 return reg_01.bits.entries + 1;
3494 static void __init probe_nr_irqs_gsi(void)
3498 nr = gsi_top + NR_IRQS_LEGACY;
3499 if (nr > nr_irqs_gsi)
3502 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3505 int get_nr_irqs_gsi(void)
3510 int __init arch_probe_nr_irqs(void)
3514 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3515 nr_irqs = NR_VECTORS * nr_cpu_ids;
3517 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3518 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3520 * for MSI and HT dyn irq
3522 nr += nr_irqs_gsi * 16;
3527 return NR_IRQS_LEGACY;
3530 int io_apic_set_pci_routing(struct device *dev, int irq,
3531 struct io_apic_irq_attr *irq_attr)
3535 if (!IO_APIC_IRQ(irq)) {
3536 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3541 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3543 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3546 #ifdef CONFIG_X86_32
3547 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3549 union IO_APIC_reg_00 reg_00;
3550 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3552 unsigned long flags;
3556 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3557 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3558 * supports up to 16 on one shared APIC bus.
3560 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3561 * advantage of new APIC bus architecture.
3564 if (physids_empty(apic_id_map))
3565 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3567 raw_spin_lock_irqsave(&ioapic_lock, flags);
3568 reg_00.raw = io_apic_read(ioapic, 0);
3569 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3571 if (apic_id >= get_physical_broadcast()) {
3572 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3573 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3574 apic_id = reg_00.bits.ID;
3578 * Every APIC in a system must have a unique ID or we get lots of nice
3579 * 'stuck on smp_invalidate_needed IPI wait' messages.
3581 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3583 for (i = 0; i < get_physical_broadcast(); i++) {
3584 if (!apic->check_apicid_used(&apic_id_map, i))
3588 if (i == get_physical_broadcast())
3589 panic("Max apic_id exceeded!\n");
3591 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3592 "trying %d\n", ioapic, apic_id, i);
3597 apic->apicid_to_cpu_present(apic_id, &tmp);
3598 physids_or(apic_id_map, apic_id_map, tmp);
3600 if (reg_00.bits.ID != apic_id) {
3601 reg_00.bits.ID = apic_id;
3603 raw_spin_lock_irqsave(&ioapic_lock, flags);
3604 io_apic_write(ioapic, 0, reg_00.raw);
3605 reg_00.raw = io_apic_read(ioapic, 0);
3606 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3609 if (reg_00.bits.ID != apic_id) {
3610 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3615 apic_printk(APIC_VERBOSE, KERN_INFO
3616 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3621 static u8 __init io_apic_unique_id(u8 id)
3623 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3624 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3625 return io_apic_get_unique_id(nr_ioapics, id);
3630 static u8 __init io_apic_unique_id(u8 id)
3633 DECLARE_BITMAP(used, 256);
3635 bitmap_zero(used, 256);
3636 for (i = 0; i < nr_ioapics; i++) {
3637 __set_bit(mpc_ioapic_id(i), used);
3639 if (!test_bit(id, used))
3641 return find_first_zero_bit(used, 256);
3645 static int __init io_apic_get_version(int ioapic)
3647 union IO_APIC_reg_01 reg_01;
3648 unsigned long flags;
3650 raw_spin_lock_irqsave(&ioapic_lock, flags);
3651 reg_01.raw = io_apic_read(ioapic, 1);
3652 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3654 return reg_01.bits.version;
3657 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3659 int ioapic, pin, idx;
3661 if (skip_ioapic_setup)
3664 ioapic = mp_find_ioapic(gsi);
3668 pin = mp_find_ioapic_pin(ioapic, gsi);
3672 idx = find_irq_entry(ioapic, pin, mp_INT);
3676 *trigger = irq_trigger(idx);
3677 *polarity = irq_polarity(idx);
3682 * This function currently is only a helper for the i386 smp boot process where
3683 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3684 * so mask in all cases should simply be apic->target_cpus()
3687 void __init setup_ioapic_dest(void)
3689 int pin, ioapic, irq, irq_entry;
3690 const struct cpumask *mask;
3691 struct irq_data *idata;
3693 if (skip_ioapic_setup == 1)
3696 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3697 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3698 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3699 if (irq_entry == -1)
3701 irq = pin_2_irq(irq_entry, ioapic, pin);
3703 if ((ioapic > 0) && (irq > 16))
3706 idata = irq_get_irq_data(irq);
3709 * Honour affinities which have been set in early boot
3711 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3712 mask = idata->affinity;
3714 mask = apic->target_cpus();
3716 if (irq_remapping_enabled)
3717 set_remapped_irq_affinity(idata, mask, false);
3719 ioapic_set_affinity(idata, mask, false);
3725 #define IOAPIC_RESOURCE_NAME_SIZE 11
3727 static struct resource *ioapic_resources;
3729 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3732 struct resource *res;
3736 if (nr_ioapics <= 0)
3739 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3742 mem = alloc_bootmem(n);
3745 mem += sizeof(struct resource) * nr_ioapics;
3747 for (i = 0; i < nr_ioapics; i++) {
3749 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3750 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3751 mem += IOAPIC_RESOURCE_NAME_SIZE;
3754 ioapic_resources = res;
3759 void __init ioapic_and_gsi_init(void)
3764 static void __init __ioapic_init_mappings(void)
3766 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3767 struct resource *ioapic_res;
3770 ioapic_res = ioapic_setup_resources(nr_ioapics);
3771 for (i = 0; i < nr_ioapics; i++) {
3772 if (smp_found_config) {
3773 ioapic_phys = mpc_ioapic_addr(i);
3774 #ifdef CONFIG_X86_32
3777 "WARNING: bogus zero IO-APIC "
3778 "address found in MPTABLE, "
3779 "disabling IO/APIC support!\n");
3780 smp_found_config = 0;
3781 skip_ioapic_setup = 1;
3782 goto fake_ioapic_page;
3786 #ifdef CONFIG_X86_32
3789 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3790 ioapic_phys = __pa(ioapic_phys);
3792 set_fixmap_nocache(idx, ioapic_phys);
3793 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3794 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3798 ioapic_res->start = ioapic_phys;
3799 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3803 probe_nr_irqs_gsi();
3806 void __init ioapic_insert_resources(void)
3809 struct resource *r = ioapic_resources;
3814 "IO APIC resources couldn't be allocated.\n");
3818 for (i = 0; i < nr_ioapics; i++) {
3819 insert_resource(&iomem_resource, r);
3824 int mp_find_ioapic(u32 gsi)
3828 if (nr_ioapics == 0)
3831 /* Find the IOAPIC that manages this GSI. */
3832 for (i = 0; i < nr_ioapics; i++) {
3833 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3834 if ((gsi >= gsi_cfg->gsi_base)
3835 && (gsi <= gsi_cfg->gsi_end))
3839 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3843 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3845 struct mp_ioapic_gsi *gsi_cfg;
3847 if (WARN_ON(ioapic == -1))
3850 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3851 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3854 return gsi - gsi_cfg->gsi_base;
3857 static __init int bad_ioapic(unsigned long address)
3859 if (nr_ioapics >= MAX_IO_APICS) {
3860 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3861 MAX_IO_APICS, nr_ioapics);
3865 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3871 static __init int bad_ioapic_register(int idx)
3873 union IO_APIC_reg_00 reg_00;
3874 union IO_APIC_reg_01 reg_01;
3875 union IO_APIC_reg_02 reg_02;
3877 reg_00.raw = io_apic_read(idx, 0);
3878 reg_01.raw = io_apic_read(idx, 1);
3879 reg_02.raw = io_apic_read(idx, 2);
3881 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3882 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3883 mpc_ioapic_addr(idx));
3890 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3894 struct mp_ioapic_gsi *gsi_cfg;
3896 if (bad_ioapic(address))
3901 ioapics[idx].mp_config.type = MP_IOAPIC;
3902 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3903 ioapics[idx].mp_config.apicaddr = address;
3905 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3907 if (bad_ioapic_register(idx)) {
3908 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3912 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3913 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3916 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3917 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3919 entries = io_apic_get_redir_entries(idx);
3920 gsi_cfg = mp_ioapic_gsi_routing(idx);
3921 gsi_cfg->gsi_base = gsi_base;
3922 gsi_cfg->gsi_end = gsi_base + entries - 1;
3925 * The number of IO-APIC IRQ registers (== #pins):
3927 ioapics[idx].nr_registers = entries;
3929 if (gsi_cfg->gsi_end >= gsi_top)
3930 gsi_top = gsi_cfg->gsi_end + 1;
3932 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3933 idx, mpc_ioapic_id(idx),
3934 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3935 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3940 /* Enable IOAPIC early just for system timer */
3941 void __init pre_init_apic_IRQ0(void)
3943 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3945 printk(KERN_INFO "Early APIC setup for system timer0\n");
3947 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3948 &phys_cpu_present_map);
3952 io_apic_setup_irq_pin(0, 0, &attr);
3953 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,