2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/compiler.h>
16 #include <linux/slab.h>
17 #include <asm/irqdomain.h>
18 #include <asm/hw_irq.h>
20 #include <asm/i8259.h>
22 #include <asm/irq_remapping.h>
24 struct apic_chip_data {
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
31 struct irq_domain *x86_vector_domain;
32 EXPORT_SYMBOL_GPL(x86_vector_domain);
33 static DEFINE_RAW_SPINLOCK(vector_lock);
34 static cpumask_var_t vector_cpumask, searched_cpumask;
35 static struct irq_chip lapic_controller;
36 #ifdef CONFIG_X86_IO_APIC
37 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
40 void lock_vector_lock(void)
42 /* Used to the online set of cpus does not change
43 * during assign_irq_vector.
45 raw_spin_lock(&vector_lock);
48 void unlock_vector_lock(void)
50 raw_spin_unlock(&vector_lock);
53 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
58 while (irq_data->parent_data)
59 irq_data = irq_data->parent_data;
61 return irq_data->chip_data;
64 struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
66 struct apic_chip_data *data = apic_chip_data(irq_data);
68 return data ? &data->cfg : NULL;
70 EXPORT_SYMBOL_GPL(irqd_cfg);
72 struct irq_cfg *irq_cfg(unsigned int irq)
74 return irqd_cfg(irq_get_irq_data(irq));
77 static struct apic_chip_data *alloc_apic_chip_data(int node)
79 struct apic_chip_data *data;
81 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
84 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
86 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
90 free_cpumask_var(data->domain);
96 static void free_apic_chip_data(struct apic_chip_data *data)
99 free_cpumask_var(data->domain);
100 free_cpumask_var(data->old_domain);
105 static int __assign_irq_vector(int irq, struct apic_chip_data *d,
106 const struct cpumask *mask)
109 * NOTE! The local APIC isn't very good at handling
110 * multiple interrupts at the same interrupt level.
111 * As the interrupt level is determined by taking the
112 * vector number and shifting that right by 4, we
113 * want to spread these out a bit so that they don't
114 * all fall in the same interrupt level.
116 * Also, we've got to be careful not to trash gate
117 * 0x80, because int 0x80 is hm, kind of importantish. ;)
119 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
120 static int current_offset = VECTOR_OFFSET_START % 16;
123 if (d->move_in_progress)
126 /* Only try and allocate irqs on cpus that are present */
127 cpumask_clear(d->old_domain);
128 cpumask_clear(searched_cpumask);
129 cpu = cpumask_first_and(mask, cpu_online_mask);
130 while (cpu < nr_cpu_ids) {
131 int new_cpu, vector, offset;
133 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
135 if (cpumask_subset(vector_cpumask, d->domain)) {
136 if (cpumask_equal(vector_cpumask, d->domain))
139 * New cpumask using the vector is a proper subset of
140 * the current in use mask. So cleanup the vector
141 * allocation for the members that are not used anymore.
143 cpumask_andnot(d->old_domain, d->domain,
145 d->move_in_progress =
146 cpumask_intersects(d->old_domain, cpu_online_mask);
147 cpumask_and(d->domain, d->domain, vector_cpumask);
151 vector = current_vector;
152 offset = current_offset;
155 if (vector >= first_system_vector) {
156 offset = (offset + 1) % 16;
157 vector = FIRST_EXTERNAL_VECTOR + offset;
160 /* If the search wrapped around, try the next cpu */
161 if (unlikely(current_vector == vector))
164 if (test_bit(vector, used_vectors))
167 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) {
168 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
172 current_vector = vector;
173 current_offset = offset;
175 cpumask_copy(d->old_domain, d->domain);
176 d->move_in_progress =
177 cpumask_intersects(d->old_domain, cpu_online_mask);
179 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask)
180 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
181 d->cfg.vector = vector;
182 cpumask_copy(d->domain, vector_cpumask);
187 * We exclude the current @vector_cpumask from the requested
188 * @mask and try again with the next online cpu in the
189 * result. We cannot modify @mask, so we use @vector_cpumask
190 * as a temporary buffer here as it will be reassigned when
191 * calling apic->vector_allocation_domain() above.
193 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
194 cpumask_andnot(vector_cpumask, mask, searched_cpumask);
195 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
201 /* cache destination APIC IDs into cfg->dest_apicid */
202 return apic->cpu_mask_to_apicid_and(mask, d->domain, &d->cfg.dest_apicid);
205 static int assign_irq_vector(int irq, struct apic_chip_data *data,
206 const struct cpumask *mask)
211 raw_spin_lock_irqsave(&vector_lock, flags);
212 err = __assign_irq_vector(irq, data, mask);
213 raw_spin_unlock_irqrestore(&vector_lock, flags);
217 static int assign_irq_vector_policy(int irq, int node,
218 struct apic_chip_data *data,
219 struct irq_alloc_info *info)
221 if (info && info->mask)
222 return assign_irq_vector(irq, data, info->mask);
223 if (node != NUMA_NO_NODE &&
224 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
226 return assign_irq_vector(irq, data, apic->target_cpus());
229 static void clear_irq_vector(int irq, struct apic_chip_data *data)
231 struct irq_desc *desc;
234 BUG_ON(!data->cfg.vector);
236 vector = data->cfg.vector;
237 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
238 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
240 data->cfg.vector = 0;
241 cpumask_clear(data->domain);
243 if (likely(!data->move_in_progress))
246 desc = irq_to_desc(irq);
247 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
248 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
250 if (per_cpu(vector_irq, cpu)[vector] != desc)
252 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
256 data->move_in_progress = 0;
259 void init_irq_alloc_info(struct irq_alloc_info *info,
260 const struct cpumask *mask)
262 memset(info, 0, sizeof(*info));
266 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
271 memset(dst, 0, sizeof(*dst));
274 static void x86_vector_free_irqs(struct irq_domain *domain,
275 unsigned int virq, unsigned int nr_irqs)
277 struct apic_chip_data *apic_data;
278 struct irq_data *irq_data;
282 for (i = 0; i < nr_irqs; i++) {
283 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
284 if (irq_data && irq_data->chip_data) {
285 raw_spin_lock_irqsave(&vector_lock, flags);
286 clear_irq_vector(virq + i, irq_data->chip_data);
287 apic_data = irq_data->chip_data;
288 irq_domain_reset_irq_data(irq_data);
289 raw_spin_unlock_irqrestore(&vector_lock, flags);
290 free_apic_chip_data(apic_data);
291 #ifdef CONFIG_X86_IO_APIC
292 if (virq + i < nr_legacy_irqs())
293 legacy_irq_data[virq + i] = NULL;
299 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
300 unsigned int nr_irqs, void *arg)
302 struct irq_alloc_info *info = arg;
303 struct apic_chip_data *data;
304 struct irq_data *irq_data;
310 /* Currently vector allocator can't guarantee contiguous allocations */
311 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
314 for (i = 0; i < nr_irqs; i++) {
315 irq_data = irq_domain_get_irq_data(domain, virq + i);
317 node = irq_data_get_node(irq_data);
318 #ifdef CONFIG_X86_IO_APIC
319 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
320 data = legacy_irq_data[virq + i];
323 data = alloc_apic_chip_data(node);
329 irq_data->chip = &lapic_controller;
330 irq_data->chip_data = data;
331 irq_data->hwirq = virq + i;
332 err = assign_irq_vector_policy(virq + i, node, data, info);
340 x86_vector_free_irqs(domain, virq, i + 1);
344 static const struct irq_domain_ops x86_vector_domain_ops = {
345 .alloc = x86_vector_alloc_irqs,
346 .free = x86_vector_free_irqs,
349 int __init arch_probe_nr_irqs(void)
353 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
354 nr_irqs = NR_VECTORS * nr_cpu_ids;
356 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
357 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
359 * for MSI and HT dyn irq
361 if (gsi_top <= NR_IRQS_LEGACY)
362 nr += 8 * nr_cpu_ids;
370 * We don't know if PIC is present at this point so we need to do
371 * probe() to get the right number of legacy IRQs.
373 return legacy_pic->probe();
376 #ifdef CONFIG_X86_IO_APIC
377 static void init_legacy_irqs(void)
379 int i, node = cpu_to_node(0);
380 struct apic_chip_data *data;
383 * For legacy IRQ's, start with assigning irq0 to irq15 to
384 * ISA_IRQ_VECTOR(i) for all cpu's.
386 for (i = 0; i < nr_legacy_irqs(); i++) {
387 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
390 data->cfg.vector = ISA_IRQ_VECTOR(i);
391 cpumask_setall(data->domain);
392 irq_set_chip_data(i, data);
396 static void init_legacy_irqs(void) { }
399 int __init arch_early_irq_init(void)
403 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
405 BUG_ON(x86_vector_domain == NULL);
406 irq_set_default_host(x86_vector_domain);
408 arch_init_msi_domain(x86_vector_domain);
409 arch_init_htirq_domain(x86_vector_domain);
411 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
412 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
414 return arch_early_ioapic_init();
417 /* Initialize vector_irq on a new cpu */
418 static void __setup_vector_irq(int cpu)
420 struct apic_chip_data *data;
421 struct irq_desc *desc;
424 /* Mark the inuse vectors */
425 for_each_irq_desc(irq, desc) {
426 struct irq_data *idata = irq_desc_get_irq_data(desc);
428 data = apic_chip_data(idata);
429 if (!data || !cpumask_test_cpu(cpu, data->domain))
431 vector = data->cfg.vector;
432 per_cpu(vector_irq, cpu)[vector] = desc;
434 /* Mark the free vectors */
435 for (vector = 0; vector < NR_VECTORS; ++vector) {
436 desc = per_cpu(vector_irq, cpu)[vector];
437 if (IS_ERR_OR_NULL(desc))
440 data = apic_chip_data(irq_desc_get_irq_data(desc));
441 if (!cpumask_test_cpu(cpu, data->domain))
442 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
447 * Setup the vector to irq mappings. Must be called with vector_lock held.
449 void setup_vector_irq(int cpu)
453 lockdep_assert_held(&vector_lock);
455 * On most of the platforms, legacy PIC delivers the interrupts on the
456 * boot cpu. But there are certain platforms where PIC interrupts are
457 * delivered to multiple cpu's. If the legacy IRQ is handled by the
458 * legacy PIC, for the new cpu that is coming online, setup the static
459 * legacy vector to irq mapping:
461 for (irq = 0; irq < nr_legacy_irqs(); irq++)
462 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
464 __setup_vector_irq(cpu);
467 static int apic_retrigger_irq(struct irq_data *irq_data)
469 struct apic_chip_data *data = apic_chip_data(irq_data);
473 raw_spin_lock_irqsave(&vector_lock, flags);
474 cpu = cpumask_first_and(data->domain, cpu_online_mask);
475 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
476 raw_spin_unlock_irqrestore(&vector_lock, flags);
481 void apic_ack_edge(struct irq_data *data)
483 irq_complete_move(irqd_cfg(data));
488 static int apic_set_affinity(struct irq_data *irq_data,
489 const struct cpumask *dest, bool force)
491 struct apic_chip_data *data = irq_data->chip_data;
492 int err, irq = irq_data->irq;
494 if (!config_enabled(CONFIG_SMP))
497 if (!cpumask_intersects(dest, cpu_online_mask))
500 err = assign_irq_vector(irq, data, dest);
502 if (assign_irq_vector(irq, data,
503 irq_data_get_affinity_mask(irq_data)))
504 pr_err("Failed to recover vector for irq %d\n", irq);
508 return IRQ_SET_MASK_OK;
511 static struct irq_chip lapic_controller = {
512 .irq_ack = apic_ack_edge,
513 .irq_set_affinity = apic_set_affinity,
514 .irq_retrigger = apic_retrigger_irq,
518 static void __send_cleanup_vector(struct apic_chip_data *data)
520 cpumask_var_t cleanup_mask;
522 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
525 for_each_cpu_and(i, data->old_domain, cpu_online_mask)
526 apic->send_IPI_mask(cpumask_of(i),
527 IRQ_MOVE_CLEANUP_VECTOR);
529 cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask);
530 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
531 free_cpumask_var(cleanup_mask);
533 data->move_in_progress = 0;
536 void send_cleanup_vector(struct irq_cfg *cfg)
538 struct apic_chip_data *data;
540 data = container_of(cfg, struct apic_chip_data, cfg);
541 if (data->move_in_progress)
542 __send_cleanup_vector(data);
545 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
551 /* Prevent vectors vanishing under us */
552 raw_spin_lock(&vector_lock);
554 me = smp_processor_id();
555 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
556 struct apic_chip_data *data;
557 struct irq_desc *desc;
561 desc = __this_cpu_read(vector_irq[vector]);
562 if (IS_ERR_OR_NULL(desc))
565 if (!raw_spin_trylock(&desc->lock)) {
566 raw_spin_unlock(&vector_lock);
568 raw_spin_lock(&vector_lock);
572 data = apic_chip_data(irq_desc_get_irq_data(desc));
577 * Check if the irq migration is in progress. If so, we
578 * haven't received the cleanup request yet for this irq.
580 if (data->move_in_progress)
583 if (vector == data->cfg.vector &&
584 cpumask_test_cpu(me, data->domain))
587 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
589 * Check if the vector that needs to be cleanedup is
590 * registered at the cpu's IRR. If so, then this is not
591 * the best time to clean it up. Lets clean it up in the
592 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
595 if (irr & (1 << (vector % 32))) {
596 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
599 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
601 raw_spin_unlock(&desc->lock);
604 raw_spin_unlock(&vector_lock);
609 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
612 struct apic_chip_data *data;
614 data = container_of(cfg, struct apic_chip_data, cfg);
615 if (likely(!data->move_in_progress))
618 me = smp_processor_id();
619 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
620 __send_cleanup_vector(data);
623 void irq_complete_move(struct irq_cfg *cfg)
625 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
628 void irq_force_complete_move(int irq)
630 struct irq_cfg *cfg = irq_cfg(irq);
633 __irq_complete_move(cfg, cfg->vector);
637 static void __init print_APIC_field(int base)
643 for (i = 0; i < 8; i++)
644 pr_cont("%08x", apic_read(base + i*0x10));
649 static void __init print_local_APIC(void *dummy)
651 unsigned int i, v, ver, maxlvt;
654 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
655 smp_processor_id(), hard_smp_processor_id());
656 v = apic_read(APIC_ID);
657 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
658 v = apic_read(APIC_LVR);
659 pr_info("... APIC VERSION: %08x\n", v);
660 ver = GET_APIC_VERSION(v);
661 maxlvt = lapic_get_maxlvt();
663 v = apic_read(APIC_TASKPRI);
664 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
667 if (APIC_INTEGRATED(ver)) {
668 if (!APIC_XAPIC(ver)) {
669 v = apic_read(APIC_ARBPRI);
670 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
671 v, v & APIC_ARBPRI_MASK);
673 v = apic_read(APIC_PROCPRI);
674 pr_debug("... APIC PROCPRI: %08x\n", v);
678 * Remote read supported only in the 82489DX and local APIC for
679 * Pentium processors.
681 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
682 v = apic_read(APIC_RRR);
683 pr_debug("... APIC RRR: %08x\n", v);
686 v = apic_read(APIC_LDR);
687 pr_debug("... APIC LDR: %08x\n", v);
688 if (!x2apic_enabled()) {
689 v = apic_read(APIC_DFR);
690 pr_debug("... APIC DFR: %08x\n", v);
692 v = apic_read(APIC_SPIV);
693 pr_debug("... APIC SPIV: %08x\n", v);
695 pr_debug("... APIC ISR field:\n");
696 print_APIC_field(APIC_ISR);
697 pr_debug("... APIC TMR field:\n");
698 print_APIC_field(APIC_TMR);
699 pr_debug("... APIC IRR field:\n");
700 print_APIC_field(APIC_IRR);
703 if (APIC_INTEGRATED(ver)) {
704 /* Due to the Pentium erratum 3AP. */
706 apic_write(APIC_ESR, 0);
708 v = apic_read(APIC_ESR);
709 pr_debug("... APIC ESR: %08x\n", v);
712 icr = apic_icr_read();
713 pr_debug("... APIC ICR: %08x\n", (u32)icr);
714 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
716 v = apic_read(APIC_LVTT);
717 pr_debug("... APIC LVTT: %08x\n", v);
721 v = apic_read(APIC_LVTPC);
722 pr_debug("... APIC LVTPC: %08x\n", v);
724 v = apic_read(APIC_LVT0);
725 pr_debug("... APIC LVT0: %08x\n", v);
726 v = apic_read(APIC_LVT1);
727 pr_debug("... APIC LVT1: %08x\n", v);
731 v = apic_read(APIC_LVTERR);
732 pr_debug("... APIC LVTERR: %08x\n", v);
735 v = apic_read(APIC_TMICT);
736 pr_debug("... APIC TMICT: %08x\n", v);
737 v = apic_read(APIC_TMCCT);
738 pr_debug("... APIC TMCCT: %08x\n", v);
739 v = apic_read(APIC_TDCR);
740 pr_debug("... APIC TDCR: %08x\n", v);
742 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
743 v = apic_read(APIC_EFEAT);
744 maxlvt = (v >> 16) & 0xff;
745 pr_debug("... APIC EFEAT: %08x\n", v);
746 v = apic_read(APIC_ECTRL);
747 pr_debug("... APIC ECTRL: %08x\n", v);
748 for (i = 0; i < maxlvt; i++) {
749 v = apic_read(APIC_EILVTn(i));
750 pr_debug("... APIC EILVT%d: %08x\n", i, v);
756 static void __init print_local_APICs(int maxcpu)
764 for_each_online_cpu(cpu) {
767 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
772 static void __init print_PIC(void)
777 if (!nr_legacy_irqs())
780 pr_debug("\nprinting PIC contents\n");
782 raw_spin_lock_irqsave(&i8259A_lock, flags);
784 v = inb(0xa1) << 8 | inb(0x21);
785 pr_debug("... PIC IMR: %04x\n", v);
787 v = inb(0xa0) << 8 | inb(0x20);
788 pr_debug("... PIC IRR: %04x\n", v);
792 v = inb(0xa0) << 8 | inb(0x20);
796 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
798 pr_debug("... PIC ISR: %04x\n", v);
800 v = inb(0x4d1) << 8 | inb(0x4d0);
801 pr_debug("... PIC ELCR: %04x\n", v);
804 static int show_lapic __initdata = 1;
805 static __init int setup_show_lapic(char *arg)
809 if (strcmp(arg, "all") == 0) {
810 show_lapic = CONFIG_NR_CPUS;
812 get_option(&arg, &num);
819 __setup("show_lapic=", setup_show_lapic);
821 static int __init print_ICs(void)
823 if (apic_verbosity == APIC_QUIET)
828 /* don't print out if apic is not there */
829 if (!cpu_has_apic && !apic_from_smp_config())
832 print_local_APICs(show_lapic);
838 late_initcall(print_ICs);