2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28 #include <linux/reboot.h>
30 #include <asm/uv/uv_mmrs.h>
31 #include <asm/uv/uv_hub.h>
32 #include <asm/current.h>
33 #include <asm/pgtable.h>
34 #include <asm/uv/bios.h>
35 #include <asm/uv/uv.h>
39 #include <asm/x86_init.h>
42 DEFINE_PER_CPU(int, x2apic_extra_bits);
44 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
46 static enum uv_system_type uv_system_type;
47 static u64 gru_start_paddr, gru_end_paddr;
48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
49 static u64 gru_dist_lmask, gru_dist_umask;
50 static union uvh_apicid uvh_apicid;
51 int uv_min_hub_revision_id;
52 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
53 unsigned int uv_apicid_hibits;
54 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
56 static struct apic apic_x2apic_uv_x;
58 static unsigned long __init uv_early_read_mmr(unsigned long addr)
60 unsigned long val, *mmr;
62 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
64 early_iounmap(mmr, sizeof(*mmr));
68 static inline bool is_GRU_range(u64 start, u64 end)
71 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
72 u64 sl = start & gru_dist_lmask; /* base offset bits */
73 u64 eu = end & gru_dist_umask;
74 u64 el = end & gru_dist_lmask;
76 /* Must reside completely within a single GRU range */
77 return (sl == gru_dist_base && el == gru_dist_base &&
78 su >= gru_first_node_paddr &&
79 su <= gru_last_node_paddr &&
82 return start >= gru_start_paddr && end <= gru_end_paddr;
86 static bool uv_is_untracked_pat_range(u64 start, u64 end)
88 return is_ISA_range(start, end) || is_GRU_range(start, end);
91 static int __init early_get_pnodeid(void)
93 union uvh_node_id_u node_id;
94 union uvh_rh_gam_config_mmr_u m_n_config;
97 /* Currently, all blades have same revision number */
98 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
99 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
100 uv_min_hub_revision_id = node_id.s.revision;
102 switch (node_id.s.part_number) {
103 case UV2_HUB_PART_NUMBER:
104 case UV2_HUB_PART_NUMBER_X:
105 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
107 case UV3_HUB_PART_NUMBER:
108 case UV3_HUB_PART_NUMBER_X:
109 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
113 uv_hub_info->hub_revision = uv_min_hub_revision_id;
114 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
118 static void __init early_get_apic_pnode_shift(void)
120 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
123 * Old bios, use default value
125 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
129 * Add an extra bit as dictated by bios to the destination apicid of
130 * interrupts potentially passing through the UV HUB. This prevents
131 * a deadlock between interrupts and IO port operations.
133 static void __init uv_set_apicid_hibit(void)
135 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
139 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
141 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
145 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
150 if (strncmp(oem_id, "SGI", 3) != 0)
154 * Determine UV arch type.
157 * SGI3: UV300 (truncated to 4 chars because of different varieties)
159 uv_hub_info->hub_revision =
160 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
161 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
162 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
164 if (uv_hub_info->hub_revision == 0)
167 pnodeid = early_get_pnodeid();
168 early_get_apic_pnode_shift();
169 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
170 x86_platform.nmi_init = uv_nmi_init;
172 if (!strcmp(oem_table_id, "UVX")) { /* most common */
173 uv_system_type = UV_X2APIC;
176 } else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */
177 uv_system_type = UV_NON_UNIQUE_APIC;
178 __this_cpu_write(x2apic_extra_bits,
179 pnodeid << uvh_apicid.s.pnode_shift);
180 uv_set_apicid_hibit();
183 } else if (!strcmp(oem_table_id, "UVL")) { /* only used for */
184 uv_system_type = UV_LEGACY_APIC; /* very small systems */
191 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
192 oem_id, oem_table_id, uv_system_type,
193 uv_min_hub_revision_id, uv_apic);
198 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
199 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
203 enum uv_system_type get_uv_system_type(void)
205 return uv_system_type;
208 int is_uv_system(void)
210 return uv_system_type != UV_NONE;
212 EXPORT_SYMBOL_GPL(is_uv_system);
214 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
215 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
217 struct uv_blade_info *uv_blade_info;
218 EXPORT_SYMBOL_GPL(uv_blade_info);
220 short *uv_node_to_blade;
221 EXPORT_SYMBOL_GPL(uv_node_to_blade);
223 short *uv_cpu_to_blade;
224 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
226 short uv_possible_blades;
227 EXPORT_SYMBOL_GPL(uv_possible_blades);
229 unsigned long sn_rtc_cycles_per_second;
230 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
232 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
237 pnode = uv_apicid_to_pnode(phys_apicid);
238 phys_apicid |= uv_apicid_hibits;
239 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
240 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
241 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
243 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
245 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
246 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
247 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
249 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
254 static void uv_send_IPI_one(int cpu, int vector)
256 unsigned long apicid;
259 apicid = per_cpu(x86_cpu_to_apicid, cpu);
260 pnode = uv_apicid_to_pnode(apicid);
261 uv_hub_send_ipi(pnode, apicid, vector);
264 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
268 for_each_cpu(cpu, mask)
269 uv_send_IPI_one(cpu, vector);
272 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
274 unsigned int this_cpu = smp_processor_id();
277 for_each_cpu(cpu, mask) {
279 uv_send_IPI_one(cpu, vector);
283 static void uv_send_IPI_allbutself(int vector)
285 unsigned int this_cpu = smp_processor_id();
288 for_each_online_cpu(cpu) {
290 uv_send_IPI_one(cpu, vector);
294 static void uv_send_IPI_all(int vector)
296 uv_send_IPI_mask(cpu_online_mask, vector);
299 static int uv_apic_id_valid(int apicid)
304 static int uv_apic_id_registered(void)
309 static void uv_init_apic_ldr(void)
314 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
315 const struct cpumask *andmask,
316 unsigned int *apicid)
321 * We're using fixed IRQ delivery, can only return one phys APIC ID.
322 * May as well be the first.
324 for_each_cpu_and(cpu, cpumask, andmask) {
325 if (cpumask_test_cpu(cpu, cpu_online_mask))
329 if (likely(cpu < nr_cpu_ids)) {
330 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
337 static unsigned int x2apic_get_apic_id(unsigned long x)
341 WARN_ON(preemptible() && num_online_cpus() > 1);
342 id = x | __this_cpu_read(x2apic_extra_bits);
347 static unsigned long set_apic_id(unsigned int id)
351 /* maskout x2apic_extra_bits ? */
356 static unsigned int uv_read_apic_id(void)
359 return x2apic_get_apic_id(apic_read(APIC_ID));
362 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
364 return uv_read_apic_id() >> index_msb;
367 static void uv_send_IPI_self(int vector)
369 apic_write(APIC_SELF_IPI, vector);
372 static int uv_probe(void)
374 return apic == &apic_x2apic_uv_x;
377 static struct apic __refdata apic_x2apic_uv_x = {
379 .name = "UV large system",
381 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
382 .apic_id_valid = uv_apic_id_valid,
383 .apic_id_registered = uv_apic_id_registered,
385 .irq_delivery_mode = dest_Fixed,
386 .irq_dest_mode = 0, /* physical */
388 .target_cpus = online_target_cpus,
390 .dest_logical = APIC_DEST_LOGICAL,
391 .check_apicid_used = NULL,
393 .vector_allocation_domain = default_vector_allocation_domain,
394 .init_apic_ldr = uv_init_apic_ldr,
396 .ioapic_phys_id_map = NULL,
397 .setup_apic_routing = NULL,
398 .cpu_present_to_apicid = default_cpu_present_to_apicid,
399 .apicid_to_cpu_present = NULL,
400 .check_phys_apicid_present = default_check_phys_apicid_present,
401 .phys_pkg_id = uv_phys_pkg_id,
403 .get_apic_id = x2apic_get_apic_id,
404 .set_apic_id = set_apic_id,
405 .apic_id_mask = 0xFFFFFFFFu,
407 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
409 .send_IPI = uv_send_IPI_one,
410 .send_IPI_mask = uv_send_IPI_mask,
411 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
412 .send_IPI_allbutself = uv_send_IPI_allbutself,
413 .send_IPI_all = uv_send_IPI_all,
414 .send_IPI_self = uv_send_IPI_self,
416 .wakeup_secondary_cpu = uv_wakeup_secondary,
417 .inquire_remote_apic = NULL,
419 .read = native_apic_msr_read,
420 .write = native_apic_msr_write,
421 .eoi_write = native_apic_msr_eoi_write,
422 .icr_read = native_x2apic_icr_read,
423 .icr_write = native_x2apic_icr_write,
424 .wait_icr_idle = native_x2apic_wait_icr_idle,
425 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
428 static void set_x2apic_extra_bits(int pnode)
430 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
434 * Called on boot cpu.
436 static __init int boot_pnode_to_blade(int pnode)
440 for (blade = 0; blade < uv_num_possible_blades(); blade++)
441 if (pnode == uv_blade_info[blade].pnode)
447 unsigned long redirect;
451 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
453 static __initdata struct redir_addr redir_addrs[] = {
454 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
455 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
456 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
459 static unsigned char get_n_lshift(int m_val)
461 union uv3h_gr0_gam_gr_config_u m_gr_config;
467 return m_val == 40 ? 40 : 39;
469 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
470 return m_gr_config.s3.m_skt;
473 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
475 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
476 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
479 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
480 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
481 if (alias.s.enable && alias.s.base == 0) {
482 *size = (1UL << alias.s.m_alias);
483 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
484 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
491 enum map_type {map_wb, map_uc};
493 static __init void map_high(char *id, unsigned long base, int pshift,
494 int bshift, int max_pnode, enum map_type map_type)
496 unsigned long bytes, paddr;
498 paddr = base << pshift;
499 bytes = (1UL << bshift) * (max_pnode + 1);
501 pr_info("UV: Map %s_HI base address NULL\n", id);
504 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
505 if (map_type == map_uc)
506 init_extra_mapping_uc(paddr, bytes);
508 init_extra_mapping_wb(paddr, bytes);
511 static __init void map_gru_distributed(unsigned long c)
513 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
519 /* only base bits 42:28 relevant in dist mode */
520 gru_dist_base = gru.v & 0x000007fff0000000UL;
521 if (!gru_dist_base) {
522 pr_info("UV: Map GRU_DIST base address NULL\n");
525 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
526 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
527 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
528 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
529 for_each_online_node(nid) {
530 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
532 init_extra_mapping_wb(paddr, bytes);
533 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
534 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
536 /* Save upper (63:M) bits of address only for is_GRU_range */
537 gru_first_node_paddr &= gru_dist_umask;
538 gru_last_node_paddr &= gru_dist_umask;
539 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n",
540 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
543 static __init void map_gru_high(int max_pnode)
545 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
546 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
548 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
550 pr_info("UV: GRU disabled\n");
554 if (is_uv3_hub() && gru.s3.mode) {
555 map_gru_distributed(gru.v);
558 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
559 gru_start_paddr = ((u64)gru.s.base << shift);
560 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
563 static __init void map_mmr_high(int max_pnode)
565 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
566 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
568 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
570 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
572 pr_info("UV: MMR disabled\n");
576 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
577 * and REDIRECT MMR regs are exactly the same on UV3.
579 struct mmioh_config {
580 unsigned long overlay;
581 unsigned long redirect;
585 static __initdata struct mmioh_config mmiohs[] = {
587 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
588 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
592 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
593 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
598 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
600 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
603 int i, n, shift, m_io, max_io;
604 int nasid, lnasid, fi, li;
607 id = mmiohs[index].id;
608 overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
609 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
610 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
611 if (!overlay.s3.enable) {
612 pr_info("UV: %s disabled\n", id);
616 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
617 base = (unsigned long)overlay.s3.base;
618 m_io = overlay.s3.m_io;
619 mmr = mmiohs[index].redirect;
620 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
621 min_pnode *= 2; /* convert to NASID */
623 max_io = lnasid = fi = li = -1;
625 for (i = 0; i < n; i++) {
626 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
628 redirect.v = uv_read_local_mmr(mmr + i * 8);
629 nasid = redirect.s3.nasid;
630 if (nasid < min_pnode || max_pnode < nasid)
631 nasid = -1; /* invalid NASID */
633 if (nasid == lnasid) {
635 if (i != n-1) /* last entry check */
639 /* check if we have a cached (or last) redirect to print */
640 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
641 unsigned long addr1, addr2;
651 addr1 = (base << shift) +
652 f * (unsigned long)(1 << m_io);
653 addr2 = (base << shift) +
654 (l + 1) * (unsigned long)(1 << m_io);
655 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
656 id, fi, li, lnasid, addr1, addr2);
664 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
665 id, base, shift, m_io, max_io);
668 map_high(id, base, shift, m_io, max_io, map_uc);
671 static __init void map_mmioh_high(int min_pnode, int max_pnode)
673 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
674 unsigned long mmr, base;
675 int shift, enable, m_io, n_io;
678 /* Map both MMIOH Regions */
679 map_mmioh_high_uv3(0, min_pnode, max_pnode);
680 map_mmioh_high_uv3(1, min_pnode, max_pnode);
685 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
686 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
687 mmioh.v = uv_read_local_mmr(mmr);
688 enable = !!mmioh.s1.enable;
689 base = mmioh.s1.base;
690 m_io = mmioh.s1.m_io;
691 n_io = mmioh.s1.n_io;
692 } else if (is_uv2_hub()) {
693 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
694 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
695 mmioh.v = uv_read_local_mmr(mmr);
696 enable = !!mmioh.s2.enable;
697 base = mmioh.s2.base;
698 m_io = mmioh.s2.m_io;
699 n_io = mmioh.s2.n_io;
704 max_pnode &= (1 << n_io) - 1;
706 "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
707 base, shift, m_io, n_io, max_pnode);
708 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
710 pr_info("UV: MMIOH disabled\n");
714 static __init void map_low_mmrs(void)
716 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
717 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
720 static __init void uv_rtc_init(void)
725 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
727 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
729 "unable to determine platform RTC clock frequency, "
731 /* BIOS gives wrong value for clock freq. so guess */
732 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
734 sn_rtc_cycles_per_second = ticks_per_sec;
738 * percpu heartbeat timer
740 static void uv_heartbeat(unsigned long ignored)
742 struct timer_list *timer = &uv_hub_info->scir.timer;
743 unsigned char bits = uv_hub_info->scir.state;
745 /* flip heartbeat bit */
746 bits ^= SCIR_CPU_HEARTBEAT;
748 /* is this cpu idle? */
749 if (idle_cpu(raw_smp_processor_id()))
750 bits &= ~SCIR_CPU_ACTIVITY;
752 bits |= SCIR_CPU_ACTIVITY;
754 /* update system controller interface reg */
755 uv_set_scir_bits(bits);
757 /* enable next timer period */
758 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
761 static void uv_heartbeat_enable(int cpu)
763 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
764 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
766 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
767 setup_timer(timer, uv_heartbeat, cpu);
768 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
769 add_timer_on(timer, cpu);
770 uv_cpu_hub_info(cpu)->scir.enabled = 1;
772 /* also ensure that boot cpu is enabled */
777 #ifdef CONFIG_HOTPLUG_CPU
778 static void uv_heartbeat_disable(int cpu)
780 if (uv_cpu_hub_info(cpu)->scir.enabled) {
781 uv_cpu_hub_info(cpu)->scir.enabled = 0;
782 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
784 uv_set_cpu_scir_bits(cpu, 0xff);
788 * cpu hotplug notifier
790 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
793 long cpu = (long)hcpu;
797 uv_heartbeat_enable(cpu);
799 case CPU_DOWN_PREPARE:
800 uv_heartbeat_disable(cpu);
808 static __init void uv_scir_register_cpu_notifier(void)
810 hotcpu_notifier(uv_scir_cpu_notify, 0);
813 #else /* !CONFIG_HOTPLUG_CPU */
815 static __init void uv_scir_register_cpu_notifier(void)
819 static __init int uv_init_heartbeat(void)
824 for_each_online_cpu(cpu)
825 uv_heartbeat_enable(cpu);
829 late_initcall(uv_init_heartbeat);
831 #endif /* !CONFIG_HOTPLUG_CPU */
833 /* Direct Legacy VGA I/O traffic to designated IOH */
834 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
835 unsigned int command_bits, u32 flags)
839 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
840 pdev->devfn, decode, command_bits, flags);
842 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
845 if ((command_bits & PCI_COMMAND_IO) == 0)
848 domain = pci_domain_nr(pdev->bus);
849 bus = pdev->bus->number;
851 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
852 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
858 * Called on each cpu to initialize the per_cpu UV data area.
859 * FIXME: hotplug not supported yet
861 void uv_cpu_init(void)
863 /* CPU 0 initilization will be done via uv_system_init. */
867 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
869 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
870 set_x2apic_extra_bits(uv_hub_info->pnode);
873 void __init uv_system_init(void)
875 union uvh_rh_gam_config_mmr_u m_n_config;
876 union uvh_node_id_u node_id;
877 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
878 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
879 int gnode_extra, min_pnode = 999999, max_pnode = -1;
880 unsigned long mmr_base, present, paddr;
881 unsigned short pnode_mask;
882 unsigned char n_lshift;
883 char *hub = (is_uv1_hub() ? "UV100/1000" :
884 (is_uv2_hub() ? "UV2000/3000" :
885 (is_uv3_hub() ? "UV300" : NULL)));
888 pr_err("UV: Unknown/unsupported UV hub\n");
891 pr_info("UV: Found %s hub\n", hub);
893 /* We now only need to map the MMRs on UV1 */
897 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
898 m_val = m_n_config.s.m_skt;
899 n_val = m_n_config.s.n_skt;
900 pnode_mask = (1 << n_val) - 1;
901 n_lshift = get_n_lshift(m_val);
903 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
906 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
907 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
908 gnode_upper = ((unsigned long)gnode_extra << m_val);
909 pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
910 n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
913 pr_info("UV: global MMR base 0x%lx\n", mmr_base);
915 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
916 uv_possible_blades +=
917 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
919 /* uv_num_possible_blades() is really the hub count */
920 pr_info("UV: Found %d blades, %d hubs\n",
921 is_uv1_hub() ? uv_num_possible_blades() :
922 (uv_num_possible_blades() + 1) / 2,
923 uv_num_possible_blades());
925 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
926 uv_blade_info = kzalloc(bytes, GFP_KERNEL);
927 BUG_ON(!uv_blade_info);
929 for (blade = 0; blade < uv_num_possible_blades(); blade++)
930 uv_blade_info[blade].memory_nid = -1;
932 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
934 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
935 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
936 BUG_ON(!uv_node_to_blade);
937 memset(uv_node_to_blade, 255, bytes);
939 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
940 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
941 BUG_ON(!uv_cpu_to_blade);
942 memset(uv_cpu_to_blade, 255, bytes);
945 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
946 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
947 for (j = 0; j < 64; j++) {
948 if (!test_bit(j, &present))
950 pnode = (i * 64 + j) & pnode_mask;
951 uv_blade_info[blade].pnode = pnode;
952 uv_blade_info[blade].nr_possible_cpus = 0;
953 uv_blade_info[blade].nr_online_cpus = 0;
954 spin_lock_init(&uv_blade_info[blade].nmi_lock);
955 min_pnode = min(pnode, min_pnode);
956 max_pnode = max(pnode, max_pnode);
962 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
963 &sn_region_size, &system_serial_number);
966 for_each_present_cpu(cpu) {
967 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
969 nid = cpu_to_node(cpu);
971 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
973 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
974 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
975 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
977 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
978 uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
980 pnode = uv_apicid_to_pnode(apicid);
981 blade = boot_pnode_to_blade(pnode);
982 lcpu = uv_blade_info[blade].nr_possible_cpus;
983 uv_blade_info[blade].nr_possible_cpus++;
985 /* Any node on the blade, else will contain -1. */
986 uv_blade_info[blade].memory_nid = nid;
988 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
989 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
990 uv_cpu_hub_info(cpu)->m_val = m_val;
991 uv_cpu_hub_info(cpu)->n_val = n_val;
992 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
993 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
994 uv_cpu_hub_info(cpu)->pnode = pnode;
995 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
996 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
997 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
998 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
999 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
1000 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
1001 uv_node_to_blade[nid] = blade;
1002 uv_cpu_to_blade[cpu] = blade;
1005 /* Add blade/pnode info for nodes without cpus */
1006 for_each_online_node(nid) {
1007 if (uv_node_to_blade[nid] >= 0)
1009 paddr = node_start_pfn(nid) << PAGE_SHIFT;
1010 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1011 blade = boot_pnode_to_blade(pnode);
1012 uv_node_to_blade[nid] = blade;
1015 map_gru_high(max_pnode);
1016 map_mmr_high(max_pnode);
1017 map_mmioh_high(min_pnode, max_pnode);
1021 uv_scir_register_cpu_notifier();
1022 proc_mkdir("sgi_uv", NULL);
1024 /* register Legacy VGA I/O redirection handler */
1025 pci_register_set_vga_state(uv_set_vga_state);
1028 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1029 * EFI is not enabled in the kdump kernel.
1031 if (is_kdump_kernel())
1032 reboot_type = BOOT_ACPI;
1035 apic_driver(apic_x2apic_uv_x);