2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
27 #include <asm/uv/uv_mmrs.h>
28 #include <asm/uv/uv_hub.h>
29 #include <asm/current.h>
30 #include <asm/pgtable.h>
31 #include <asm/uv/bios.h>
32 #include <asm/uv/uv.h>
36 #include <asm/x86_init.h>
38 DEFINE_PER_CPU(int, x2apic_extra_bits);
40 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
42 static enum uv_system_type uv_system_type;
43 static u64 gru_start_paddr, gru_end_paddr;
44 static union uvh_apicid uvh_apicid;
45 int uv_min_hub_revision_id;
46 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
47 unsigned int uv_apicid_hibits;
48 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
49 static DEFINE_SPINLOCK(uv_nmi_lock);
51 static inline bool is_GRU_range(u64 start, u64 end)
53 return start >= gru_start_paddr && end <= gru_end_paddr;
56 static bool uv_is_untracked_pat_range(u64 start, u64 end)
58 return is_ISA_range(start, end) || is_GRU_range(start, end);
61 static int early_get_nodeid(void)
63 union uvh_node_id_u node_id;
66 mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
68 early_iounmap(mmr, sizeof(*mmr));
70 /* Currently, all blades have same revision number */
71 uv_min_hub_revision_id = node_id.s.revision;
73 return node_id.s.node_id;
76 static void __init early_get_apic_pnode_shift(void)
80 mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_APICID, sizeof(*mmr));
82 early_iounmap(mmr, sizeof(*mmr));
85 * Old bios, use default value
87 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
91 * Add an extra bit as dictated by bios to the destination apicid of
92 * interrupts potentially passing through the UV HUB. This prevents
93 * a deadlock between interrupts and IO port operations.
95 static void __init uv_set_apicid_hibit(void)
97 union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
100 mmr = early_ioremap(UV_LOCAL_MMR_BASE |
101 UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK, sizeof(*mmr));
102 apicid_mask.v = *mmr;
103 early_iounmap(mmr, sizeof(*mmr));
104 uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
107 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
111 if (!strcmp(oem_id, "SGI")) {
112 nodeid = early_get_nodeid();
113 early_get_apic_pnode_shift();
114 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
115 x86_platform.nmi_init = uv_nmi_init;
116 if (!strcmp(oem_table_id, "UVL"))
117 uv_system_type = UV_LEGACY_APIC;
118 else if (!strcmp(oem_table_id, "UVX"))
119 uv_system_type = UV_X2APIC;
120 else if (!strcmp(oem_table_id, "UVH")) {
121 __get_cpu_var(x2apic_extra_bits) =
122 nodeid << (uvh_apicid.s.pnode_shift - 1);
123 uv_system_type = UV_NON_UNIQUE_APIC;
124 uv_set_apicid_hibit();
131 enum uv_system_type get_uv_system_type(void)
133 return uv_system_type;
136 int is_uv_system(void)
138 return uv_system_type != UV_NONE;
140 EXPORT_SYMBOL_GPL(is_uv_system);
142 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
143 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
145 struct uv_blade_info *uv_blade_info;
146 EXPORT_SYMBOL_GPL(uv_blade_info);
148 short *uv_node_to_blade;
149 EXPORT_SYMBOL_GPL(uv_node_to_blade);
151 short *uv_cpu_to_blade;
152 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
154 short uv_possible_blades;
155 EXPORT_SYMBOL_GPL(uv_possible_blades);
157 unsigned long sn_rtc_cycles_per_second;
158 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
160 static const struct cpumask *uv_target_cpus(void)
162 return cpu_online_mask;
165 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
167 cpumask_clear(retmask);
168 cpumask_set_cpu(cpu, retmask);
171 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
177 pnode = uv_apicid_to_pnode(phys_apicid);
178 phys_apicid |= uv_apicid_hibits;
179 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
180 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
181 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
183 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
186 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
187 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
188 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
190 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
192 atomic_set(&init_deasserted, 1);
197 static void uv_send_IPI_one(int cpu, int vector)
199 unsigned long apicid;
202 apicid = per_cpu(x86_cpu_to_apicid, cpu);
203 pnode = uv_apicid_to_pnode(apicid);
204 uv_hub_send_ipi(pnode, apicid, vector);
207 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
211 for_each_cpu(cpu, mask)
212 uv_send_IPI_one(cpu, vector);
215 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
217 unsigned int this_cpu = smp_processor_id();
220 for_each_cpu(cpu, mask) {
222 uv_send_IPI_one(cpu, vector);
226 static void uv_send_IPI_allbutself(int vector)
228 unsigned int this_cpu = smp_processor_id();
231 for_each_online_cpu(cpu) {
233 uv_send_IPI_one(cpu, vector);
237 static void uv_send_IPI_all(int vector)
239 uv_send_IPI_mask(cpu_online_mask, vector);
242 static int uv_apic_id_registered(void)
247 static void uv_init_apic_ldr(void)
251 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
254 * We're using fixed IRQ delivery, can only return one phys APIC ID.
255 * May as well be the first.
257 int cpu = cpumask_first(cpumask);
259 if ((unsigned)cpu < nr_cpu_ids)
260 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
266 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
267 const struct cpumask *andmask)
272 * We're using fixed IRQ delivery, can only return one phys APIC ID.
273 * May as well be the first.
275 for_each_cpu_and(cpu, cpumask, andmask) {
276 if (cpumask_test_cpu(cpu, cpu_online_mask))
279 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
282 static unsigned int x2apic_get_apic_id(unsigned long x)
286 WARN_ON(preemptible() && num_online_cpus() > 1);
287 id = x | __get_cpu_var(x2apic_extra_bits);
292 static unsigned long set_apic_id(unsigned int id)
296 /* maskout x2apic_extra_bits ? */
301 static unsigned int uv_read_apic_id(void)
304 return x2apic_get_apic_id(apic_read(APIC_ID));
307 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
309 return uv_read_apic_id() >> index_msb;
312 static void uv_send_IPI_self(int vector)
314 apic_write(APIC_SELF_IPI, vector);
317 struct apic __refdata apic_x2apic_uv_x = {
319 .name = "UV large system",
321 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
322 .apic_id_registered = uv_apic_id_registered,
324 .irq_delivery_mode = dest_Fixed,
325 .irq_dest_mode = 0, /* physical */
327 .target_cpus = uv_target_cpus,
329 .dest_logical = APIC_DEST_LOGICAL,
330 .check_apicid_used = NULL,
331 .check_apicid_present = NULL,
333 .vector_allocation_domain = uv_vector_allocation_domain,
334 .init_apic_ldr = uv_init_apic_ldr,
336 .ioapic_phys_id_map = NULL,
337 .setup_apic_routing = NULL,
338 .multi_timer_check = NULL,
339 .apicid_to_node = NULL,
340 .cpu_to_logical_apicid = NULL,
341 .cpu_present_to_apicid = default_cpu_present_to_apicid,
342 .apicid_to_cpu_present = NULL,
343 .setup_portio_remap = NULL,
344 .check_phys_apicid_present = default_check_phys_apicid_present,
345 .enable_apic_mode = NULL,
346 .phys_pkg_id = uv_phys_pkg_id,
347 .mps_oem_check = NULL,
349 .get_apic_id = x2apic_get_apic_id,
350 .set_apic_id = set_apic_id,
351 .apic_id_mask = 0xFFFFFFFFu,
353 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
354 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
356 .send_IPI_mask = uv_send_IPI_mask,
357 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
358 .send_IPI_allbutself = uv_send_IPI_allbutself,
359 .send_IPI_all = uv_send_IPI_all,
360 .send_IPI_self = uv_send_IPI_self,
362 .wakeup_secondary_cpu = uv_wakeup_secondary,
363 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
364 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
365 .wait_for_init_deassert = NULL,
366 .smp_callin_clear_local_apic = NULL,
367 .inquire_remote_apic = NULL,
369 .read = native_apic_msr_read,
370 .write = native_apic_msr_write,
371 .icr_read = native_x2apic_icr_read,
372 .icr_write = native_x2apic_icr_write,
373 .wait_icr_idle = native_x2apic_wait_icr_idle,
374 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
377 static __cpuinit void set_x2apic_extra_bits(int pnode)
379 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
383 * Called on boot cpu.
385 static __init int boot_pnode_to_blade(int pnode)
389 for (blade = 0; blade < uv_num_possible_blades(); blade++)
390 if (pnode == uv_blade_info[blade].pnode)
396 unsigned long redirect;
400 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
402 static __initdata struct redir_addr redir_addrs[] = {
403 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
404 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
405 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
408 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
410 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
411 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
414 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
415 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
416 if (alias.s.enable && alias.s.base == 0) {
417 *size = (1UL << alias.s.m_alias);
418 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
419 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
426 enum map_type {map_wb, map_uc};
428 static __init void map_high(char *id, unsigned long base, int pshift,
429 int bshift, int max_pnode, enum map_type map_type)
431 unsigned long bytes, paddr;
433 paddr = base << pshift;
434 bytes = (1UL << bshift) * (max_pnode + 1);
435 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
437 if (map_type == map_uc)
438 init_extra_mapping_uc(paddr, bytes);
440 init_extra_mapping_wb(paddr, bytes);
443 static __init void map_gru_high(int max_pnode)
445 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
446 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
448 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
450 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
451 gru_start_paddr = ((u64)gru.s.base << shift);
452 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
457 static __init void map_mmr_high(int max_pnode)
459 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
460 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
462 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
464 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
467 static __init void map_mmioh_high(int max_pnode)
469 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
470 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
472 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
474 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
478 static __init void map_low_mmrs(void)
480 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
481 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
484 static __init void uv_rtc_init(void)
489 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
491 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
493 "unable to determine platform RTC clock frequency, "
495 /* BIOS gives wrong value for clock freq. so guess */
496 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
498 sn_rtc_cycles_per_second = ticks_per_sec;
502 * percpu heartbeat timer
504 static void uv_heartbeat(unsigned long ignored)
506 struct timer_list *timer = &uv_hub_info->scir.timer;
507 unsigned char bits = uv_hub_info->scir.state;
509 /* flip heartbeat bit */
510 bits ^= SCIR_CPU_HEARTBEAT;
512 /* is this cpu idle? */
513 if (idle_cpu(raw_smp_processor_id()))
514 bits &= ~SCIR_CPU_ACTIVITY;
516 bits |= SCIR_CPU_ACTIVITY;
518 /* update system controller interface reg */
519 uv_set_scir_bits(bits);
521 /* enable next timer period */
522 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
525 static void __cpuinit uv_heartbeat_enable(int cpu)
527 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
528 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
530 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
531 setup_timer(timer, uv_heartbeat, cpu);
532 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
533 add_timer_on(timer, cpu);
534 uv_cpu_hub_info(cpu)->scir.enabled = 1;
536 /* also ensure that boot cpu is enabled */
541 #ifdef CONFIG_HOTPLUG_CPU
542 static void __cpuinit uv_heartbeat_disable(int cpu)
544 if (uv_cpu_hub_info(cpu)->scir.enabled) {
545 uv_cpu_hub_info(cpu)->scir.enabled = 0;
546 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
548 uv_set_cpu_scir_bits(cpu, 0xff);
552 * cpu hotplug notifier
554 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
555 unsigned long action, void *hcpu)
557 long cpu = (long)hcpu;
561 uv_heartbeat_enable(cpu);
563 case CPU_DOWN_PREPARE:
564 uv_heartbeat_disable(cpu);
572 static __init void uv_scir_register_cpu_notifier(void)
574 hotcpu_notifier(uv_scir_cpu_notify, 0);
577 #else /* !CONFIG_HOTPLUG_CPU */
579 static __init void uv_scir_register_cpu_notifier(void)
583 static __init int uv_init_heartbeat(void)
588 for_each_online_cpu(cpu)
589 uv_heartbeat_enable(cpu);
593 late_initcall(uv_init_heartbeat);
595 #endif /* !CONFIG_HOTPLUG_CPU */
597 /* Direct Legacy VGA I/O traffic to designated IOH */
598 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
599 unsigned int command_bits, bool change_bridge)
603 PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
604 pdev->devfn, decode, command_bits, change_bridge);
609 if ((command_bits & PCI_COMMAND_IO) == 0)
612 domain = pci_domain_nr(pdev->bus);
613 bus = pdev->bus->number;
615 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
616 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
622 * Called on each cpu to initialize the per_cpu UV data area.
623 * FIXME: hotplug not supported yet
625 void __cpuinit uv_cpu_init(void)
627 /* CPU 0 initilization will be done via uv_system_init. */
631 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
633 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
634 set_x2apic_extra_bits(uv_hub_info->pnode);
638 * When NMI is received, print a stack trace.
640 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
642 if (reason != DIE_NMIUNKNOWN)
646 /* do nothing if entering the crash kernel */
649 * Use a lock so only one cpu prints at a time
650 * to prevent intermixed output.
652 spin_lock(&uv_nmi_lock);
653 pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
655 spin_unlock(&uv_nmi_lock);
660 static struct notifier_block uv_dump_stack_nmi_nb = {
661 .notifier_call = uv_handle_nmi
664 void uv_register_nmi_notifier(void)
666 if (register_die_notifier(&uv_dump_stack_nmi_nb))
667 printk(KERN_WARNING "UV NMI handler failed to register\n");
670 void uv_nmi_init(void)
675 * Unmask NMI on all cpus
677 value = apic_read(APIC_LVT1) | APIC_DM_NMI;
678 value &= ~APIC_LVT_MASKED;
679 apic_write(APIC_LVT1, value);
682 void __init uv_system_init(void)
684 union uvh_rh_gam_config_mmr_u m_n_config;
685 union uvh_node_id_u node_id;
686 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
687 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
688 int gnode_extra, max_pnode = 0;
689 unsigned long mmr_base, present, paddr;
690 unsigned short pnode_mask;
694 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
695 m_val = m_n_config.s.m_skt;
696 n_val = m_n_config.s.n_skt;
698 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
700 pnode_mask = (1 << n_val) - 1;
701 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
702 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
703 gnode_upper = ((unsigned long)gnode_extra << m_val);
704 printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
705 n_val, m_val, gnode_upper, gnode_extra);
707 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
709 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
710 uv_possible_blades +=
711 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
712 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
714 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
715 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
716 BUG_ON(!uv_blade_info);
717 for (blade = 0; blade < uv_num_possible_blades(); blade++)
718 uv_blade_info[blade].memory_nid = -1;
720 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
722 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
723 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
724 BUG_ON(!uv_node_to_blade);
725 memset(uv_node_to_blade, 255, bytes);
727 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
728 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
729 BUG_ON(!uv_cpu_to_blade);
730 memset(uv_cpu_to_blade, 255, bytes);
733 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
734 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
735 for (j = 0; j < 64; j++) {
736 if (!test_bit(j, &present))
738 pnode = (i * 64 + j);
739 uv_blade_info[blade].pnode = pnode;
740 uv_blade_info[blade].nr_possible_cpus = 0;
741 uv_blade_info[blade].nr_online_cpus = 0;
742 max_pnode = max(pnode, max_pnode);
748 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
749 &sn_region_size, &system_serial_number);
752 for_each_present_cpu(cpu) {
753 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
755 nid = cpu_to_node(cpu);
757 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
759 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
760 pnode = uv_apicid_to_pnode(apicid);
761 blade = boot_pnode_to_blade(pnode);
762 lcpu = uv_blade_info[blade].nr_possible_cpus;
763 uv_blade_info[blade].nr_possible_cpus++;
765 /* Any node on the blade, else will contain -1. */
766 uv_blade_info[blade].memory_nid = nid;
768 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
769 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
770 uv_cpu_hub_info(cpu)->m_val = m_val;
771 uv_cpu_hub_info(cpu)->n_val = n_val;
772 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
773 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
774 uv_cpu_hub_info(cpu)->pnode = pnode;
775 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
776 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
777 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
778 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
779 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
780 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
781 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
782 uv_node_to_blade[nid] = blade;
783 uv_cpu_to_blade[cpu] = blade;
786 /* Add blade/pnode info for nodes without cpus */
787 for_each_online_node(nid) {
788 if (uv_node_to_blade[nid] >= 0)
790 paddr = node_start_pfn(nid) << PAGE_SHIFT;
791 paddr = uv_soc_phys_ram_to_gpa(paddr);
792 pnode = (paddr >> m_val) & pnode_mask;
793 blade = boot_pnode_to_blade(pnode);
794 uv_node_to_blade[nid] = blade;
797 map_gru_high(max_pnode);
798 map_mmr_high(max_pnode);
799 map_mmioh_high(max_pnode);
802 uv_scir_register_cpu_notifier();
803 uv_register_nmi_notifier();
804 proc_mkdir("sgi_uv", NULL);
806 /* register Legacy VGA I/O redirection handler */
807 pci_register_set_vga_state(uv_set_vga_state);