2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/arch_hooks.h>
38 #include <asm/pgalloc.h>
39 #include <asm/genapic.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
52 unsigned int num_processors;
54 unsigned disabled_cpus __cpuinitdata;
56 /* Processor that is doing the boot up */
57 unsigned int boot_cpu_physical_apicid = -1U;
60 * The highest APIC ID seen during enumeration.
62 * This determines the messaging protocol we can use: if all APIC IDs
63 * are in the 0 ... 7 range, then we can use logical addressing which
64 * has some performance advantages (better broadcasting).
66 * If there's an APIC ID above 8, we use physical addressing.
68 unsigned int max_physical_apicid;
71 * Bitmask of physically existing CPUs:
73 physid_mask_t phys_cpu_present_map;
76 * Map cpu index to physical APIC ID
78 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
79 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
85 * Knob to control our willingness to enable the local APIC.
89 static int force_enable_local_apic;
91 * APIC command line parameters
93 static int __init parse_lapic(char *arg)
95 force_enable_local_apic = 1;
98 early_param("lapic", parse_lapic);
99 /* Local APIC was disabled by the BIOS and enabled by the kernel */
100 static int enabled_via_apicbase;
105 static int apic_calibrate_pmtmr __initdata;
106 static __init int setup_apicpmtimer(char *s)
108 apic_calibrate_pmtmr = 1;
112 __setup("apicpmtimer", setup_apicpmtimer);
121 /* x2apic enabled before OS handover */
122 static int x2apic_preenabled;
123 static int disable_x2apic;
124 static __init int setup_nox2apic(char *str)
127 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
130 early_param("nox2apic", setup_nox2apic);
133 unsigned long mp_lapic_addr;
135 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
136 static int disable_apic_timer __cpuinitdata;
137 /* Local APIC timer works in C2 */
138 int local_apic_timer_c2_ok;
139 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
141 int first_system_vector = 0xfe;
144 * Debug level, exported for io_apic.c
146 unsigned int apic_verbosity;
150 /* Have we found an MP table */
151 int smp_found_config;
153 static struct resource lapic_resource = {
154 .name = "Local APIC",
155 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
158 static unsigned int calibration_result;
160 static int lapic_next_event(unsigned long delta,
161 struct clock_event_device *evt);
162 static void lapic_timer_setup(enum clock_event_mode mode,
163 struct clock_event_device *evt);
164 static void lapic_timer_broadcast(const struct cpumask *mask);
165 static void apic_pm_activate(void);
168 * The local apic timer can be used for any function which is CPU local.
170 static struct clock_event_device lapic_clockevent = {
172 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
173 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
175 .set_mode = lapic_timer_setup,
176 .set_next_event = lapic_next_event,
177 .broadcast = lapic_timer_broadcast,
181 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
183 static unsigned long apic_phys;
186 * Get the LAPIC version
188 static inline int lapic_get_version(void)
190 return GET_APIC_VERSION(apic_read(APIC_LVR));
194 * Check, if the APIC is integrated or a separate chip
196 static inline int lapic_is_integrated(void)
201 return APIC_INTEGRATED(lapic_get_version());
206 * Check, whether this is a modern or a first generation APIC
208 static int modern_apic(void)
210 /* AMD systems use old APIC versions, so check the CPU */
211 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
212 boot_cpu_data.x86 >= 0xf)
214 return lapic_get_version() >= 0x14;
218 * Paravirt kernels also might be using these below ops. So we still
219 * use generic apic_read()/apic_write(), which might be pointing to different
220 * ops in PARAVIRT case.
222 void xapic_wait_icr_idle(void)
224 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
228 u32 safe_xapic_wait_icr_idle(void)
235 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
239 } while (timeout++ < 1000);
244 void xapic_icr_write(u32 low, u32 id)
246 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
247 apic_write(APIC_ICR, low);
250 static u64 xapic_icr_read(void)
254 icr2 = apic_read(APIC_ICR2);
255 icr1 = apic_read(APIC_ICR);
257 return icr1 | ((u64)icr2 << 32);
260 static struct apic_ops xapic_ops = {
261 .read = native_apic_mem_read,
262 .write = native_apic_mem_write,
263 .icr_read = xapic_icr_read,
264 .icr_write = xapic_icr_write,
265 .wait_icr_idle = xapic_wait_icr_idle,
266 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
269 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
270 EXPORT_SYMBOL_GPL(apic_ops);
273 static void x2apic_wait_icr_idle(void)
275 /* no need to wait for icr idle in x2apic */
279 static u32 safe_x2apic_wait_icr_idle(void)
281 /* no need to wait for icr idle in x2apic */
285 void x2apic_icr_write(u32 low, u32 id)
287 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
290 static u64 x2apic_icr_read(void)
294 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
298 static struct apic_ops x2apic_ops = {
299 .read = native_apic_msr_read,
300 .write = native_apic_msr_write,
301 .icr_read = x2apic_icr_read,
302 .icr_write = x2apic_icr_write,
303 .wait_icr_idle = x2apic_wait_icr_idle,
304 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
309 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
311 void __cpuinit enable_NMI_through_LVT0(void)
315 /* unmask and set to NMI */
318 /* Level triggered for 82489DX (32bit mode) */
319 if (!lapic_is_integrated())
320 v |= APIC_LVT_LEVEL_TRIGGER;
322 apic_write(APIC_LVT0, v);
327 * get_physical_broadcast - Get number of physical broadcast IDs
329 int get_physical_broadcast(void)
331 return modern_apic() ? 0xff : 0xf;
336 * lapic_get_maxlvt - get the maximum number of local vector table entries
338 int lapic_get_maxlvt(void)
342 v = apic_read(APIC_LVR);
344 * - we always have APIC integrated on 64bit mode
345 * - 82489DXs do not report # of LVT entries
347 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
355 #define APIC_DIVISOR 16
358 * This function sets up the local APIC timer, with a timeout of
359 * 'clocks' APIC bus clock. During calibration we actually call
360 * this function twice on the boot CPU, once with a bogus timeout
361 * value, second time for real. The other (noncalibrating) CPUs
362 * call this function only once, with the real, calibrated value.
364 * We do reads before writes even if unnecessary, to get around the
365 * P5 APIC double write bug.
367 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
369 unsigned int lvtt_value, tmp_value;
371 lvtt_value = LOCAL_TIMER_VECTOR;
373 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
374 if (!lapic_is_integrated())
375 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
378 lvtt_value |= APIC_LVT_MASKED;
380 apic_write(APIC_LVTT, lvtt_value);
385 tmp_value = apic_read(APIC_TDCR);
386 apic_write(APIC_TDCR,
387 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
391 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
395 * Setup extended LVT, AMD specific (K8, family 10h)
397 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
398 * MCE interrupts are supported. Thus MCE offset must be set to 0.
400 * If mask=1, the LVT entry does not generate interrupts while mask=0
401 * enables the vector. See also the BKDGs.
404 #define APIC_EILVT_LVTOFF_MCE 0
405 #define APIC_EILVT_LVTOFF_IBS 1
407 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
409 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
410 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
415 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
417 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
418 return APIC_EILVT_LVTOFF_MCE;
421 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
423 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
424 return APIC_EILVT_LVTOFF_IBS;
426 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
429 * Program the next event, relative to now
431 static int lapic_next_event(unsigned long delta,
432 struct clock_event_device *evt)
434 apic_write(APIC_TMICT, delta);
439 * Setup the lapic timer in periodic or oneshot mode
441 static void lapic_timer_setup(enum clock_event_mode mode,
442 struct clock_event_device *evt)
447 /* Lapic used as dummy for broadcast ? */
448 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
451 local_irq_save(flags);
454 case CLOCK_EVT_MODE_PERIODIC:
455 case CLOCK_EVT_MODE_ONESHOT:
456 __setup_APIC_LVTT(calibration_result,
457 mode != CLOCK_EVT_MODE_PERIODIC, 1);
459 case CLOCK_EVT_MODE_UNUSED:
460 case CLOCK_EVT_MODE_SHUTDOWN:
461 v = apic_read(APIC_LVTT);
462 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
463 apic_write(APIC_LVTT, v);
464 apic_write(APIC_TMICT, 0xffffffff);
466 case CLOCK_EVT_MODE_RESUME:
467 /* Nothing to do here */
471 local_irq_restore(flags);
475 * Local APIC timer broadcast function
477 static void lapic_timer_broadcast(const struct cpumask *mask)
480 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
485 * Setup the local APIC timer for this CPU. Copy the initilized values
486 * of the boot CPU and register the clock event in the framework.
488 static void __cpuinit setup_APIC_timer(void)
490 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
492 memcpy(levt, &lapic_clockevent, sizeof(*levt));
493 levt->cpumask = cpumask_of(smp_processor_id());
495 clockevents_register_device(levt);
499 * In this functions we calibrate APIC bus clocks to the external timer.
501 * We want to do the calibration only once since we want to have local timer
502 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
505 * This was previously done by reading the PIT/HPET and waiting for a wrap
506 * around to find out, that a tick has elapsed. I have a box, where the PIT
507 * readout is broken, so it never gets out of the wait loop again. This was
508 * also reported by others.
510 * Monitoring the jiffies value is inaccurate and the clockevents
511 * infrastructure allows us to do a simple substitution of the interrupt
514 * The calibration routine also uses the pm_timer when possible, as the PIT
515 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
516 * back to normal later in the boot process).
519 #define LAPIC_CAL_LOOPS (HZ/10)
521 static __initdata int lapic_cal_loops = -1;
522 static __initdata long lapic_cal_t1, lapic_cal_t2;
523 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
524 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
525 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
528 * Temporary interrupt handler.
530 static void __init lapic_cal_handler(struct clock_event_device *dev)
532 unsigned long long tsc = 0;
533 long tapic = apic_read(APIC_TMCCT);
534 unsigned long pm = acpi_pm_read_early();
539 switch (lapic_cal_loops++) {
541 lapic_cal_t1 = tapic;
542 lapic_cal_tsc1 = tsc;
544 lapic_cal_j1 = jiffies;
547 case LAPIC_CAL_LOOPS:
548 lapic_cal_t2 = tapic;
549 lapic_cal_tsc2 = tsc;
550 if (pm < lapic_cal_pm1)
551 pm += ACPI_PM_OVRRUN;
553 lapic_cal_j2 = jiffies;
559 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
561 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
562 const long pm_thresh = pm_100ms / 100;
566 #ifndef CONFIG_X86_PM_TIMER
570 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
572 /* Check, if the PM timer is available */
576 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
578 if (deltapm > (pm_100ms - pm_thresh) &&
579 deltapm < (pm_100ms + pm_thresh)) {
580 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
584 res = (((u64)deltapm) * mult) >> 22;
585 do_div(res, 1000000);
586 pr_warning("APIC calibration not consistent "
587 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
589 /* Correct the lapic counter value */
590 res = (((u64)(*delta)) * pm_100ms);
591 do_div(res, deltapm);
592 pr_info("APIC delta adjusted to PM-Timer: "
593 "%lu (%ld)\n", (unsigned long)res, *delta);
596 /* Correct the tsc counter value */
598 res = (((u64)(*deltatsc)) * pm_100ms);
599 do_div(res, deltapm);
600 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
601 "PM-Timer: %lu (%ld) \n",
602 (unsigned long)res, *deltatsc);
603 *deltatsc = (long)res;
609 static int __init calibrate_APIC_clock(void)
611 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
612 void (*real_handler)(struct clock_event_device *dev);
613 unsigned long deltaj;
614 long delta, deltatsc;
615 int pm_referenced = 0;
619 /* Replace the global interrupt handler */
620 real_handler = global_clock_event->event_handler;
621 global_clock_event->event_handler = lapic_cal_handler;
624 * Setup the APIC counter to maximum. There is no way the lapic
625 * can underflow in the 100ms detection time frame
627 __setup_APIC_LVTT(0xffffffff, 0, 0);
629 /* Let the interrupts run */
632 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
637 /* Restore the real event handler */
638 global_clock_event->event_handler = real_handler;
640 /* Build delta t1-t2 as apic timer counts down */
641 delta = lapic_cal_t1 - lapic_cal_t2;
642 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
644 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
646 /* we trust the PM based calibration if possible */
647 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
650 /* Calculate the scaled math multiplication factor */
651 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
652 lapic_clockevent.shift);
653 lapic_clockevent.max_delta_ns =
654 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
655 lapic_clockevent.min_delta_ns =
656 clockevent_delta2ns(0xF, &lapic_clockevent);
658 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
660 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
661 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
662 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
666 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
668 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
669 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
672 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
674 calibration_result / (1000000 / HZ),
675 calibration_result % (1000000 / HZ));
678 * Do a sanity check on the APIC calibration result
680 if (calibration_result < (1000000 / HZ)) {
682 pr_warning("APIC frequency too slow, disabling apic timer\n");
686 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
689 * PM timer calibration failed or not turned on
690 * so lets try APIC timer based calibration
692 if (!pm_referenced) {
693 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
696 * Setup the apic timer manually
698 levt->event_handler = lapic_cal_handler;
699 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
700 lapic_cal_loops = -1;
702 /* Let the interrupts run */
705 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
708 /* Stop the lapic timer */
709 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
712 deltaj = lapic_cal_j2 - lapic_cal_j1;
713 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
715 /* Check, if the jiffies result is consistent */
716 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
717 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
719 levt->features |= CLOCK_EVT_FEAT_DUMMY;
723 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
724 pr_warning("APIC timer disabled due to verification failure\n");
732 * Setup the boot APIC
734 * Calibrate and verify the result.
736 void __init setup_boot_APIC_clock(void)
739 * The local apic timer can be disabled via the kernel
740 * commandline or from the CPU detection code. Register the lapic
741 * timer as a dummy clock event source on SMP systems, so the
742 * broadcast mechanism is used. On UP systems simply ignore it.
744 if (disable_apic_timer) {
745 pr_info("Disabling APIC timer\n");
746 /* No broadcast on UP ! */
747 if (num_possible_cpus() > 1) {
748 lapic_clockevent.mult = 1;
754 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
755 "calibrating APIC timer ...\n");
757 if (calibrate_APIC_clock()) {
758 /* No broadcast on UP ! */
759 if (num_possible_cpus() > 1)
765 * If nmi_watchdog is set to IO_APIC, we need the
766 * PIT/HPET going. Otherwise register lapic as a dummy
769 if (nmi_watchdog != NMI_IO_APIC)
770 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
772 pr_warning("APIC timer registered as dummy,"
773 " due to nmi_watchdog=%d!\n", nmi_watchdog);
775 /* Setup the lapic or request the broadcast */
779 void __cpuinit setup_secondary_APIC_clock(void)
785 * The guts of the apic timer interrupt
787 static void local_apic_timer_interrupt(void)
789 int cpu = smp_processor_id();
790 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
793 * Normally we should not be here till LAPIC has been initialized but
794 * in some cases like kdump, its possible that there is a pending LAPIC
795 * timer interrupt from previous kernel's context and is delivered in
796 * new kernel the moment interrupts are enabled.
798 * Interrupts are enabled early and LAPIC is setup much later, hence
799 * its possible that when we get here evt->event_handler is NULL.
800 * Check for event_handler being NULL and discard the interrupt as
803 if (!evt->event_handler) {
804 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
806 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
811 * the NMI deadlock-detector uses this.
813 inc_irq_stat(apic_timer_irqs);
815 evt->event_handler(evt);
819 * Local APIC timer interrupt. This is the most natural way for doing
820 * local interrupts, but local timer interrupts can be emulated by
821 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
823 * [ if a single-CPU system runs an SMP kernel then we call the local
824 * interrupt as well. Thus we cannot inline the local irq ... ]
826 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
828 struct pt_regs *old_regs = set_irq_regs(regs);
831 * NOTE! We'd better ACK the irq immediately,
832 * because timer handling can be slow.
836 * update_process_times() expects us to have done irq_enter().
837 * Besides, if we don't timer interrupts ignore the global
838 * interrupt lock, which is the WrongThing (tm) to do.
842 local_apic_timer_interrupt();
845 set_irq_regs(old_regs);
848 int setup_profiling_timer(unsigned int multiplier)
854 * Local APIC start and shutdown
858 * clear_local_APIC - shutdown the local APIC
860 * This is called, when a CPU is disabled and before rebooting, so the state of
861 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
862 * leftovers during boot.
864 void clear_local_APIC(void)
869 /* APIC hasn't been mapped yet */
873 maxlvt = lapic_get_maxlvt();
875 * Masking an LVT entry can trigger a local APIC error
876 * if the vector is zero. Mask LVTERR first to prevent this.
879 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
880 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
883 * Careful: we have to set masks only first to deassert
884 * any level-triggered sources.
886 v = apic_read(APIC_LVTT);
887 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
888 v = apic_read(APIC_LVT0);
889 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
890 v = apic_read(APIC_LVT1);
891 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
893 v = apic_read(APIC_LVTPC);
894 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
897 /* lets not touch this if we didn't frob it */
898 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
900 v = apic_read(APIC_LVTTHMR);
901 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
905 * Clean APIC state for other OSs:
907 apic_write(APIC_LVTT, APIC_LVT_MASKED);
908 apic_write(APIC_LVT0, APIC_LVT_MASKED);
909 apic_write(APIC_LVT1, APIC_LVT_MASKED);
911 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
913 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
915 /* Integrated APIC (!82489DX) ? */
916 if (lapic_is_integrated()) {
918 /* Clear ESR due to Pentium errata 3AP and 11AP */
919 apic_write(APIC_ESR, 0);
925 * disable_local_APIC - clear and disable the local APIC
927 void disable_local_APIC(void)
931 /* APIC hasn't been mapped yet */
938 * Disable APIC (implies clearing of registers
941 value = apic_read(APIC_SPIV);
942 value &= ~APIC_SPIV_APIC_ENABLED;
943 apic_write(APIC_SPIV, value);
947 * When LAPIC was disabled by the BIOS and enabled by the kernel,
948 * restore the disabled state.
950 if (enabled_via_apicbase) {
953 rdmsr(MSR_IA32_APICBASE, l, h);
954 l &= ~MSR_IA32_APICBASE_ENABLE;
955 wrmsr(MSR_IA32_APICBASE, l, h);
961 * If Linux enabled the LAPIC against the BIOS default disable it down before
962 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
963 * not power-off. Additionally clear all LVT entries before disable_local_APIC
964 * for the case where Linux didn't enable the LAPIC.
966 void lapic_shutdown(void)
973 local_irq_save(flags);
976 if (!enabled_via_apicbase)
980 disable_local_APIC();
983 local_irq_restore(flags);
987 * This is to verify that we're looking at a real local APIC.
988 * Check these against your board if the CPUs aren't getting
989 * started for no apparent reason.
991 int __init verify_local_APIC(void)
993 unsigned int reg0, reg1;
996 * The version register is read-only in a real APIC.
998 reg0 = apic_read(APIC_LVR);
999 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1000 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1001 reg1 = apic_read(APIC_LVR);
1002 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1005 * The two version reads above should print the same
1006 * numbers. If the second one is different, then we
1007 * poke at a non-APIC.
1013 * Check if the version looks reasonably.
1015 reg1 = GET_APIC_VERSION(reg0);
1016 if (reg1 == 0x00 || reg1 == 0xff)
1018 reg1 = lapic_get_maxlvt();
1019 if (reg1 < 0x02 || reg1 == 0xff)
1023 * The ID register is read/write in a real APIC.
1025 reg0 = apic_read(APIC_ID);
1026 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1027 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1028 reg1 = apic_read(APIC_ID);
1029 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1030 apic_write(APIC_ID, reg0);
1031 if (reg1 != (reg0 ^ apic->apic_id_mask))
1035 * The next two are just to see if we have sane values.
1036 * They're only really relevant if we're in Virtual Wire
1037 * compatibility mode, but most boxes are anymore.
1039 reg0 = apic_read(APIC_LVT0);
1040 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1041 reg1 = apic_read(APIC_LVT1);
1042 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1048 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1050 void __init sync_Arb_IDs(void)
1053 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1056 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1062 apic_wait_icr_idle();
1064 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1065 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1066 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1070 * An initial setup of the virtual wire mode.
1072 void __init init_bsp_APIC(void)
1077 * Don't do the setup now if we have a SMP BIOS as the
1078 * through-I/O-APIC virtual wire mode might be active.
1080 if (smp_found_config || !cpu_has_apic)
1084 * Do not trust the local APIC being empty at bootup.
1091 value = apic_read(APIC_SPIV);
1092 value &= ~APIC_VECTOR_MASK;
1093 value |= APIC_SPIV_APIC_ENABLED;
1095 #ifdef CONFIG_X86_32
1096 /* This bit is reserved on P4/Xeon and should be cleared */
1097 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1098 (boot_cpu_data.x86 == 15))
1099 value &= ~APIC_SPIV_FOCUS_DISABLED;
1102 value |= APIC_SPIV_FOCUS_DISABLED;
1103 value |= SPURIOUS_APIC_VECTOR;
1104 apic_write(APIC_SPIV, value);
1107 * Set up the virtual wire mode.
1109 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1110 value = APIC_DM_NMI;
1111 if (!lapic_is_integrated()) /* 82489DX */
1112 value |= APIC_LVT_LEVEL_TRIGGER;
1113 apic_write(APIC_LVT1, value);
1116 static void __cpuinit lapic_setup_esr(void)
1118 unsigned int oldvalue, value, maxlvt;
1120 if (!lapic_is_integrated()) {
1121 pr_info("No ESR for 82489DX.\n");
1125 if (apic->disable_esr) {
1127 * Something untraceable is creating bad interrupts on
1128 * secondary quads ... for the moment, just leave the
1129 * ESR disabled - we can't do anything useful with the
1130 * errors anyway - mbligh
1132 pr_info("Leaving ESR disabled.\n");
1136 maxlvt = lapic_get_maxlvt();
1137 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1138 apic_write(APIC_ESR, 0);
1139 oldvalue = apic_read(APIC_ESR);
1141 /* enables sending errors */
1142 value = ERROR_APIC_VECTOR;
1143 apic_write(APIC_LVTERR, value);
1146 * spec says clear errors after enabling vector.
1149 apic_write(APIC_ESR, 0);
1150 value = apic_read(APIC_ESR);
1151 if (value != oldvalue)
1152 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1153 "vector: 0x%08x after: 0x%08x\n",
1159 * setup_local_APIC - setup the local APIC
1161 void __cpuinit setup_local_APIC(void)
1167 arch_disable_smp_support();
1171 #ifdef CONFIG_X86_32
1172 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1173 if (lapic_is_integrated() && apic->disable_esr) {
1174 apic_write(APIC_ESR, 0);
1175 apic_write(APIC_ESR, 0);
1176 apic_write(APIC_ESR, 0);
1177 apic_write(APIC_ESR, 0);
1184 * Double-check whether this APIC is really registered.
1185 * This is meaningless in clustered apic mode, so we skip it.
1187 if (!apic->apic_id_registered())
1191 * Intel recommends to set DFR, LDR and TPR before enabling
1192 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1193 * document number 292116). So here it goes...
1195 apic->init_apic_ldr();
1198 * Set Task Priority to 'accept all'. We never change this
1201 value = apic_read(APIC_TASKPRI);
1202 value &= ~APIC_TPRI_MASK;
1203 apic_write(APIC_TASKPRI, value);
1206 * After a crash, we no longer service the interrupts and a pending
1207 * interrupt from previous kernel might still have ISR bit set.
1209 * Most probably by now CPU has serviced that pending interrupt and
1210 * it might not have done the ack_APIC_irq() because it thought,
1211 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1212 * does not clear the ISR bit and cpu thinks it has already serivced
1213 * the interrupt. Hence a vector might get locked. It was noticed
1214 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1216 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1217 value = apic_read(APIC_ISR + i*0x10);
1218 for (j = 31; j >= 0; j--) {
1225 * Now that we are all set up, enable the APIC
1227 value = apic_read(APIC_SPIV);
1228 value &= ~APIC_VECTOR_MASK;
1232 value |= APIC_SPIV_APIC_ENABLED;
1234 #ifdef CONFIG_X86_32
1236 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1237 * certain networking cards. If high frequency interrupts are
1238 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1239 * entry is masked/unmasked at a high rate as well then sooner or
1240 * later IOAPIC line gets 'stuck', no more interrupts are received
1241 * from the device. If focus CPU is disabled then the hang goes
1244 * [ This bug can be reproduced easily with a level-triggered
1245 * PCI Ne2000 networking cards and PII/PIII processors, dual
1249 * Actually disabling the focus CPU check just makes the hang less
1250 * frequent as it makes the interrupt distributon model be more
1251 * like LRU than MRU (the short-term load is more even across CPUs).
1252 * See also the comment in end_level_ioapic_irq(). --macro
1256 * - enable focus processor (bit==0)
1257 * - 64bit mode always use processor focus
1258 * so no need to set it
1260 value &= ~APIC_SPIV_FOCUS_DISABLED;
1264 * Set spurious IRQ vector
1266 value |= SPURIOUS_APIC_VECTOR;
1267 apic_write(APIC_SPIV, value);
1270 * Set up LVT0, LVT1:
1272 * set up through-local-APIC on the BP's LINT0. This is not
1273 * strictly necessary in pure symmetric-IO mode, but sometimes
1274 * we delegate interrupts to the 8259A.
1277 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1279 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1280 if (!smp_processor_id() && (pic_mode || !value)) {
1281 value = APIC_DM_EXTINT;
1282 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1283 smp_processor_id());
1285 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1286 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1287 smp_processor_id());
1289 apic_write(APIC_LVT0, value);
1292 * only the BP should see the LINT1 NMI signal, obviously.
1294 if (!smp_processor_id())
1295 value = APIC_DM_NMI;
1297 value = APIC_DM_NMI | APIC_LVT_MASKED;
1298 if (!lapic_is_integrated()) /* 82489DX */
1299 value |= APIC_LVT_LEVEL_TRIGGER;
1300 apic_write(APIC_LVT1, value);
1305 void __cpuinit end_local_APIC_setup(void)
1309 #ifdef CONFIG_X86_32
1312 /* Disable the local apic timer */
1313 value = apic_read(APIC_LVTT);
1314 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1315 apic_write(APIC_LVTT, value);
1319 setup_apic_nmi_watchdog(NULL);
1324 void check_x2apic(void)
1328 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1330 if (msr & X2APIC_ENABLE) {
1331 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1332 x2apic_preenabled = x2apic = 1;
1333 apic_ops = &x2apic_ops;
1337 void enable_x2apic(void)
1341 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1342 if (!(msr & X2APIC_ENABLE)) {
1343 pr_info("Enabling x2apic\n");
1344 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1348 void __init enable_IR_x2apic(void)
1350 #ifdef CONFIG_INTR_REMAP
1352 unsigned long flags;
1354 if (!cpu_has_x2apic)
1357 if (!x2apic_preenabled && disable_x2apic) {
1358 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1359 "because of nox2apic\n");
1363 if (x2apic_preenabled && disable_x2apic)
1364 panic("Bios already enabled x2apic, can't enforce nox2apic");
1366 if (!x2apic_preenabled && skip_ioapic_setup) {
1367 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1368 "because of skipping io-apic setup\n");
1372 ret = dmar_table_init();
1374 pr_info("dmar_table_init() failed with %d:\n", ret);
1376 if (x2apic_preenabled)
1377 panic("x2apic enabled by bios. But IR enabling failed");
1379 pr_info("Not enabling x2apic,Intr-remapping\n");
1383 local_irq_save(flags);
1386 ret = save_mask_IO_APIC_setup();
1388 pr_info("Saving IO-APIC state failed: %d\n", ret);
1392 ret = enable_intr_remapping(1);
1394 if (ret && x2apic_preenabled) {
1395 local_irq_restore(flags);
1396 panic("x2apic enabled by bios. But IR enabling failed");
1404 apic_ops = &x2apic_ops;
1411 * IR enabling failed
1413 restore_IO_APIC_setup();
1415 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1419 local_irq_restore(flags);
1422 if (!x2apic_preenabled)
1423 pr_info("Enabled x2apic and interrupt-remapping\n");
1425 pr_info("Enabled Interrupt-remapping\n");
1427 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1429 if (!cpu_has_x2apic)
1432 if (x2apic_preenabled)
1433 panic("x2apic enabled prior OS handover,"
1434 " enable CONFIG_INTR_REMAP");
1436 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1442 #endif /* HAVE_X2APIC */
1444 #ifdef CONFIG_X86_64
1446 * Detect and enable local APICs on non-SMP boards.
1447 * Original code written by Keir Fraser.
1448 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1449 * not correctly set up (usually the APIC timer won't work etc.)
1451 static int __init detect_init_APIC(void)
1453 if (!cpu_has_apic) {
1454 pr_info("No local APIC present\n");
1458 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1459 boot_cpu_physical_apicid = 0;
1464 * Detect and initialize APIC
1466 static int __init detect_init_APIC(void)
1470 /* Disabled by kernel option? */
1474 switch (boot_cpu_data.x86_vendor) {
1475 case X86_VENDOR_AMD:
1476 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1477 (boot_cpu_data.x86 >= 15))
1480 case X86_VENDOR_INTEL:
1481 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1482 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1489 if (!cpu_has_apic) {
1491 * Over-ride BIOS and try to enable the local APIC only if
1492 * "lapic" specified.
1494 if (!force_enable_local_apic) {
1495 pr_info("Local APIC disabled by BIOS -- "
1496 "you can enable it with \"lapic\"\n");
1500 * Some BIOSes disable the local APIC in the APIC_BASE
1501 * MSR. This can only be done in software for Intel P6 or later
1502 * and AMD K7 (Model > 1) or later.
1504 rdmsr(MSR_IA32_APICBASE, l, h);
1505 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1506 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1507 l &= ~MSR_IA32_APICBASE_BASE;
1508 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1509 wrmsr(MSR_IA32_APICBASE, l, h);
1510 enabled_via_apicbase = 1;
1514 * The APIC feature bit should now be enabled
1517 features = cpuid_edx(1);
1518 if (!(features & (1 << X86_FEATURE_APIC))) {
1519 pr_warning("Could not enable APIC!\n");
1522 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1523 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1525 /* The BIOS may have set up the APIC at some other address */
1526 rdmsr(MSR_IA32_APICBASE, l, h);
1527 if (l & MSR_IA32_APICBASE_ENABLE)
1528 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1530 pr_info("Found and enabled local APIC!\n");
1537 pr_info("No local APIC present or hardware disabled\n");
1542 #ifdef CONFIG_X86_64
1543 void __init early_init_lapic_mapping(void)
1545 unsigned long phys_addr;
1548 * If no local APIC can be found then go out
1549 * : it means there is no mpatable and MADT
1551 if (!smp_found_config)
1554 phys_addr = mp_lapic_addr;
1556 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1557 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1558 APIC_BASE, phys_addr);
1561 * Fetch the APIC ID of the BSP in case we have a
1562 * default configuration (or the MP table is broken).
1564 boot_cpu_physical_apicid = read_apic_id();
1569 * init_apic_mappings - initialize APIC mappings
1571 void __init init_apic_mappings(void)
1575 boot_cpu_physical_apicid = read_apic_id();
1581 * If no local APIC can be found then set up a fake all
1582 * zeroes page to simulate the local APIC and another
1583 * one for the IO-APIC.
1585 if (!smp_found_config && detect_init_APIC()) {
1586 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1587 apic_phys = __pa(apic_phys);
1589 apic_phys = mp_lapic_addr;
1591 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1592 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1593 APIC_BASE, apic_phys);
1596 * Fetch the APIC ID of the BSP in case we have a
1597 * default configuration (or the MP table is broken).
1599 if (boot_cpu_physical_apicid == -1U)
1600 boot_cpu_physical_apicid = read_apic_id();
1604 * This initializes the IO-APIC and APIC hardware if this is
1607 int apic_version[MAX_APICS];
1609 int __init APIC_init_uniprocessor(void)
1612 pr_info("Apic disabled\n");
1615 #ifdef CONFIG_X86_64
1616 if (!cpu_has_apic) {
1618 pr_info("Apic disabled by BIOS\n");
1622 if (!smp_found_config && !cpu_has_apic)
1626 * Complain if the BIOS pretends there is one.
1628 if (!cpu_has_apic &&
1629 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1630 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1631 boot_cpu_physical_apicid);
1632 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1640 #ifdef CONFIG_X86_64
1641 default_setup_apic_routing();
1644 verify_local_APIC();
1647 #ifdef CONFIG_X86_64
1648 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1651 * Hack: In case of kdump, after a crash, kernel might be booting
1652 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1653 * might be zero if read from MP tables. Get it from LAPIC.
1655 # ifdef CONFIG_CRASH_DUMP
1656 boot_cpu_physical_apicid = read_apic_id();
1659 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1662 #ifdef CONFIG_X86_IO_APIC
1664 * Now enable IO-APICs, actually call clear_IO_APIC
1665 * We need clear_IO_APIC before enabling error vector
1667 if (!skip_ioapic_setup && nr_ioapics)
1671 end_local_APIC_setup();
1673 #ifdef CONFIG_X86_IO_APIC
1674 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1678 localise_nmi_watchdog();
1681 localise_nmi_watchdog();
1685 #ifdef CONFIG_X86_64
1686 check_nmi_watchdog();
1693 * Local APIC interrupts
1697 * This interrupt should _never_ happen with our APIC/SMP architecture
1699 void smp_spurious_interrupt(struct pt_regs *regs)
1706 * Check if this really is a spurious interrupt and ACK it
1707 * if it is a vectored one. Just in case...
1708 * Spurious interrupts should not be ACKed.
1710 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1711 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1714 inc_irq_stat(irq_spurious_count);
1716 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1717 pr_info("spurious APIC interrupt on CPU#%d, "
1718 "should never happen.\n", smp_processor_id());
1723 * This interrupt should never happen with our APIC/SMP architecture
1725 void smp_error_interrupt(struct pt_regs *regs)
1731 /* First tickle the hardware, only then report what went on. -- REW */
1732 v = apic_read(APIC_ESR);
1733 apic_write(APIC_ESR, 0);
1734 v1 = apic_read(APIC_ESR);
1736 atomic_inc(&irq_err_count);
1739 * Here is what the APIC error bits mean:
1741 * 1: Receive CS error
1742 * 2: Send accept error
1743 * 3: Receive accept error
1745 * 5: Send illegal vector
1746 * 6: Received illegal vector
1747 * 7: Illegal register address
1749 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1750 smp_processor_id(), v , v1);
1755 * connect_bsp_APIC - attach the APIC to the interrupt system
1757 void __init connect_bsp_APIC(void)
1759 #ifdef CONFIG_X86_32
1762 * Do not trust the local APIC being empty at bootup.
1766 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1767 * local APIC to INT and NMI lines.
1769 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1770 "enabling APIC mode.\n");
1775 if (apic->enable_apic_mode)
1776 apic->enable_apic_mode();
1780 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1781 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1783 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1786 void disconnect_bsp_APIC(int virt_wire_setup)
1790 #ifdef CONFIG_X86_32
1793 * Put the board back into PIC mode (has an effect only on
1794 * certain older boards). Note that APIC interrupts, including
1795 * IPIs, won't work beyond this point! The only exception are
1798 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1799 "entering PIC mode.\n");
1806 /* Go back to Virtual Wire compatibility mode */
1808 /* For the spurious interrupt use vector F, and enable it */
1809 value = apic_read(APIC_SPIV);
1810 value &= ~APIC_VECTOR_MASK;
1811 value |= APIC_SPIV_APIC_ENABLED;
1813 apic_write(APIC_SPIV, value);
1815 if (!virt_wire_setup) {
1817 * For LVT0 make it edge triggered, active high,
1818 * external and enabled
1820 value = apic_read(APIC_LVT0);
1821 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1822 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1823 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1824 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1825 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1826 apic_write(APIC_LVT0, value);
1829 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1833 * For LVT1 make it edge triggered, active high,
1836 value = apic_read(APIC_LVT1);
1837 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1838 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1839 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1840 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1841 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1842 apic_write(APIC_LVT1, value);
1845 void __cpuinit generic_processor_info(int apicid, int version)
1852 if (version == 0x0) {
1853 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1854 "fixing up to 0x10. (tell your hw vendor)\n",
1858 apic_version[apicid] = version;
1860 if (num_processors >= nr_cpu_ids) {
1861 int max = nr_cpu_ids;
1862 int thiscpu = max + disabled_cpus;
1865 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1866 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1873 cpu = cpumask_next_zero(-1, cpu_present_mask);
1875 if (version != apic_version[boot_cpu_physical_apicid])
1877 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1878 apic_version[boot_cpu_physical_apicid], cpu, version);
1880 physid_set(apicid, phys_cpu_present_map);
1881 if (apicid == boot_cpu_physical_apicid) {
1883 * x86_bios_cpu_apicid is required to have processors listed
1884 * in same order as logical cpu numbers. Hence the first
1885 * entry is BSP, and so on.
1889 if (apicid > max_physical_apicid)
1890 max_physical_apicid = apicid;
1892 #ifdef CONFIG_X86_32
1894 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1895 * but we need to work other dependencies like SMP_SUSPEND etc
1896 * before this can be done without some confusion.
1897 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1898 * - Ashok Raj <ashok.raj@intel.com>
1900 if (max_physical_apicid >= 8) {
1901 switch (boot_cpu_data.x86_vendor) {
1902 case X86_VENDOR_INTEL:
1903 if (!APIC_XAPIC(version)) {
1907 /* If P4 and above fall through */
1908 case X86_VENDOR_AMD:
1914 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1915 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1916 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1919 set_cpu_possible(cpu, true);
1920 set_cpu_present(cpu, true);
1923 int hard_smp_processor_id(void)
1925 return read_apic_id();
1928 void default_init_apic_ldr(void)
1932 apic_write(APIC_DFR, APIC_DFR_VALUE);
1933 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1934 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1935 apic_write(APIC_LDR, val);
1938 #ifdef CONFIG_X86_32
1939 int default_apicid_to_node(int logical_apicid)
1942 return apicid_2_node[hard_smp_processor_id()];
1956 * 'active' is true if the local APIC was enabled by us and
1957 * not the BIOS; this signifies that we are also responsible
1958 * for disabling it before entering apm/acpi suspend
1961 /* r/w apic fields */
1962 unsigned int apic_id;
1963 unsigned int apic_taskpri;
1964 unsigned int apic_ldr;
1965 unsigned int apic_dfr;
1966 unsigned int apic_spiv;
1967 unsigned int apic_lvtt;
1968 unsigned int apic_lvtpc;
1969 unsigned int apic_lvt0;
1970 unsigned int apic_lvt1;
1971 unsigned int apic_lvterr;
1972 unsigned int apic_tmict;
1973 unsigned int apic_tdcr;
1974 unsigned int apic_thmr;
1977 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1979 unsigned long flags;
1982 if (!apic_pm_state.active)
1985 maxlvt = lapic_get_maxlvt();
1987 apic_pm_state.apic_id = apic_read(APIC_ID);
1988 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1989 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1990 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1991 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1992 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1994 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1995 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1996 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1997 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1998 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1999 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2000 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2002 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2005 local_irq_save(flags);
2006 disable_local_APIC();
2007 local_irq_restore(flags);
2011 static int lapic_resume(struct sys_device *dev)
2014 unsigned long flags;
2017 if (!apic_pm_state.active)
2020 maxlvt = lapic_get_maxlvt();
2022 local_irq_save(flags);
2031 * Make sure the APICBASE points to the right address
2033 * FIXME! This will be wrong if we ever support suspend on
2034 * SMP! We'll need to do this as part of the CPU restore!
2036 rdmsr(MSR_IA32_APICBASE, l, h);
2037 l &= ~MSR_IA32_APICBASE_BASE;
2038 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2039 wrmsr(MSR_IA32_APICBASE, l, h);
2042 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2043 apic_write(APIC_ID, apic_pm_state.apic_id);
2044 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2045 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2046 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2047 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2048 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2049 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2050 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2052 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2055 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2056 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2057 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2058 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2059 apic_write(APIC_ESR, 0);
2060 apic_read(APIC_ESR);
2061 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2062 apic_write(APIC_ESR, 0);
2063 apic_read(APIC_ESR);
2065 local_irq_restore(flags);
2071 * This device has no shutdown method - fully functioning local APICs
2072 * are needed on every CPU up until machine_halt/restart/poweroff.
2075 static struct sysdev_class lapic_sysclass = {
2077 .resume = lapic_resume,
2078 .suspend = lapic_suspend,
2081 static struct sys_device device_lapic = {
2083 .cls = &lapic_sysclass,
2086 static void __cpuinit apic_pm_activate(void)
2088 apic_pm_state.active = 1;
2091 static int __init init_lapic_sysfs(void)
2097 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2099 error = sysdev_class_register(&lapic_sysclass);
2101 error = sysdev_register(&device_lapic);
2104 device_initcall(init_lapic_sysfs);
2106 #else /* CONFIG_PM */
2108 static void apic_pm_activate(void) { }
2110 #endif /* CONFIG_PM */
2112 #ifdef CONFIG_X86_64
2114 * apic_is_clustered_box() -- Check if we can expect good TSC
2116 * Thus far, the major user of this is IBM's Summit2 series:
2118 * Clustered boxes may have unsynced TSC problems if they are
2119 * multi-chassis. Use available data to take a good guess.
2120 * If in doubt, go HPET.
2122 __cpuinit int apic_is_clustered_box(void)
2124 int i, clusters, zeros;
2126 u16 *bios_cpu_apicid;
2127 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2130 * there is not this kind of box with AMD CPU yet.
2131 * Some AMD box with quadcore cpu and 8 sockets apicid
2132 * will be [4, 0x23] or [8, 0x27] could be thought to
2133 * vsmp box still need checking...
2135 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2138 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2139 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2141 for (i = 0; i < nr_cpu_ids; i++) {
2142 /* are we being called early in kernel startup? */
2143 if (bios_cpu_apicid) {
2144 id = bios_cpu_apicid[i];
2145 } else if (i < nr_cpu_ids) {
2147 id = per_cpu(x86_bios_cpu_apicid, i);
2153 if (id != BAD_APICID)
2154 __set_bit(APIC_CLUSTERID(id), clustermap);
2157 /* Problem: Partially populated chassis may not have CPUs in some of
2158 * the APIC clusters they have been allocated. Only present CPUs have
2159 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2160 * Since clusters are allocated sequentially, count zeros only if
2161 * they are bounded by ones.
2165 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2166 if (test_bit(i, clustermap)) {
2167 clusters += 1 + zeros;
2173 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2174 * not guaranteed to be synced between boards
2176 if (is_vsmp_box() && clusters > 1)
2180 * If clusters > 2, then should be multi-chassis.
2181 * May have to revisit this when multi-core + hyperthreaded CPUs come
2182 * out, but AFAIK this will work even for them.
2184 return (clusters > 2);
2189 * APIC command line parameters
2191 static int __init setup_disableapic(char *arg)
2194 setup_clear_cpu_cap(X86_FEATURE_APIC);
2197 early_param("disableapic", setup_disableapic);
2199 /* same as disableapic, for compatibility */
2200 static int __init setup_nolapic(char *arg)
2202 return setup_disableapic(arg);
2204 early_param("nolapic", setup_nolapic);
2206 static int __init parse_lapic_timer_c2_ok(char *arg)
2208 local_apic_timer_c2_ok = 1;
2211 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2213 static int __init parse_disable_apic_timer(char *arg)
2215 disable_apic_timer = 1;
2218 early_param("noapictimer", parse_disable_apic_timer);
2220 static int __init parse_nolapic_timer(char *arg)
2222 disable_apic_timer = 1;
2225 early_param("nolapic_timer", parse_nolapic_timer);
2227 static int __init apic_set_verbosity(char *arg)
2230 #ifdef CONFIG_X86_64
2231 skip_ioapic_setup = 0;
2237 if (strcmp("debug", arg) == 0)
2238 apic_verbosity = APIC_DEBUG;
2239 else if (strcmp("verbose", arg) == 0)
2240 apic_verbosity = APIC_VERBOSE;
2242 pr_warning("APIC Verbosity level %s not recognised"
2243 " use apic=verbose or apic=debug\n", arg);
2249 early_param("apic", apic_set_verbosity);
2251 static int __init lapic_insert_resource(void)
2256 /* Put local APIC into the resource map. */
2257 lapic_resource.start = apic_phys;
2258 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2259 insert_resource(&iomem_resource, &lapic_resource);
2265 * need call insert after e820_reserve_resources()
2266 * that is using request_resource
2268 late_initcall(lapic_insert_resource);