2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
71 int first_system_vector = 0xfe;
73 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
76 * Debug level, exported for io_apic.c
78 unsigned int apic_verbosity;
82 /* Have we found an MP table */
85 static struct resource lapic_resource = {
87 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
90 static unsigned int calibration_result;
92 static int lapic_next_event(unsigned long delta,
93 struct clock_event_device *evt);
94 static void lapic_timer_setup(enum clock_event_mode mode,
95 struct clock_event_device *evt);
96 static void lapic_timer_broadcast(cpumask_t mask);
97 static void apic_pm_activate(void);
100 * The local apic timer can be used for any function which is CPU local.
102 static struct clock_event_device lapic_clockevent = {
104 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
105 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
107 .set_mode = lapic_timer_setup,
108 .set_next_event = lapic_next_event,
109 .broadcast = lapic_timer_broadcast,
113 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase;
118 static unsigned long apic_phys;
121 * Get the LAPIC version
123 static inline int lapic_get_version(void)
125 return GET_APIC_VERSION(apic_read(APIC_LVR));
129 * Check, if the APIC is integrated or a separate chip
131 static inline int lapic_is_integrated(void)
133 return APIC_INTEGRATED(lapic_get_version());
137 * Check, whether this is a modern or a first generation APIC
139 static int modern_apic(void)
141 /* AMD systems use old APIC versions, so check the CPU */
142 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
143 boot_cpu_data.x86 >= 0xf)
145 return lapic_get_version() >= 0x14;
148 void apic_wait_icr_idle(void)
150 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
154 u32 safe_apic_wait_icr_idle(void)
161 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
165 } while (timeout++ < 1000);
171 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
173 void __cpuinit enable_NMI_through_LVT0(void)
175 unsigned int v = APIC_DM_NMI;
177 /* Level triggered for 82489DX */
178 if (!lapic_is_integrated())
179 v |= APIC_LVT_LEVEL_TRIGGER;
180 apic_write(APIC_LVT0, v);
184 * get_physical_broadcast - Get number of physical broadcast IDs
186 int get_physical_broadcast(void)
188 return modern_apic() ? 0xff : 0xf;
192 * lapic_get_maxlvt - get the maximum number of local vector table entries
194 int lapic_get_maxlvt(void)
196 unsigned int v = apic_read(APIC_LVR);
198 /* 82489DXs do not report # of LVT entries. */
199 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
206 /* Clock divisor is set to 16 */
207 #define APIC_DIVISOR 16
210 * This function sets up the local APIC timer, with a timeout of
211 * 'clocks' APIC bus clock. During calibration we actually call
212 * this function twice on the boot CPU, once with a bogus timeout
213 * value, second time for real. The other (noncalibrating) CPUs
214 * call this function only once, with the real, calibrated value.
216 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
218 unsigned int lvtt_value, tmp_value;
220 lvtt_value = LOCAL_TIMER_VECTOR;
222 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
223 if (!lapic_is_integrated())
224 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
227 lvtt_value |= APIC_LVT_MASKED;
229 apic_write(APIC_LVTT, lvtt_value);
234 tmp_value = apic_read(APIC_TDCR);
235 apic_write(APIC_TDCR,
236 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
240 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
244 * Program the next event, relative to now
246 static int lapic_next_event(unsigned long delta,
247 struct clock_event_device *evt)
249 apic_write(APIC_TMICT, delta);
254 * Setup the lapic timer in periodic or oneshot mode
256 static void lapic_timer_setup(enum clock_event_mode mode,
257 struct clock_event_device *evt)
262 /* Lapic used for broadcast ? */
263 if (!local_apic_timer_verify_ok)
266 local_irq_save(flags);
269 case CLOCK_EVT_MODE_PERIODIC:
270 case CLOCK_EVT_MODE_ONESHOT:
271 __setup_APIC_LVTT(calibration_result,
272 mode != CLOCK_EVT_MODE_PERIODIC, 1);
274 case CLOCK_EVT_MODE_UNUSED:
275 case CLOCK_EVT_MODE_SHUTDOWN:
276 v = apic_read(APIC_LVTT);
277 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
278 apic_write(APIC_LVTT, v);
280 case CLOCK_EVT_MODE_RESUME:
281 /* Nothing to do here */
285 local_irq_restore(flags);
289 * Local APIC timer broadcast function
291 static void lapic_timer_broadcast(cpumask_t mask)
294 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
299 * Setup the local APIC timer for this CPU. Copy the initilized values
300 * of the boot CPU and register the clock event in the framework.
302 static void __devinit setup_APIC_timer(void)
304 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
306 memcpy(levt, &lapic_clockevent, sizeof(*levt));
307 levt->cpumask = cpumask_of_cpu(smp_processor_id());
309 clockevents_register_device(levt);
313 * In this functions we calibrate APIC bus clocks to the external timer.
315 * We want to do the calibration only once since we want to have local timer
316 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
319 * This was previously done by reading the PIT/HPET and waiting for a wrap
320 * around to find out, that a tick has elapsed. I have a box, where the PIT
321 * readout is broken, so it never gets out of the wait loop again. This was
322 * also reported by others.
324 * Monitoring the jiffies value is inaccurate and the clockevents
325 * infrastructure allows us to do a simple substitution of the interrupt
328 * The calibration routine also uses the pm_timer when possible, as the PIT
329 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
330 * back to normal later in the boot process).
333 #define LAPIC_CAL_LOOPS (HZ/10)
335 static __initdata int lapic_cal_loops = -1;
336 static __initdata long lapic_cal_t1, lapic_cal_t2;
337 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
338 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
339 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
342 * Temporary interrupt handler.
344 static void __init lapic_cal_handler(struct clock_event_device *dev)
346 unsigned long long tsc = 0;
347 long tapic = apic_read(APIC_TMCCT);
348 unsigned long pm = acpi_pm_read_early();
353 switch (lapic_cal_loops++) {
355 lapic_cal_t1 = tapic;
356 lapic_cal_tsc1 = tsc;
358 lapic_cal_j1 = jiffies;
361 case LAPIC_CAL_LOOPS:
362 lapic_cal_t2 = tapic;
363 lapic_cal_tsc2 = tsc;
364 if (pm < lapic_cal_pm1)
365 pm += ACPI_PM_OVRRUN;
367 lapic_cal_j2 = jiffies;
372 static int __init calibrate_APIC_clock(void)
374 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
375 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
376 const long pm_thresh = pm_100ms/100;
377 void (*real_handler)(struct clock_event_device *dev);
378 unsigned long deltaj;
380 int pm_referenced = 0;
384 /* Replace the global interrupt handler */
385 real_handler = global_clock_event->event_handler;
386 global_clock_event->event_handler = lapic_cal_handler;
389 * Setup the APIC counter to 1e9. There is no way the lapic
390 * can underflow in the 100ms detection time frame
392 __setup_APIC_LVTT(1000000000, 0, 0);
394 /* Let the interrupts run */
397 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
402 /* Restore the real event handler */
403 global_clock_event->event_handler = real_handler;
405 /* Build delta t1-t2 as apic timer counts down */
406 delta = lapic_cal_t1 - lapic_cal_t2;
407 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
409 /* Check, if the PM timer is available */
410 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
411 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
417 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
419 if (deltapm > (pm_100ms - pm_thresh) &&
420 deltapm < (pm_100ms + pm_thresh)) {
421 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
423 res = (((u64) deltapm) * mult) >> 22;
424 do_div(res, 1000000);
425 printk(KERN_WARNING "APIC calibration not consistent "
426 "with PM Timer: %ldms instead of 100ms\n",
428 /* Correct the lapic counter value */
429 res = (((u64) delta) * pm_100ms);
430 do_div(res, deltapm);
431 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
432 "%lu (%ld)\n", (unsigned long) res, delta);
438 /* Calculate the scaled math multiplication factor */
439 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
440 lapic_clockevent.shift);
441 lapic_clockevent.max_delta_ns =
442 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
443 lapic_clockevent.min_delta_ns =
444 clockevent_delta2ns(0xF, &lapic_clockevent);
446 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
448 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
449 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
450 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
454 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
455 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
457 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
458 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
461 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
463 calibration_result / (1000000 / HZ),
464 calibration_result % (1000000 / HZ));
467 * Do a sanity check on the APIC calibration result
469 if (calibration_result < (1000000 / HZ)) {
472 "APIC frequency too slow, disabling apic timer\n");
476 local_apic_timer_verify_ok = 1;
478 /* We trust the pm timer based calibration */
479 if (!pm_referenced) {
480 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
483 * Setup the apic timer manually
485 levt->event_handler = lapic_cal_handler;
486 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
487 lapic_cal_loops = -1;
489 /* Let the interrupts run */
492 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
497 /* Stop the lapic timer */
498 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
503 deltaj = lapic_cal_j2 - lapic_cal_j1;
504 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
506 /* Check, if the jiffies result is consistent */
507 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
508 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
510 local_apic_timer_verify_ok = 0;
514 if (!local_apic_timer_verify_ok) {
516 "APIC timer disabled due to verification failure.\n");
524 * Setup the boot APIC
526 * Calibrate and verify the result.
528 void __init setup_boot_APIC_clock(void)
531 * The local apic timer can be disabled via the kernel
532 * commandline or from the CPU detection code. Register the lapic
533 * timer as a dummy clock event source on SMP systems, so the
534 * broadcast mechanism is used. On UP systems simply ignore it.
536 if (local_apic_timer_disabled) {
537 /* No broadcast on UP ! */
538 if (num_possible_cpus() > 1) {
539 lapic_clockevent.mult = 1;
545 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
546 "calibrating APIC timer ...\n");
548 if (calibrate_APIC_clock()) {
549 /* No broadcast on UP ! */
550 if (num_possible_cpus() > 1)
556 * If nmi_watchdog is set to IO_APIC, we need the
557 * PIT/HPET going. Otherwise register lapic as a dummy
560 if (nmi_watchdog != NMI_IO_APIC)
561 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
563 printk(KERN_WARNING "APIC timer registered as dummy,"
564 " due to nmi_watchdog=%d!\n", nmi_watchdog);
566 /* Setup the lapic or request the broadcast */
570 void __devinit setup_secondary_APIC_clock(void)
576 * The guts of the apic timer interrupt
578 static void local_apic_timer_interrupt(void)
580 int cpu = smp_processor_id();
581 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
584 * Normally we should not be here till LAPIC has been initialized but
585 * in some cases like kdump, its possible that there is a pending LAPIC
586 * timer interrupt from previous kernel's context and is delivered in
587 * new kernel the moment interrupts are enabled.
589 * Interrupts are enabled early and LAPIC is setup much later, hence
590 * its possible that when we get here evt->event_handler is NULL.
591 * Check for event_handler being NULL and discard the interrupt as
594 if (!evt->event_handler) {
596 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
598 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
603 * the NMI deadlock-detector uses this.
605 per_cpu(irq_stat, cpu).apic_timer_irqs++;
607 evt->event_handler(evt);
611 * Local APIC timer interrupt. This is the most natural way for doing
612 * local interrupts, but local timer interrupts can be emulated by
613 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
615 * [ if a single-CPU system runs an SMP kernel then we call the local
616 * interrupt as well. Thus we cannot inline the local irq ... ]
618 void smp_apic_timer_interrupt(struct pt_regs *regs)
620 struct pt_regs *old_regs = set_irq_regs(regs);
623 * NOTE! We'd better ACK the irq immediately,
624 * because timer handling can be slow.
628 * update_process_times() expects us to have done irq_enter().
629 * Besides, if we don't timer interrupts ignore the global
630 * interrupt lock, which is the WrongThing (tm) to do.
633 local_apic_timer_interrupt();
636 set_irq_regs(old_regs);
639 int setup_profiling_timer(unsigned int multiplier)
645 * Setup extended LVT, AMD specific (K8, family 10h)
647 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
648 * MCE interrupts are supported. Thus MCE offset must be set to 0.
650 * If mask=1, the LVT entry does not generate interrupts while mask=0
651 * enables the vector. See also the BKDGs.
654 #define APIC_EILVT_LVTOFF_MCE 0
655 #define APIC_EILVT_LVTOFF_IBS 1
657 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
659 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
660 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
664 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
666 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
667 return APIC_EILVT_LVTOFF_MCE;
670 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
672 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
673 return APIC_EILVT_LVTOFF_IBS;
675 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
678 * Local APIC start and shutdown
682 * clear_local_APIC - shutdown the local APIC
684 * This is called, when a CPU is disabled and before rebooting, so the state of
685 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
686 * leftovers during boot.
688 void clear_local_APIC(void)
693 /* APIC hasn't been mapped yet */
697 maxlvt = lapic_get_maxlvt();
699 * Masking an LVT entry can trigger a local APIC error
700 * if the vector is zero. Mask LVTERR first to prevent this.
703 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
704 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
707 * Careful: we have to set masks only first to deassert
708 * any level-triggered sources.
710 v = apic_read(APIC_LVTT);
711 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
712 v = apic_read(APIC_LVT0);
713 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
714 v = apic_read(APIC_LVT1);
715 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
717 v = apic_read(APIC_LVTPC);
718 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
721 /* lets not touch this if we didn't frob it */
722 #ifdef CONFIG_X86_MCE_P4THERMAL
724 v = apic_read(APIC_LVTTHMR);
725 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
729 * Clean APIC state for other OSs:
731 apic_write(APIC_LVTT, APIC_LVT_MASKED);
732 apic_write(APIC_LVT0, APIC_LVT_MASKED);
733 apic_write(APIC_LVT1, APIC_LVT_MASKED);
735 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
737 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
739 #ifdef CONFIG_X86_MCE_P4THERMAL
741 apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);
743 /* Integrated APIC (!82489DX) ? */
744 if (lapic_is_integrated()) {
746 /* Clear ESR due to Pentium errata 3AP and 11AP */
747 apic_write(APIC_ESR, 0);
753 * disable_local_APIC - clear and disable the local APIC
755 void disable_local_APIC(void)
762 * Disable APIC (implies clearing of registers
765 value = apic_read(APIC_SPIV);
766 value &= ~APIC_SPIV_APIC_ENABLED;
767 apic_write(APIC_SPIV, value);
770 * When LAPIC was disabled by the BIOS and enabled by the kernel,
771 * restore the disabled state.
773 if (enabled_via_apicbase) {
776 rdmsr(MSR_IA32_APICBASE, l, h);
777 l &= ~MSR_IA32_APICBASE_ENABLE;
778 wrmsr(MSR_IA32_APICBASE, l, h);
783 * If Linux enabled the LAPIC against the BIOS default disable it down before
784 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
785 * not power-off. Additionally clear all LVT entries before disable_local_APIC
786 * for the case where Linux didn't enable the LAPIC.
788 void lapic_shutdown(void)
795 local_irq_save(flags);
798 if (enabled_via_apicbase)
799 disable_local_APIC();
801 local_irq_restore(flags);
805 * This is to verify that we're looking at a real local APIC.
806 * Check these against your board if the CPUs aren't getting
807 * started for no apparent reason.
809 int __init verify_local_APIC(void)
811 unsigned int reg0, reg1;
814 * The version register is read-only in a real APIC.
816 reg0 = apic_read(APIC_LVR);
817 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
818 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
819 reg1 = apic_read(APIC_LVR);
820 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
823 * The two version reads above should print the same
824 * numbers. If the second one is different, then we
825 * poke at a non-APIC.
831 * Check if the version looks reasonably.
833 reg1 = GET_APIC_VERSION(reg0);
834 if (reg1 == 0x00 || reg1 == 0xff)
836 reg1 = lapic_get_maxlvt();
837 if (reg1 < 0x02 || reg1 == 0xff)
841 * The ID register is read/write in a real APIC.
843 reg0 = apic_read(APIC_ID);
844 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
847 * The next two are just to see if we have sane values.
848 * They're only really relevant if we're in Virtual Wire
849 * compatibility mode, but most boxes are anymore.
851 reg0 = apic_read(APIC_LVT0);
852 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
853 reg1 = apic_read(APIC_LVT1);
854 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
860 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
862 void __init sync_Arb_IDs(void)
865 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
868 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
873 apic_wait_icr_idle();
875 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
877 APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
881 * An initial setup of the virtual wire mode.
883 void __init init_bsp_APIC(void)
888 * Don't do the setup now if we have a SMP BIOS as the
889 * through-I/O-APIC virtual wire mode might be active.
891 if (smp_found_config || !cpu_has_apic)
895 * Do not trust the local APIC being empty at bootup.
902 value = apic_read(APIC_SPIV);
903 value &= ~APIC_VECTOR_MASK;
904 value |= APIC_SPIV_APIC_ENABLED;
906 /* This bit is reserved on P4/Xeon and should be cleared */
907 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
908 (boot_cpu_data.x86 == 15))
909 value &= ~APIC_SPIV_FOCUS_DISABLED;
911 value |= APIC_SPIV_FOCUS_DISABLED;
912 value |= SPURIOUS_APIC_VECTOR;
913 apic_write(APIC_SPIV, value);
916 * Set up the virtual wire mode.
918 apic_write(APIC_LVT0, APIC_DM_EXTINT);
920 if (!lapic_is_integrated()) /* 82489DX */
921 value |= APIC_LVT_LEVEL_TRIGGER;
922 apic_write(APIC_LVT1, value);
925 static void __cpuinit lapic_setup_esr(void)
927 unsigned long oldvalue, value, maxlvt;
928 if (lapic_is_integrated() && !esr_disable) {
930 maxlvt = lapic_get_maxlvt();
931 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
932 apic_write(APIC_ESR, 0);
933 oldvalue = apic_read(APIC_ESR);
935 /* enables sending errors */
936 value = ERROR_APIC_VECTOR;
937 apic_write(APIC_LVTERR, value);
939 * spec says clear errors after enabling vector.
942 apic_write(APIC_ESR, 0);
943 value = apic_read(APIC_ESR);
944 if (value != oldvalue)
945 apic_printk(APIC_VERBOSE, "ESR value before enabling "
946 "vector: 0x%08lx after: 0x%08lx\n",
951 * Something untraceable is creating bad interrupts on
952 * secondary quads ... for the moment, just leave the
953 * ESR disabled - we can't do anything useful with the
954 * errors anyway - mbligh
956 printk(KERN_INFO "Leaving ESR disabled.\n");
958 printk(KERN_INFO "No ESR for 82489DX.\n");
964 * setup_local_APIC - setup the local APIC
966 void __cpuinit setup_local_APIC(void)
968 unsigned long value, integrated;
971 /* Pound the ESR really hard over the head with a big hammer - mbligh */
973 apic_write(APIC_ESR, 0);
974 apic_write(APIC_ESR, 0);
975 apic_write(APIC_ESR, 0);
976 apic_write(APIC_ESR, 0);
979 integrated = lapic_is_integrated();
982 * Double-check whether this APIC is really registered.
984 if (!apic_id_registered())
988 * Intel recommends to set DFR, LDR and TPR before enabling
989 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
990 * document number 292116). So here it goes...
995 * Set Task Priority to 'accept all'. We never change this
998 value = apic_read(APIC_TASKPRI);
999 value &= ~APIC_TPRI_MASK;
1000 apic_write(APIC_TASKPRI, value);
1003 * After a crash, we no longer service the interrupts and a pending
1004 * interrupt from previous kernel might still have ISR bit set.
1006 * Most probably by now CPU has serviced that pending interrupt and
1007 * it might not have done the ack_APIC_irq() because it thought,
1008 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1009 * does not clear the ISR bit and cpu thinks it has already serivced
1010 * the interrupt. Hence a vector might get locked. It was noticed
1011 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1013 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1014 value = apic_read(APIC_ISR + i*0x10);
1015 for (j = 31; j >= 0; j--) {
1022 * Now that we are all set up, enable the APIC
1024 value = apic_read(APIC_SPIV);
1025 value &= ~APIC_VECTOR_MASK;
1029 value |= APIC_SPIV_APIC_ENABLED;
1032 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1033 * certain networking cards. If high frequency interrupts are
1034 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1035 * entry is masked/unmasked at a high rate as well then sooner or
1036 * later IOAPIC line gets 'stuck', no more interrupts are received
1037 * from the device. If focus CPU is disabled then the hang goes
1040 * [ This bug can be reproduced easily with a level-triggered
1041 * PCI Ne2000 networking cards and PII/PIII processors, dual
1045 * Actually disabling the focus CPU check just makes the hang less
1046 * frequent as it makes the interrupt distributon model be more
1047 * like LRU than MRU (the short-term load is more even across CPUs).
1048 * See also the comment in end_level_ioapic_irq(). --macro
1051 /* Enable focus processor (bit==0) */
1052 value &= ~APIC_SPIV_FOCUS_DISABLED;
1055 * Set spurious IRQ vector
1057 value |= SPURIOUS_APIC_VECTOR;
1058 apic_write(APIC_SPIV, value);
1061 * Set up LVT0, LVT1:
1063 * set up through-local-APIC on the BP's LINT0. This is not
1064 * strictly necessary in pure symmetric-IO mode, but sometimes
1065 * we delegate interrupts to the 8259A.
1068 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1070 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1071 if (!smp_processor_id() && (pic_mode || !value)) {
1072 value = APIC_DM_EXTINT;
1073 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1074 smp_processor_id());
1076 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1077 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1078 smp_processor_id());
1080 apic_write(APIC_LVT0, value);
1083 * only the BP should see the LINT1 NMI signal, obviously.
1085 if (!smp_processor_id())
1086 value = APIC_DM_NMI;
1088 value = APIC_DM_NMI | APIC_LVT_MASKED;
1089 if (!integrated) /* 82489DX */
1090 value |= APIC_LVT_LEVEL_TRIGGER;
1091 apic_write(APIC_LVT1, value);
1094 void __cpuinit end_local_APIC_setup(void)
1096 unsigned long value;
1099 /* Disable the local apic timer */
1100 value = apic_read(APIC_LVTT);
1101 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1102 apic_write(APIC_LVTT, value);
1104 setup_apic_nmi_watchdog(NULL);
1109 * Detect and initialize APIC
1111 static int __init detect_init_APIC(void)
1115 /* Disabled by kernel option? */
1119 switch (boot_cpu_data.x86_vendor) {
1120 case X86_VENDOR_AMD:
1121 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1122 (boot_cpu_data.x86 == 15))
1125 case X86_VENDOR_INTEL:
1126 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1127 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1134 if (!cpu_has_apic) {
1136 * Over-ride BIOS and try to enable the local APIC only if
1137 * "lapic" specified.
1139 if (!force_enable_local_apic) {
1140 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1141 "you can enable it with \"lapic\"\n");
1145 * Some BIOSes disable the local APIC in the APIC_BASE
1146 * MSR. This can only be done in software for Intel P6 or later
1147 * and AMD K7 (Model > 1) or later.
1149 rdmsr(MSR_IA32_APICBASE, l, h);
1150 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1152 "Local APIC disabled by BIOS -- reenabling.\n");
1153 l &= ~MSR_IA32_APICBASE_BASE;
1154 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1155 wrmsr(MSR_IA32_APICBASE, l, h);
1156 enabled_via_apicbase = 1;
1160 * The APIC feature bit should now be enabled
1163 features = cpuid_edx(1);
1164 if (!(features & (1 << X86_FEATURE_APIC))) {
1165 printk(KERN_WARNING "Could not enable APIC!\n");
1168 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1169 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1171 /* The BIOS may have set up the APIC at some other address */
1172 rdmsr(MSR_IA32_APICBASE, l, h);
1173 if (l & MSR_IA32_APICBASE_ENABLE)
1174 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1176 printk(KERN_INFO "Found and enabled local APIC!\n");
1183 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1188 * init_apic_mappings - initialize APIC mappings
1190 void __init init_apic_mappings(void)
1193 * If no local APIC can be found then set up a fake all
1194 * zeroes page to simulate the local APIC and another
1195 * one for the IO-APIC.
1197 if (!smp_found_config && detect_init_APIC()) {
1198 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1199 apic_phys = __pa(apic_phys);
1201 apic_phys = mp_lapic_addr;
1203 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1204 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1208 * Fetch the APIC ID of the BSP in case we have a
1209 * default configuration (or the MP table is broken).
1211 if (boot_cpu_physical_apicid == -1U)
1212 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
1217 * This initializes the IO-APIC and APIC hardware if this is
1221 int apic_version[MAX_APICS];
1223 int __init APIC_init_uniprocessor(void)
1225 if (!smp_found_config && !cpu_has_apic)
1229 * Complain if the BIOS pretends there is one.
1231 if (!cpu_has_apic &&
1232 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1233 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1234 boot_cpu_physical_apicid);
1235 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1239 verify_local_APIC();
1244 * Hack: In case of kdump, after a crash, kernel might be booting
1245 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1246 * might be zero if read from MP tables. Get it from LAPIC.
1248 #ifdef CONFIG_CRASH_DUMP
1249 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
1251 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1255 #ifdef CONFIG_X86_IO_APIC
1256 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1258 localise_nmi_watchdog();
1259 end_local_APIC_setup();
1260 #ifdef CONFIG_X86_IO_APIC
1261 if (smp_found_config)
1262 if (!skip_ioapic_setup && nr_ioapics)
1271 * Local APIC interrupts
1275 * This interrupt should _never_ happen with our APIC/SMP architecture
1277 void smp_spurious_interrupt(struct pt_regs *regs)
1283 * Check if this really is a spurious interrupt and ACK it
1284 * if it is a vectored one. Just in case...
1285 * Spurious interrupts should not be ACKed.
1287 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1288 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1291 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1292 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1293 "should never happen.\n", smp_processor_id());
1294 __get_cpu_var(irq_stat).irq_spurious_count++;
1299 * This interrupt should never happen with our APIC/SMP architecture
1301 void smp_error_interrupt(struct pt_regs *regs)
1303 unsigned long v, v1;
1306 /* First tickle the hardware, only then report what went on. -- REW */
1307 v = apic_read(APIC_ESR);
1308 apic_write(APIC_ESR, 0);
1309 v1 = apic_read(APIC_ESR);
1311 atomic_inc(&irq_err_count);
1313 /* Here is what the APIC error bits mean:
1316 2: Send accept error
1317 3: Receive accept error
1319 5: Send illegal vector
1320 6: Received illegal vector
1321 7: Illegal register address
1323 printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1324 smp_processor_id(), v , v1);
1329 void __init smp_intr_init(void)
1332 * IRQ0 must be given a fixed assignment and initialized,
1333 * because it's used before the IO-APIC is set up.
1335 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1338 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1339 * IPI, driven by wakeup.
1341 alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1343 /* IPI for invalidation */
1344 alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1346 /* IPI for generic function call */
1347 alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
1349 /* IPI for single call function */
1350 set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
1351 call_function_single_interrupt);
1356 * Initialize APIC interrupts
1358 void __init apic_intr_init(void)
1363 /* self generated IPI for local APIC timer */
1364 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
1366 /* IPI vectors for APIC spurious and error interrupts */
1367 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
1368 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
1370 /* thermal monitor LVT interrupt */
1371 #ifdef CONFIG_X86_MCE_P4THERMAL
1372 alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
1377 * connect_bsp_APIC - attach the APIC to the interrupt system
1379 void __init connect_bsp_APIC(void)
1383 * Do not trust the local APIC being empty at bootup.
1387 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1388 * local APIC to INT and NMI lines.
1390 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1391 "enabling APIC mode.\n");
1399 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1400 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1402 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1405 void disconnect_bsp_APIC(int virt_wire_setup)
1409 * Put the board back into PIC mode (has an effect only on
1410 * certain older boards). Note that APIC interrupts, including
1411 * IPIs, won't work beyond this point! The only exception are
1414 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1415 "entering PIC mode.\n");
1419 /* Go back to Virtual Wire compatibility mode */
1420 unsigned long value;
1422 /* For the spurious interrupt use vector F, and enable it */
1423 value = apic_read(APIC_SPIV);
1424 value &= ~APIC_VECTOR_MASK;
1425 value |= APIC_SPIV_APIC_ENABLED;
1427 apic_write(APIC_SPIV, value);
1429 if (!virt_wire_setup) {
1431 * For LVT0 make it edge triggered, active high,
1432 * external and enabled
1434 value = apic_read(APIC_LVT0);
1435 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1436 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1437 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1438 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1439 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1440 apic_write(APIC_LVT0, value);
1443 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1447 * For LVT1 make it edge triggered, active high, nmi and
1450 value = apic_read(APIC_LVT1);
1452 APIC_MODE_MASK | APIC_SEND_PENDING |
1453 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1454 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1455 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1456 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1457 apic_write(APIC_LVT1, value);
1461 void __cpuinit generic_processor_info(int apicid, int version)
1465 physid_mask_t phys_cpu;
1470 if (version == 0x0) {
1471 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1472 "fixing up to 0x10. (tell your hw vendor)\n",
1476 apic_version[apicid] = version;
1478 phys_cpu = apicid_to_cpu_present(apicid);
1479 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
1481 if (num_processors >= NR_CPUS) {
1482 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1483 " Processor ignored.\n", NR_CPUS);
1488 cpus_complement(tmp_map, cpu_present_map);
1489 cpu = first_cpu(tmp_map);
1491 if (apicid == boot_cpu_physical_apicid)
1493 * x86_bios_cpu_apicid is required to have processors listed
1494 * in same order as logical cpu numbers. Hence the first
1495 * entry is BSP, and so on.
1499 if (apicid > max_physical_apicid)
1500 max_physical_apicid = apicid;
1503 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1504 * but we need to work other dependencies like SMP_SUSPEND etc
1505 * before this can be done without some confusion.
1506 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1507 * - Ashok Raj <ashok.raj@intel.com>
1509 if (max_physical_apicid >= 8) {
1510 switch (boot_cpu_data.x86_vendor) {
1511 case X86_VENDOR_INTEL:
1512 if (!APIC_XAPIC(version)) {
1516 /* If P4 and above fall through */
1517 case X86_VENDOR_AMD:
1522 /* are we being called early in kernel startup? */
1523 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1524 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1525 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1527 cpu_to_apicid[cpu] = apicid;
1528 bios_cpu_apicid[cpu] = apicid;
1530 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1531 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1534 cpu_set(cpu, cpu_possible_map);
1535 cpu_set(cpu, cpu_present_map);
1545 /* r/w apic fields */
1546 unsigned int apic_id;
1547 unsigned int apic_taskpri;
1548 unsigned int apic_ldr;
1549 unsigned int apic_dfr;
1550 unsigned int apic_spiv;
1551 unsigned int apic_lvtt;
1552 unsigned int apic_lvtpc;
1553 unsigned int apic_lvt0;
1554 unsigned int apic_lvt1;
1555 unsigned int apic_lvterr;
1556 unsigned int apic_tmict;
1557 unsigned int apic_tdcr;
1558 unsigned int apic_thmr;
1561 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1563 unsigned long flags;
1566 if (!apic_pm_state.active)
1569 maxlvt = lapic_get_maxlvt();
1571 apic_pm_state.apic_id = apic_read(APIC_ID);
1572 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1573 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1574 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1575 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1576 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1578 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1579 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1580 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1581 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1582 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1583 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1584 #ifdef CONFIG_X86_MCE_P4THERMAL
1586 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1589 local_irq_save(flags);
1590 disable_local_APIC();
1591 local_irq_restore(flags);
1595 static int lapic_resume(struct sys_device *dev)
1598 unsigned long flags;
1601 if (!apic_pm_state.active)
1604 maxlvt = lapic_get_maxlvt();
1606 local_irq_save(flags);
1609 * Make sure the APICBASE points to the right address
1611 * FIXME! This will be wrong if we ever support suspend on
1612 * SMP! We'll need to do this as part of the CPU restore!
1614 rdmsr(MSR_IA32_APICBASE, l, h);
1615 l &= ~MSR_IA32_APICBASE_BASE;
1616 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1617 wrmsr(MSR_IA32_APICBASE, l, h);
1619 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1620 apic_write(APIC_ID, apic_pm_state.apic_id);
1621 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1622 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1623 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1624 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1625 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1626 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1627 #ifdef CONFIG_X86_MCE_P4THERMAL
1629 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1632 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1633 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1634 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1635 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1636 apic_write(APIC_ESR, 0);
1637 apic_read(APIC_ESR);
1638 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1639 apic_write(APIC_ESR, 0);
1640 apic_read(APIC_ESR);
1641 local_irq_restore(flags);
1646 * This device has no shutdown method - fully functioning local APICs
1647 * are needed on every CPU up until machine_halt/restart/poweroff.
1650 static struct sysdev_class lapic_sysclass = {
1652 .resume = lapic_resume,
1653 .suspend = lapic_suspend,
1656 static struct sys_device device_lapic = {
1658 .cls = &lapic_sysclass,
1661 static void __devinit apic_pm_activate(void)
1663 apic_pm_state.active = 1;
1666 static int __init init_lapic_sysfs(void)
1672 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1674 error = sysdev_class_register(&lapic_sysclass);
1676 error = sysdev_register(&device_lapic);
1679 device_initcall(init_lapic_sysfs);
1681 #else /* CONFIG_PM */
1683 static void apic_pm_activate(void) { }
1685 #endif /* CONFIG_PM */
1688 * APIC command line parameters
1690 static int __init parse_lapic(char *arg)
1692 force_enable_local_apic = 1;
1695 early_param("lapic", parse_lapic);
1697 static int __init parse_nolapic(char *arg)
1700 setup_clear_cpu_cap(X86_FEATURE_APIC);
1703 early_param("nolapic", parse_nolapic);
1705 static int __init parse_disable_lapic_timer(char *arg)
1707 local_apic_timer_disabled = 1;
1710 early_param("nolapic_timer", parse_disable_lapic_timer);
1712 static int __init parse_lapic_timer_c2_ok(char *arg)
1714 local_apic_timer_c2_ok = 1;
1717 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1719 static int __init apic_set_verbosity(char *arg)
1724 if (strcmp(arg, "debug") == 0)
1725 apic_verbosity = APIC_DEBUG;
1726 else if (strcmp(arg, "verbose") == 0)
1727 apic_verbosity = APIC_VERBOSE;
1731 early_param("apic", apic_set_verbosity);
1733 static int __init lapic_insert_resource(void)
1738 /* Put local APIC into the resource map. */
1739 lapic_resource.start = apic_phys;
1740 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1741 insert_resource(&iomem_resource, &lapic_resource);
1747 * need call insert after e820_reserve_resources()
1748 * that is using request_resource
1750 late_initcall(lapic_insert_resource);