2 #include <linux/sched.h>
3 #include <linux/sched/clock.h>
5 #include <asm/cpufeature.h>
12 #define ACE_PRESENT (1 << 6)
13 #define ACE_ENABLED (1 << 7)
14 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
16 #define RNG_PRESENT (1 << 2)
17 #define RNG_ENABLED (1 << 3)
18 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
20 static void init_c3(struct cpuinfo_x86 *c)
24 /* Test for Centaur Extended Feature Flags presence */
25 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
26 u32 tmp = cpuid_edx(0xC0000001);
28 /* enable ACE unit, if present and disabled */
29 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
30 rdmsr(MSR_VIA_FCR, lo, hi);
31 lo |= ACE_FCR; /* enable ACE unit */
32 wrmsr(MSR_VIA_FCR, lo, hi);
33 pr_info("CPU: Enabled ACE h/w crypto\n");
36 /* enable RNG unit, if present and disabled */
37 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
38 rdmsr(MSR_VIA_RNG, lo, hi);
39 lo |= RNG_ENABLE; /* enable RNG unit */
40 wrmsr(MSR_VIA_RNG, lo, hi);
41 pr_info("CPU: Enabled h/w RNG\n");
44 /* store Centaur Extended Feature Flags as
45 * word 5 of the CPU capability bit array
47 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
50 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
51 if (c->x86_model >= 6 && c->x86_model <= 13) {
52 rdmsr(MSR_VIA_FCR, lo, hi);
54 wrmsr(MSR_VIA_FCR, lo, hi);
55 set_cpu_cap(c, X86_FEATURE_CX8);
58 /* Before Nehemiah, the C3's had 3dNOW! */
59 if (c->x86_model >= 6 && c->x86_model < 9)
60 set_cpu_cap(c, X86_FEATURE_3DNOW);
62 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
63 c->x86_cache_alignment = c->x86_clflush_size * 2;
64 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
67 cpu_detect_cache_sizes(c);
91 static void early_init_centaur(struct cpuinfo_x86 *c)
96 /* Emulate MTRRs using Centaur's MCR. */
97 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
101 if (c->x86_model >= 0xf)
102 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
106 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
110 static void init_centaur(struct cpuinfo_x86 *c)
120 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
121 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
123 clear_cpu_cap(c, 0*32+31);
125 early_init_centaur(c);
129 switch (c->x86_model) {
132 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
134 pr_notice("Disabling bugged TSC.\n");
135 clear_cpu_cap(c, X86_FEATURE_TSC);
138 switch (c->x86_mask) {
149 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
155 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
163 rdmsr(MSR_IDT_FCR1, lo, hi);
164 newlo = (lo|fcr_set) & (~fcr_clr);
167 pr_info("Centaur FCR was 0x%X now 0x%X\n",
169 wrmsr(MSR_IDT_FCR1, newlo, hi);
171 pr_info("Centaur FCR is 0x%X\n", lo);
173 /* Emulate MTRRs using Centaur's MCR. */
174 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
176 set_cpu_cap(c, X86_FEATURE_CX8);
177 /* Set 3DNow! on Winchip 2 and above. */
178 if (c->x86_model >= 8)
179 set_cpu_cap(c, X86_FEATURE_3DNOW);
180 /* See if we can find out some more. */
181 if (cpuid_eax(0x80000000) >= 0x80000005) {
183 cpuid(0x80000005, &aa, &bb, &cc, &dd);
184 /* Add L1 data and code cache sizes. */
185 c->x86_cache_size = (cc>>24)+(dd>>24);
187 sprintf(c->x86_model_id, "WinChip %s", name);
195 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
201 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
203 /* VIA C3 CPUs (670-68F) need further shifting. */
204 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
208 * There's also an erratum in Nehemiah stepping 1, which
209 * returns '65KB' instead of '64KB'
210 * - Note, it seems this may only be in engineering samples.
212 if ((c->x86 == 6) && (c->x86_model == 9) &&
213 (c->x86_mask == 1) && (size == 65))
219 static const struct cpu_dev centaur_cpu_dev = {
220 .c_vendor = "Centaur",
221 .c_ident = { "CentaurHauls" },
222 .c_early_init = early_init_centaur,
223 .c_init = init_centaur,
225 .legacy_cache_size = centaur_size_cache,
227 .c_x86_vendor = X86_VENDOR_CENTAUR,
230 cpu_dev_register(centaur_cpu_dev);