1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <linux/numa.h>
45 #include <asm/microcode.h>
46 #include <asm/microcode_intel.h>
48 #ifdef CONFIG_X86_LOCAL_APIC
49 #include <asm/uv/uv.h>
54 /* all of these masks are initialized in setup_cpu_local_masks() */
55 cpumask_var_t cpu_initialized_mask;
56 cpumask_var_t cpu_callout_mask;
57 cpumask_var_t cpu_callin_mask;
59 /* representing cpus for which sibling maps can be computed */
60 cpumask_var_t cpu_sibling_setup_mask;
62 /* correctly size the local cpu masks */
63 void __init setup_cpu_local_masks(void)
65 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
66 alloc_bootmem_cpumask_var(&cpu_callin_mask);
67 alloc_bootmem_cpumask_var(&cpu_callout_mask);
68 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
71 static void default_init(struct cpuinfo_x86 *c)
74 cpu_detect_cache_sizes(c);
76 /* Not much we can do here... */
77 /* Check if at least it has cpuid */
78 if (c->cpuid_level == -1) {
79 /* No cpuid. It must be an ancient CPU */
81 strcpy(c->x86_model_id, "486");
83 strcpy(c->x86_model_id, "386");
86 clear_sched_clock_stable();
89 static const struct cpu_dev default_cpu = {
90 .c_init = default_init,
91 .c_vendor = "Unknown",
92 .c_x86_vendor = X86_VENDOR_UNKNOWN,
95 static const struct cpu_dev *this_cpu = &default_cpu;
97 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
100 * We need valid kernel segments for data and code in long mode too
101 * IRET will check the segment types kkeil 2000/10/28
102 * Also sysret mandates a special GDT layout
104 * TLS descriptors are currently at a different place compared to i386.
105 * Hopefully nobody expects them at a fixed place (Wine?)
107 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
108 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
109 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
112 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
115 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
117 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
119 * Segments used for calling PnP BIOS have byte granularity.
120 * They code segments and data segments have fixed 64k limits,
121 * the transfer segment sizes are set at run time.
124 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
126 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
128 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
130 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
132 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
134 * The APM segments have byte granularity and their bases
135 * are set at run time. All have 64k limits.
138 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
140 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
142 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
144 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
145 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
146 GDT_STACK_CANARY_INIT
149 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
151 static int __init x86_mpx_setup(char *s)
153 /* require an exact match without trailing characters */
157 /* do not emit a message if the feature is not present */
158 if (!boot_cpu_has(X86_FEATURE_MPX))
161 setup_clear_cpu_cap(X86_FEATURE_MPX);
162 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
165 __setup("nompx", x86_mpx_setup);
167 static int __init x86_noinvpcid_setup(char *s)
169 /* noinvpcid doesn't accept parameters */
173 /* do not emit a message if the feature is not present */
174 if (!boot_cpu_has(X86_FEATURE_INVPCID))
177 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
178 pr_info("noinvpcid: INVPCID feature disabled\n");
181 early_param("noinvpcid", x86_noinvpcid_setup);
184 static int cachesize_override = -1;
185 static int disable_x86_serial_nr = 1;
187 static int __init cachesize_setup(char *str)
189 get_option(&str, &cachesize_override);
192 __setup("cachesize=", cachesize_setup);
194 static int __init x86_sep_setup(char *s)
196 setup_clear_cpu_cap(X86_FEATURE_SEP);
199 __setup("nosep", x86_sep_setup);
201 /* Standard macro to see if a specific flag is changeable */
202 static inline int flag_is_changeable_p(u32 flag)
207 * Cyrix and IDT cpus allow disabling of CPUID
208 * so the code below may return different results
209 * when it is executed before and after enabling
210 * the CPUID. Add "volatile" to not allow gcc to
211 * optimize the subsequent calls to this function.
213 asm volatile ("pushfl \n\t"
224 : "=&r" (f1), "=&r" (f2)
227 return ((f1^f2) & flag) != 0;
230 /* Probe for the CPUID instruction */
231 int have_cpuid_p(void)
233 return flag_is_changeable_p(X86_EFLAGS_ID);
236 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
238 unsigned long lo, hi;
240 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
243 /* Disable processor serial number: */
245 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
247 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
249 pr_notice("CPU serial number disabled.\n");
250 clear_cpu_cap(c, X86_FEATURE_PN);
252 /* Disabling the serial number may affect the cpuid level */
253 c->cpuid_level = cpuid_eax(0);
256 static int __init x86_serial_nr_setup(char *s)
258 disable_x86_serial_nr = 0;
261 __setup("serialnumber", x86_serial_nr_setup);
263 static inline int flag_is_changeable_p(u32 flag)
267 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
272 static __init int setup_disable_smep(char *arg)
274 setup_clear_cpu_cap(X86_FEATURE_SMEP);
275 /* Check for things that depend on SMEP being enabled: */
276 check_mpx_erratum(&boot_cpu_data);
279 __setup("nosmep", setup_disable_smep);
281 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
283 if (cpu_has(c, X86_FEATURE_SMEP))
284 cr4_set_bits(X86_CR4_SMEP);
287 static __init int setup_disable_smap(char *arg)
289 setup_clear_cpu_cap(X86_FEATURE_SMAP);
292 __setup("nosmap", setup_disable_smap);
294 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
296 unsigned long eflags = native_save_fl();
298 /* This should have been cleared long ago */
299 BUG_ON(eflags & X86_EFLAGS_AC);
301 if (cpu_has(c, X86_FEATURE_SMAP)) {
302 #ifdef CONFIG_X86_SMAP
303 cr4_set_bits(X86_CR4_SMAP);
305 cr4_clear_bits(X86_CR4_SMAP);
311 * Protection Keys are not available in 32-bit mode.
313 static bool pku_disabled;
315 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
317 /* check the boot processor, plus compile options for PKU: */
318 if (!cpu_feature_enabled(X86_FEATURE_PKU))
320 /* checks the actual processor's cpuid bits: */
321 if (!cpu_has(c, X86_FEATURE_PKU))
326 cr4_set_bits(X86_CR4_PKE);
328 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
329 * cpuid bit to be set. We need to ensure that we
330 * update that bit in this CPU's "cpu_info".
335 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
336 static __init int setup_disable_pku(char *arg)
339 * Do not clear the X86_FEATURE_PKU bit. All of the
340 * runtime checks are against OSPKE so clearing the
343 * This way, we will see "pku" in cpuinfo, but not
344 * "ospke", which is exactly what we want. It shows
345 * that the CPU has PKU, but the OS has not enabled it.
346 * This happens to be exactly how a system would look
347 * if we disabled the config option.
349 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
353 __setup("nopku", setup_disable_pku);
354 #endif /* CONFIG_X86_64 */
357 * Some CPU features depend on higher CPUID levels, which may not always
358 * be available due to CPUID level capping or broken virtualization
359 * software. Add those features to this table to auto-disable them.
361 struct cpuid_dependent_feature {
366 static const struct cpuid_dependent_feature
367 cpuid_dependent_features[] = {
368 { X86_FEATURE_MWAIT, 0x00000005 },
369 { X86_FEATURE_DCA, 0x00000009 },
370 { X86_FEATURE_XSAVE, 0x0000000d },
374 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
376 const struct cpuid_dependent_feature *df;
378 for (df = cpuid_dependent_features; df->feature; df++) {
380 if (!cpu_has(c, df->feature))
383 * Note: cpuid_level is set to -1 if unavailable, but
384 * extended_extended_level is set to 0 if unavailable
385 * and the legitimate extended levels are all negative
386 * when signed; hence the weird messing around with
389 if (!((s32)df->level < 0 ?
390 (u32)df->level > (u32)c->extended_cpuid_level :
391 (s32)df->level > (s32)c->cpuid_level))
394 clear_cpu_cap(c, df->feature);
398 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
399 x86_cap_flag(df->feature), df->level);
404 * Naming convention should be: <Name> [(<Codename>)]
405 * This table only is used unless init_<vendor>() below doesn't set it;
406 * in particular, if CPUID levels 0x80000002..4 are supported, this
410 /* Look up CPU names by table lookup. */
411 static const char *table_lookup_model(struct cpuinfo_x86 *c)
414 const struct legacy_cpu_model_info *info;
416 if (c->x86_model >= 16)
417 return NULL; /* Range check */
422 info = this_cpu->legacy_models;
424 while (info->family) {
425 if (info->family == c->x86)
426 return info->model_names[c->x86_model];
430 return NULL; /* Not found */
433 __u32 cpu_caps_cleared[NCAPINTS];
434 __u32 cpu_caps_set[NCAPINTS];
436 void load_percpu_segment(int cpu)
439 loadsegment(fs, __KERNEL_PERCPU);
441 __loadsegment_simple(gs, 0);
442 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
444 load_stack_canary_segment();
448 * Current gdt points %fs at the "master" per-cpu area: after this,
449 * it's on the real one.
451 void switch_to_new_gdt(int cpu)
453 struct desc_ptr gdt_descr;
455 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
456 gdt_descr.size = GDT_SIZE - 1;
457 load_gdt(&gdt_descr);
458 /* Reload the per-cpu base */
460 load_percpu_segment(cpu);
463 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
465 static void get_model_name(struct cpuinfo_x86 *c)
470 if (c->extended_cpuid_level < 0x80000004)
473 v = (unsigned int *)c->x86_model_id;
474 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
475 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
476 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
477 c->x86_model_id[48] = 0;
479 /* Trim whitespace */
480 p = q = s = &c->x86_model_id[0];
486 /* Note the last non-whitespace index */
496 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
498 unsigned int n, dummy, ebx, ecx, edx, l2size;
500 n = c->extended_cpuid_level;
502 if (n >= 0x80000005) {
503 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
504 c->x86_cache_size = (ecx>>24) + (edx>>24);
506 /* On K8 L1 TLB is inclusive, so don't count it */
511 if (n < 0x80000006) /* Some chips just has a large L1. */
514 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
518 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
520 /* do processor-specific cache resizing */
521 if (this_cpu->legacy_cache_size)
522 l2size = this_cpu->legacy_cache_size(c, l2size);
524 /* Allow user to override all this if necessary. */
525 if (cachesize_override != -1)
526 l2size = cachesize_override;
529 return; /* Again, no L2 cache is possible */
532 c->x86_cache_size = l2size;
535 u16 __read_mostly tlb_lli_4k[NR_INFO];
536 u16 __read_mostly tlb_lli_2m[NR_INFO];
537 u16 __read_mostly tlb_lli_4m[NR_INFO];
538 u16 __read_mostly tlb_lld_4k[NR_INFO];
539 u16 __read_mostly tlb_lld_2m[NR_INFO];
540 u16 __read_mostly tlb_lld_4m[NR_INFO];
541 u16 __read_mostly tlb_lld_1g[NR_INFO];
543 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
545 if (this_cpu->c_detect_tlb)
546 this_cpu->c_detect_tlb(c);
548 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
549 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
550 tlb_lli_4m[ENTRIES]);
552 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
553 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
554 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
557 void detect_ht(struct cpuinfo_x86 *c)
560 u32 eax, ebx, ecx, edx;
561 int index_msb, core_bits;
564 if (!cpu_has(c, X86_FEATURE_HT))
567 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
570 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
573 cpuid(1, &eax, &ebx, &ecx, &edx);
575 smp_num_siblings = (ebx & 0xff0000) >> 16;
577 if (smp_num_siblings == 1) {
578 pr_info_once("CPU0: Hyper-Threading is disabled\n");
582 if (smp_num_siblings <= 1)
585 index_msb = get_count_order(smp_num_siblings);
586 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
588 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
590 index_msb = get_count_order(smp_num_siblings);
592 core_bits = get_count_order(c->x86_max_cores);
594 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
595 ((1 << core_bits) - 1);
598 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
599 pr_info("CPU: Physical Processor ID: %d\n",
601 pr_info("CPU: Processor Core ID: %d\n",
608 static void get_cpu_vendor(struct cpuinfo_x86 *c)
610 char *v = c->x86_vendor_id;
613 for (i = 0; i < X86_VENDOR_NUM; i++) {
617 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
618 (cpu_devs[i]->c_ident[1] &&
619 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
621 this_cpu = cpu_devs[i];
622 c->x86_vendor = this_cpu->c_x86_vendor;
627 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
628 "CPU: Your system may be unstable.\n", v);
630 c->x86_vendor = X86_VENDOR_UNKNOWN;
631 this_cpu = &default_cpu;
634 void cpu_detect(struct cpuinfo_x86 *c)
636 /* Get vendor name */
637 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
638 (unsigned int *)&c->x86_vendor_id[0],
639 (unsigned int *)&c->x86_vendor_id[8],
640 (unsigned int *)&c->x86_vendor_id[4]);
643 /* Intel-defined flags: level 0x00000001 */
644 if (c->cpuid_level >= 0x00000001) {
645 u32 junk, tfms, cap0, misc;
647 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
648 c->x86 = x86_family(tfms);
649 c->x86_model = x86_model(tfms);
650 c->x86_mask = x86_stepping(tfms);
652 if (cap0 & (1<<19)) {
653 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
654 c->x86_cache_alignment = c->x86_clflush_size;
659 void get_cpu_cap(struct cpuinfo_x86 *c)
661 u32 eax, ebx, ecx, edx;
663 /* Intel-defined flags: level 0x00000001 */
664 if (c->cpuid_level >= 0x00000001) {
665 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
667 c->x86_capability[CPUID_1_ECX] = ecx;
668 c->x86_capability[CPUID_1_EDX] = edx;
671 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
672 if (c->cpuid_level >= 0x00000006)
673 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
675 /* Additional Intel-defined flags: level 0x00000007 */
676 if (c->cpuid_level >= 0x00000007) {
677 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
678 c->x86_capability[CPUID_7_0_EBX] = ebx;
679 c->x86_capability[CPUID_7_ECX] = ecx;
682 /* Extended state features: level 0x0000000d */
683 if (c->cpuid_level >= 0x0000000d) {
684 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
686 c->x86_capability[CPUID_D_1_EAX] = eax;
689 /* Additional Intel-defined flags: level 0x0000000F */
690 if (c->cpuid_level >= 0x0000000F) {
692 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
693 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
694 c->x86_capability[CPUID_F_0_EDX] = edx;
696 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
697 /* will be overridden if occupancy monitoring exists */
698 c->x86_cache_max_rmid = ebx;
700 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
701 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
702 c->x86_capability[CPUID_F_1_EDX] = edx;
704 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
705 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
706 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
707 c->x86_cache_max_rmid = ecx;
708 c->x86_cache_occ_scale = ebx;
711 c->x86_cache_max_rmid = -1;
712 c->x86_cache_occ_scale = -1;
716 /* AMD-defined flags: level 0x80000001 */
717 eax = cpuid_eax(0x80000000);
718 c->extended_cpuid_level = eax;
720 if ((eax & 0xffff0000) == 0x80000000) {
721 if (eax >= 0x80000001) {
722 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
724 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
725 c->x86_capability[CPUID_8000_0001_EDX] = edx;
729 if (c->extended_cpuid_level >= 0x80000007) {
730 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
732 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
736 if (c->extended_cpuid_level >= 0x80000008) {
737 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
739 c->x86_virt_bits = (eax >> 8) & 0xff;
740 c->x86_phys_bits = eax & 0xff;
741 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
744 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
745 c->x86_phys_bits = 36;
748 if (c->extended_cpuid_level >= 0x8000000a)
749 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
751 init_scattered_cpuid_features(c);
754 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
760 * First of all, decide if this is a 486 or higher
761 * It's a 486 if we can modify the AC flag
763 if (flag_is_changeable_p(X86_EFLAGS_AC))
768 for (i = 0; i < X86_VENDOR_NUM; i++)
769 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
770 c->x86_vendor_id[0] = 0;
771 cpu_devs[i]->c_identify(c);
772 if (c->x86_vendor_id[0]) {
781 * Do minimum CPU detection early.
782 * Fields really needed: vendor, cpuid_level, family, model, mask,
784 * The others are not touched to avoid unwanted side effects.
786 * WARNING: this function is only called on the BP. Don't add code here
787 * that is supposed to run on all CPUs.
789 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
792 c->x86_clflush_size = 64;
793 c->x86_phys_bits = 36;
794 c->x86_virt_bits = 48;
796 c->x86_clflush_size = 32;
797 c->x86_phys_bits = 32;
798 c->x86_virt_bits = 32;
800 c->x86_cache_alignment = c->x86_clflush_size;
802 memset(&c->x86_capability, 0, sizeof c->x86_capability);
803 c->extended_cpuid_level = 0;
806 identify_cpu_without_cpuid(c);
808 /* cyrix could have cpuid enabled via c_identify()*/
809 if (have_cpuid_p()) {
814 if (this_cpu->c_early_init)
815 this_cpu->c_early_init(c);
818 filter_cpuid_features(c, false);
820 if (this_cpu->c_bsp_init)
821 this_cpu->c_bsp_init(c);
824 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
828 void __init early_cpu_init(void)
830 const struct cpu_dev *const *cdev;
833 #ifdef CONFIG_PROCESSOR_SELECT
834 pr_info("KERNEL supported cpus:\n");
837 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
838 const struct cpu_dev *cpudev = *cdev;
840 if (count >= X86_VENDOR_NUM)
842 cpu_devs[count] = cpudev;
845 #ifdef CONFIG_PROCESSOR_SELECT
849 for (j = 0; j < 2; j++) {
850 if (!cpudev->c_ident[j])
852 pr_info(" %s %s\n", cpudev->c_vendor,
858 early_identify_cpu(&boot_cpu_data);
862 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
863 * unfortunately, that's not true in practice because of early VIA
864 * chips and (more importantly) broken virtualizers that are not easy
865 * to detect. In the latter case it doesn't even *fail* reliably, so
866 * probing for it doesn't even work. Disable it completely on 32-bit
867 * unless we can find a reliable way to detect all the broken cases.
868 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
870 static void detect_nopl(struct cpuinfo_x86 *c)
873 clear_cpu_cap(c, X86_FEATURE_NOPL);
875 set_cpu_cap(c, X86_FEATURE_NOPL);
879 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
883 * Empirically, writing zero to a segment selector on AMD does
884 * not clear the base, whereas writing zero to a segment
885 * selector on Intel does clear the base. Intel's behavior
886 * allows slightly faster context switches in the common case
887 * where GS is unused by the prev and next threads.
889 * Since neither vendor documents this anywhere that I can see,
890 * detect it directly instead of hardcoding the choice by
893 * I've designated AMD's behavior as the "bug" because it's
894 * counterintuitive and less friendly.
897 unsigned long old_base, tmp;
898 rdmsrl(MSR_FS_BASE, old_base);
899 wrmsrl(MSR_FS_BASE, 1);
901 rdmsrl(MSR_FS_BASE, tmp);
903 set_cpu_bug(c, X86_BUG_NULL_SEG);
904 wrmsrl(MSR_FS_BASE, old_base);
908 static void generic_identify(struct cpuinfo_x86 *c)
910 c->extended_cpuid_level = 0;
913 identify_cpu_without_cpuid(c);
915 /* cyrix could have cpuid enabled via c_identify()*/
925 if (c->cpuid_level >= 0x00000001) {
926 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
929 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
931 c->apicid = c->initial_apicid;
934 c->phys_proc_id = c->initial_apicid;
937 get_model_name(c); /* Default name */
941 detect_null_seg_behavior(c);
944 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
945 * systems that run Linux at CPL > 0 may or may not have the
946 * issue, but, even if they have the issue, there's absolutely
947 * nothing we can do about it because we can't use the real IRET
950 * NB: For the time being, only 32-bit kernels support
951 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
952 * whether to apply espfix using paravirt hooks. If any
953 * non-paravirt system ever shows up that does *not* have the
954 * ESPFIX issue, we can change this.
957 # ifdef CONFIG_PARAVIRT
959 extern void native_iret(void);
960 if (pv_cpu_ops.iret == native_iret)
961 set_cpu_bug(c, X86_BUG_ESPFIX);
964 set_cpu_bug(c, X86_BUG_ESPFIX);
969 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
972 * The heavy lifting of max_rmid and cache_occ_scale are handled
973 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
974 * in case CQM bits really aren't there in this CPU.
976 if (c != &boot_cpu_data) {
977 boot_cpu_data.x86_cache_max_rmid =
978 min(boot_cpu_data.x86_cache_max_rmid,
979 c->x86_cache_max_rmid);
984 * Validate that ACPI/mptables have the same information about the
985 * effective APIC id and update the package map.
987 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
990 unsigned int apicid, cpu = smp_processor_id();
992 apicid = apic->cpu_present_to_apicid(cpu);
994 if (apicid != c->apicid) {
995 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
996 cpu, apicid, c->initial_apicid);
998 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1000 c->logical_proc_id = 0;
1005 * This does the hard work of actually picking apart the CPU stuff...
1007 static void identify_cpu(struct cpuinfo_x86 *c)
1011 c->loops_per_jiffy = loops_per_jiffy;
1012 c->x86_cache_size = -1;
1013 c->x86_vendor = X86_VENDOR_UNKNOWN;
1014 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1015 c->x86_vendor_id[0] = '\0'; /* Unset */
1016 c->x86_model_id[0] = '\0'; /* Unset */
1017 c->x86_max_cores = 1;
1018 c->x86_coreid_bits = 0;
1019 #ifdef CONFIG_X86_64
1020 c->x86_clflush_size = 64;
1021 c->x86_phys_bits = 36;
1022 c->x86_virt_bits = 48;
1024 c->cpuid_level = -1; /* CPUID not detected */
1025 c->x86_clflush_size = 32;
1026 c->x86_phys_bits = 32;
1027 c->x86_virt_bits = 32;
1029 c->x86_cache_alignment = c->x86_clflush_size;
1030 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1032 generic_identify(c);
1034 if (this_cpu->c_identify)
1035 this_cpu->c_identify(c);
1037 /* Clear/Set all flags overridden by options, after probe */
1038 for (i = 0; i < NCAPINTS; i++) {
1039 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1040 c->x86_capability[i] |= cpu_caps_set[i];
1043 #ifdef CONFIG_X86_64
1044 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1048 * Vendor-specific initialization. In this section we
1049 * canonicalize the feature flags, meaning if there are
1050 * features a certain CPU supports which CPUID doesn't
1051 * tell us, CPUID claiming incorrect flags, or other bugs,
1052 * we handle them here.
1054 * At the end of this section, c->x86_capability better
1055 * indicate the features this CPU genuinely supports!
1057 if (this_cpu->c_init)
1058 this_cpu->c_init(c);
1060 clear_sched_clock_stable();
1062 /* Disable the PN if appropriate */
1063 squash_the_stupid_serial_number(c);
1065 /* Set up SMEP/SMAP */
1070 * The vendor-specific functions might have changed features.
1071 * Now we do "generic changes."
1074 /* Filter out anything that depends on CPUID levels we don't have */
1075 filter_cpuid_features(c, true);
1077 /* If the model name is still unset, do table lookup. */
1078 if (!c->x86_model_id[0]) {
1080 p = table_lookup_model(c);
1082 strcpy(c->x86_model_id, p);
1084 /* Last resort... */
1085 sprintf(c->x86_model_id, "%02x/%02x",
1086 c->x86, c->x86_model);
1089 #ifdef CONFIG_X86_64
1095 x86_init_cache_qos(c);
1099 * Clear/Set all flags overridden by options, need do it
1100 * before following smp all cpus cap AND.
1102 for (i = 0; i < NCAPINTS; i++) {
1103 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1104 c->x86_capability[i] |= cpu_caps_set[i];
1108 * On SMP, boot_cpu_data holds the common feature set between
1109 * all CPUs; so make sure that we indicate which features are
1110 * common between the CPUs. The first time this routine gets
1111 * executed, c == &boot_cpu_data.
1113 if (c != &boot_cpu_data) {
1114 /* AND the already accumulated flags with these */
1115 for (i = 0; i < NCAPINTS; i++)
1116 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1118 /* OR, i.e. replicate the bug flags */
1119 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1120 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1123 /* Init Machine Check Exception if available. */
1126 select_idle_routine(c);
1129 numa_add_cpu(smp_processor_id());
1134 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1135 * on 32-bit kernels:
1137 #ifdef CONFIG_X86_32
1138 void enable_sep_cpu(void)
1140 struct tss_struct *tss;
1143 if (!boot_cpu_has(X86_FEATURE_SEP))
1147 tss = &per_cpu(cpu_tss, cpu);
1150 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1151 * see the big comment in struct x86_hw_tss's definition.
1154 tss->x86_tss.ss1 = __KERNEL_CS;
1155 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1157 wrmsr(MSR_IA32_SYSENTER_ESP,
1158 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1161 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1167 void __init identify_boot_cpu(void)
1169 identify_cpu(&boot_cpu_data);
1170 #ifdef CONFIG_X86_32
1174 cpu_detect_tlb(&boot_cpu_data);
1177 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1179 BUG_ON(c == &boot_cpu_data);
1181 #ifdef CONFIG_X86_32
1185 validate_apic_and_package_id(c);
1188 static __init int setup_noclflush(char *arg)
1190 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1191 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1194 __setup("noclflush", setup_noclflush);
1196 void print_cpu_info(struct cpuinfo_x86 *c)
1198 const char *vendor = NULL;
1200 if (c->x86_vendor < X86_VENDOR_NUM) {
1201 vendor = this_cpu->c_vendor;
1203 if (c->cpuid_level >= 0)
1204 vendor = c->x86_vendor_id;
1207 if (vendor && !strstr(c->x86_model_id, vendor))
1208 pr_cont("%s ", vendor);
1210 if (c->x86_model_id[0])
1211 pr_cont("%s", c->x86_model_id);
1213 pr_cont("%d86", c->x86);
1215 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1217 if (c->x86_mask || c->cpuid_level >= 0)
1218 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1223 static __init int setup_disablecpuid(char *arg)
1227 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1228 setup_clear_cpu_cap(bit);
1234 __setup("clearcpuid=", setup_disablecpuid);
1236 #ifdef CONFIG_X86_64
1237 struct desc_ptr idt_descr __ro_after_init = {
1238 .size = NR_VECTORS * 16 - 1,
1239 .address = (unsigned long) idt_table,
1241 const struct desc_ptr debug_idt_descr = {
1242 .size = NR_VECTORS * 16 - 1,
1243 .address = (unsigned long) debug_idt_table,
1246 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1247 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1250 * The following percpu variables are hot. Align current_task to
1251 * cacheline size such that they fall in the same cacheline.
1253 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1255 EXPORT_PER_CPU_SYMBOL(current_task);
1257 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1258 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1260 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1262 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1263 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1266 * Special IST stacks which the CPU switches to when it calls
1267 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1268 * limit), all of them are 4K, except the debug stack which
1271 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1272 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1273 [DEBUG_STACK - 1] = DEBUG_STKSZ
1276 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1277 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1279 /* May not be marked __init: used by software suspend */
1280 void syscall_init(void)
1282 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1283 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1285 #ifdef CONFIG_IA32_EMULATION
1286 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1288 * This only works on Intel CPUs.
1289 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1290 * This does not cause SYSENTER to jump to the wrong location, because
1291 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1293 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1294 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1295 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1297 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1298 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1299 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1300 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1303 /* Flags to clear on syscall */
1304 wrmsrl(MSR_SYSCALL_MASK,
1305 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1306 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1310 * Copies of the original ist values from the tss are only accessed during
1311 * debugging, no special alignment required.
1313 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1315 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1316 DEFINE_PER_CPU(int, debug_stack_usage);
1318 int is_debug_stack(unsigned long addr)
1320 return __this_cpu_read(debug_stack_usage) ||
1321 (addr <= __this_cpu_read(debug_stack_addr) &&
1322 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1324 NOKPROBE_SYMBOL(is_debug_stack);
1326 DEFINE_PER_CPU(u32, debug_idt_ctr);
1328 void debug_stack_set_zero(void)
1330 this_cpu_inc(debug_idt_ctr);
1333 NOKPROBE_SYMBOL(debug_stack_set_zero);
1335 void debug_stack_reset(void)
1337 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1339 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1342 NOKPROBE_SYMBOL(debug_stack_reset);
1344 #else /* CONFIG_X86_64 */
1346 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1347 EXPORT_PER_CPU_SYMBOL(current_task);
1348 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1349 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1352 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1353 * the top of the kernel stack. Use an extra percpu variable to track the
1354 * top of the kernel stack directly.
1356 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1357 (unsigned long)&init_thread_union + THREAD_SIZE;
1358 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1360 #ifdef CONFIG_CC_STACKPROTECTOR
1361 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1364 #endif /* CONFIG_X86_64 */
1367 * Clear all 6 debug registers:
1369 static void clear_all_debug_regs(void)
1373 for (i = 0; i < 8; i++) {
1374 /* Ignore db4, db5 */
1375 if ((i == 4) || (i == 5))
1384 * Restore debug regs if using kgdbwait and you have a kernel debugger
1385 * connection established.
1387 static void dbg_restore_debug_regs(void)
1389 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1390 arch_kgdb_ops.correct_hw_break();
1392 #else /* ! CONFIG_KGDB */
1393 #define dbg_restore_debug_regs()
1394 #endif /* ! CONFIG_KGDB */
1396 static void wait_for_master_cpu(int cpu)
1400 * wait for ACK from master CPU before continuing
1401 * with AP initialization
1403 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1404 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1410 * cpu_init() initializes state that is per-CPU. Some data is already
1411 * initialized (naturally) in the bootstrap process, such as the GDT
1412 * and IDT. We reload them nevertheless, this function acts as a
1413 * 'CPU state barrier', nothing should get across.
1414 * A lot of state is already set up in PDA init for 64 bit
1416 #ifdef CONFIG_X86_64
1420 struct orig_ist *oist;
1421 struct task_struct *me;
1422 struct tss_struct *t;
1424 int cpu = raw_smp_processor_id();
1427 wait_for_master_cpu(cpu);
1430 * Initialize the CR4 shadow before doing anything that could
1438 t = &per_cpu(cpu_tss, cpu);
1439 oist = &per_cpu(orig_ist, cpu);
1442 if (this_cpu_read(numa_node) == 0 &&
1443 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1444 set_numa_node(early_cpu_to_node(cpu));
1449 pr_debug("Initializing CPU#%d\n", cpu);
1451 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1454 * Initialize the per-CPU GDT with the boot GDT,
1455 * and set up the GDT descriptor:
1458 switch_to_new_gdt(cpu);
1463 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1466 wrmsrl(MSR_FS_BASE, 0);
1467 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1474 * set up and load the per-CPU TSS
1476 if (!oist->ist[0]) {
1477 char *estacks = per_cpu(exception_stacks, cpu);
1479 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1480 estacks += exception_stack_sizes[v];
1481 oist->ist[v] = t->x86_tss.ist[v] =
1482 (unsigned long)estacks;
1483 if (v == DEBUG_STACK-1)
1484 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1488 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1491 * <= is required because the CPU will access up to
1492 * 8 bits beyond the end of the IO permission bitmap.
1494 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1495 t->io_bitmap[i] = ~0UL;
1497 atomic_inc(&init_mm.mm_count);
1498 me->active_mm = &init_mm;
1500 enter_lazy_tlb(&init_mm, me);
1502 load_sp0(t, ¤t->thread);
1503 set_tss_desc(cpu, t);
1505 load_mm_ldt(&init_mm);
1507 clear_all_debug_regs();
1508 dbg_restore_debug_regs();
1520 int cpu = smp_processor_id();
1521 struct task_struct *curr = current;
1522 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1523 struct thread_struct *thread = &curr->thread;
1525 wait_for_master_cpu(cpu);
1528 * Initialize the CR4 shadow before doing anything that could
1533 show_ucode_info_early();
1535 pr_info("Initializing CPU#%d\n", cpu);
1537 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1538 boot_cpu_has(X86_FEATURE_TSC) ||
1539 boot_cpu_has(X86_FEATURE_DE))
1540 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1543 switch_to_new_gdt(cpu);
1546 * Set up and load the per-CPU TSS and LDT
1548 atomic_inc(&init_mm.mm_count);
1549 curr->active_mm = &init_mm;
1551 enter_lazy_tlb(&init_mm, curr);
1553 load_sp0(t, thread);
1554 set_tss_desc(cpu, t);
1556 load_mm_ldt(&init_mm);
1558 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1560 #ifdef CONFIG_DOUBLEFAULT
1561 /* Set up doublefault TSS pointer in the GDT */
1562 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1565 clear_all_debug_regs();
1566 dbg_restore_debug_regs();
1572 static void bsp_resume(void)
1574 if (this_cpu->c_bsp_resume)
1575 this_cpu->c_bsp_resume(&boot_cpu_data);
1578 static struct syscore_ops cpu_syscore_ops = {
1579 .resume = bsp_resume,
1582 static int __init init_cpu_syscore(void)
1584 register_syscore_ops(&cpu_syscore_ops);
1587 core_initcall(init_cpu_syscore);