1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
20 #include <asm/perf_counter.h>
25 #ifdef CONFIG_X86_LOCAL_APIC
26 #include <asm/mpspec.h>
28 #include <mach_apic.h>
29 #include <asm/genapic.h>
33 #include <asm/pgtable.h>
34 #include <asm/processor.h>
36 #include <asm/atomic.h>
37 #include <asm/proto.h>
38 #include <asm/sections.h>
39 #include <asm/setup.h>
40 #include <asm/hypervisor.h>
44 static struct cpu_dev *this_cpu __cpuinitdata;
47 /* We need valid kernel segments for data and code in long mode too
48 * IRET will check the segment types kkeil 2000/10/28
49 * Also sysret mandates a special GDT layout
51 /* The TLS descriptors are currently at a different place compared to i386.
52 Hopefully nobody expects them at a fixed place (Wine?) */
53 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
54 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
55 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
56 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
57 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
58 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
59 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
62 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
63 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
64 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
65 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
66 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
68 * Segments used for calling PnP BIOS have byte granularity.
69 * They code segments and data segments have fixed 64k limits,
70 * the transfer segment sizes are set at run time.
73 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
75 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
77 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
79 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
81 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
83 * The APM segments have byte granularity and their bases
84 * are set at run time. All have 64k limits.
87 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
89 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
91 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
93 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
94 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
97 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
100 static int cachesize_override __cpuinitdata = -1;
101 static int disable_x86_serial_nr __cpuinitdata = 1;
103 static int __init cachesize_setup(char *str)
105 get_option(&str, &cachesize_override);
108 __setup("cachesize=", cachesize_setup);
110 static int __init x86_fxsr_setup(char *s)
112 setup_clear_cpu_cap(X86_FEATURE_FXSR);
113 setup_clear_cpu_cap(X86_FEATURE_XMM);
116 __setup("nofxsr", x86_fxsr_setup);
118 static int __init x86_sep_setup(char *s)
120 setup_clear_cpu_cap(X86_FEATURE_SEP);
123 __setup("nosep", x86_sep_setup);
125 /* Standard macro to see if a specific flag is changeable */
126 static inline int flag_is_changeable_p(u32 flag)
131 * Cyrix and IDT cpus allow disabling of CPUID
132 * so the code below may return different results
133 * when it is executed before and after enabling
134 * the CPUID. Add "volatile" to not allow gcc to
135 * optimize the subsequent calls to this function.
137 asm volatile ("pushfl\n\t"
147 : "=&r" (f1), "=&r" (f2)
150 return ((f1^f2) & flag) != 0;
153 /* Probe for the CPUID instruction */
154 static int __cpuinit have_cpuid_p(void)
156 return flag_is_changeable_p(X86_EFLAGS_ID);
159 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
161 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
162 /* Disable processor serial number */
163 unsigned long lo, hi;
164 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
166 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
167 printk(KERN_NOTICE "CPU serial number disabled.\n");
168 clear_cpu_cap(c, X86_FEATURE_PN);
170 /* Disabling the serial number may affect the cpuid level */
171 c->cpuid_level = cpuid_eax(0);
175 static int __init x86_serial_nr_setup(char *s)
177 disable_x86_serial_nr = 0;
180 __setup("serialnumber", x86_serial_nr_setup);
182 static inline int flag_is_changeable_p(u32 flag)
186 /* Probe for the CPUID instruction */
187 static inline int have_cpuid_p(void)
191 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
197 * Naming convention should be: <Name> [(<Codename>)]
198 * This table only is used unless init_<vendor>() below doesn't set it;
199 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
203 /* Look up CPU names by table lookup. */
204 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
206 struct cpu_model_info *info;
208 if (c->x86_model >= 16)
209 return NULL; /* Range check */
214 info = this_cpu->c_models;
216 while (info && info->family) {
217 if (info->family == c->x86)
218 return info->model_names[c->x86_model];
221 return NULL; /* Not found */
224 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
226 /* Current gdt points %fs at the "master" per-cpu area: after this,
227 * it's on the real one. */
228 void switch_to_new_gdt(void)
230 struct desc_ptr gdt_descr;
232 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
233 gdt_descr.size = GDT_SIZE - 1;
234 load_gdt(&gdt_descr);
236 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
240 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
242 static void __cpuinit default_init(struct cpuinfo_x86 *c)
245 display_cacheinfo(c);
247 /* Not much we can do here... */
248 /* Check if at least it has cpuid */
249 if (c->cpuid_level == -1) {
250 /* No cpuid. It must be an ancient CPU */
252 strcpy(c->x86_model_id, "486");
253 else if (c->x86 == 3)
254 strcpy(c->x86_model_id, "386");
259 static struct cpu_dev __cpuinitdata default_cpu = {
260 .c_init = default_init,
261 .c_vendor = "Unknown",
262 .c_x86_vendor = X86_VENDOR_UNKNOWN,
265 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
270 if (c->extended_cpuid_level < 0x80000004)
273 v = (unsigned int *) c->x86_model_id;
274 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
275 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
276 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
277 c->x86_model_id[48] = 0;
279 /* Intel chips right-justify this string for some dumb reason;
280 undo that brain damage */
281 p = q = &c->x86_model_id[0];
287 while (q <= &c->x86_model_id[48])
288 *q++ = '\0'; /* Zero-pad the rest */
292 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
294 unsigned int n, dummy, ebx, ecx, edx, l2size;
296 n = c->extended_cpuid_level;
298 if (n >= 0x80000005) {
299 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
300 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
301 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
302 c->x86_cache_size = (ecx>>24) + (edx>>24);
304 /* On K8 L1 TLB is inclusive, so don't count it */
309 if (n < 0x80000006) /* Some chips just has a large L1. */
312 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
316 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
318 /* do processor-specific cache resizing */
319 if (this_cpu->c_size_cache)
320 l2size = this_cpu->c_size_cache(c, l2size);
322 /* Allow user to override all this if necessary. */
323 if (cachesize_override != -1)
324 l2size = cachesize_override;
327 return; /* Again, no L2 cache is possible */
330 c->x86_cache_size = l2size;
332 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
336 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
339 u32 eax, ebx, ecx, edx;
340 int index_msb, core_bits;
342 if (!cpu_has(c, X86_FEATURE_HT))
345 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
348 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
351 cpuid(1, &eax, &ebx, &ecx, &edx);
353 smp_num_siblings = (ebx & 0xff0000) >> 16;
355 if (smp_num_siblings == 1) {
356 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
357 } else if (smp_num_siblings > 1) {
359 if (smp_num_siblings > NR_CPUS) {
360 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
362 smp_num_siblings = 1;
366 index_msb = get_count_order(smp_num_siblings);
368 c->phys_proc_id = phys_pkg_id(index_msb);
370 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
373 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
375 index_msb = get_count_order(smp_num_siblings);
377 core_bits = get_count_order(c->x86_max_cores);
380 c->cpu_core_id = phys_pkg_id(index_msb) &
381 ((1 << core_bits) - 1);
383 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
384 ((1 << core_bits) - 1);
389 if ((c->x86_max_cores * smp_num_siblings) > 1) {
390 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
392 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
398 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
400 char *v = c->x86_vendor_id;
404 for (i = 0; i < X86_VENDOR_NUM; i++) {
408 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
409 (cpu_devs[i]->c_ident[1] &&
410 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
411 this_cpu = cpu_devs[i];
412 c->x86_vendor = this_cpu->c_x86_vendor;
419 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
420 printk(KERN_ERR "CPU: Your system may be unstable.\n");
423 c->x86_vendor = X86_VENDOR_UNKNOWN;
424 this_cpu = &default_cpu;
427 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
429 /* Get vendor name */
430 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
431 (unsigned int *)&c->x86_vendor_id[0],
432 (unsigned int *)&c->x86_vendor_id[8],
433 (unsigned int *)&c->x86_vendor_id[4]);
436 /* Intel-defined flags: level 0x00000001 */
437 if (c->cpuid_level >= 0x00000001) {
438 u32 junk, tfms, cap0, misc;
439 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
440 c->x86 = (tfms >> 8) & 0xf;
441 c->x86_model = (tfms >> 4) & 0xf;
442 c->x86_mask = tfms & 0xf;
444 c->x86 += (tfms >> 20) & 0xff;
446 c->x86_model += ((tfms >> 16) & 0xf) << 4;
447 if (cap0 & (1<<19)) {
448 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
449 c->x86_cache_alignment = c->x86_clflush_size;
454 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
459 /* Intel-defined flags: level 0x00000001 */
460 if (c->cpuid_level >= 0x00000001) {
461 u32 capability, excap;
462 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
463 c->x86_capability[0] = capability;
464 c->x86_capability[4] = excap;
467 /* AMD-defined flags: level 0x80000001 */
468 xlvl = cpuid_eax(0x80000000);
469 c->extended_cpuid_level = xlvl;
470 if ((xlvl & 0xffff0000) == 0x80000000) {
471 if (xlvl >= 0x80000001) {
472 c->x86_capability[1] = cpuid_edx(0x80000001);
473 c->x86_capability[6] = cpuid_ecx(0x80000001);
478 if (c->extended_cpuid_level >= 0x80000008) {
479 u32 eax = cpuid_eax(0x80000008);
481 c->x86_virt_bits = (eax >> 8) & 0xff;
482 c->x86_phys_bits = eax & 0xff;
486 if (c->extended_cpuid_level >= 0x80000007)
487 c->x86_power = cpuid_edx(0x80000007);
491 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
497 * First of all, decide if this is a 486 or higher
498 * It's a 486 if we can modify the AC flag
500 if (flag_is_changeable_p(X86_EFLAGS_AC))
505 for (i = 0; i < X86_VENDOR_NUM; i++)
506 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
507 c->x86_vendor_id[0] = 0;
508 cpu_devs[i]->c_identify(c);
509 if (c->x86_vendor_id[0]) {
518 * Do minimum CPU detection early.
519 * Fields really needed: vendor, cpuid_level, family, model, mask,
521 * The others are not touched to avoid unwanted side effects.
523 * WARNING: this function is only called on the BP. Don't add code here
524 * that is supposed to run on all CPUs.
526 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
529 c->x86_clflush_size = 64;
531 c->x86_clflush_size = 32;
533 c->x86_cache_alignment = c->x86_clflush_size;
535 memset(&c->x86_capability, 0, sizeof c->x86_capability);
536 c->extended_cpuid_level = 0;
539 identify_cpu_without_cpuid(c);
541 /* cyrix could have cpuid enabled via c_identify()*/
551 if (this_cpu->c_early_init)
552 this_cpu->c_early_init(c);
554 validate_pat_support(c);
557 c->cpu_index = boot_cpu_id;
561 void __init early_cpu_init(void)
563 struct cpu_dev **cdev;
566 printk("KERNEL supported cpus:\n");
567 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
568 struct cpu_dev *cpudev = *cdev;
571 if (count >= X86_VENDOR_NUM)
573 cpu_devs[count] = cpudev;
576 for (j = 0; j < 2; j++) {
577 if (!cpudev->c_ident[j])
579 printk(" %s %s\n", cpudev->c_vendor,
584 early_identify_cpu(&boot_cpu_data);
588 * The NOPL instruction is supposed to exist on all CPUs with
589 * family >= 6; unfortunately, that's not true in practice because
590 * of early VIA chips and (more importantly) broken virtualizers that
591 * are not easy to detect. In the latter case it doesn't even *fail*
592 * reliably, so probing for it doesn't even work. Disable it completely
593 * unless we can find a reliable way to detect all the broken cases.
595 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
597 clear_cpu_cap(c, X86_FEATURE_NOPL);
600 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
602 c->extended_cpuid_level = 0;
605 identify_cpu_without_cpuid(c);
607 /* cyrix could have cpuid enabled via c_identify()*/
617 if (c->cpuid_level >= 0x00000001) {
618 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
620 # ifdef CONFIG_X86_HT
621 c->apicid = phys_pkg_id(c->initial_apicid, 0);
623 c->apicid = c->initial_apicid;
628 c->phys_proc_id = c->initial_apicid;
632 get_model_name(c); /* Default name */
634 init_scattered_cpuid_features(c);
639 * This does the hard work of actually picking apart the CPU stuff...
641 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
645 c->loops_per_jiffy = loops_per_jiffy;
646 c->x86_cache_size = -1;
647 c->x86_vendor = X86_VENDOR_UNKNOWN;
648 c->x86_model = c->x86_mask = 0; /* So far unknown... */
649 c->x86_vendor_id[0] = '\0'; /* Unset */
650 c->x86_model_id[0] = '\0'; /* Unset */
651 c->x86_max_cores = 1;
652 c->x86_coreid_bits = 0;
654 c->x86_clflush_size = 64;
656 c->cpuid_level = -1; /* CPUID not detected */
657 c->x86_clflush_size = 32;
659 c->x86_cache_alignment = c->x86_clflush_size;
660 memset(&c->x86_capability, 0, sizeof c->x86_capability);
664 if (this_cpu->c_identify)
665 this_cpu->c_identify(c);
668 c->apicid = phys_pkg_id(0);
672 * Vendor-specific initialization. In this section we
673 * canonicalize the feature flags, meaning if there are
674 * features a certain CPU supports which CPUID doesn't
675 * tell us, CPUID claiming incorrect flags, or other bugs,
676 * we handle them here.
678 * At the end of this section, c->x86_capability better
679 * indicate the features this CPU genuinely supports!
681 if (this_cpu->c_init)
684 /* Disable the PN if appropriate */
685 squash_the_stupid_serial_number(c);
688 * The vendor-specific functions might have changed features. Now
689 * we do "generic changes."
692 /* If the model name is still unset, do table lookup. */
693 if (!c->x86_model_id[0]) {
695 p = table_lookup_model(c);
697 strcpy(c->x86_model_id, p);
700 sprintf(c->x86_model_id, "%02x/%02x",
701 c->x86, c->x86_model);
710 * On SMP, boot_cpu_data holds the common feature set between
711 * all CPUs; so make sure that we indicate which features are
712 * common between the CPUs. The first time this routine gets
713 * executed, c == &boot_cpu_data.
715 if (c != &boot_cpu_data) {
716 /* AND the already accumulated flags with these */
717 for (i = 0; i < NCAPINTS; i++)
718 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
721 /* Clear all flags overriden by options */
722 for (i = 0; i < NCAPINTS; i++)
723 c->x86_capability[i] &= ~cleared_cpu_caps[i];
725 #ifdef CONFIG_X86_MCE
726 /* Init Machine Check Exception if available. */
730 select_idle_routine(c);
732 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
733 numa_add_cpu(smp_processor_id());
738 static void vgetcpu_set_mode(void)
740 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
741 vgetcpu_mode = VGETCPU_RDTSCP;
743 vgetcpu_mode = VGETCPU_LSL;
747 void __init identify_boot_cpu(void)
749 identify_cpu(&boot_cpu_data);
756 init_hw_perf_counters();
759 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
761 BUG_ON(c == &boot_cpu_data);
774 static struct msr_range msr_range_array[] __cpuinitdata = {
775 { 0x00000000, 0x00000418},
776 { 0xc0000000, 0xc000040b},
777 { 0xc0010000, 0xc0010142},
778 { 0xc0011000, 0xc001103b},
781 static void __cpuinit print_cpu_msr(void)
786 unsigned index_min, index_max;
788 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
789 index_min = msr_range_array[i].min;
790 index_max = msr_range_array[i].max;
791 for (index = index_min; index < index_max; index++) {
792 if (rdmsrl_amd_safe(index, &val))
794 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
799 static int show_msr __cpuinitdata;
800 static __init int setup_show_msr(char *arg)
804 get_option(&arg, &num);
810 __setup("show_msr=", setup_show_msr);
812 static __init int setup_noclflush(char *arg)
814 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
817 __setup("noclflush", setup_noclflush);
819 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
823 if (c->x86_vendor < X86_VENDOR_NUM)
824 vendor = this_cpu->c_vendor;
825 else if (c->cpuid_level >= 0)
826 vendor = c->x86_vendor_id;
828 if (vendor && !strstr(c->x86_model_id, vendor))
829 printk(KERN_CONT "%s ", vendor);
831 if (c->x86_model_id[0])
832 printk(KERN_CONT "%s", c->x86_model_id);
834 printk(KERN_CONT "%d86", c->x86);
836 if (c->x86_mask || c->cpuid_level >= 0)
837 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
839 printk(KERN_CONT "\n");
842 if (c->cpu_index < show_msr)
850 static __init int setup_disablecpuid(char *arg)
853 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
854 setup_clear_cpu_cap(bit);
859 __setup("clearcpuid=", setup_disablecpuid);
861 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
864 struct x8664_pda **_cpu_pda __read_mostly;
865 EXPORT_SYMBOL(_cpu_pda);
867 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
869 static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
871 void __cpuinit pda_init(int cpu)
873 struct x8664_pda *pda = cpu_pda(cpu);
875 /* Setup up data that may be needed in __get_free_pages early */
878 /* Memory clobbers used to order PDA accessed */
880 wrmsrl(MSR_GS_BASE, pda);
883 pda->cpunumber = cpu;
885 pda->kernelstack = (unsigned long)stack_thread_info() -
886 PDA_STACKOFFSET + THREAD_SIZE;
887 pda->active_mm = &init_mm;
891 /* others are initialized in smpboot.c */
892 pda->pcurrent = &init_task;
893 pda->irqstackptr = boot_cpu_stack;
894 pda->irqstackptr += IRQSTACKSIZE - 64;
896 if (!pda->irqstackptr) {
897 pda->irqstackptr = (char *)
898 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
899 if (!pda->irqstackptr)
900 panic("cannot allocate irqstack for cpu %d",
902 pda->irqstackptr += IRQSTACKSIZE - 64;
905 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
906 pda->nodenumber = cpu_to_node(cpu);
910 static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
911 DEBUG_STKSZ] __page_aligned_bss;
913 extern asmlinkage void ignore_sysret(void);
915 /* May not be marked __init: used by software suspend */
916 void syscall_init(void)
919 * LSTAR and STAR live in a bit strange symbiosis.
920 * They both write to the same internal register. STAR allows to
921 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
923 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
924 wrmsrl(MSR_LSTAR, system_call);
925 wrmsrl(MSR_CSTAR, ignore_sysret);
927 #ifdef CONFIG_IA32_EMULATION
928 syscall32_cpu_init();
931 /* Flags to clear on syscall */
932 wrmsrl(MSR_SYSCALL_MASK,
933 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
936 unsigned long kernel_eflags;
939 * Copies of the original ist values from the tss are only accessed during
940 * debugging, no special alignment required.
942 DEFINE_PER_CPU(struct orig_ist, orig_ist);
946 /* Make sure %fs is initialized properly in idle threads */
947 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
949 memset(regs, 0, sizeof(struct pt_regs));
950 regs->fs = __KERNEL_PERCPU;
956 * cpu_init() initializes state that is per-CPU. Some data is already
957 * initialized (naturally) in the bootstrap process, such as the GDT
958 * and IDT. We reload them nevertheless, this function acts as a
959 * 'CPU state barrier', nothing should get across.
960 * A lot of state is already set up in PDA init for 64 bit
963 void __cpuinit cpu_init(void)
965 int cpu = stack_smp_processor_id();
966 struct tss_struct *t = &per_cpu(init_tss, cpu);
967 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
969 char *estacks = NULL;
970 struct task_struct *me;
973 /* CPU 0 is initialised in head64.c */
977 estacks = boot_exception_stacks;
981 if (cpu_test_and_set(cpu, cpu_initialized))
982 panic("CPU#%d already initialized!\n", cpu);
984 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
986 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
989 * Initialize the per-CPU GDT with the boot GDT,
990 * and set up the GDT descriptor:
994 load_idt((const struct desc_ptr *)&idt_descr);
996 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
999 wrmsrl(MSR_FS_BASE, 0);
1000 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1004 if (cpu != 0 && x2apic)
1008 * set up and load the per-CPU TSS
1010 if (!orig_ist->ist[0]) {
1011 static const unsigned int order[N_EXCEPTION_STACKS] = {
1012 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
1013 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
1015 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1017 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
1019 panic("Cannot allocate exception "
1020 "stack %ld %d\n", v, cpu);
1022 estacks += PAGE_SIZE << order[v];
1023 orig_ist->ist[v] = t->x86_tss.ist[v] =
1024 (unsigned long)estacks;
1028 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1030 * <= is required because the CPU will access up to
1031 * 8 bits beyond the end of the IO permission bitmap.
1033 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1034 t->io_bitmap[i] = ~0UL;
1036 atomic_inc(&init_mm.mm_count);
1037 me->active_mm = &init_mm;
1040 enter_lazy_tlb(&init_mm, me);
1042 load_sp0(t, ¤t->thread);
1043 set_tss_desc(cpu, t);
1045 load_LDT(&init_mm.context);
1049 * If the kgdb is connected no debug regs should be altered. This
1050 * is only applicable when KGDB and a KGDB I/O module are built
1051 * into the kernel and you are using early debugging with
1052 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1054 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1055 arch_kgdb_ops.correct_hw_break();
1059 * Clear all 6 debug registers:
1062 set_debugreg(0UL, 0);
1063 set_debugreg(0UL, 1);
1064 set_debugreg(0UL, 2);
1065 set_debugreg(0UL, 3);
1066 set_debugreg(0UL, 6);
1067 set_debugreg(0UL, 7);
1069 /* If the kgdb is connected no debug regs should be altered. */
1075 raw_local_save_flags(kernel_eflags);
1083 void __cpuinit cpu_init(void)
1085 int cpu = smp_processor_id();
1086 struct task_struct *curr = current;
1087 struct tss_struct *t = &per_cpu(init_tss, cpu);
1088 struct thread_struct *thread = &curr->thread;
1090 if (cpu_test_and_set(cpu, cpu_initialized)) {
1091 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1092 for (;;) local_irq_enable();
1095 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1097 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1098 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1100 load_idt(&idt_descr);
1101 switch_to_new_gdt();
1104 * Set up and load the per-CPU TSS and LDT
1106 atomic_inc(&init_mm.mm_count);
1107 curr->active_mm = &init_mm;
1110 enter_lazy_tlb(&init_mm, curr);
1112 load_sp0(t, thread);
1113 set_tss_desc(cpu, t);
1115 load_LDT(&init_mm.context);
1117 #ifdef CONFIG_DOUBLEFAULT
1118 /* Set up doublefault TSS pointer in the GDT */
1119 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1123 asm volatile ("mov %0, %%gs" : : "r" (0));
1125 /* Clear all 6 debug registers: */
1134 * Force FPU initialization:
1137 current_thread_info()->status = TS_XSAVE;
1139 current_thread_info()->status = 0;
1141 mxcsr_feature_mask_init();
1144 * Boot processor to setup the FP and extended state context info.
1146 if (smp_processor_id() == boot_cpu_id)
1147 init_thread_xstate();