1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/hwcap2.h>
39 #include <linux/numa.h>
46 #include <asm/microcode.h>
47 #include <asm/microcode_intel.h>
49 #ifdef CONFIG_X86_LOCAL_APIC
50 #include <asm/uv/uv.h>
55 u32 elf_hwcap2 __read_mostly;
57 /* all of these masks are initialized in setup_cpu_local_masks() */
58 cpumask_var_t cpu_initialized_mask;
59 cpumask_var_t cpu_callout_mask;
60 cpumask_var_t cpu_callin_mask;
62 /* representing cpus for which sibling maps can be computed */
63 cpumask_var_t cpu_sibling_setup_mask;
65 /* correctly size the local cpu masks */
66 void __init setup_cpu_local_masks(void)
68 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
69 alloc_bootmem_cpumask_var(&cpu_callin_mask);
70 alloc_bootmem_cpumask_var(&cpu_callout_mask);
71 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
74 static void default_init(struct cpuinfo_x86 *c)
77 cpu_detect_cache_sizes(c);
79 /* Not much we can do here... */
80 /* Check if at least it has cpuid */
81 if (c->cpuid_level == -1) {
82 /* No cpuid. It must be an ancient CPU */
84 strcpy(c->x86_model_id, "486");
86 strcpy(c->x86_model_id, "386");
89 clear_sched_clock_stable();
92 static const struct cpu_dev default_cpu = {
93 .c_init = default_init,
94 .c_vendor = "Unknown",
95 .c_x86_vendor = X86_VENDOR_UNKNOWN,
98 static const struct cpu_dev *this_cpu = &default_cpu;
100 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
103 * We need valid kernel segments for data and code in long mode too
104 * IRET will check the segment types kkeil 2000/10/28
105 * Also sysret mandates a special GDT layout
107 * TLS descriptors are currently at a different place compared to i386.
108 * Hopefully nobody expects them at a fixed place (Wine?)
110 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
111 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
113 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
117 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
118 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
119 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
120 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
122 * Segments used for calling PnP BIOS have byte granularity.
123 * They code segments and data segments have fixed 64k limits,
124 * the transfer segment sizes are set at run time.
127 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
129 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
131 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
133 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
135 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
137 * The APM segments have byte granularity and their bases
138 * are set at run time. All have 64k limits.
141 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
143 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
145 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
147 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
148 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
149 GDT_STACK_CANARY_INIT
152 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
154 static int __init x86_mpx_setup(char *s)
156 /* require an exact match without trailing characters */
160 /* do not emit a message if the feature is not present */
161 if (!boot_cpu_has(X86_FEATURE_MPX))
164 setup_clear_cpu_cap(X86_FEATURE_MPX);
165 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
168 __setup("nompx", x86_mpx_setup);
170 static int __init x86_noinvpcid_setup(char *s)
172 /* noinvpcid doesn't accept parameters */
176 /* do not emit a message if the feature is not present */
177 if (!boot_cpu_has(X86_FEATURE_INVPCID))
180 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
181 pr_info("noinvpcid: INVPCID feature disabled\n");
184 early_param("noinvpcid", x86_noinvpcid_setup);
187 static int cachesize_override = -1;
188 static int disable_x86_serial_nr = 1;
190 static int __init cachesize_setup(char *str)
192 get_option(&str, &cachesize_override);
195 __setup("cachesize=", cachesize_setup);
197 static int __init x86_sep_setup(char *s)
199 setup_clear_cpu_cap(X86_FEATURE_SEP);
202 __setup("nosep", x86_sep_setup);
204 /* Standard macro to see if a specific flag is changeable */
205 static inline int flag_is_changeable_p(u32 flag)
210 * Cyrix and IDT cpus allow disabling of CPUID
211 * so the code below may return different results
212 * when it is executed before and after enabling
213 * the CPUID. Add "volatile" to not allow gcc to
214 * optimize the subsequent calls to this function.
216 asm volatile ("pushfl \n\t"
227 : "=&r" (f1), "=&r" (f2)
230 return ((f1^f2) & flag) != 0;
233 /* Probe for the CPUID instruction */
234 int have_cpuid_p(void)
236 return flag_is_changeable_p(X86_EFLAGS_ID);
239 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
241 unsigned long lo, hi;
243 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
246 /* Disable processor serial number: */
248 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
250 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
252 pr_notice("CPU serial number disabled.\n");
253 clear_cpu_cap(c, X86_FEATURE_PN);
255 /* Disabling the serial number may affect the cpuid level */
256 c->cpuid_level = cpuid_eax(0);
259 static int __init x86_serial_nr_setup(char *s)
261 disable_x86_serial_nr = 0;
264 __setup("serialnumber", x86_serial_nr_setup);
266 static inline int flag_is_changeable_p(u32 flag)
270 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
275 static __init int setup_disable_smep(char *arg)
277 setup_clear_cpu_cap(X86_FEATURE_SMEP);
278 /* Check for things that depend on SMEP being enabled: */
279 check_mpx_erratum(&boot_cpu_data);
282 __setup("nosmep", setup_disable_smep);
284 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
286 if (cpu_has(c, X86_FEATURE_SMEP))
287 cr4_set_bits(X86_CR4_SMEP);
290 static __init int setup_disable_smap(char *arg)
292 setup_clear_cpu_cap(X86_FEATURE_SMAP);
295 __setup("nosmap", setup_disable_smap);
297 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
299 unsigned long eflags = native_save_fl();
301 /* This should have been cleared long ago */
302 BUG_ON(eflags & X86_EFLAGS_AC);
304 if (cpu_has(c, X86_FEATURE_SMAP)) {
305 #ifdef CONFIG_X86_SMAP
306 cr4_set_bits(X86_CR4_SMAP);
308 cr4_clear_bits(X86_CR4_SMAP);
314 * Protection Keys are not available in 32-bit mode.
316 static bool pku_disabled;
318 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
320 /* check the boot processor, plus compile options for PKU: */
321 if (!cpu_feature_enabled(X86_FEATURE_PKU))
323 /* checks the actual processor's cpuid bits: */
324 if (!cpu_has(c, X86_FEATURE_PKU))
329 cr4_set_bits(X86_CR4_PKE);
331 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
332 * cpuid bit to be set. We need to ensure that we
333 * update that bit in this CPU's "cpu_info".
338 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
339 static __init int setup_disable_pku(char *arg)
342 * Do not clear the X86_FEATURE_PKU bit. All of the
343 * runtime checks are against OSPKE so clearing the
346 * This way, we will see "pku" in cpuinfo, but not
347 * "ospke", which is exactly what we want. It shows
348 * that the CPU has PKU, but the OS has not enabled it.
349 * This happens to be exactly how a system would look
350 * if we disabled the config option.
352 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
356 __setup("nopku", setup_disable_pku);
357 #endif /* CONFIG_X86_64 */
360 * Some CPU features depend on higher CPUID levels, which may not always
361 * be available due to CPUID level capping or broken virtualization
362 * software. Add those features to this table to auto-disable them.
364 struct cpuid_dependent_feature {
369 static const struct cpuid_dependent_feature
370 cpuid_dependent_features[] = {
371 { X86_FEATURE_MWAIT, 0x00000005 },
372 { X86_FEATURE_DCA, 0x00000009 },
373 { X86_FEATURE_XSAVE, 0x0000000d },
377 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
379 const struct cpuid_dependent_feature *df;
381 for (df = cpuid_dependent_features; df->feature; df++) {
383 if (!cpu_has(c, df->feature))
386 * Note: cpuid_level is set to -1 if unavailable, but
387 * extended_extended_level is set to 0 if unavailable
388 * and the legitimate extended levels are all negative
389 * when signed; hence the weird messing around with
392 if (!((s32)df->level < 0 ?
393 (u32)df->level > (u32)c->extended_cpuid_level :
394 (s32)df->level > (s32)c->cpuid_level))
397 clear_cpu_cap(c, df->feature);
401 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
402 x86_cap_flag(df->feature), df->level);
407 * Naming convention should be: <Name> [(<Codename>)]
408 * This table only is used unless init_<vendor>() below doesn't set it;
409 * in particular, if CPUID levels 0x80000002..4 are supported, this
413 /* Look up CPU names by table lookup. */
414 static const char *table_lookup_model(struct cpuinfo_x86 *c)
417 const struct legacy_cpu_model_info *info;
419 if (c->x86_model >= 16)
420 return NULL; /* Range check */
425 info = this_cpu->legacy_models;
427 while (info->family) {
428 if (info->family == c->x86)
429 return info->model_names[c->x86_model];
433 return NULL; /* Not found */
436 __u32 cpu_caps_cleared[NCAPINTS];
437 __u32 cpu_caps_set[NCAPINTS];
439 void load_percpu_segment(int cpu)
442 loadsegment(fs, __KERNEL_PERCPU);
444 __loadsegment_simple(gs, 0);
445 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
447 load_stack_canary_segment();
451 * Current gdt points %fs at the "master" per-cpu area: after this,
452 * it's on the real one.
454 void switch_to_new_gdt(int cpu)
456 struct desc_ptr gdt_descr;
458 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
459 gdt_descr.size = GDT_SIZE - 1;
460 load_gdt(&gdt_descr);
461 /* Reload the per-cpu base */
463 load_percpu_segment(cpu);
466 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
468 static void get_model_name(struct cpuinfo_x86 *c)
473 if (c->extended_cpuid_level < 0x80000004)
476 v = (unsigned int *)c->x86_model_id;
477 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
478 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
479 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
480 c->x86_model_id[48] = 0;
482 /* Trim whitespace */
483 p = q = s = &c->x86_model_id[0];
489 /* Note the last non-whitespace index */
499 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
501 unsigned int n, dummy, ebx, ecx, edx, l2size;
503 n = c->extended_cpuid_level;
505 if (n >= 0x80000005) {
506 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
507 c->x86_cache_size = (ecx>>24) + (edx>>24);
509 /* On K8 L1 TLB is inclusive, so don't count it */
514 if (n < 0x80000006) /* Some chips just has a large L1. */
517 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
521 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
523 /* do processor-specific cache resizing */
524 if (this_cpu->legacy_cache_size)
525 l2size = this_cpu->legacy_cache_size(c, l2size);
527 /* Allow user to override all this if necessary. */
528 if (cachesize_override != -1)
529 l2size = cachesize_override;
532 return; /* Again, no L2 cache is possible */
535 c->x86_cache_size = l2size;
538 u16 __read_mostly tlb_lli_4k[NR_INFO];
539 u16 __read_mostly tlb_lli_2m[NR_INFO];
540 u16 __read_mostly tlb_lli_4m[NR_INFO];
541 u16 __read_mostly tlb_lld_4k[NR_INFO];
542 u16 __read_mostly tlb_lld_2m[NR_INFO];
543 u16 __read_mostly tlb_lld_4m[NR_INFO];
544 u16 __read_mostly tlb_lld_1g[NR_INFO];
546 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
548 if (this_cpu->c_detect_tlb)
549 this_cpu->c_detect_tlb(c);
551 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
552 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
553 tlb_lli_4m[ENTRIES]);
555 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
556 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
557 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
560 void detect_ht(struct cpuinfo_x86 *c)
563 u32 eax, ebx, ecx, edx;
564 int index_msb, core_bits;
567 if (!cpu_has(c, X86_FEATURE_HT))
570 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
573 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
576 cpuid(1, &eax, &ebx, &ecx, &edx);
578 smp_num_siblings = (ebx & 0xff0000) >> 16;
580 if (smp_num_siblings == 1) {
581 pr_info_once("CPU0: Hyper-Threading is disabled\n");
585 if (smp_num_siblings <= 1)
588 index_msb = get_count_order(smp_num_siblings);
589 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
591 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
593 index_msb = get_count_order(smp_num_siblings);
595 core_bits = get_count_order(c->x86_max_cores);
597 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
598 ((1 << core_bits) - 1);
601 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
602 pr_info("CPU: Physical Processor ID: %d\n",
604 pr_info("CPU: Processor Core ID: %d\n",
611 static void get_cpu_vendor(struct cpuinfo_x86 *c)
613 char *v = c->x86_vendor_id;
616 for (i = 0; i < X86_VENDOR_NUM; i++) {
620 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
621 (cpu_devs[i]->c_ident[1] &&
622 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
624 this_cpu = cpu_devs[i];
625 c->x86_vendor = this_cpu->c_x86_vendor;
630 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
631 "CPU: Your system may be unstable.\n", v);
633 c->x86_vendor = X86_VENDOR_UNKNOWN;
634 this_cpu = &default_cpu;
637 void cpu_detect(struct cpuinfo_x86 *c)
639 /* Get vendor name */
640 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
641 (unsigned int *)&c->x86_vendor_id[0],
642 (unsigned int *)&c->x86_vendor_id[8],
643 (unsigned int *)&c->x86_vendor_id[4]);
646 /* Intel-defined flags: level 0x00000001 */
647 if (c->cpuid_level >= 0x00000001) {
648 u32 junk, tfms, cap0, misc;
650 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
651 c->x86 = x86_family(tfms);
652 c->x86_model = x86_model(tfms);
653 c->x86_mask = x86_stepping(tfms);
655 if (cap0 & (1<<19)) {
656 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
657 c->x86_cache_alignment = c->x86_clflush_size;
662 static void apply_forced_caps(struct cpuinfo_x86 *c)
666 for (i = 0; i < NCAPINTS; i++) {
667 c->x86_capability[i] &= ~cpu_caps_cleared[i];
668 c->x86_capability[i] |= cpu_caps_set[i];
672 void get_cpu_cap(struct cpuinfo_x86 *c)
674 u32 eax, ebx, ecx, edx;
676 /* Intel-defined flags: level 0x00000001 */
677 if (c->cpuid_level >= 0x00000001) {
678 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
680 c->x86_capability[CPUID_1_ECX] = ecx;
681 c->x86_capability[CPUID_1_EDX] = edx;
684 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
685 if (c->cpuid_level >= 0x00000006)
686 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
688 /* Additional Intel-defined flags: level 0x00000007 */
689 if (c->cpuid_level >= 0x00000007) {
690 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
691 c->x86_capability[CPUID_7_0_EBX] = ebx;
692 c->x86_capability[CPUID_7_ECX] = ecx;
695 /* Extended state features: level 0x0000000d */
696 if (c->cpuid_level >= 0x0000000d) {
697 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
699 c->x86_capability[CPUID_D_1_EAX] = eax;
702 /* Additional Intel-defined flags: level 0x0000000F */
703 if (c->cpuid_level >= 0x0000000F) {
705 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
706 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
707 c->x86_capability[CPUID_F_0_EDX] = edx;
709 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
710 /* will be overridden if occupancy monitoring exists */
711 c->x86_cache_max_rmid = ebx;
713 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
714 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
715 c->x86_capability[CPUID_F_1_EDX] = edx;
717 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
718 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
719 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
720 c->x86_cache_max_rmid = ecx;
721 c->x86_cache_occ_scale = ebx;
724 c->x86_cache_max_rmid = -1;
725 c->x86_cache_occ_scale = -1;
729 /* AMD-defined flags: level 0x80000001 */
730 eax = cpuid_eax(0x80000000);
731 c->extended_cpuid_level = eax;
733 if ((eax & 0xffff0000) == 0x80000000) {
734 if (eax >= 0x80000001) {
735 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
737 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
738 c->x86_capability[CPUID_8000_0001_EDX] = edx;
742 if (c->extended_cpuid_level >= 0x80000007) {
743 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
745 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
749 if (c->extended_cpuid_level >= 0x80000008) {
750 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
752 c->x86_virt_bits = (eax >> 8) & 0xff;
753 c->x86_phys_bits = eax & 0xff;
754 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
757 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
758 c->x86_phys_bits = 36;
761 if (c->extended_cpuid_level >= 0x8000000a)
762 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
764 init_scattered_cpuid_features(c);
767 * Clear/Set all flags overridden by options, after probe.
768 * This needs to happen each time we re-probe, which may happen
769 * several times during CPU initialization.
771 apply_forced_caps(c);
774 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
780 * First of all, decide if this is a 486 or higher
781 * It's a 486 if we can modify the AC flag
783 if (flag_is_changeable_p(X86_EFLAGS_AC))
788 for (i = 0; i < X86_VENDOR_NUM; i++)
789 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
790 c->x86_vendor_id[0] = 0;
791 cpu_devs[i]->c_identify(c);
792 if (c->x86_vendor_id[0]) {
801 * Do minimum CPU detection early.
802 * Fields really needed: vendor, cpuid_level, family, model, mask,
804 * The others are not touched to avoid unwanted side effects.
806 * WARNING: this function is only called on the BP. Don't add code here
807 * that is supposed to run on all CPUs.
809 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
812 c->x86_clflush_size = 64;
813 c->x86_phys_bits = 36;
814 c->x86_virt_bits = 48;
816 c->x86_clflush_size = 32;
817 c->x86_phys_bits = 32;
818 c->x86_virt_bits = 32;
820 c->x86_cache_alignment = c->x86_clflush_size;
822 memset(&c->x86_capability, 0, sizeof c->x86_capability);
823 c->extended_cpuid_level = 0;
825 /* cyrix could have cpuid enabled via c_identify()*/
826 if (have_cpuid_p()) {
830 setup_force_cpu_cap(X86_FEATURE_CPUID);
832 if (this_cpu->c_early_init)
833 this_cpu->c_early_init(c);
836 filter_cpuid_features(c, false);
838 if (this_cpu->c_bsp_init)
839 this_cpu->c_bsp_init(c);
841 identify_cpu_without_cpuid(c);
842 setup_clear_cpu_cap(X86_FEATURE_CPUID);
845 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
849 void __init early_cpu_init(void)
851 const struct cpu_dev *const *cdev;
854 #ifdef CONFIG_PROCESSOR_SELECT
855 pr_info("KERNEL supported cpus:\n");
858 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
859 const struct cpu_dev *cpudev = *cdev;
861 if (count >= X86_VENDOR_NUM)
863 cpu_devs[count] = cpudev;
866 #ifdef CONFIG_PROCESSOR_SELECT
870 for (j = 0; j < 2; j++) {
871 if (!cpudev->c_ident[j])
873 pr_info(" %s %s\n", cpudev->c_vendor,
879 early_identify_cpu(&boot_cpu_data);
883 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
884 * unfortunately, that's not true in practice because of early VIA
885 * chips and (more importantly) broken virtualizers that are not easy
886 * to detect. In the latter case it doesn't even *fail* reliably, so
887 * probing for it doesn't even work. Disable it completely on 32-bit
888 * unless we can find a reliable way to detect all the broken cases.
889 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
891 static void detect_nopl(struct cpuinfo_x86 *c)
894 clear_cpu_cap(c, X86_FEATURE_NOPL);
896 set_cpu_cap(c, X86_FEATURE_NOPL);
900 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
904 * Empirically, writing zero to a segment selector on AMD does
905 * not clear the base, whereas writing zero to a segment
906 * selector on Intel does clear the base. Intel's behavior
907 * allows slightly faster context switches in the common case
908 * where GS is unused by the prev and next threads.
910 * Since neither vendor documents this anywhere that I can see,
911 * detect it directly instead of hardcoding the choice by
914 * I've designated AMD's behavior as the "bug" because it's
915 * counterintuitive and less friendly.
918 unsigned long old_base, tmp;
919 rdmsrl(MSR_FS_BASE, old_base);
920 wrmsrl(MSR_FS_BASE, 1);
922 rdmsrl(MSR_FS_BASE, tmp);
924 set_cpu_bug(c, X86_BUG_NULL_SEG);
925 wrmsrl(MSR_FS_BASE, old_base);
929 static void generic_identify(struct cpuinfo_x86 *c)
931 c->extended_cpuid_level = 0;
934 identify_cpu_without_cpuid(c);
936 /* cyrix could have cpuid enabled via c_identify()*/
946 if (c->cpuid_level >= 0x00000001) {
947 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
950 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
952 c->apicid = c->initial_apicid;
955 c->phys_proc_id = c->initial_apicid;
958 get_model_name(c); /* Default name */
962 detect_null_seg_behavior(c);
965 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
966 * systems that run Linux at CPL > 0 may or may not have the
967 * issue, but, even if they have the issue, there's absolutely
968 * nothing we can do about it because we can't use the real IRET
971 * NB: For the time being, only 32-bit kernels support
972 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
973 * whether to apply espfix using paravirt hooks. If any
974 * non-paravirt system ever shows up that does *not* have the
975 * ESPFIX issue, we can change this.
978 # ifdef CONFIG_PARAVIRT
980 extern void native_iret(void);
981 if (pv_cpu_ops.iret == native_iret)
982 set_cpu_bug(c, X86_BUG_ESPFIX);
985 set_cpu_bug(c, X86_BUG_ESPFIX);
990 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
993 * The heavy lifting of max_rmid and cache_occ_scale are handled
994 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
995 * in case CQM bits really aren't there in this CPU.
997 if (c != &boot_cpu_data) {
998 boot_cpu_data.x86_cache_max_rmid =
999 min(boot_cpu_data.x86_cache_max_rmid,
1000 c->x86_cache_max_rmid);
1005 * Validate that ACPI/mptables have the same information about the
1006 * effective APIC id and update the package map.
1008 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1011 unsigned int apicid, cpu = smp_processor_id();
1013 apicid = apic->cpu_present_to_apicid(cpu);
1015 if (apicid != c->apicid) {
1016 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1017 cpu, apicid, c->initial_apicid);
1019 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1021 c->logical_proc_id = 0;
1026 * This does the hard work of actually picking apart the CPU stuff...
1028 static void identify_cpu(struct cpuinfo_x86 *c)
1032 c->loops_per_jiffy = loops_per_jiffy;
1033 c->x86_cache_size = -1;
1034 c->x86_vendor = X86_VENDOR_UNKNOWN;
1035 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1036 c->x86_vendor_id[0] = '\0'; /* Unset */
1037 c->x86_model_id[0] = '\0'; /* Unset */
1038 c->x86_max_cores = 1;
1039 c->x86_coreid_bits = 0;
1041 #ifdef CONFIG_X86_64
1042 c->x86_clflush_size = 64;
1043 c->x86_phys_bits = 36;
1044 c->x86_virt_bits = 48;
1046 c->cpuid_level = -1; /* CPUID not detected */
1047 c->x86_clflush_size = 32;
1048 c->x86_phys_bits = 32;
1049 c->x86_virt_bits = 32;
1051 c->x86_cache_alignment = c->x86_clflush_size;
1052 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1054 generic_identify(c);
1056 if (this_cpu->c_identify)
1057 this_cpu->c_identify(c);
1059 /* Clear/Set all flags overridden by options, after probe */
1060 apply_forced_caps(c);
1062 #ifdef CONFIG_X86_64
1063 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1067 * Vendor-specific initialization. In this section we
1068 * canonicalize the feature flags, meaning if there are
1069 * features a certain CPU supports which CPUID doesn't
1070 * tell us, CPUID claiming incorrect flags, or other bugs,
1071 * we handle them here.
1073 * At the end of this section, c->x86_capability better
1074 * indicate the features this CPU genuinely supports!
1076 if (this_cpu->c_init)
1077 this_cpu->c_init(c);
1079 clear_sched_clock_stable();
1081 /* Disable the PN if appropriate */
1082 squash_the_stupid_serial_number(c);
1084 /* Set up SMEP/SMAP */
1089 * The vendor-specific functions might have changed features.
1090 * Now we do "generic changes."
1093 /* Filter out anything that depends on CPUID levels we don't have */
1094 filter_cpuid_features(c, true);
1096 /* If the model name is still unset, do table lookup. */
1097 if (!c->x86_model_id[0]) {
1099 p = table_lookup_model(c);
1101 strcpy(c->x86_model_id, p);
1103 /* Last resort... */
1104 sprintf(c->x86_model_id, "%02x/%02x",
1105 c->x86, c->x86_model);
1108 #ifdef CONFIG_X86_64
1114 x86_init_cache_qos(c);
1118 * Clear/Set all flags overridden by options, need do it
1119 * before following smp all cpus cap AND.
1121 apply_forced_caps(c);
1124 * On SMP, boot_cpu_data holds the common feature set between
1125 * all CPUs; so make sure that we indicate which features are
1126 * common between the CPUs. The first time this routine gets
1127 * executed, c == &boot_cpu_data.
1129 if (c != &boot_cpu_data) {
1130 /* AND the already accumulated flags with these */
1131 for (i = 0; i < NCAPINTS; i++)
1132 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1134 /* OR, i.e. replicate the bug flags */
1135 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1136 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1139 /* Init Machine Check Exception if available. */
1142 select_idle_routine(c);
1145 numa_add_cpu(smp_processor_id());
1150 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1151 * on 32-bit kernels:
1153 #ifdef CONFIG_X86_32
1154 void enable_sep_cpu(void)
1156 struct tss_struct *tss;
1159 if (!boot_cpu_has(X86_FEATURE_SEP))
1163 tss = &per_cpu(cpu_tss, cpu);
1166 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1167 * see the big comment in struct x86_hw_tss's definition.
1170 tss->x86_tss.ss1 = __KERNEL_CS;
1171 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1173 wrmsr(MSR_IA32_SYSENTER_ESP,
1174 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1177 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1183 void __init identify_boot_cpu(void)
1185 identify_cpu(&boot_cpu_data);
1186 #ifdef CONFIG_X86_32
1190 cpu_detect_tlb(&boot_cpu_data);
1193 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1195 BUG_ON(c == &boot_cpu_data);
1197 #ifdef CONFIG_X86_32
1201 validate_apic_and_package_id(c);
1204 static __init int setup_noclflush(char *arg)
1206 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1207 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1210 __setup("noclflush", setup_noclflush);
1212 void print_cpu_info(struct cpuinfo_x86 *c)
1214 const char *vendor = NULL;
1216 if (c->x86_vendor < X86_VENDOR_NUM) {
1217 vendor = this_cpu->c_vendor;
1219 if (c->cpuid_level >= 0)
1220 vendor = c->x86_vendor_id;
1223 if (vendor && !strstr(c->x86_model_id, vendor))
1224 pr_cont("%s ", vendor);
1226 if (c->x86_model_id[0])
1227 pr_cont("%s", c->x86_model_id);
1229 pr_cont("%d86", c->x86);
1231 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1233 if (c->x86_mask || c->cpuid_level >= 0)
1234 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1239 static __init int setup_disablecpuid(char *arg)
1243 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1244 setup_clear_cpu_cap(bit);
1250 __setup("clearcpuid=", setup_disablecpuid);
1252 #ifdef CONFIG_X86_64
1253 struct desc_ptr idt_descr __ro_after_init = {
1254 .size = NR_VECTORS * 16 - 1,
1255 .address = (unsigned long) idt_table,
1257 const struct desc_ptr debug_idt_descr = {
1258 .size = NR_VECTORS * 16 - 1,
1259 .address = (unsigned long) debug_idt_table,
1262 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1263 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1266 * The following percpu variables are hot. Align current_task to
1267 * cacheline size such that they fall in the same cacheline.
1269 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1271 EXPORT_PER_CPU_SYMBOL(current_task);
1273 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1274 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1276 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1278 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1279 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1282 * Special IST stacks which the CPU switches to when it calls
1283 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1284 * limit), all of them are 4K, except the debug stack which
1287 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1288 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1289 [DEBUG_STACK - 1] = DEBUG_STKSZ
1292 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1293 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1295 /* May not be marked __init: used by software suspend */
1296 void syscall_init(void)
1298 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1299 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1301 #ifdef CONFIG_IA32_EMULATION
1302 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1304 * This only works on Intel CPUs.
1305 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1306 * This does not cause SYSENTER to jump to the wrong location, because
1307 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1309 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1310 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1311 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1313 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1314 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1315 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1316 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1319 /* Flags to clear on syscall */
1320 wrmsrl(MSR_SYSCALL_MASK,
1321 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1322 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1326 * Copies of the original ist values from the tss are only accessed during
1327 * debugging, no special alignment required.
1329 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1331 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1332 DEFINE_PER_CPU(int, debug_stack_usage);
1334 int is_debug_stack(unsigned long addr)
1336 return __this_cpu_read(debug_stack_usage) ||
1337 (addr <= __this_cpu_read(debug_stack_addr) &&
1338 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1340 NOKPROBE_SYMBOL(is_debug_stack);
1342 DEFINE_PER_CPU(u32, debug_idt_ctr);
1344 void debug_stack_set_zero(void)
1346 this_cpu_inc(debug_idt_ctr);
1349 NOKPROBE_SYMBOL(debug_stack_set_zero);
1351 void debug_stack_reset(void)
1353 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1355 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1358 NOKPROBE_SYMBOL(debug_stack_reset);
1360 #else /* CONFIG_X86_64 */
1362 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1363 EXPORT_PER_CPU_SYMBOL(current_task);
1364 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1365 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1368 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1369 * the top of the kernel stack. Use an extra percpu variable to track the
1370 * top of the kernel stack directly.
1372 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1373 (unsigned long)&init_thread_union + THREAD_SIZE;
1374 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1376 #ifdef CONFIG_CC_STACKPROTECTOR
1377 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1380 #endif /* CONFIG_X86_64 */
1383 * Clear all 6 debug registers:
1385 static void clear_all_debug_regs(void)
1389 for (i = 0; i < 8; i++) {
1390 /* Ignore db4, db5 */
1391 if ((i == 4) || (i == 5))
1400 * Restore debug regs if using kgdbwait and you have a kernel debugger
1401 * connection established.
1403 static void dbg_restore_debug_regs(void)
1405 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1406 arch_kgdb_ops.correct_hw_break();
1408 #else /* ! CONFIG_KGDB */
1409 #define dbg_restore_debug_regs()
1410 #endif /* ! CONFIG_KGDB */
1412 static void wait_for_master_cpu(int cpu)
1416 * wait for ACK from master CPU before continuing
1417 * with AP initialization
1419 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1420 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1426 * cpu_init() initializes state that is per-CPU. Some data is already
1427 * initialized (naturally) in the bootstrap process, such as the GDT
1428 * and IDT. We reload them nevertheless, this function acts as a
1429 * 'CPU state barrier', nothing should get across.
1430 * A lot of state is already set up in PDA init for 64 bit
1432 #ifdef CONFIG_X86_64
1436 struct orig_ist *oist;
1437 struct task_struct *me;
1438 struct tss_struct *t;
1440 int cpu = raw_smp_processor_id();
1443 wait_for_master_cpu(cpu);
1446 * Initialize the CR4 shadow before doing anything that could
1454 t = &per_cpu(cpu_tss, cpu);
1455 oist = &per_cpu(orig_ist, cpu);
1458 if (this_cpu_read(numa_node) == 0 &&
1459 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1460 set_numa_node(early_cpu_to_node(cpu));
1465 pr_debug("Initializing CPU#%d\n", cpu);
1467 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1470 * Initialize the per-CPU GDT with the boot GDT,
1471 * and set up the GDT descriptor:
1474 switch_to_new_gdt(cpu);
1479 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1482 wrmsrl(MSR_FS_BASE, 0);
1483 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1490 * set up and load the per-CPU TSS
1492 if (!oist->ist[0]) {
1493 char *estacks = per_cpu(exception_stacks, cpu);
1495 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1496 estacks += exception_stack_sizes[v];
1497 oist->ist[v] = t->x86_tss.ist[v] =
1498 (unsigned long)estacks;
1499 if (v == DEBUG_STACK-1)
1500 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1504 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1507 * <= is required because the CPU will access up to
1508 * 8 bits beyond the end of the IO permission bitmap.
1510 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1511 t->io_bitmap[i] = ~0UL;
1513 atomic_inc(&init_mm.mm_count);
1514 me->active_mm = &init_mm;
1516 enter_lazy_tlb(&init_mm, me);
1518 load_sp0(t, ¤t->thread);
1519 set_tss_desc(cpu, t);
1521 load_mm_ldt(&init_mm);
1523 clear_all_debug_regs();
1524 dbg_restore_debug_regs();
1536 int cpu = smp_processor_id();
1537 struct task_struct *curr = current;
1538 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1539 struct thread_struct *thread = &curr->thread;
1541 wait_for_master_cpu(cpu);
1544 * Initialize the CR4 shadow before doing anything that could
1549 show_ucode_info_early();
1551 pr_info("Initializing CPU#%d\n", cpu);
1553 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1554 boot_cpu_has(X86_FEATURE_TSC) ||
1555 boot_cpu_has(X86_FEATURE_DE))
1556 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1559 switch_to_new_gdt(cpu);
1562 * Set up and load the per-CPU TSS and LDT
1564 atomic_inc(&init_mm.mm_count);
1565 curr->active_mm = &init_mm;
1567 enter_lazy_tlb(&init_mm, curr);
1569 load_sp0(t, thread);
1570 set_tss_desc(cpu, t);
1572 load_mm_ldt(&init_mm);
1574 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1576 #ifdef CONFIG_DOUBLEFAULT
1577 /* Set up doublefault TSS pointer in the GDT */
1578 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1581 clear_all_debug_regs();
1582 dbg_restore_debug_regs();
1588 static void bsp_resume(void)
1590 if (this_cpu->c_bsp_resume)
1591 this_cpu->c_bsp_resume(&boot_cpu_data);
1594 static struct syscore_ops cpu_syscore_ops = {
1595 .resume = bsp_resume,
1598 static int __init init_cpu_syscore(void)
1600 register_syscore_ops(&cpu_syscore_ops);
1603 core_initcall(init_cpu_syscore);