2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
5 * Since the original Pentium M, most new Intel CPUs support Enhanced
8 * Despite the "SpeedStep" in the name, this is almost entirely unlike
9 * traditional SpeedStep.
11 * Modelled on speedstep.c
13 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/cpufreq.h>
20 #include <linux/sched.h> /* current */
21 #include <linux/delay.h>
22 #include <linux/compiler.h>
25 #include <asm/processor.h>
26 #include <asm/cpufeature.h>
28 #define PFX "speedstep-centrino: "
29 #define MAINTAINER "cpufreq@lists.linux.org.uk"
31 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
33 #define INTEL_MSR_RANGE (0xffff)
37 __u8 x86; /* CPU family */
38 __u8 x86_model; /* model */
39 __u8 x86_mask; /* stepping */
51 static const struct cpu_id cpu_ids[] = {
52 [CPU_BANIAS] = { 6, 9, 5 },
53 [CPU_DOTHAN_A1] = { 6, 13, 1 },
54 [CPU_DOTHAN_A2] = { 6, 13, 2 },
55 [CPU_DOTHAN_B0] = { 6, 13, 6 },
56 [CPU_MP4HT_D0] = {15, 3, 4 },
57 [CPU_MP4HT_E0] = {15, 4, 1 },
59 #define N_IDS ARRAY_SIZE(cpu_ids)
63 const struct cpu_id *cpu_id;
64 const char *model_name;
65 unsigned max_freq; /* max clock in kHz */
67 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
69 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
71 /* Operating points for current CPU */
72 static struct cpu_model *centrino_model[NR_CPUS];
73 static const struct cpu_id *centrino_cpu[NR_CPUS];
75 static struct cpufreq_driver centrino_driver;
77 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
79 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
80 frequency/voltage operating point; frequency in MHz, volts in mV.
81 This is stored as "index" in the structure. */
84 .frequency = (mhz) * 1000, \
85 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
89 * These voltage tables were derived from the Intel Pentium M
90 * datasheet, document 25261202.pdf, Table 5. I have verified they
91 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
95 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
96 static struct cpufreq_frequency_table banias_900[] =
101 { .frequency = CPUFREQ_TABLE_END }
104 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
105 static struct cpufreq_frequency_table banias_1000[] =
111 { .frequency = CPUFREQ_TABLE_END }
114 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
115 static struct cpufreq_frequency_table banias_1100[] =
122 { .frequency = CPUFREQ_TABLE_END }
126 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
127 static struct cpufreq_frequency_table banias_1200[] =
135 { .frequency = CPUFREQ_TABLE_END }
138 /* Intel Pentium M processor 1.30GHz (Banias) */
139 static struct cpufreq_frequency_table banias_1300[] =
146 { .frequency = CPUFREQ_TABLE_END }
149 /* Intel Pentium M processor 1.40GHz (Banias) */
150 static struct cpufreq_frequency_table banias_1400[] =
157 { .frequency = CPUFREQ_TABLE_END }
160 /* Intel Pentium M processor 1.50GHz (Banias) */
161 static struct cpufreq_frequency_table banias_1500[] =
169 { .frequency = CPUFREQ_TABLE_END }
172 /* Intel Pentium M processor 1.60GHz (Banias) */
173 static struct cpufreq_frequency_table banias_1600[] =
181 { .frequency = CPUFREQ_TABLE_END }
184 /* Intel Pentium M processor 1.70GHz (Banias) */
185 static struct cpufreq_frequency_table banias_1700[] =
193 { .frequency = CPUFREQ_TABLE_END }
197 #define _BANIAS(cpuid, max, name) \
199 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
200 .max_freq = (max)*1000, \
201 .op_points = banias_##max, \
203 #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
205 /* CPU models, their operating frequency range, and freq/voltage
207 static struct cpu_model models[] =
209 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
219 /* NULL model_name is a wildcard */
220 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
221 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
222 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
223 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
224 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
231 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
233 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
234 struct cpu_model *model;
236 for(model = models; model->cpu_id != NULL; model++)
237 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
238 (model->model_name == NULL ||
239 strcmp(cpu->x86_model_id, model->model_name) == 0))
242 if (model->cpu_id == NULL) {
243 /* No match at all */
244 dprintk("no support for CPU model \"%s\": "
245 "send /proc/cpuinfo to " MAINTAINER "\n",
250 if (model->op_points == NULL) {
251 /* Matched a non-match */
252 dprintk("no table support for CPU model \"%s\"\n",
254 dprintk("try using the acpi-cpufreq driver\n");
258 centrino_model[policy->cpu] = model;
260 dprintk("found \"%s\": max frequency: %dkHz\n",
261 model->model_name, model->max_freq);
267 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
268 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
270 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
272 if ((c->x86 == x->x86) &&
273 (c->x86_model == x->x86_model) &&
274 (c->x86_mask == x->x86_mask))
279 /* To be called only after centrino_model is initialized */
280 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
285 * Extract clock in kHz from PERF_CTL value
286 * for centrino, as some DSDTs are buggy.
287 * Ideally, this can be done using the acpi_data structure.
289 if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
290 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
291 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
292 msr = (msr >> 8) & 0xff;
296 if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
300 for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
301 if (msr == centrino_model[cpu]->op_points[i].index)
302 return centrino_model[cpu]->op_points[i].frequency;
305 return centrino_model[cpu]->op_points[i-1].frequency;
310 /* Return the current CPU frequency in kHz */
311 static unsigned int get_cur_freq(unsigned int cpu)
315 cpumask_t saved_mask;
316 cpumask_of_cpu_ptr(new_mask, cpu);
318 saved_mask = current->cpus_allowed;
319 set_cpus_allowed_ptr(current, new_mask);
320 if (smp_processor_id() != cpu)
323 rdmsr(MSR_IA32_PERF_STATUS, l, h);
324 clock_freq = extract_clock(l, cpu, 0);
326 if (unlikely(clock_freq == 0)) {
328 * On some CPUs, we can see transient MSR values (which are
329 * not present in _PSS), while CPU is doing some automatic
330 * P-state transition (like TM2). Get the last freq set
333 rdmsr(MSR_IA32_PERF_CTL, l, h);
334 clock_freq = extract_clock(l, cpu, 1);
337 set_cpus_allowed_ptr(current, &saved_mask);
342 static int centrino_cpu_init(struct cpufreq_policy *policy)
344 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
350 /* Only Intel makes Enhanced Speedstep-capable CPUs */
351 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
354 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
355 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
357 if (policy->cpu != 0)
360 for (i = 0; i < N_IDS; i++)
361 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
365 centrino_cpu[policy->cpu] = &cpu_ids[i];
367 if (!centrino_cpu[policy->cpu]) {
368 dprintk("found unsupported CPU with "
369 "Enhanced SpeedStep: send /proc/cpuinfo to "
374 if (centrino_cpu_init_table(policy)) {
378 /* Check to see if Enhanced SpeedStep is enabled, and try to
380 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
382 if (!(l & (1<<16))) {
384 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
385 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
387 /* check to see if it stuck */
388 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
389 if (!(l & (1<<16))) {
390 printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
395 freq = get_cur_freq(policy->cpu);
397 policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
400 dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
402 ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
406 cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
411 static int centrino_cpu_exit(struct cpufreq_policy *policy)
413 unsigned int cpu = policy->cpu;
415 if (!centrino_model[cpu])
418 cpufreq_frequency_table_put_attr(cpu);
420 centrino_model[cpu] = NULL;
426 * centrino_verify - verifies a new CPUFreq policy
427 * @policy: new policy
429 * Limit must be within this model's frequency range at least one
432 static int centrino_verify (struct cpufreq_policy *policy)
434 return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
438 * centrino_setpolicy - set a new CPUFreq policy
439 * @policy: new policy
440 * @target_freq: the target frequency
441 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
443 * Sets a new CPUFreq policy.
446 cpumask_t online_policy_cpus;
447 cpumask_t saved_mask;
449 cpumask_t covered_cpus;
452 static int centrino_target (struct cpufreq_policy *policy,
453 unsigned int target_freq,
454 unsigned int relation)
456 unsigned int newstate = 0;
457 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
458 struct cpufreq_freqs freqs;
460 unsigned int j, k, first_cpu, tmp;
461 CPUMASK_ALLOC(allmasks);
462 CPUMASK_VAR(online_policy_cpus, allmasks);
463 CPUMASK_VAR(saved_mask, allmasks);
464 CPUMASK_VAR(set_mask, allmasks);
465 CPUMASK_VAR(covered_cpus, allmasks);
467 if (unlikely(allmasks == NULL))
470 if (unlikely(centrino_model[cpu] == NULL)) {
475 if (unlikely(cpufreq_frequency_table_target(policy,
476 centrino_model[cpu]->op_points,
484 #ifdef CONFIG_HOTPLUG_CPU
485 /* cpufreq holds the hotplug lock, so we are safe from here on */
486 cpus_and(*online_policy_cpus, cpu_online_map, policy->cpus);
488 *online_policy_cpus = policy->cpus;
491 *saved_mask = current->cpus_allowed;
493 cpus_clear(*covered_cpus);
494 for_each_cpu_mask_nr(j, *online_policy_cpus) {
496 * Support for SMP systems.
497 * Make sure we are running on CPU that wants to change freq
499 cpus_clear(*set_mask);
500 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
501 cpus_or(*set_mask, *set_mask, *online_policy_cpus);
503 cpu_set(j, *set_mask);
505 set_cpus_allowed_ptr(current, set_mask);
507 if (unlikely(!cpu_isset(smp_processor_id(), *set_mask))) {
508 dprintk("couldn't limit to CPUs in this domain\n");
511 /* We haven't started the transition yet. */
518 msr = centrino_model[cpu]->op_points[newstate].index;
521 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
522 if (msr == (oldmsr & 0xffff)) {
523 dprintk("no change needed - msr was and needs "
524 "to be %x\n", oldmsr);
529 freqs.old = extract_clock(oldmsr, cpu, 0);
530 freqs.new = extract_clock(msr, cpu, 0);
532 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
533 target_freq, freqs.old, freqs.new, msr);
535 for_each_cpu_mask_nr(k, *online_policy_cpus) {
537 cpufreq_notify_transition(&freqs,
542 /* all but 16 LSB are reserved, treat them with care */
548 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
549 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
554 cpu_set(j, *covered_cpus);
558 for_each_cpu_mask_nr(k, *online_policy_cpus) {
560 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
563 if (unlikely(retval)) {
565 * We have failed halfway through the frequency change.
566 * We have sent callbacks to policy->cpus and
567 * MSRs have already been written on coverd_cpus.
571 if (!cpus_empty(*covered_cpus)) {
572 cpumask_of_cpu_ptr_declare(new_mask);
574 for_each_cpu_mask_nr(j, *covered_cpus) {
575 cpumask_of_cpu_ptr_next(new_mask, j);
576 set_cpus_allowed_ptr(current, new_mask);
577 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
582 freqs.new = freqs.old;
584 for_each_cpu_mask_nr(j, *online_policy_cpus) {
586 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
587 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
590 set_cpus_allowed_ptr(current, saved_mask);
596 set_cpus_allowed_ptr(current, saved_mask);
598 CPUMASK_FREE(allmasks);
602 static struct freq_attr* centrino_attr[] = {
603 &cpufreq_freq_attr_scaling_available_freqs,
607 static struct cpufreq_driver centrino_driver = {
608 .name = "centrino", /* should be speedstep-centrino,
609 but there's a 16 char limit */
610 .init = centrino_cpu_init,
611 .exit = centrino_cpu_exit,
612 .verify = centrino_verify,
613 .target = centrino_target,
615 .attr = centrino_attr,
616 .owner = THIS_MODULE,
621 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
623 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
624 * unsupported devices, -ENOENT if there's no voltage table for this
625 * particular CPU model, -EINVAL on problems during initiatization,
626 * and zero on success.
628 * This is quite picky. Not only does the CPU have to advertise the
629 * "est" flag in the cpuid capability flags, we look for a specific
630 * CPU model and stepping, and we need to have the exact model name in
631 * our voltage tables. That is, be paranoid about not releasing
632 * someone's valuable magic smoke.
634 static int __init centrino_init(void)
636 struct cpuinfo_x86 *cpu = &cpu_data(0);
638 if (!cpu_has(cpu, X86_FEATURE_EST))
641 return cpufreq_register_driver(¢rino_driver);
644 static void __exit centrino_exit(void)
646 cpufreq_unregister_driver(¢rino_driver);
649 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
650 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
651 MODULE_LICENSE ("GPL");
653 late_initcall(centrino_init);
654 module_exit(centrino_exit);