2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 static DEFINE_MUTEX(mce_read_mutex);
51 #define rcu_dereference_check_mce(p) \
52 rcu_dereference_check((p), \
53 rcu_read_lock_sched_held() || \
54 lockdep_is_held(&mce_read_mutex))
56 #define CREATE_TRACE_POINTS
57 #include <trace/events/mce.h>
59 int mce_disabled __read_mostly;
61 #define MISC_MCELOG_MINOR 227
63 #define SPINUNIT 100 /* 100ns */
67 DEFINE_PER_CPU(unsigned, mce_exception_count);
71 * 0: always panic on uncorrected errors, log corrected errors
72 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
73 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
74 * 3: never panic or SIGBUS, log all errors (for testing only)
76 static int tolerant __read_mostly = 1;
77 static int banks __read_mostly;
78 static int rip_msr __read_mostly;
79 static int mce_bootlog __read_mostly = -1;
80 static int monarch_timeout __read_mostly = -1;
81 static int mce_panic_timeout __read_mostly;
82 static int mce_dont_log_ce __read_mostly;
83 int mce_cmci_disabled __read_mostly;
84 int mce_ignore_ce __read_mostly;
85 int mce_ser __read_mostly;
87 struct mce_bank *mce_banks __read_mostly;
89 /* User mode helper program triggered by machine check event */
90 static unsigned long mce_need_notify;
91 static char mce_helper[128];
92 static char *mce_helper_argv[2] = { mce_helper, NULL };
94 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
99 * CPU/chipset specific EDAC code can register a notifier call here to print
100 * MCE errors in a human-readable form.
102 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
103 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
105 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
108 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
109 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
114 static struct notifier_block mce_dec_nb = {
115 .notifier_call = default_decode_mce,
119 /* MCA banks polled by the period polling timer for corrected events */
120 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
121 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
124 static DEFINE_PER_CPU(struct work_struct, mce_work);
126 /* Do initial initialization of a struct mce */
127 void mce_setup(struct mce *m)
129 memset(m, 0, sizeof(struct mce));
130 m->cpu = m->extcpu = smp_processor_id();
132 /* We hope get_seconds stays lockless */
133 m->time = get_seconds();
134 m->cpuvendor = boot_cpu_data.x86_vendor;
135 m->cpuid = cpuid_eax(1);
137 m->socketid = cpu_data(m->extcpu).phys_proc_id;
139 m->apicid = cpu_data(m->extcpu).initial_apicid;
140 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
143 DEFINE_PER_CPU(struct mce, injectm);
144 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
147 * Lockless MCE logging infrastructure.
148 * This avoids deadlocks on printk locks without having to break locks. Also
149 * separate MCEs from kernel messages to avoid bogus bug reports.
152 static struct mce_log mcelog = {
153 .signature = MCE_LOG_SIGNATURE,
155 .recordlen = sizeof(struct mce),
158 void mce_log(struct mce *mce)
160 unsigned next, entry;
162 /* Emit the trace record: */
163 trace_mce_record(mce);
168 entry = rcu_dereference_check_mce(mcelog.next);
171 * When the buffer fills up discard new entries.
172 * Assume that the earlier errors are the more
175 if (entry >= MCE_LOG_LEN) {
176 set_bit(MCE_OVERFLOW,
177 (unsigned long *)&mcelog.flags);
180 /* Old left over entry. Skip: */
181 if (mcelog.entry[entry].finished) {
189 if (cmpxchg(&mcelog.next, entry, next) == entry)
192 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
194 mcelog.entry[entry].finished = 1;
198 set_bit(0, &mce_need_notify);
201 static void print_mce(struct mce *m)
203 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
204 m->extcpu, m->mcgstatus, m->bank, m->status);
207 pr_emerg("RIP%s %02x:<%016Lx> ",
208 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
211 if (m->cs == __KERNEL_CS)
212 print_symbol("{%s}", m->ip);
216 pr_emerg("TSC %llx ", m->tsc);
218 pr_cont("ADDR %llx ", m->addr);
220 pr_cont("MISC %llx ", m->misc);
223 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
224 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
227 * Print out human-readable details about the MCE error,
228 * (if the CPU has an implementation for that)
230 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
233 static void print_mce_head(void)
235 pr_emerg("\nHARDWARE ERROR\n");
238 static void print_mce_tail(void)
240 pr_emerg("This is not a software problem!\n");
243 #define PANIC_TIMEOUT 5 /* 5 seconds */
245 static atomic_t mce_paniced;
247 static int fake_panic;
248 static atomic_t mce_fake_paniced;
250 /* Panic in progress. Enable interrupts and wait for final IPI */
251 static void wait_for_panic(void)
253 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
257 while (timeout-- > 0)
259 if (panic_timeout == 0)
260 panic_timeout = mce_panic_timeout;
261 panic("Panicing machine check CPU died");
264 static void mce_panic(char *msg, struct mce *final, char *exp)
270 * Make sure only one CPU runs in machine check panic
272 if (atomic_inc_return(&mce_paniced) > 1)
279 /* Don't log too much for fake panic */
280 if (atomic_inc_return(&mce_fake_paniced) > 1)
284 /* First print corrected ones that are still unlogged */
285 for (i = 0; i < MCE_LOG_LEN; i++) {
286 struct mce *m = &mcelog.entry[i];
287 if (!(m->status & MCI_STATUS_VAL))
289 if (!(m->status & MCI_STATUS_UC))
292 /* Now print uncorrected but with the final one last */
293 for (i = 0; i < MCE_LOG_LEN; i++) {
294 struct mce *m = &mcelog.entry[i];
295 if (!(m->status & MCI_STATUS_VAL))
297 if (!(m->status & MCI_STATUS_UC))
299 if (!final || memcmp(m, final, sizeof(struct mce)))
305 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
308 printk(KERN_EMERG "Machine check: %s\n", exp);
310 if (panic_timeout == 0)
311 panic_timeout = mce_panic_timeout;
314 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
317 /* Support code for software error injection */
319 static int msr_to_offset(u32 msr)
321 unsigned bank = __get_cpu_var(injectm.bank);
324 return offsetof(struct mce, ip);
325 if (msr == MSR_IA32_MCx_STATUS(bank))
326 return offsetof(struct mce, status);
327 if (msr == MSR_IA32_MCx_ADDR(bank))
328 return offsetof(struct mce, addr);
329 if (msr == MSR_IA32_MCx_MISC(bank))
330 return offsetof(struct mce, misc);
331 if (msr == MSR_IA32_MCG_STATUS)
332 return offsetof(struct mce, mcgstatus);
336 /* MSR access wrappers used for error injection */
337 static u64 mce_rdmsrl(u32 msr)
341 if (__get_cpu_var(injectm).finished) {
342 int offset = msr_to_offset(msr);
346 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
349 if (rdmsrl_safe(msr, &v)) {
350 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
352 * Return zero in case the access faulted. This should
353 * not happen normally but can happen if the CPU does
354 * something weird, or if the code is buggy.
362 static void mce_wrmsrl(u32 msr, u64 v)
364 if (__get_cpu_var(injectm).finished) {
365 int offset = msr_to_offset(msr);
368 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
375 * Simple lockless ring to communicate PFNs from the exception handler with the
376 * process context work function. This is vastly simplified because there's
377 * only a single reader and a single writer.
379 #define MCE_RING_SIZE 16 /* we use one entry less */
382 unsigned short start;
384 unsigned long ring[MCE_RING_SIZE];
386 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
388 /* Runs with CPU affinity in workqueue */
389 static int mce_ring_empty(void)
391 struct mce_ring *r = &__get_cpu_var(mce_ring);
393 return r->start == r->end;
396 static int mce_ring_get(unsigned long *pfn)
403 r = &__get_cpu_var(mce_ring);
404 if (r->start == r->end)
406 *pfn = r->ring[r->start];
407 r->start = (r->start + 1) % MCE_RING_SIZE;
414 /* Always runs in MCE context with preempt off */
415 static int mce_ring_add(unsigned long pfn)
417 struct mce_ring *r = &__get_cpu_var(mce_ring);
420 next = (r->end + 1) % MCE_RING_SIZE;
421 if (next == r->start)
423 r->ring[r->end] = pfn;
429 int mce_available(struct cpuinfo_x86 *c)
433 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
436 static void mce_schedule_work(void)
438 if (!mce_ring_empty()) {
439 struct work_struct *work = &__get_cpu_var(mce_work);
440 if (!work_pending(work))
446 * Get the address of the instruction at the time of the machine check
449 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
452 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
460 m->ip = mce_rdmsrl(rip_msr);
463 #ifdef CONFIG_X86_LOCAL_APIC
465 * Called after interrupts have been reenabled again
466 * when a MCE happened during an interrupts off region
469 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
480 static void mce_report_event(struct pt_regs *regs)
482 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
485 * Triggering the work queue here is just an insurance
486 * policy in case the syscall exit notify handler
487 * doesn't run soon enough or ends up running on the
488 * wrong CPU (can happen when audit sleeps)
494 #ifdef CONFIG_X86_LOCAL_APIC
496 * Without APIC do not notify. The event will be picked
503 * When interrupts are disabled we cannot use
504 * kernel services safely. Trigger an self interrupt
505 * through the APIC to instead do the notification
506 * after interrupts are reenabled again.
508 apic->send_IPI_self(MCE_SELF_VECTOR);
511 * Wait for idle afterwards again so that we don't leave the
512 * APIC in a non idle state because the normal APIC writes
515 apic_wait_icr_idle();
519 DEFINE_PER_CPU(unsigned, mce_poll_count);
522 * Poll for corrected events or events that happened before reset.
523 * Those are just logged through /dev/mcelog.
525 * This is executed in standard interrupt context.
527 * Note: spec recommends to panic for fatal unsignalled
528 * errors here. However this would be quite problematic --
529 * we would need to reimplement the Monarch handling and
530 * it would mess up the exclusion between exception handler
531 * and poll hander -- * so we skip this for now.
532 * These cases should not happen anyways, or only when the CPU
533 * is already totally * confused. In this case it's likely it will
534 * not fully execute the machine check handler either.
536 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
541 __get_cpu_var(mce_poll_count)++;
545 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
546 for (i = 0; i < banks; i++) {
547 if (!mce_banks[i].ctl || !test_bit(i, *b))
556 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
557 if (!(m.status & MCI_STATUS_VAL))
561 * Uncorrected or signalled events are handled by the exception
562 * handler when it is enabled, so don't process those here.
564 * TBD do the same check for MCI_STATUS_EN here?
566 if (!(flags & MCP_UC) &&
567 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
570 if (m.status & MCI_STATUS_MISCV)
571 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
572 if (m.status & MCI_STATUS_ADDRV)
573 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
575 if (!(flags & MCP_TIMESTAMP))
578 * Don't get the IP here because it's unlikely to
579 * have anything to do with the actual error location.
581 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
583 add_taint(TAINT_MACHINE_CHECK);
587 * Clear state for this bank.
589 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
593 * Don't clear MCG_STATUS here because it's only defined for
599 EXPORT_SYMBOL_GPL(machine_check_poll);
602 * Do a quick check if any of the events requires a panic.
603 * This decides if we keep the events around or clear them.
605 static int mce_no_way_out(struct mce *m, char **msg)
609 for (i = 0; i < banks; i++) {
610 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
611 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
618 * Variable to establish order between CPUs while scanning.
619 * Each CPU spins initially until executing is equal its number.
621 static atomic_t mce_executing;
624 * Defines order of CPUs on entry. First CPU becomes Monarch.
626 static atomic_t mce_callin;
629 * Check if a timeout waiting for other CPUs happened.
631 static int mce_timed_out(u64 *t)
634 * The others already did panic for some reason.
635 * Bail out like in a timeout.
636 * rmb() to tell the compiler that system_state
637 * might have been modified by someone else.
640 if (atomic_read(&mce_paniced))
642 if (!monarch_timeout)
644 if ((s64)*t < SPINUNIT) {
645 /* CHECKME: Make panic default for 1 too? */
647 mce_panic("Timeout synchronizing machine check over CPUs",
654 touch_nmi_watchdog();
659 * The Monarch's reign. The Monarch is the CPU who entered
660 * the machine check handler first. It waits for the others to
661 * raise the exception too and then grades them. When any
662 * error is fatal panic. Only then let the others continue.
664 * The other CPUs entering the MCE handler will be controlled by the
665 * Monarch. They are called Subjects.
667 * This way we prevent any potential data corruption in a unrecoverable case
668 * and also makes sure always all CPU's errors are examined.
670 * Also this detects the case of a machine check event coming from outer
671 * space (not detected by any CPUs) In this case some external agent wants
672 * us to shut down, so panic too.
674 * The other CPUs might still decide to panic if the handler happens
675 * in a unrecoverable place, but in this case the system is in a semi-stable
676 * state and won't corrupt anything by itself. It's ok to let the others
677 * continue for a bit first.
679 * All the spin loops have timeouts; when a timeout happens a CPU
680 * typically elects itself to be Monarch.
682 static void mce_reign(void)
685 struct mce *m = NULL;
686 int global_worst = 0;
691 * This CPU is the Monarch and the other CPUs have run
692 * through their handlers.
693 * Grade the severity of the errors of all the CPUs.
695 for_each_possible_cpu(cpu) {
696 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
698 if (severity > global_worst) {
700 global_worst = severity;
701 m = &per_cpu(mces_seen, cpu);
706 * Cannot recover? Panic here then.
707 * This dumps all the mces in the log buffer and stops the
710 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
711 mce_panic("Fatal Machine check", m, msg);
714 * For UC somewhere we let the CPU who detects it handle it.
715 * Also must let continue the others, otherwise the handling
716 * CPU could deadlock on a lock.
720 * No machine check event found. Must be some external
721 * source or one CPU is hung. Panic.
723 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
724 mce_panic("Machine check from unknown source", NULL, NULL);
727 * Now clear all the mces_seen so that they don't reappear on
730 for_each_possible_cpu(cpu)
731 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
734 static atomic_t global_nwo;
737 * Start of Monarch synchronization. This waits until all CPUs have
738 * entered the exception handler and then determines if any of them
739 * saw a fatal event that requires panic. Then it executes them
740 * in the entry order.
741 * TBD double check parallel CPU hotunplug
743 static int mce_start(int *no_way_out)
746 int cpus = num_online_cpus();
747 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
752 atomic_add(*no_way_out, &global_nwo);
754 * global_nwo should be updated before mce_callin
757 order = atomic_inc_return(&mce_callin);
762 while (atomic_read(&mce_callin) != cpus) {
763 if (mce_timed_out(&timeout)) {
764 atomic_set(&global_nwo, 0);
771 * mce_callin should be read before global_nwo
777 * Monarch: Starts executing now, the others wait.
779 atomic_set(&mce_executing, 1);
782 * Subject: Now start the scanning loop one by one in
783 * the original callin order.
784 * This way when there are any shared banks it will be
785 * only seen by one CPU before cleared, avoiding duplicates.
787 while (atomic_read(&mce_executing) < order) {
788 if (mce_timed_out(&timeout)) {
789 atomic_set(&global_nwo, 0);
797 * Cache the global no_way_out state.
799 *no_way_out = atomic_read(&global_nwo);
805 * Synchronize between CPUs after main scanning loop.
806 * This invokes the bulk of the Monarch processing.
808 static int mce_end(int order)
811 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
819 * Allow others to run.
821 atomic_inc(&mce_executing);
824 /* CHECKME: Can this race with a parallel hotplug? */
825 int cpus = num_online_cpus();
828 * Monarch: Wait for everyone to go through their scanning
831 while (atomic_read(&mce_executing) <= cpus) {
832 if (mce_timed_out(&timeout))
842 * Subject: Wait for Monarch to finish.
844 while (atomic_read(&mce_executing) != 0) {
845 if (mce_timed_out(&timeout))
851 * Don't reset anything. That's done by the Monarch.
857 * Reset all global state.
860 atomic_set(&global_nwo, 0);
861 atomic_set(&mce_callin, 0);
865 * Let others run again.
867 atomic_set(&mce_executing, 0);
872 * Check if the address reported by the CPU is in a format we can parse.
873 * It would be possible to add code for most other cases, but all would
874 * be somewhat complicated (e.g. segment offset would require an instruction
875 * parser). So only support physical addresses upto page granuality for now.
877 static int mce_usable_address(struct mce *m)
879 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
881 if ((m->misc & 0x3f) > PAGE_SHIFT)
883 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
888 static void mce_clear_state(unsigned long *toclear)
892 for (i = 0; i < banks; i++) {
893 if (test_bit(i, toclear))
894 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
899 * The actual machine check handler. This only handles real
900 * exceptions when something got corrupted coming in through int 18.
902 * This is executed in NMI context not subject to normal locking rules. This
903 * implies that most kernel services cannot be safely used. Don't even
904 * think about putting a printk in there!
906 * On Intel systems this is entered on all CPUs in parallel through
907 * MCE broadcast. However some CPUs might be broken beyond repair,
908 * so be always careful when synchronizing with others.
910 void do_machine_check(struct pt_regs *regs, long error_code)
912 struct mce m, *final;
917 * Establish sequential order between the CPUs entering the machine
922 * If no_way_out gets set, there is no safe way to recover from this
923 * MCE. If tolerant is cranked up, we'll try anyway.
927 * If kill_it gets set, there might be a way to recover from this
931 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
932 char *msg = "Unknown";
934 atomic_inc(&mce_entry);
936 __get_cpu_var(mce_exception_count)++;
938 if (notify_die(DIE_NMI, "machine check", regs, error_code,
939 18, SIGKILL) == NOTIFY_STOP)
946 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
947 final = &__get_cpu_var(mces_seen);
950 no_way_out = mce_no_way_out(&m, &msg);
955 * When no restart IP must always kill or panic.
957 if (!(m.mcgstatus & MCG_STATUS_RIPV))
961 * Go through all the banks in exclusion of the other CPUs.
962 * This way we don't report duplicated events on shared banks
963 * because the first one to see it will clear it.
965 order = mce_start(&no_way_out);
966 for (i = 0; i < banks; i++) {
967 __clear_bit(i, toclear);
968 if (!mce_banks[i].ctl)
975 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
976 if ((m.status & MCI_STATUS_VAL) == 0)
980 * Non uncorrected or non signaled errors are handled by
981 * machine_check_poll. Leave them alone, unless this panics.
983 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
988 * Set taint even when machine check was not enabled.
990 add_taint(TAINT_MACHINE_CHECK);
992 severity = mce_severity(&m, tolerant, NULL);
995 * When machine check was for corrected handler don't touch,
996 * unless we're panicing.
998 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1000 __set_bit(i, toclear);
1001 if (severity == MCE_NO_SEVERITY) {
1003 * Machine check event was not enabled. Clear, but
1010 * Kill on action required.
1012 if (severity == MCE_AR_SEVERITY)
1015 if (m.status & MCI_STATUS_MISCV)
1016 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1017 if (m.status & MCI_STATUS_ADDRV)
1018 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1021 * Action optional error. Queue address for later processing.
1022 * When the ring overflows we just ignore the AO error.
1023 * RED-PEN add some logging mechanism when
1024 * usable_address or mce_add_ring fails.
1025 * RED-PEN don't ignore overflow for tolerant == 0
1027 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1028 mce_ring_add(m.addr >> PAGE_SHIFT);
1030 mce_get_rip(&m, regs);
1033 if (severity > worst) {
1040 mce_clear_state(toclear);
1043 * Do most of the synchronization with other CPUs.
1044 * When there's any problem use only local no_way_out state.
1046 if (mce_end(order) < 0)
1047 no_way_out = worst >= MCE_PANIC_SEVERITY;
1050 * If we have decided that we just CAN'T continue, and the user
1051 * has not set tolerant to an insane level, give up and die.
1053 * This is mainly used in the case when the system doesn't
1054 * support MCE broadcasting or it has been disabled.
1056 if (no_way_out && tolerant < 3)
1057 mce_panic("Fatal machine check on current CPU", final, msg);
1060 * If the error seems to be unrecoverable, something should be
1061 * done. Try to kill as little as possible. If we can kill just
1062 * one task, do that. If the user has set the tolerance very
1063 * high, don't try to do anything at all.
1066 if (kill_it && tolerant < 3)
1067 force_sig(SIGBUS, current);
1069 /* notify userspace ASAP */
1070 set_thread_flag(TIF_MCE_NOTIFY);
1073 mce_report_event(regs);
1074 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1076 atomic_dec(&mce_entry);
1079 EXPORT_SYMBOL_GPL(do_machine_check);
1081 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1082 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1084 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1088 * Called after mce notification in process context. This code
1089 * is allowed to sleep. Call the high level VM handler to process
1090 * any corrupted pages.
1091 * Assume that the work queue code only calls this one at a time
1093 * Note we don't disable preemption, so this code might run on the wrong
1094 * CPU. In this case the event is picked up by the scheduled work queue.
1095 * This is merely a fast path to expedite processing in some common
1098 void mce_notify_process(void)
1102 while (mce_ring_get(&pfn))
1103 memory_failure(pfn, MCE_VECTOR);
1106 static void mce_process_work(struct work_struct *dummy)
1108 mce_notify_process();
1111 #ifdef CONFIG_X86_MCE_INTEL
1113 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1114 * @cpu: The CPU on which the event occurred.
1115 * @status: Event status information
1117 * This function should be called by the thermal interrupt after the
1118 * event has been processed and the decision was made to log the event
1121 * The status parameter will be saved to the 'status' field of 'struct mce'
1122 * and historically has been the register value of the
1123 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1125 void mce_log_therm_throt_event(__u64 status)
1130 m.bank = MCE_THERMAL_BANK;
1134 #endif /* CONFIG_X86_MCE_INTEL */
1137 * Periodic polling timer for "silent" machine check errors. If the
1138 * poller finds an MCE, poll 2x faster. When the poller finds no more
1139 * errors, poll 2x slower (up to check_interval seconds).
1141 static int check_interval = 5 * 60; /* 5 minutes */
1143 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1144 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1146 static void mce_start_timer(unsigned long data)
1148 struct timer_list *t = &per_cpu(mce_timer, data);
1151 WARN_ON(smp_processor_id() != data);
1153 if (mce_available(¤t_cpu_data)) {
1154 machine_check_poll(MCP_TIMESTAMP,
1155 &__get_cpu_var(mce_poll_banks));
1159 * Alert userspace if needed. If we logged an MCE, reduce the
1160 * polling interval, otherwise increase the polling interval.
1162 n = &__get_cpu_var(mce_next_interval);
1163 if (mce_notify_irq())
1164 *n = max(*n/2, HZ/100);
1166 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1168 t->expires = jiffies + *n;
1169 add_timer_on(t, smp_processor_id());
1172 static void mce_do_trigger(struct work_struct *work)
1174 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1177 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1180 * Notify the user(s) about new machine check events.
1181 * Can be called from interrupt context, but not from machine check/NMI
1184 int mce_notify_irq(void)
1186 /* Not more than two messages every minute */
1187 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1189 clear_thread_flag(TIF_MCE_NOTIFY);
1191 if (test_and_clear_bit(0, &mce_need_notify)) {
1192 wake_up_interruptible(&mce_wait);
1195 * There is no risk of missing notifications because
1196 * work_pending is always cleared before the function is
1199 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1200 schedule_work(&mce_trigger_work);
1202 if (__ratelimit(&ratelimit))
1203 printk(KERN_INFO "Machine check events logged\n");
1209 EXPORT_SYMBOL_GPL(mce_notify_irq);
1211 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1215 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1218 for (i = 0; i < banks; i++) {
1219 struct mce_bank *b = &mce_banks[i];
1228 * Initialize Machine Checks for a CPU.
1230 static int __cpuinit __mcheck_cpu_cap_init(void)
1235 rdmsrl(MSR_IA32_MCG_CAP, cap);
1237 b = cap & MCG_BANKCNT_MASK;
1239 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1241 if (b > MAX_NR_BANKS) {
1243 "MCE: Using only %u machine check banks out of %u\n",
1248 /* Don't support asymmetric configurations today */
1249 WARN_ON(banks != 0 && b != banks);
1252 int err = __mcheck_cpu_mce_banks_init();
1258 /* Use accurate RIP reporting if available. */
1259 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1260 rip_msr = MSR_IA32_MCG_EIP;
1262 if (cap & MCG_SER_P)
1268 static void __mcheck_cpu_init_generic(void)
1270 mce_banks_t all_banks;
1275 * Log the machine checks left over from the previous reset.
1277 bitmap_fill(all_banks, MAX_NR_BANKS);
1278 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1280 set_in_cr4(X86_CR4_MCE);
1282 rdmsrl(MSR_IA32_MCG_CAP, cap);
1283 if (cap & MCG_CTL_P)
1284 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1286 for (i = 0; i < banks; i++) {
1287 struct mce_bank *b = &mce_banks[i];
1291 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1292 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1296 /* Add per CPU specific workarounds here */
1297 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1299 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1300 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1304 /* This should be disabled by the BIOS, but isn't always */
1305 if (c->x86_vendor == X86_VENDOR_AMD) {
1306 if (c->x86 == 15 && banks > 4) {
1308 * disable GART TBL walk error reporting, which
1309 * trips off incorrectly with the IOMMU & 3ware
1312 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1314 if (c->x86 <= 17 && mce_bootlog < 0) {
1316 * Lots of broken BIOS around that don't clear them
1317 * by default and leave crap in there. Don't log:
1322 * Various K7s with broken bank 0 around. Always disable
1325 if (c->x86 == 6 && banks > 0)
1326 mce_banks[0].ctl = 0;
1329 if (c->x86_vendor == X86_VENDOR_INTEL) {
1331 * SDM documents that on family 6 bank 0 should not be written
1332 * because it aliases to another special BIOS controlled
1334 * But it's not aliased anymore on model 0x1a+
1335 * Don't ignore bank 0 completely because there could be a
1336 * valid event later, merely don't write CTL0.
1339 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1340 mce_banks[0].init = 0;
1343 * All newer Intel systems support MCE broadcasting. Enable
1344 * synchronization with a one second timeout.
1346 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1347 monarch_timeout < 0)
1348 monarch_timeout = USEC_PER_SEC;
1351 * There are also broken BIOSes on some Pentium M and
1354 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1357 if (monarch_timeout < 0)
1358 monarch_timeout = 0;
1359 if (mce_bootlog != 0)
1360 mce_panic_timeout = 30;
1365 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1369 switch (c->x86_vendor) {
1370 case X86_VENDOR_INTEL:
1371 intel_p5_mcheck_init(c);
1373 case X86_VENDOR_CENTAUR:
1374 winchip_mcheck_init(c);
1379 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1381 switch (c->x86_vendor) {
1382 case X86_VENDOR_INTEL:
1383 mce_intel_feature_init(c);
1385 case X86_VENDOR_AMD:
1386 mce_amd_feature_init(c);
1393 static void __mcheck_cpu_init_timer(void)
1395 struct timer_list *t = &__get_cpu_var(mce_timer);
1396 int *n = &__get_cpu_var(mce_next_interval);
1398 setup_timer(t, mce_start_timer, smp_processor_id());
1403 *n = check_interval * HZ;
1406 t->expires = round_jiffies(jiffies + *n);
1407 add_timer_on(t, smp_processor_id());
1410 /* Handle unconfigured int18 (should never happen) */
1411 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1413 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1414 smp_processor_id());
1417 /* Call the installed machine check handler for this CPU setup. */
1418 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1419 unexpected_machine_check;
1422 * Called for each booted CPU to set up machine checks.
1423 * Must be called with preempt off:
1425 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1430 __mcheck_cpu_ancient_init(c);
1432 if (!mce_available(c))
1435 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1440 machine_check_vector = do_machine_check;
1442 __mcheck_cpu_init_generic();
1443 __mcheck_cpu_init_vendor(c);
1444 __mcheck_cpu_init_timer();
1445 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1450 * Character device to read and clear the MCE log.
1453 static DEFINE_SPINLOCK(mce_state_lock);
1454 static int open_count; /* #times opened */
1455 static int open_exclu; /* already open exclusive? */
1457 static int mce_open(struct inode *inode, struct file *file)
1459 spin_lock(&mce_state_lock);
1461 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1462 spin_unlock(&mce_state_lock);
1467 if (file->f_flags & O_EXCL)
1471 spin_unlock(&mce_state_lock);
1473 return nonseekable_open(inode, file);
1476 static int mce_release(struct inode *inode, struct file *file)
1478 spin_lock(&mce_state_lock);
1483 spin_unlock(&mce_state_lock);
1488 static void collect_tscs(void *data)
1490 unsigned long *cpu_tsc = (unsigned long *)data;
1492 rdtscll(cpu_tsc[smp_processor_id()]);
1495 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1498 char __user *buf = ubuf;
1499 unsigned long *cpu_tsc;
1500 unsigned prev, next;
1503 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1507 mutex_lock(&mce_read_mutex);
1508 next = rcu_dereference_check_mce(mcelog.next);
1510 /* Only supports full reads right now */
1511 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1512 mutex_unlock(&mce_read_mutex);
1521 for (i = prev; i < next; i++) {
1522 unsigned long start = jiffies;
1524 while (!mcelog.entry[i].finished) {
1525 if (time_after_eq(jiffies, start + 2)) {
1526 memset(mcelog.entry + i, 0,
1527 sizeof(struct mce));
1533 err |= copy_to_user(buf, mcelog.entry + i,
1534 sizeof(struct mce));
1535 buf += sizeof(struct mce);
1540 memset(mcelog.entry + prev, 0,
1541 (next - prev) * sizeof(struct mce));
1543 next = cmpxchg(&mcelog.next, prev, 0);
1544 } while (next != prev);
1546 synchronize_sched();
1549 * Collect entries that were still getting written before the
1552 on_each_cpu(collect_tscs, cpu_tsc, 1);
1554 for (i = next; i < MCE_LOG_LEN; i++) {
1555 if (mcelog.entry[i].finished &&
1556 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1557 err |= copy_to_user(buf, mcelog.entry+i,
1558 sizeof(struct mce));
1560 buf += sizeof(struct mce);
1561 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1564 mutex_unlock(&mce_read_mutex);
1567 return err ? -EFAULT : buf - ubuf;
1570 static unsigned int mce_poll(struct file *file, poll_table *wait)
1572 poll_wait(file, &mce_wait, wait);
1573 if (rcu_dereference_check_mce(mcelog.next))
1574 return POLLIN | POLLRDNORM;
1578 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1580 int __user *p = (int __user *)arg;
1582 if (!capable(CAP_SYS_ADMIN))
1586 case MCE_GET_RECORD_LEN:
1587 return put_user(sizeof(struct mce), p);
1588 case MCE_GET_LOG_LEN:
1589 return put_user(MCE_LOG_LEN, p);
1590 case MCE_GETCLEAR_FLAGS: {
1594 flags = mcelog.flags;
1595 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1597 return put_user(flags, p);
1604 /* Modified in mce-inject.c, so not static or const */
1605 struct file_operations mce_chrdev_ops = {
1607 .release = mce_release,
1610 .unlocked_ioctl = mce_ioctl,
1612 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1614 static struct miscdevice mce_log_device = {
1621 * mce=off Disables machine check
1622 * mce=no_cmci Disables CMCI
1623 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1624 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1625 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1626 * monarchtimeout is how long to wait for other CPUs on machine
1627 * check, or 0 to not wait
1628 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1629 * mce=nobootlog Don't log MCEs from before booting.
1631 static int __init mcheck_enable(char *str)
1639 if (!strcmp(str, "off"))
1641 else if (!strcmp(str, "no_cmci"))
1642 mce_cmci_disabled = 1;
1643 else if (!strcmp(str, "dont_log_ce"))
1644 mce_dont_log_ce = 1;
1645 else if (!strcmp(str, "ignore_ce"))
1647 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1648 mce_bootlog = (str[0] == 'b');
1649 else if (isdigit(str[0])) {
1650 get_option(&str, &tolerant);
1653 get_option(&str, &monarch_timeout);
1656 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1662 __setup("mce", mcheck_enable);
1664 int __init mcheck_init(void)
1666 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1668 mcheck_intel_therm_init();
1678 * Disable machine checks on suspend and shutdown. We can't really handle
1681 static int mce_disable_error_reporting(void)
1685 for (i = 0; i < banks; i++) {
1686 struct mce_bank *b = &mce_banks[i];
1689 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1694 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1696 return mce_disable_error_reporting();
1699 static int mce_shutdown(struct sys_device *dev)
1701 return mce_disable_error_reporting();
1705 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1706 * Only one CPU is active at this time, the others get re-added later using
1709 static int mce_resume(struct sys_device *dev)
1711 __mcheck_cpu_init_generic();
1712 __mcheck_cpu_init_vendor(¤t_cpu_data);
1717 static void mce_cpu_restart(void *data)
1719 del_timer_sync(&__get_cpu_var(mce_timer));
1720 if (!mce_available(¤t_cpu_data))
1722 __mcheck_cpu_init_generic();
1723 __mcheck_cpu_init_timer();
1726 /* Reinit MCEs after user configuration changes */
1727 static void mce_restart(void)
1729 on_each_cpu(mce_cpu_restart, NULL, 1);
1732 /* Toggle features for corrected errors */
1733 static void mce_disable_ce(void *all)
1735 if (!mce_available(¤t_cpu_data))
1738 del_timer_sync(&__get_cpu_var(mce_timer));
1742 static void mce_enable_ce(void *all)
1744 if (!mce_available(¤t_cpu_data))
1749 __mcheck_cpu_init_timer();
1752 static struct sysdev_class mce_sysclass = {
1753 .suspend = mce_suspend,
1754 .shutdown = mce_shutdown,
1755 .resume = mce_resume,
1756 .name = "machinecheck",
1759 DEFINE_PER_CPU(struct sys_device, mce_dev);
1762 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1764 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1766 return container_of(attr, struct mce_bank, attr);
1769 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1772 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1775 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1776 const char *buf, size_t size)
1780 if (strict_strtoull(buf, 0, &new) < 0)
1783 attr_to_bank(attr)->ctl = new;
1790 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1792 strcpy(buf, mce_helper);
1794 return strlen(mce_helper) + 1;
1797 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1798 const char *buf, size_t siz)
1802 strncpy(mce_helper, buf, sizeof(mce_helper));
1803 mce_helper[sizeof(mce_helper)-1] = 0;
1804 p = strchr(mce_helper, '\n');
1809 return strlen(mce_helper) + !!p;
1812 static ssize_t set_ignore_ce(struct sys_device *s,
1813 struct sysdev_attribute *attr,
1814 const char *buf, size_t size)
1818 if (strict_strtoull(buf, 0, &new) < 0)
1821 if (mce_ignore_ce ^ !!new) {
1823 /* disable ce features */
1824 on_each_cpu(mce_disable_ce, (void *)1, 1);
1827 /* enable ce features */
1829 on_each_cpu(mce_enable_ce, (void *)1, 1);
1835 static ssize_t set_cmci_disabled(struct sys_device *s,
1836 struct sysdev_attribute *attr,
1837 const char *buf, size_t size)
1841 if (strict_strtoull(buf, 0, &new) < 0)
1844 if (mce_cmci_disabled ^ !!new) {
1847 on_each_cpu(mce_disable_ce, NULL, 1);
1848 mce_cmci_disabled = 1;
1851 mce_cmci_disabled = 0;
1852 on_each_cpu(mce_enable_ce, NULL, 1);
1858 static ssize_t store_int_with_restart(struct sys_device *s,
1859 struct sysdev_attribute *attr,
1860 const char *buf, size_t size)
1862 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1867 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1868 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1869 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1870 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1872 static struct sysdev_ext_attribute attr_check_interval = {
1873 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1874 store_int_with_restart),
1878 static struct sysdev_ext_attribute attr_ignore_ce = {
1879 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1883 static struct sysdev_ext_attribute attr_cmci_disabled = {
1884 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1888 static struct sysdev_attribute *mce_attrs[] = {
1889 &attr_tolerant.attr,
1890 &attr_check_interval.attr,
1892 &attr_monarch_timeout.attr,
1893 &attr_dont_log_ce.attr,
1894 &attr_ignore_ce.attr,
1895 &attr_cmci_disabled.attr,
1899 static cpumask_var_t mce_dev_initialized;
1901 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1902 static __cpuinit int mce_create_device(unsigned int cpu)
1907 if (!mce_available(&boot_cpu_data))
1910 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1911 per_cpu(mce_dev, cpu).id = cpu;
1912 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1914 err = sysdev_register(&per_cpu(mce_dev, cpu));
1918 for (i = 0; mce_attrs[i]; i++) {
1919 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1923 for (j = 0; j < banks; j++) {
1924 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1925 &mce_banks[j].attr);
1929 cpumask_set_cpu(cpu, mce_dev_initialized);
1934 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1937 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1939 sysdev_unregister(&per_cpu(mce_dev, cpu));
1944 static __cpuinit void mce_remove_device(unsigned int cpu)
1948 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1951 for (i = 0; mce_attrs[i]; i++)
1952 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1954 for (i = 0; i < banks; i++)
1955 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1957 sysdev_unregister(&per_cpu(mce_dev, cpu));
1958 cpumask_clear_cpu(cpu, mce_dev_initialized);
1961 /* Make sure there are no machine checks on offlined CPUs. */
1962 static void __cpuinit mce_disable_cpu(void *h)
1964 unsigned long action = *(unsigned long *)h;
1967 if (!mce_available(¤t_cpu_data))
1970 if (!(action & CPU_TASKS_FROZEN))
1972 for (i = 0; i < banks; i++) {
1973 struct mce_bank *b = &mce_banks[i];
1976 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1980 static void __cpuinit mce_reenable_cpu(void *h)
1982 unsigned long action = *(unsigned long *)h;
1985 if (!mce_available(¤t_cpu_data))
1988 if (!(action & CPU_TASKS_FROZEN))
1990 for (i = 0; i < banks; i++) {
1991 struct mce_bank *b = &mce_banks[i];
1994 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1998 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1999 static int __cpuinit
2000 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2002 unsigned int cpu = (unsigned long)hcpu;
2003 struct timer_list *t = &per_cpu(mce_timer, cpu);
2007 case CPU_ONLINE_FROZEN:
2008 mce_create_device(cpu);
2009 if (threshold_cpu_callback)
2010 threshold_cpu_callback(action, cpu);
2013 case CPU_DEAD_FROZEN:
2014 if (threshold_cpu_callback)
2015 threshold_cpu_callback(action, cpu);
2016 mce_remove_device(cpu);
2018 case CPU_DOWN_PREPARE:
2019 case CPU_DOWN_PREPARE_FROZEN:
2021 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2023 case CPU_DOWN_FAILED:
2024 case CPU_DOWN_FAILED_FROZEN:
2025 if (!mce_ignore_ce && check_interval) {
2026 t->expires = round_jiffies(jiffies +
2027 __get_cpu_var(mce_next_interval));
2028 add_timer_on(t, cpu);
2030 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2033 /* intentionally ignoring frozen here */
2034 cmci_rediscover(cpu);
2040 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2041 .notifier_call = mce_cpu_callback,
2044 static __init void mce_init_banks(void)
2048 for (i = 0; i < banks; i++) {
2049 struct mce_bank *b = &mce_banks[i];
2050 struct sysdev_attribute *a = &b->attr;
2052 sysfs_attr_init(&a->attr);
2053 a->attr.name = b->attrname;
2054 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2056 a->attr.mode = 0644;
2057 a->show = show_bank;
2058 a->store = set_bank;
2062 static __init int mcheck_init_device(void)
2067 if (!mce_available(&boot_cpu_data))
2070 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2074 err = sysdev_class_register(&mce_sysclass);
2078 for_each_online_cpu(i) {
2079 err = mce_create_device(i);
2084 register_hotcpu_notifier(&mce_cpu_notifier);
2085 misc_register(&mce_log_device);
2090 device_initcall(mcheck_init_device);
2093 * Old style boot options parsing. Only for compatibility.
2095 static int __init mcheck_disable(char *str)
2100 __setup("nomce", mcheck_disable);
2102 #ifdef CONFIG_DEBUG_FS
2103 struct dentry *mce_get_debugfs_dir(void)
2105 static struct dentry *dmce;
2108 dmce = debugfs_create_dir("mce", NULL);
2113 static void mce_reset(void)
2116 atomic_set(&mce_fake_paniced, 0);
2117 atomic_set(&mce_executing, 0);
2118 atomic_set(&mce_callin, 0);
2119 atomic_set(&global_nwo, 0);
2122 static int fake_panic_get(void *data, u64 *val)
2128 static int fake_panic_set(void *data, u64 val)
2135 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2136 fake_panic_set, "%llu\n");
2138 static int __init mcheck_debugfs_init(void)
2140 struct dentry *dmce, *ffake_panic;
2142 dmce = mce_get_debugfs_dir();
2145 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2152 late_initcall(mcheck_debugfs_init);