2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
44 #include <linux/jump_label.h>
46 #include <asm/intel-family.h>
47 #include <asm/processor.h>
48 #include <asm/traps.h>
49 #include <asm/tlbflush.h>
53 #include "mce-internal.h"
55 static DEFINE_MUTEX(mce_chrdev_read_mutex);
57 static int mce_chrdev_open_count; /* #times opened */
59 #define mce_log_get_idx_check(p) \
61 RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \
62 !lockdep_is_held(&mce_chrdev_read_mutex), \
63 "suspicious mce_log_get_idx_check() usage"); \
64 smp_load_acquire(&(p)); \
67 #define CREATE_TRACE_POINTS
68 #include <trace/events/mce.h>
70 #define SPINUNIT 100 /* 100ns */
72 DEFINE_PER_CPU(unsigned, mce_exception_count);
74 struct mce_bank *mce_banks __read_mostly;
75 struct mce_vendor_flags mce_flags __read_mostly;
77 struct mca_config mca_cfg __read_mostly = {
81 * 0: always panic on uncorrected errors, log corrected errors
82 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
83 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
84 * 3: never panic or SIGBUS, log all errors (for testing only)
90 /* User mode helper program triggered by machine check event */
91 static unsigned long mce_need_notify;
92 static char mce_helper[128];
93 static char *mce_helper_argv[2] = { mce_helper, NULL };
95 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
97 static DEFINE_PER_CPU(struct mce, mces_seen);
98 static int cpu_missing;
101 * MCA banks polled by the period polling timer for corrected events.
102 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
104 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
105 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
109 * MCA banks controlled through firmware first for corrected errors.
110 * This is a global list of banks for which we won't enable CMCI and we
111 * won't poll. Firmware controls these banks and is responsible for
112 * reporting corrected errors through GHES. Uncorrected/recoverable
113 * errors are still notified through a machine check.
115 mce_banks_t mce_banks_ce_disabled;
117 static struct work_struct mce_work;
118 static struct irq_work mce_irq_work;
120 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
123 * CPU/chipset specific EDAC code can register a notifier call here to print
124 * MCE errors in a human-readable form.
126 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
128 /* Do initial initialization of a struct mce */
129 void mce_setup(struct mce *m)
131 memset(m, 0, sizeof(struct mce));
132 m->cpu = m->extcpu = smp_processor_id();
133 /* We hope get_seconds stays lockless */
134 m->time = get_seconds();
135 m->cpuvendor = boot_cpu_data.x86_vendor;
136 m->cpuid = cpuid_eax(1);
137 m->socketid = cpu_data(m->extcpu).phys_proc_id;
138 m->apicid = cpu_data(m->extcpu).initial_apicid;
139 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
141 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
142 rdmsrl(MSR_PPIN, m->ppin);
145 DEFINE_PER_CPU(struct mce, injectm);
146 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
149 * Lockless MCE logging infrastructure.
150 * This avoids deadlocks on printk locks without having to break locks. Also
151 * separate MCEs from kernel messages to avoid bogus bug reports.
154 static struct mce_log mcelog = {
155 .signature = MCE_LOG_SIGNATURE,
157 .recordlen = sizeof(struct mce),
160 void mce_log(struct mce *mce)
162 unsigned next, entry;
164 /* Emit the trace record: */
165 trace_mce_record(mce);
167 if (!mce_gen_pool_add(mce))
168 irq_work_queue(&mce_irq_work);
172 entry = mce_log_get_idx_check(mcelog.next);
176 * When the buffer fills up discard new entries.
177 * Assume that the earlier errors are the more
180 if (entry >= MCE_LOG_LEN) {
181 set_bit(MCE_OVERFLOW,
182 (unsigned long *)&mcelog.flags);
185 /* Old left over entry. Skip: */
186 if (mcelog.entry[entry].finished) {
194 if (cmpxchg(&mcelog.next, entry, next) == entry)
197 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
199 mcelog.entry[entry].finished = 1;
202 set_bit(0, &mce_need_notify);
205 void mce_inject_log(struct mce *m)
207 mutex_lock(&mce_chrdev_read_mutex);
209 mutex_unlock(&mce_chrdev_read_mutex);
211 EXPORT_SYMBOL_GPL(mce_inject_log);
213 static struct notifier_block mce_srao_nb;
215 static atomic_t num_notifiers;
217 void mce_register_decode_chain(struct notifier_block *nb)
219 atomic_inc(&num_notifiers);
221 WARN_ON(nb->priority > MCE_PRIO_LOWEST && nb->priority < MCE_PRIO_EDAC);
223 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
225 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
227 void mce_unregister_decode_chain(struct notifier_block *nb)
229 atomic_dec(&num_notifiers);
231 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
233 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
235 static inline u32 ctl_reg(int bank)
237 return MSR_IA32_MCx_CTL(bank);
240 static inline u32 status_reg(int bank)
242 return MSR_IA32_MCx_STATUS(bank);
245 static inline u32 addr_reg(int bank)
247 return MSR_IA32_MCx_ADDR(bank);
250 static inline u32 misc_reg(int bank)
252 return MSR_IA32_MCx_MISC(bank);
255 static inline u32 smca_ctl_reg(int bank)
257 return MSR_AMD64_SMCA_MCx_CTL(bank);
260 static inline u32 smca_status_reg(int bank)
262 return MSR_AMD64_SMCA_MCx_STATUS(bank);
265 static inline u32 smca_addr_reg(int bank)
267 return MSR_AMD64_SMCA_MCx_ADDR(bank);
270 static inline u32 smca_misc_reg(int bank)
272 return MSR_AMD64_SMCA_MCx_MISC(bank);
275 struct mca_msr_regs msr_ops = {
277 .status = status_reg,
282 static void __print_mce(struct mce *m)
284 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
286 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
287 m->mcgstatus, m->bank, m->status);
290 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
291 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
294 if (m->cs == __KERNEL_CS)
295 print_symbol("{%s}", m->ip);
299 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
301 pr_cont("ADDR %llx ", m->addr);
303 pr_cont("MISC %llx ", m->misc);
305 if (mce_flags.smca) {
307 pr_cont("SYND %llx ", m->synd);
309 pr_cont("IPID %llx ", m->ipid);
314 * Note this output is parsed by external tools and old fields
315 * should not be changed.
317 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
318 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
319 cpu_data(m->extcpu).microcode);
322 static void print_mce(struct mce *m)
329 * Print out human-readable details about the MCE error,
330 * (if the CPU has an implementation for that)
332 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
333 if (ret == NOTIFY_STOP)
336 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
339 #define PANIC_TIMEOUT 5 /* 5 seconds */
341 static atomic_t mce_panicked;
343 static int fake_panic;
344 static atomic_t mce_fake_panicked;
346 /* Panic in progress. Enable interrupts and wait for final IPI */
347 static void wait_for_panic(void)
349 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
353 while (timeout-- > 0)
355 if (panic_timeout == 0)
356 panic_timeout = mca_cfg.panic_timeout;
357 panic("Panicing machine check CPU died");
360 static void mce_panic(const char *msg, struct mce *final, char *exp)
363 struct llist_node *pending;
364 struct mce_evt_llist *l;
368 * Make sure only one CPU runs in machine check panic
370 if (atomic_inc_return(&mce_panicked) > 1)
377 /* Don't log too much for fake panic */
378 if (atomic_inc_return(&mce_fake_panicked) > 1)
381 pending = mce_gen_pool_prepare_records();
382 /* First print corrected ones that are still unlogged */
383 llist_for_each_entry(l, pending, llnode) {
384 struct mce *m = &l->mce;
385 if (!(m->status & MCI_STATUS_UC)) {
388 apei_err = apei_write_mce(m);
391 /* Now print uncorrected but with the final one last */
392 llist_for_each_entry(l, pending, llnode) {
393 struct mce *m = &l->mce;
394 if (!(m->status & MCI_STATUS_UC))
396 if (!final || mce_cmp(m, final)) {
399 apei_err = apei_write_mce(m);
405 apei_err = apei_write_mce(final);
408 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
410 pr_emerg(HW_ERR "Machine check: %s\n", exp);
412 if (panic_timeout == 0)
413 panic_timeout = mca_cfg.panic_timeout;
416 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
419 /* Support code for software error injection */
421 static int msr_to_offset(u32 msr)
423 unsigned bank = __this_cpu_read(injectm.bank);
425 if (msr == mca_cfg.rip_msr)
426 return offsetof(struct mce, ip);
427 if (msr == msr_ops.status(bank))
428 return offsetof(struct mce, status);
429 if (msr == msr_ops.addr(bank))
430 return offsetof(struct mce, addr);
431 if (msr == msr_ops.misc(bank))
432 return offsetof(struct mce, misc);
433 if (msr == MSR_IA32_MCG_STATUS)
434 return offsetof(struct mce, mcgstatus);
438 /* MSR access wrappers used for error injection */
439 static u64 mce_rdmsrl(u32 msr)
443 if (__this_cpu_read(injectm.finished)) {
444 int offset = msr_to_offset(msr);
448 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
451 if (rdmsrl_safe(msr, &v)) {
452 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
454 * Return zero in case the access faulted. This should
455 * not happen normally but can happen if the CPU does
456 * something weird, or if the code is buggy.
464 static void mce_wrmsrl(u32 msr, u64 v)
466 if (__this_cpu_read(injectm.finished)) {
467 int offset = msr_to_offset(msr);
470 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
477 * Collect all global (w.r.t. this processor) status about this machine
478 * check into our "mce" struct so that we can use it later to assess
479 * the severity of the problem as we read per-bank specific details.
481 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
485 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
488 * Get the address of the instruction at the time of
489 * the machine check error.
491 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
496 * When in VM86 mode make the cs look like ring 3
497 * always. This is a lie, but it's better than passing
498 * the additional vm86 bit around everywhere.
500 if (v8086_mode(regs))
503 /* Use accurate RIP reporting if available. */
505 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
509 int mce_available(struct cpuinfo_x86 *c)
511 if (mca_cfg.disabled)
513 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
516 static void mce_schedule_work(void)
518 if (!mce_gen_pool_empty())
519 schedule_work(&mce_work);
522 static void mce_irq_work_cb(struct irq_work *entry)
528 static void mce_report_event(struct pt_regs *regs)
530 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
533 * Triggering the work queue here is just an insurance
534 * policy in case the syscall exit notify handler
535 * doesn't run soon enough or ends up running on the
536 * wrong CPU (can happen when audit sleeps)
542 irq_work_queue(&mce_irq_work);
546 * Check if the address reported by the CPU is in a format we can parse.
547 * It would be possible to add code for most other cases, but all would
548 * be somewhat complicated (e.g. segment offset would require an instruction
549 * parser). So only support physical addresses up to page granuality for now.
551 static int mce_usable_address(struct mce *m)
553 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
556 /* Checks after this one are Intel-specific: */
557 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
560 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
562 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
567 static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
570 struct mce *mce = (struct mce *)data;
576 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
577 pfn = mce->addr >> PAGE_SHIFT;
578 memory_failure(pfn, MCE_VECTOR, 0);
583 static struct notifier_block mce_srao_nb = {
584 .notifier_call = srao_decode_notifier,
585 .priority = MCE_PRIO_SRAO,
588 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
591 struct mce *m = (struct mce *)data;
597 * Run the default notifier if we have only the SRAO
598 * notifier and us registered.
600 if (atomic_read(&num_notifiers) > 2)
603 /* Don't print when mcelog is running */
604 if (mce_chrdev_open_count > 0)
612 static struct notifier_block mce_default_nb = {
613 .notifier_call = mce_default_notifier,
614 /* lowest prio, we want it to run last. */
615 .priority = MCE_PRIO_LOWEST,
619 * Read ADDR and MISC registers.
621 static void mce_read_aux(struct mce *m, int i)
623 if (m->status & MCI_STATUS_MISCV)
624 m->misc = mce_rdmsrl(msr_ops.misc(i));
626 if (m->status & MCI_STATUS_ADDRV) {
627 m->addr = mce_rdmsrl(msr_ops.addr(i));
630 * Mask the reported address by the reported granularity.
632 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
633 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
639 * Extract [55:<lsb>] where lsb is the least significant
640 * *valid* bit of the address bits.
642 if (mce_flags.smca) {
643 u8 lsb = (m->addr >> 56) & 0x3f;
645 m->addr &= GENMASK_ULL(55, lsb);
649 if (mce_flags.smca) {
650 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
652 if (m->status & MCI_STATUS_SYNDV)
653 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
657 static bool memory_error(struct mce *m)
659 struct cpuinfo_x86 *c = &boot_cpu_data;
661 if (c->x86_vendor == X86_VENDOR_AMD) {
662 /* ErrCodeExt[20:16] */
663 u8 xec = (m->status >> 16) & 0x1f;
665 return (xec == 0x0 || xec == 0x8);
666 } else if (c->x86_vendor == X86_VENDOR_INTEL) {
668 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
670 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
671 * indicating a memory error. Bit 8 is used for indicating a
672 * cache hierarchy error. The combination of bit 2 and bit 3
673 * is used for indicating a `generic' cache hierarchy error
674 * But we can't just blindly check the above bits, because if
675 * bit 11 is set, then it is a bus/interconnect error - and
676 * either way the above bits just gives more detail on what
677 * bus/interconnect error happened. Note that bit 12 can be
678 * ignored, as it's the "filter" bit.
680 return (m->status & 0xef80) == BIT(7) ||
681 (m->status & 0xef00) == BIT(8) ||
682 (m->status & 0xeffc) == 0xc;
688 DEFINE_PER_CPU(unsigned, mce_poll_count);
691 * Poll for corrected events or events that happened before reset.
692 * Those are just logged through /dev/mcelog.
694 * This is executed in standard interrupt context.
696 * Note: spec recommends to panic for fatal unsignalled
697 * errors here. However this would be quite problematic --
698 * we would need to reimplement the Monarch handling and
699 * it would mess up the exclusion between exception handler
700 * and poll hander -- * so we skip this for now.
701 * These cases should not happen anyways, or only when the CPU
702 * is already totally * confused. In this case it's likely it will
703 * not fully execute the machine check handler either.
705 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
707 bool error_seen = false;
712 this_cpu_inc(mce_poll_count);
714 mce_gather_info(&m, NULL);
716 if (flags & MCP_TIMESTAMP)
719 for (i = 0; i < mca_cfg.banks; i++) {
720 if (!mce_banks[i].ctl || !test_bit(i, *b))
728 m.status = mce_rdmsrl(msr_ops.status(i));
729 if (!(m.status & MCI_STATUS_VAL))
733 * Uncorrected or signalled events are handled by the exception
734 * handler when it is enabled, so don't process those here.
736 * TBD do the same check for MCI_STATUS_EN here?
738 if (!(flags & MCP_UC) &&
739 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
746 severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
748 if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m))
749 if (m.status & MCI_STATUS_ADDRV)
750 m.severity = severity;
753 * Don't get the IP here because it's unlikely to
754 * have anything to do with the actual error location.
756 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
758 else if (mce_usable_address(&m)) {
760 * Although we skipped logging this, we still want
761 * to take action. Add to the pool so the registered
762 * notifiers will see it.
764 if (!mce_gen_pool_add(&m))
769 * Clear state for this bank.
771 mce_wrmsrl(msr_ops.status(i), 0);
775 * Don't clear MCG_STATUS here because it's only defined for
783 EXPORT_SYMBOL_GPL(machine_check_poll);
786 * Do a quick check if any of the events requires a panic.
787 * This decides if we keep the events around or clear them.
789 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
790 struct pt_regs *regs)
795 for (i = 0; i < mca_cfg.banks; i++) {
796 m->status = mce_rdmsrl(msr_ops.status(i));
797 if (m->status & MCI_STATUS_VAL) {
798 __set_bit(i, validp);
799 if (quirk_no_way_out)
800 quirk_no_way_out(i, m, regs);
803 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
812 * Variable to establish order between CPUs while scanning.
813 * Each CPU spins initially until executing is equal its number.
815 static atomic_t mce_executing;
818 * Defines order of CPUs on entry. First CPU becomes Monarch.
820 static atomic_t mce_callin;
823 * Check if a timeout waiting for other CPUs happened.
825 static int mce_timed_out(u64 *t, const char *msg)
828 * The others already did panic for some reason.
829 * Bail out like in a timeout.
830 * rmb() to tell the compiler that system_state
831 * might have been modified by someone else.
834 if (atomic_read(&mce_panicked))
836 if (!mca_cfg.monarch_timeout)
838 if ((s64)*t < SPINUNIT) {
839 if (mca_cfg.tolerant <= 1)
840 mce_panic(msg, NULL, NULL);
846 touch_nmi_watchdog();
851 * The Monarch's reign. The Monarch is the CPU who entered
852 * the machine check handler first. It waits for the others to
853 * raise the exception too and then grades them. When any
854 * error is fatal panic. Only then let the others continue.
856 * The other CPUs entering the MCE handler will be controlled by the
857 * Monarch. They are called Subjects.
859 * This way we prevent any potential data corruption in a unrecoverable case
860 * and also makes sure always all CPU's errors are examined.
862 * Also this detects the case of a machine check event coming from outer
863 * space (not detected by any CPUs) In this case some external agent wants
864 * us to shut down, so panic too.
866 * The other CPUs might still decide to panic if the handler happens
867 * in a unrecoverable place, but in this case the system is in a semi-stable
868 * state and won't corrupt anything by itself. It's ok to let the others
869 * continue for a bit first.
871 * All the spin loops have timeouts; when a timeout happens a CPU
872 * typically elects itself to be Monarch.
874 static void mce_reign(void)
877 struct mce *m = NULL;
878 int global_worst = 0;
883 * This CPU is the Monarch and the other CPUs have run
884 * through their handlers.
885 * Grade the severity of the errors of all the CPUs.
887 for_each_possible_cpu(cpu) {
888 int severity = mce_severity(&per_cpu(mces_seen, cpu),
891 if (severity > global_worst) {
893 global_worst = severity;
894 m = &per_cpu(mces_seen, cpu);
899 * Cannot recover? Panic here then.
900 * This dumps all the mces in the log buffer and stops the
903 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
904 mce_panic("Fatal machine check", m, msg);
907 * For UC somewhere we let the CPU who detects it handle it.
908 * Also must let continue the others, otherwise the handling
909 * CPU could deadlock on a lock.
913 * No machine check event found. Must be some external
914 * source or one CPU is hung. Panic.
916 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
917 mce_panic("Fatal machine check from unknown source", NULL, NULL);
920 * Now clear all the mces_seen so that they don't reappear on
923 for_each_possible_cpu(cpu)
924 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
927 static atomic_t global_nwo;
930 * Start of Monarch synchronization. This waits until all CPUs have
931 * entered the exception handler and then determines if any of them
932 * saw a fatal event that requires panic. Then it executes them
933 * in the entry order.
934 * TBD double check parallel CPU hotunplug
936 static int mce_start(int *no_way_out)
939 int cpus = num_online_cpus();
940 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
945 atomic_add(*no_way_out, &global_nwo);
947 * Rely on the implied barrier below, such that global_nwo
948 * is updated before mce_callin.
950 order = atomic_inc_return(&mce_callin);
955 while (atomic_read(&mce_callin) != cpus) {
956 if (mce_timed_out(&timeout,
957 "Timeout: Not all CPUs entered broadcast exception handler")) {
958 atomic_set(&global_nwo, 0);
965 * mce_callin should be read before global_nwo
971 * Monarch: Starts executing now, the others wait.
973 atomic_set(&mce_executing, 1);
976 * Subject: Now start the scanning loop one by one in
977 * the original callin order.
978 * This way when there are any shared banks it will be
979 * only seen by one CPU before cleared, avoiding duplicates.
981 while (atomic_read(&mce_executing) < order) {
982 if (mce_timed_out(&timeout,
983 "Timeout: Subject CPUs unable to finish machine check processing")) {
984 atomic_set(&global_nwo, 0);
992 * Cache the global no_way_out state.
994 *no_way_out = atomic_read(&global_nwo);
1000 * Synchronize between CPUs after main scanning loop.
1001 * This invokes the bulk of the Monarch processing.
1003 static int mce_end(int order)
1006 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1014 * Allow others to run.
1016 atomic_inc(&mce_executing);
1019 /* CHECKME: Can this race with a parallel hotplug? */
1020 int cpus = num_online_cpus();
1023 * Monarch: Wait for everyone to go through their scanning
1026 while (atomic_read(&mce_executing) <= cpus) {
1027 if (mce_timed_out(&timeout,
1028 "Timeout: Monarch CPU unable to finish machine check processing"))
1038 * Subject: Wait for Monarch to finish.
1040 while (atomic_read(&mce_executing) != 0) {
1041 if (mce_timed_out(&timeout,
1042 "Timeout: Monarch CPU did not finish machine check processing"))
1048 * Don't reset anything. That's done by the Monarch.
1054 * Reset all global state.
1057 atomic_set(&global_nwo, 0);
1058 atomic_set(&mce_callin, 0);
1062 * Let others run again.
1064 atomic_set(&mce_executing, 0);
1068 static void mce_clear_state(unsigned long *toclear)
1072 for (i = 0; i < mca_cfg.banks; i++) {
1073 if (test_bit(i, toclear))
1074 mce_wrmsrl(msr_ops.status(i), 0);
1078 static int do_memory_failure(struct mce *m)
1080 int flags = MF_ACTION_REQUIRED;
1083 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1084 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1085 flags |= MF_MUST_KILL;
1086 ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags);
1088 pr_err("Memory error not recovered");
1093 * The actual machine check handler. This only handles real
1094 * exceptions when something got corrupted coming in through int 18.
1096 * This is executed in NMI context not subject to normal locking rules. This
1097 * implies that most kernel services cannot be safely used. Don't even
1098 * think about putting a printk in there!
1100 * On Intel systems this is entered on all CPUs in parallel through
1101 * MCE broadcast. However some CPUs might be broken beyond repair,
1102 * so be always careful when synchronizing with others.
1104 void do_machine_check(struct pt_regs *regs, long error_code)
1106 struct mca_config *cfg = &mca_cfg;
1107 struct mce m, *final;
1113 * Establish sequential order between the CPUs entering the machine
1118 * If no_way_out gets set, there is no safe way to recover from this
1119 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1123 * If kill_it gets set, there might be a way to recover from this
1127 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1128 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1129 char *msg = "Unknown";
1132 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1137 /* If this CPU is offline, just bail out. */
1138 if (cpu_is_offline(smp_processor_id())) {
1141 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1142 if (mcgstatus & MCG_STATUS_RIPV) {
1143 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1150 this_cpu_inc(mce_exception_count);
1155 mce_gather_info(&m, regs);
1158 final = this_cpu_ptr(&mces_seen);
1161 memset(valid_banks, 0, sizeof(valid_banks));
1162 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1167 * When no restart IP might need to kill or panic.
1168 * Assume the worst for now, but if we find the
1169 * severity is MCE_AR_SEVERITY we have other options.
1171 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1175 * Check if this MCE is signaled to only this logical processor,
1178 if (m.cpuvendor == X86_VENDOR_INTEL)
1179 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1182 * Go through all banks in exclusion of the other CPUs. This way we
1183 * don't report duplicated events on shared banks because the first one
1184 * to see it will clear it. If this is a Local MCE, then no need to
1185 * perform rendezvous.
1188 order = mce_start(&no_way_out);
1190 for (i = 0; i < cfg->banks; i++) {
1191 __clear_bit(i, toclear);
1192 if (!test_bit(i, valid_banks))
1194 if (!mce_banks[i].ctl)
1201 m.status = mce_rdmsrl(msr_ops.status(i));
1202 if ((m.status & MCI_STATUS_VAL) == 0)
1206 * Non uncorrected or non signaled errors are handled by
1207 * machine_check_poll. Leave them alone, unless this panics.
1209 if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1214 * Set taint even when machine check was not enabled.
1216 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1218 severity = mce_severity(&m, cfg->tolerant, NULL, true);
1221 * When machine check was for corrected/deferred handler don't
1222 * touch, unless we're panicing.
1224 if ((severity == MCE_KEEP_SEVERITY ||
1225 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1227 __set_bit(i, toclear);
1228 if (severity == MCE_NO_SEVERITY) {
1230 * Machine check event was not enabled. Clear, but
1236 mce_read_aux(&m, i);
1238 /* assuming valid severity level != 0 */
1239 m.severity = severity;
1243 if (severity > worst) {
1249 /* mce_clear_state will clear *final, save locally for use later */
1253 mce_clear_state(toclear);
1256 * Do most of the synchronization with other CPUs.
1257 * When there's any problem use only local no_way_out state.
1260 if (mce_end(order) < 0)
1261 no_way_out = worst >= MCE_PANIC_SEVERITY;
1264 * Local MCE skipped calling mce_reign()
1265 * If we found a fatal error, we need to panic here.
1267 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
1268 mce_panic("Machine check from unknown source",
1273 * If tolerant is at an insane level we drop requests to kill
1274 * processes and continue even when there is no way out.
1276 if (cfg->tolerant == 3)
1278 else if (no_way_out)
1279 mce_panic("Fatal machine check on current CPU", &m, msg);
1282 mce_report_event(regs);
1283 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1287 if (worst != MCE_AR_SEVERITY && !kill_it)
1290 /* Fault was in user mode and we need to take some action */
1291 if ((m.cs & 3) == 3) {
1292 ist_begin_non_atomic(regs);
1295 if (kill_it || do_memory_failure(&m))
1296 force_sig(SIGBUS, current);
1297 local_irq_disable();
1298 ist_end_non_atomic();
1300 if (!fixup_exception(regs, X86_TRAP_MC))
1301 mce_panic("Failed kernel mode recovery", &m, NULL);
1307 EXPORT_SYMBOL_GPL(do_machine_check);
1309 #ifndef CONFIG_MEMORY_FAILURE
1310 int memory_failure(unsigned long pfn, int vector, int flags)
1312 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1313 BUG_ON(flags & MF_ACTION_REQUIRED);
1314 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1315 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1323 * Periodic polling timer for "silent" machine check errors. If the
1324 * poller finds an MCE, poll 2x faster. When the poller finds no more
1325 * errors, poll 2x slower (up to check_interval seconds).
1327 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1329 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1330 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1332 static unsigned long mce_adjust_timer_default(unsigned long interval)
1337 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1339 static void __start_timer(struct timer_list *t, unsigned long interval)
1341 unsigned long when = jiffies + interval;
1342 unsigned long flags;
1344 local_irq_save(flags);
1346 if (!timer_pending(t) || time_before(when, t->expires))
1347 mod_timer(t, round_jiffies(when));
1349 local_irq_restore(flags);
1352 static void mce_timer_fn(unsigned long data)
1354 struct timer_list *t = this_cpu_ptr(&mce_timer);
1355 int cpu = smp_processor_id();
1358 WARN_ON(cpu != data);
1360 iv = __this_cpu_read(mce_next_interval);
1362 if (mce_available(this_cpu_ptr(&cpu_info))) {
1363 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1365 if (mce_intel_cmci_poll()) {
1366 iv = mce_adjust_timer(iv);
1372 * Alert userspace if needed. If we logged an MCE, reduce the polling
1373 * interval, otherwise increase the polling interval.
1375 if (mce_notify_irq())
1376 iv = max(iv / 2, (unsigned long) HZ/100);
1378 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1381 __this_cpu_write(mce_next_interval, iv);
1382 __start_timer(t, iv);
1386 * Ensure that the timer is firing in @interval from now.
1388 void mce_timer_kick(unsigned long interval)
1390 struct timer_list *t = this_cpu_ptr(&mce_timer);
1391 unsigned long iv = __this_cpu_read(mce_next_interval);
1393 __start_timer(t, interval);
1396 __this_cpu_write(mce_next_interval, interval);
1399 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1400 static void mce_timer_delete_all(void)
1404 for_each_online_cpu(cpu)
1405 del_timer_sync(&per_cpu(mce_timer, cpu));
1408 static void mce_do_trigger(struct work_struct *work)
1410 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1413 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1416 * Notify the user(s) about new machine check events.
1417 * Can be called from interrupt context, but not from machine check/NMI
1420 int mce_notify_irq(void)
1422 /* Not more than two messages every minute */
1423 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1425 if (test_and_clear_bit(0, &mce_need_notify)) {
1426 /* wake processes polling /dev/mcelog */
1427 wake_up_interruptible(&mce_chrdev_wait);
1430 schedule_work(&mce_trigger_work);
1432 if (__ratelimit(&ratelimit))
1433 pr_info(HW_ERR "Machine check events logged\n");
1439 EXPORT_SYMBOL_GPL(mce_notify_irq);
1441 static int __mcheck_cpu_mce_banks_init(void)
1444 u8 num_banks = mca_cfg.banks;
1446 mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL);
1450 for (i = 0; i < num_banks; i++) {
1451 struct mce_bank *b = &mce_banks[i];
1460 * Initialize Machine Checks for a CPU.
1462 static int __mcheck_cpu_cap_init(void)
1467 rdmsrl(MSR_IA32_MCG_CAP, cap);
1469 b = cap & MCG_BANKCNT_MASK;
1471 pr_info("CPU supports %d MCE banks\n", b);
1473 if (b > MAX_NR_BANKS) {
1474 pr_warn("Using only %u machine check banks out of %u\n",
1479 /* Don't support asymmetric configurations today */
1480 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1484 int err = __mcheck_cpu_mce_banks_init();
1490 /* Use accurate RIP reporting if available. */
1491 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1492 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1494 if (cap & MCG_SER_P)
1500 static void __mcheck_cpu_init_generic(void)
1502 enum mcp_flags m_fl = 0;
1503 mce_banks_t all_banks;
1506 if (!mca_cfg.bootlog)
1510 * Log the machine checks left over from the previous reset.
1512 bitmap_fill(all_banks, MAX_NR_BANKS);
1513 machine_check_poll(MCP_UC | m_fl, &all_banks);
1515 cr4_set_bits(X86_CR4_MCE);
1517 rdmsrl(MSR_IA32_MCG_CAP, cap);
1518 if (cap & MCG_CTL_P)
1519 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1522 static void __mcheck_cpu_init_clear_banks(void)
1526 for (i = 0; i < mca_cfg.banks; i++) {
1527 struct mce_bank *b = &mce_banks[i];
1531 wrmsrl(msr_ops.ctl(i), b->ctl);
1532 wrmsrl(msr_ops.status(i), 0);
1537 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1538 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1539 * Vol 3B Table 15-20). But this confuses both the code that determines
1540 * whether the machine check occurred in kernel or user mode, and also
1541 * the severity assessment code. Pretend that EIPV was set, and take the
1542 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1544 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1548 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1550 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1551 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1552 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1554 (MCI_STATUS_UC|MCI_STATUS_EN|
1555 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1556 MCI_STATUS_AR|MCACOD_INSTR))
1559 m->mcgstatus |= MCG_STATUS_EIPV;
1564 /* Add per CPU specific workarounds here */
1565 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1567 struct mca_config *cfg = &mca_cfg;
1569 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1570 pr_info("unknown CPU type - not enabling MCE support\n");
1574 /* This should be disabled by the BIOS, but isn't always */
1575 if (c->x86_vendor == X86_VENDOR_AMD) {
1576 if (c->x86 == 15 && cfg->banks > 4) {
1578 * disable GART TBL walk error reporting, which
1579 * trips off incorrectly with the IOMMU & 3ware
1582 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1584 if (c->x86 < 17 && cfg->bootlog < 0) {
1586 * Lots of broken BIOS around that don't clear them
1587 * by default and leave crap in there. Don't log:
1592 * Various K7s with broken bank 0 around. Always disable
1595 if (c->x86 == 6 && cfg->banks > 0)
1596 mce_banks[0].ctl = 0;
1599 * overflow_recov is supported for F15h Models 00h-0fh
1600 * even though we don't have a CPUID bit for it.
1602 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1603 mce_flags.overflow_recov = 1;
1606 * Turn off MC4_MISC thresholding banks on those models since
1607 * they're not supported there.
1609 if (c->x86 == 0x15 &&
1610 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1615 0x00000413, /* MC4_MISC0 */
1616 0xc0000408, /* MC4_MISC1 */
1619 rdmsrl(MSR_K7_HWCR, hwcr);
1621 /* McStatusWrEn has to be set */
1622 need_toggle = !(hwcr & BIT(18));
1625 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1627 /* Clear CntP bit safely */
1628 for (i = 0; i < ARRAY_SIZE(msrs); i++)
1629 msr_clear_bit(msrs[i], 62);
1631 /* restore old settings */
1633 wrmsrl(MSR_K7_HWCR, hwcr);
1637 if (c->x86_vendor == X86_VENDOR_INTEL) {
1639 * SDM documents that on family 6 bank 0 should not be written
1640 * because it aliases to another special BIOS controlled
1642 * But it's not aliased anymore on model 0x1a+
1643 * Don't ignore bank 0 completely because there could be a
1644 * valid event later, merely don't write CTL0.
1647 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1648 mce_banks[0].init = 0;
1651 * All newer Intel systems support MCE broadcasting. Enable
1652 * synchronization with a one second timeout.
1654 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1655 cfg->monarch_timeout < 0)
1656 cfg->monarch_timeout = USEC_PER_SEC;
1659 * There are also broken BIOSes on some Pentium M and
1662 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1665 if (c->x86 == 6 && c->x86_model == 45)
1666 quirk_no_way_out = quirk_sandybridge_ifu;
1668 if (cfg->monarch_timeout < 0)
1669 cfg->monarch_timeout = 0;
1670 if (cfg->bootlog != 0)
1671 cfg->panic_timeout = 30;
1676 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1681 switch (c->x86_vendor) {
1682 case X86_VENDOR_INTEL:
1683 intel_p5_mcheck_init(c);
1686 case X86_VENDOR_CENTAUR:
1687 winchip_mcheck_init(c);
1697 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1699 switch (c->x86_vendor) {
1700 case X86_VENDOR_INTEL:
1701 mce_intel_feature_init(c);
1702 mce_adjust_timer = cmci_intel_adjust_timer;
1705 case X86_VENDOR_AMD: {
1706 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1707 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1708 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1711 * Install proper ops for Scalable MCA enabled processors
1713 if (mce_flags.smca) {
1714 msr_ops.ctl = smca_ctl_reg;
1715 msr_ops.status = smca_status_reg;
1716 msr_ops.addr = smca_addr_reg;
1717 msr_ops.misc = smca_misc_reg;
1719 mce_amd_feature_init(c);
1729 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1731 switch (c->x86_vendor) {
1732 case X86_VENDOR_INTEL:
1733 mce_intel_feature_clear(c);
1740 static void mce_start_timer(struct timer_list *t)
1742 unsigned long iv = check_interval * HZ;
1744 if (mca_cfg.ignore_ce || !iv)
1747 this_cpu_write(mce_next_interval, iv);
1748 __start_timer(t, iv);
1751 static void __mcheck_cpu_setup_timer(void)
1753 struct timer_list *t = this_cpu_ptr(&mce_timer);
1754 unsigned int cpu = smp_processor_id();
1756 setup_pinned_timer(t, mce_timer_fn, cpu);
1759 static void __mcheck_cpu_init_timer(void)
1761 struct timer_list *t = this_cpu_ptr(&mce_timer);
1762 unsigned int cpu = smp_processor_id();
1764 setup_pinned_timer(t, mce_timer_fn, cpu);
1768 /* Handle unconfigured int18 (should never happen) */
1769 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1771 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1772 smp_processor_id());
1775 /* Call the installed machine check handler for this CPU setup. */
1776 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1777 unexpected_machine_check;
1780 * Called for each booted CPU to set up machine checks.
1781 * Must be called with preempt off:
1783 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1785 if (mca_cfg.disabled)
1788 if (__mcheck_cpu_ancient_init(c))
1791 if (!mce_available(c))
1794 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1795 mca_cfg.disabled = true;
1799 if (mce_gen_pool_init()) {
1800 mca_cfg.disabled = true;
1801 pr_emerg("Couldn't allocate MCE records pool!\n");
1805 machine_check_vector = do_machine_check;
1807 __mcheck_cpu_init_generic();
1808 __mcheck_cpu_init_vendor(c);
1809 __mcheck_cpu_init_clear_banks();
1810 __mcheck_cpu_setup_timer();
1814 * Called for each booted CPU to clear some machine checks opt-ins
1816 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1818 if (mca_cfg.disabled)
1821 if (!mce_available(c))
1825 * Possibly to clear general settings generic to x86
1826 * __mcheck_cpu_clear_generic(c);
1828 __mcheck_cpu_clear_vendor(c);
1833 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1836 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1837 static int mce_chrdev_open_exclu; /* already open exclusive? */
1839 static int mce_chrdev_open(struct inode *inode, struct file *file)
1841 spin_lock(&mce_chrdev_state_lock);
1843 if (mce_chrdev_open_exclu ||
1844 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1845 spin_unlock(&mce_chrdev_state_lock);
1850 if (file->f_flags & O_EXCL)
1851 mce_chrdev_open_exclu = 1;
1852 mce_chrdev_open_count++;
1854 spin_unlock(&mce_chrdev_state_lock);
1856 return nonseekable_open(inode, file);
1859 static int mce_chrdev_release(struct inode *inode, struct file *file)
1861 spin_lock(&mce_chrdev_state_lock);
1863 mce_chrdev_open_count--;
1864 mce_chrdev_open_exclu = 0;
1866 spin_unlock(&mce_chrdev_state_lock);
1871 static void collect_tscs(void *data)
1873 unsigned long *cpu_tsc = (unsigned long *)data;
1875 cpu_tsc[smp_processor_id()] = rdtsc();
1878 static int mce_apei_read_done;
1880 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1881 static int __mce_read_apei(char __user **ubuf, size_t usize)
1887 if (usize < sizeof(struct mce))
1890 rc = apei_read_mce(&m, &record_id);
1891 /* Error or no more MCE record */
1893 mce_apei_read_done = 1;
1895 * When ERST is disabled, mce_chrdev_read() should return
1896 * "no record" instead of "no device."
1903 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1906 * In fact, we should have cleared the record after that has
1907 * been flushed to the disk or sent to network in
1908 * /sbin/mcelog, but we have no interface to support that now,
1909 * so just clear it to avoid duplication.
1911 rc = apei_clear_mce(record_id);
1913 mce_apei_read_done = 1;
1916 *ubuf += sizeof(struct mce);
1921 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1922 size_t usize, loff_t *off)
1924 char __user *buf = ubuf;
1925 unsigned long *cpu_tsc;
1926 unsigned prev, next;
1929 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1933 mutex_lock(&mce_chrdev_read_mutex);
1935 if (!mce_apei_read_done) {
1936 err = __mce_read_apei(&buf, usize);
1937 if (err || buf != ubuf)
1941 next = mce_log_get_idx_check(mcelog.next);
1943 /* Only supports full reads right now */
1945 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1951 for (i = prev; i < next; i++) {
1952 unsigned long start = jiffies;
1953 struct mce *m = &mcelog.entry[i];
1955 while (!m->finished) {
1956 if (time_after_eq(jiffies, start + 2)) {
1957 memset(m, 0, sizeof(*m));
1963 err |= copy_to_user(buf, m, sizeof(*m));
1969 memset(mcelog.entry + prev, 0,
1970 (next - prev) * sizeof(struct mce));
1972 next = cmpxchg(&mcelog.next, prev, 0);
1973 } while (next != prev);
1975 synchronize_sched();
1978 * Collect entries that were still getting written before the
1981 on_each_cpu(collect_tscs, cpu_tsc, 1);
1983 for (i = next; i < MCE_LOG_LEN; i++) {
1984 struct mce *m = &mcelog.entry[i];
1986 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1987 err |= copy_to_user(buf, m, sizeof(*m));
1990 memset(m, 0, sizeof(*m));
1998 mutex_unlock(&mce_chrdev_read_mutex);
2001 return err ? err : buf - ubuf;
2004 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
2006 poll_wait(file, &mce_chrdev_wait, wait);
2007 if (READ_ONCE(mcelog.next))
2008 return POLLIN | POLLRDNORM;
2009 if (!mce_apei_read_done && apei_check_mce())
2010 return POLLIN | POLLRDNORM;
2014 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
2017 int __user *p = (int __user *)arg;
2019 if (!capable(CAP_SYS_ADMIN))
2023 case MCE_GET_RECORD_LEN:
2024 return put_user(sizeof(struct mce), p);
2025 case MCE_GET_LOG_LEN:
2026 return put_user(MCE_LOG_LEN, p);
2027 case MCE_GETCLEAR_FLAGS: {
2031 flags = mcelog.flags;
2032 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
2034 return put_user(flags, p);
2041 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
2042 size_t usize, loff_t *off);
2044 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
2045 const char __user *ubuf,
2046 size_t usize, loff_t *off))
2050 EXPORT_SYMBOL_GPL(register_mce_write_callback);
2052 static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
2053 size_t usize, loff_t *off)
2056 return mce_write(filp, ubuf, usize, off);
2061 static const struct file_operations mce_chrdev_ops = {
2062 .open = mce_chrdev_open,
2063 .release = mce_chrdev_release,
2064 .read = mce_chrdev_read,
2065 .write = mce_chrdev_write,
2066 .poll = mce_chrdev_poll,
2067 .unlocked_ioctl = mce_chrdev_ioctl,
2068 .llseek = no_llseek,
2071 static struct miscdevice mce_chrdev_device = {
2077 static void __mce_disable_bank(void *arg)
2079 int bank = *((int *)arg);
2080 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2081 cmci_disable_bank(bank);
2084 void mce_disable_bank(int bank)
2086 if (bank >= mca_cfg.banks) {
2088 "Ignoring request to disable invalid MCA bank %d.\n",
2092 set_bit(bank, mce_banks_ce_disabled);
2093 on_each_cpu(__mce_disable_bank, &bank, 1);
2097 * mce=off Disables machine check
2098 * mce=no_cmci Disables CMCI
2099 * mce=no_lmce Disables LMCE
2100 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2101 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2102 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2103 * monarchtimeout is how long to wait for other CPUs on machine
2104 * check, or 0 to not wait
2105 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
2106 * mce=nobootlog Don't log MCEs from before booting.
2107 * mce=bios_cmci_threshold Don't program the CMCI threshold
2108 * mce=recovery force enable memcpy_mcsafe()
2110 static int __init mcheck_enable(char *str)
2112 struct mca_config *cfg = &mca_cfg;
2120 if (!strcmp(str, "off"))
2121 cfg->disabled = true;
2122 else if (!strcmp(str, "no_cmci"))
2123 cfg->cmci_disabled = true;
2124 else if (!strcmp(str, "no_lmce"))
2125 cfg->lmce_disabled = true;
2126 else if (!strcmp(str, "dont_log_ce"))
2127 cfg->dont_log_ce = true;
2128 else if (!strcmp(str, "ignore_ce"))
2129 cfg->ignore_ce = true;
2130 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2131 cfg->bootlog = (str[0] == 'b');
2132 else if (!strcmp(str, "bios_cmci_threshold"))
2133 cfg->bios_cmci_threshold = true;
2134 else if (!strcmp(str, "recovery"))
2135 cfg->recovery = true;
2136 else if (isdigit(str[0])) {
2137 if (get_option(&str, &cfg->tolerant) == 2)
2138 get_option(&str, &(cfg->monarch_timeout));
2140 pr_info("mce argument %s ignored. Please use /sys\n", str);
2145 __setup("mce", mcheck_enable);
2147 int __init mcheck_init(void)
2149 mcheck_intel_therm_init();
2150 mce_register_decode_chain(&mce_srao_nb);
2151 mce_register_decode_chain(&mce_default_nb);
2152 mcheck_vendor_init_severity();
2154 INIT_WORK(&mce_work, mce_gen_pool_process);
2155 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2161 * mce_syscore: PM support
2165 * Disable machine checks on suspend and shutdown. We can't really handle
2168 static void mce_disable_error_reporting(void)
2172 for (i = 0; i < mca_cfg.banks; i++) {
2173 struct mce_bank *b = &mce_banks[i];
2176 wrmsrl(msr_ops.ctl(i), 0);
2181 static void vendor_disable_error_reporting(void)
2184 * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
2185 * Disabling them for just a single offlined CPU is bad, since it will
2186 * inhibit reporting for all shared resources on the socket like the
2187 * last level cache (LLC), the integrated memory controller (iMC), etc.
2189 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2192 mce_disable_error_reporting();
2195 static int mce_syscore_suspend(void)
2197 vendor_disable_error_reporting();
2201 static void mce_syscore_shutdown(void)
2203 vendor_disable_error_reporting();
2207 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2208 * Only one CPU is active at this time, the others get re-added later using
2211 static void mce_syscore_resume(void)
2213 __mcheck_cpu_init_generic();
2214 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2215 __mcheck_cpu_init_clear_banks();
2218 static struct syscore_ops mce_syscore_ops = {
2219 .suspend = mce_syscore_suspend,
2220 .shutdown = mce_syscore_shutdown,
2221 .resume = mce_syscore_resume,
2225 * mce_device: Sysfs support
2228 static void mce_cpu_restart(void *data)
2230 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2232 __mcheck_cpu_init_generic();
2233 __mcheck_cpu_init_clear_banks();
2234 __mcheck_cpu_init_timer();
2237 /* Reinit MCEs after user configuration changes */
2238 static void mce_restart(void)
2240 mce_timer_delete_all();
2241 on_each_cpu(mce_cpu_restart, NULL, 1);
2244 /* Toggle features for corrected errors */
2245 static void mce_disable_cmci(void *data)
2247 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2252 static void mce_enable_ce(void *all)
2254 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2259 __mcheck_cpu_init_timer();
2262 static struct bus_type mce_subsys = {
2263 .name = "machinecheck",
2264 .dev_name = "machinecheck",
2267 DEFINE_PER_CPU(struct device *, mce_device);
2269 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2271 return container_of(attr, struct mce_bank, attr);
2274 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2277 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2280 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2281 const char *buf, size_t size)
2285 if (kstrtou64(buf, 0, &new) < 0)
2288 attr_to_bank(attr)->ctl = new;
2295 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
2297 strcpy(buf, mce_helper);
2299 return strlen(mce_helper) + 1;
2302 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
2303 const char *buf, size_t siz)
2307 strncpy(mce_helper, buf, sizeof(mce_helper));
2308 mce_helper[sizeof(mce_helper)-1] = 0;
2309 p = strchr(mce_helper, '\n');
2314 return strlen(mce_helper) + !!p;
2317 static ssize_t set_ignore_ce(struct device *s,
2318 struct device_attribute *attr,
2319 const char *buf, size_t size)
2323 if (kstrtou64(buf, 0, &new) < 0)
2326 if (mca_cfg.ignore_ce ^ !!new) {
2328 /* disable ce features */
2329 mce_timer_delete_all();
2330 on_each_cpu(mce_disable_cmci, NULL, 1);
2331 mca_cfg.ignore_ce = true;
2333 /* enable ce features */
2334 mca_cfg.ignore_ce = false;
2335 on_each_cpu(mce_enable_ce, (void *)1, 1);
2341 static ssize_t set_cmci_disabled(struct device *s,
2342 struct device_attribute *attr,
2343 const char *buf, size_t size)
2347 if (kstrtou64(buf, 0, &new) < 0)
2350 if (mca_cfg.cmci_disabled ^ !!new) {
2353 on_each_cpu(mce_disable_cmci, NULL, 1);
2354 mca_cfg.cmci_disabled = true;
2357 mca_cfg.cmci_disabled = false;
2358 on_each_cpu(mce_enable_ce, NULL, 1);
2364 static ssize_t store_int_with_restart(struct device *s,
2365 struct device_attribute *attr,
2366 const char *buf, size_t size)
2368 ssize_t ret = device_store_int(s, attr, buf, size);
2373 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2374 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2375 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2376 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2378 static struct dev_ext_attribute dev_attr_check_interval = {
2379 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2383 static struct dev_ext_attribute dev_attr_ignore_ce = {
2384 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2388 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2389 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2390 &mca_cfg.cmci_disabled
2393 static struct device_attribute *mce_device_attrs[] = {
2394 &dev_attr_tolerant.attr,
2395 &dev_attr_check_interval.attr,
2397 &dev_attr_monarch_timeout.attr,
2398 &dev_attr_dont_log_ce.attr,
2399 &dev_attr_ignore_ce.attr,
2400 &dev_attr_cmci_disabled.attr,
2404 static cpumask_var_t mce_device_initialized;
2406 static void mce_device_release(struct device *dev)
2411 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2412 static int mce_device_create(unsigned int cpu)
2418 if (!mce_available(&boot_cpu_data))
2421 dev = per_cpu(mce_device, cpu);
2425 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2429 dev->bus = &mce_subsys;
2430 dev->release = &mce_device_release;
2432 err = device_register(dev);
2438 for (i = 0; mce_device_attrs[i]; i++) {
2439 err = device_create_file(dev, mce_device_attrs[i]);
2443 for (j = 0; j < mca_cfg.banks; j++) {
2444 err = device_create_file(dev, &mce_banks[j].attr);
2448 cpumask_set_cpu(cpu, mce_device_initialized);
2449 per_cpu(mce_device, cpu) = dev;
2454 device_remove_file(dev, &mce_banks[j].attr);
2457 device_remove_file(dev, mce_device_attrs[i]);
2459 device_unregister(dev);
2464 static void mce_device_remove(unsigned int cpu)
2466 struct device *dev = per_cpu(mce_device, cpu);
2469 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2472 for (i = 0; mce_device_attrs[i]; i++)
2473 device_remove_file(dev, mce_device_attrs[i]);
2475 for (i = 0; i < mca_cfg.banks; i++)
2476 device_remove_file(dev, &mce_banks[i].attr);
2478 device_unregister(dev);
2479 cpumask_clear_cpu(cpu, mce_device_initialized);
2480 per_cpu(mce_device, cpu) = NULL;
2483 /* Make sure there are no machine checks on offlined CPUs. */
2484 static void mce_disable_cpu(void)
2486 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2489 if (!cpuhp_tasks_frozen)
2492 vendor_disable_error_reporting();
2495 static void mce_reenable_cpu(void)
2499 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2502 if (!cpuhp_tasks_frozen)
2504 for (i = 0; i < mca_cfg.banks; i++) {
2505 struct mce_bank *b = &mce_banks[i];
2508 wrmsrl(msr_ops.ctl(i), b->ctl);
2512 static int mce_cpu_dead(unsigned int cpu)
2514 mce_intel_hcpu_update(cpu);
2516 /* intentionally ignoring frozen here */
2517 if (!cpuhp_tasks_frozen)
2522 static int mce_cpu_online(unsigned int cpu)
2524 struct timer_list *t = this_cpu_ptr(&mce_timer);
2527 mce_device_create(cpu);
2529 ret = mce_threshold_create_device(cpu);
2531 mce_device_remove(cpu);
2539 static int mce_cpu_pre_down(unsigned int cpu)
2541 struct timer_list *t = this_cpu_ptr(&mce_timer);
2545 mce_threshold_remove_device(cpu);
2546 mce_device_remove(cpu);
2550 static __init void mce_init_banks(void)
2554 for (i = 0; i < mca_cfg.banks; i++) {
2555 struct mce_bank *b = &mce_banks[i];
2556 struct device_attribute *a = &b->attr;
2558 sysfs_attr_init(&a->attr);
2559 a->attr.name = b->attrname;
2560 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2562 a->attr.mode = 0644;
2563 a->show = show_bank;
2564 a->store = set_bank;
2568 static __init int mcheck_init_device(void)
2570 enum cpuhp_state hp_online;
2573 if (!mce_available(&boot_cpu_data)) {
2578 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2585 err = subsys_system_register(&mce_subsys, NULL);
2589 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2594 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2595 mce_cpu_online, mce_cpu_pre_down);
2597 goto err_out_online;
2600 register_syscore_ops(&mce_syscore_ops);
2602 /* register character device /dev/mcelog */
2603 err = misc_register(&mce_chrdev_device);
2610 unregister_syscore_ops(&mce_syscore_ops);
2611 cpuhp_remove_state(hp_online);
2614 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2617 free_cpumask_var(mce_device_initialized);
2620 pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err);
2624 device_initcall_sync(mcheck_init_device);
2627 * Old style boot options parsing. Only for compatibility.
2629 static int __init mcheck_disable(char *str)
2631 mca_cfg.disabled = true;
2634 __setup("nomce", mcheck_disable);
2636 #ifdef CONFIG_DEBUG_FS
2637 struct dentry *mce_get_debugfs_dir(void)
2639 static struct dentry *dmce;
2642 dmce = debugfs_create_dir("mce", NULL);
2647 static void mce_reset(void)
2650 atomic_set(&mce_fake_panicked, 0);
2651 atomic_set(&mce_executing, 0);
2652 atomic_set(&mce_callin, 0);
2653 atomic_set(&global_nwo, 0);
2656 static int fake_panic_get(void *data, u64 *val)
2662 static int fake_panic_set(void *data, u64 val)
2669 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2670 fake_panic_set, "%llu\n");
2672 static int __init mcheck_debugfs_init(void)
2674 struct dentry *dmce, *ffake_panic;
2676 dmce = mce_get_debugfs_dir();
2679 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2687 static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2690 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2691 EXPORT_SYMBOL_GPL(mcsafe_key);
2693 static int __init mcheck_late_init(void)
2695 if (mca_cfg.recovery)
2696 static_branch_inc(&mcsafe_key);
2698 mcheck_debugfs_init();
2701 * Flush out everything that has been logged during early boot, now that
2702 * everything has been initialized (workqueues, decoders, ...).
2704 mce_schedule_work();
2708 late_initcall(mcheck_late_init);