2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/ras.h>
39 #include <linux/smp.h>
42 #include <linux/debugfs.h>
43 #include <linux/irq_work.h>
44 #include <linux/export.h>
45 #include <linux/jump_label.h>
47 #include <asm/intel-family.h>
48 #include <asm/processor.h>
49 #include <asm/traps.h>
50 #include <asm/tlbflush.h>
53 #include <asm/reboot.h>
55 #include "mce-internal.h"
57 static DEFINE_MUTEX(mce_log_mutex);
59 #define CREATE_TRACE_POINTS
60 #include <trace/events/mce.h>
62 #define SPINUNIT 100 /* 100ns */
64 DEFINE_PER_CPU(unsigned, mce_exception_count);
66 struct mce_bank *mce_banks __read_mostly;
67 struct mce_vendor_flags mce_flags __read_mostly;
69 struct mca_config mca_cfg __read_mostly = {
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
82 static DEFINE_PER_CPU(struct mce, mces_seen);
83 static unsigned long mce_need_notify;
84 static int cpu_missing;
87 * MCA banks polled by the period polling timer for corrected events.
88 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
90 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
91 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
95 * MCA banks controlled through firmware first for corrected errors.
96 * This is a global list of banks for which we won't enable CMCI and we
97 * won't poll. Firmware controls these banks and is responsible for
98 * reporting corrected errors through GHES. Uncorrected/recoverable
99 * errors are still notified through a machine check.
101 mce_banks_t mce_banks_ce_disabled;
103 static struct work_struct mce_work;
104 static struct irq_work mce_irq_work;
106 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
109 * CPU/chipset specific EDAC code can register a notifier call here to print
110 * MCE errors in a human-readable form.
112 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
114 /* Do initial initialization of a struct mce */
115 void mce_setup(struct mce *m)
117 memset(m, 0, sizeof(struct mce));
118 m->cpu = m->extcpu = smp_processor_id();
119 /* We hope get_seconds stays lockless */
120 m->time = get_seconds();
121 m->cpuvendor = boot_cpu_data.x86_vendor;
122 m->cpuid = cpuid_eax(1);
123 m->socketid = cpu_data(m->extcpu).phys_proc_id;
124 m->apicid = cpu_data(m->extcpu).initial_apicid;
125 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
127 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
128 rdmsrl(MSR_PPIN, m->ppin);
131 DEFINE_PER_CPU(struct mce, injectm);
132 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
134 void mce_log(struct mce *m)
136 if (!mce_gen_pool_add(m))
137 irq_work_queue(&mce_irq_work);
140 void mce_inject_log(struct mce *m)
142 mutex_lock(&mce_log_mutex);
144 mutex_unlock(&mce_log_mutex);
146 EXPORT_SYMBOL_GPL(mce_inject_log);
148 static struct notifier_block mce_srao_nb;
151 * We run the default notifier if we have only the SRAO, the first and the
152 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
153 * notifiers registered on the chain.
155 #define NUM_DEFAULT_NOTIFIERS 3
156 static atomic_t num_notifiers;
158 void mce_register_decode_chain(struct notifier_block *nb)
160 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
163 atomic_inc(&num_notifiers);
165 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
167 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
169 void mce_unregister_decode_chain(struct notifier_block *nb)
171 atomic_dec(&num_notifiers);
173 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
175 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
177 static inline u32 ctl_reg(int bank)
179 return MSR_IA32_MCx_CTL(bank);
182 static inline u32 status_reg(int bank)
184 return MSR_IA32_MCx_STATUS(bank);
187 static inline u32 addr_reg(int bank)
189 return MSR_IA32_MCx_ADDR(bank);
192 static inline u32 misc_reg(int bank)
194 return MSR_IA32_MCx_MISC(bank);
197 static inline u32 smca_ctl_reg(int bank)
199 return MSR_AMD64_SMCA_MCx_CTL(bank);
202 static inline u32 smca_status_reg(int bank)
204 return MSR_AMD64_SMCA_MCx_STATUS(bank);
207 static inline u32 smca_addr_reg(int bank)
209 return MSR_AMD64_SMCA_MCx_ADDR(bank);
212 static inline u32 smca_misc_reg(int bank)
214 return MSR_AMD64_SMCA_MCx_MISC(bank);
217 struct mca_msr_regs msr_ops = {
219 .status = status_reg,
224 static void __print_mce(struct mce *m)
226 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
228 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
229 m->mcgstatus, m->bank, m->status);
232 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
233 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
236 if (m->cs == __KERNEL_CS)
237 print_symbol("{%s}", m->ip);
241 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
243 pr_cont("ADDR %llx ", m->addr);
245 pr_cont("MISC %llx ", m->misc);
247 if (mce_flags.smca) {
249 pr_cont("SYND %llx ", m->synd);
251 pr_cont("IPID %llx ", m->ipid);
256 * Note this output is parsed by external tools and old fields
257 * should not be changed.
259 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
260 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
261 cpu_data(m->extcpu).microcode);
264 static void print_mce(struct mce *m)
267 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
270 #define PANIC_TIMEOUT 5 /* 5 seconds */
272 static atomic_t mce_panicked;
274 static int fake_panic;
275 static atomic_t mce_fake_panicked;
277 /* Panic in progress. Enable interrupts and wait for final IPI */
278 static void wait_for_panic(void)
280 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
284 while (timeout-- > 0)
286 if (panic_timeout == 0)
287 panic_timeout = mca_cfg.panic_timeout;
288 panic("Panicing machine check CPU died");
291 static void mce_panic(const char *msg, struct mce *final, char *exp)
294 struct llist_node *pending;
295 struct mce_evt_llist *l;
299 * Make sure only one CPU runs in machine check panic
301 if (atomic_inc_return(&mce_panicked) > 1)
308 /* Don't log too much for fake panic */
309 if (atomic_inc_return(&mce_fake_panicked) > 1)
312 pending = mce_gen_pool_prepare_records();
313 /* First print corrected ones that are still unlogged */
314 llist_for_each_entry(l, pending, llnode) {
315 struct mce *m = &l->mce;
316 if (!(m->status & MCI_STATUS_UC)) {
319 apei_err = apei_write_mce(m);
322 /* Now print uncorrected but with the final one last */
323 llist_for_each_entry(l, pending, llnode) {
324 struct mce *m = &l->mce;
325 if (!(m->status & MCI_STATUS_UC))
327 if (!final || mce_cmp(m, final)) {
330 apei_err = apei_write_mce(m);
336 apei_err = apei_write_mce(final);
339 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
341 pr_emerg(HW_ERR "Machine check: %s\n", exp);
343 if (panic_timeout == 0)
344 panic_timeout = mca_cfg.panic_timeout;
347 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
350 /* Support code for software error injection */
352 static int msr_to_offset(u32 msr)
354 unsigned bank = __this_cpu_read(injectm.bank);
356 if (msr == mca_cfg.rip_msr)
357 return offsetof(struct mce, ip);
358 if (msr == msr_ops.status(bank))
359 return offsetof(struct mce, status);
360 if (msr == msr_ops.addr(bank))
361 return offsetof(struct mce, addr);
362 if (msr == msr_ops.misc(bank))
363 return offsetof(struct mce, misc);
364 if (msr == MSR_IA32_MCG_STATUS)
365 return offsetof(struct mce, mcgstatus);
369 /* MSR access wrappers used for error injection */
370 static u64 mce_rdmsrl(u32 msr)
374 if (__this_cpu_read(injectm.finished)) {
375 int offset = msr_to_offset(msr);
379 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
382 if (rdmsrl_safe(msr, &v)) {
383 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
385 * Return zero in case the access faulted. This should
386 * not happen normally but can happen if the CPU does
387 * something weird, or if the code is buggy.
395 static void mce_wrmsrl(u32 msr, u64 v)
397 if (__this_cpu_read(injectm.finished)) {
398 int offset = msr_to_offset(msr);
401 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
408 * Collect all global (w.r.t. this processor) status about this machine
409 * check into our "mce" struct so that we can use it later to assess
410 * the severity of the problem as we read per-bank specific details.
412 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
416 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
419 * Get the address of the instruction at the time of
420 * the machine check error.
422 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
427 * When in VM86 mode make the cs look like ring 3
428 * always. This is a lie, but it's better than passing
429 * the additional vm86 bit around everywhere.
431 if (v8086_mode(regs))
434 /* Use accurate RIP reporting if available. */
436 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
440 int mce_available(struct cpuinfo_x86 *c)
442 if (mca_cfg.disabled)
444 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
447 static void mce_schedule_work(void)
449 if (!mce_gen_pool_empty())
450 schedule_work(&mce_work);
453 static void mce_irq_work_cb(struct irq_work *entry)
458 static void mce_report_event(struct pt_regs *regs)
460 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
463 * Triggering the work queue here is just an insurance
464 * policy in case the syscall exit notify handler
465 * doesn't run soon enough or ends up running on the
466 * wrong CPU (can happen when audit sleeps)
472 irq_work_queue(&mce_irq_work);
476 * Check if the address reported by the CPU is in a format we can parse.
477 * It would be possible to add code for most other cases, but all would
478 * be somewhat complicated (e.g. segment offset would require an instruction
479 * parser). So only support physical addresses up to page granuality for now.
481 static int mce_usable_address(struct mce *m)
483 if (!(m->status & MCI_STATUS_ADDRV))
486 /* Checks after this one are Intel-specific: */
487 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
490 if (!(m->status & MCI_STATUS_MISCV))
493 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
496 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
502 bool mce_is_memory_error(struct mce *m)
504 if (m->cpuvendor == X86_VENDOR_AMD) {
505 /* ErrCodeExt[20:16] */
506 u8 xec = (m->status >> 16) & 0x1f;
508 return (xec == 0x0 || xec == 0x8);
509 } else if (m->cpuvendor == X86_VENDOR_INTEL) {
511 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
513 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
514 * indicating a memory error. Bit 8 is used for indicating a
515 * cache hierarchy error. The combination of bit 2 and bit 3
516 * is used for indicating a `generic' cache hierarchy error
517 * But we can't just blindly check the above bits, because if
518 * bit 11 is set, then it is a bus/interconnect error - and
519 * either way the above bits just gives more detail on what
520 * bus/interconnect error happened. Note that bit 12 can be
521 * ignored, as it's the "filter" bit.
523 return (m->status & 0xef80) == BIT(7) ||
524 (m->status & 0xef00) == BIT(8) ||
525 (m->status & 0xeffc) == 0xc;
530 EXPORT_SYMBOL_GPL(mce_is_memory_error);
532 static bool cec_add_mce(struct mce *m)
537 /* We eat only correctable DRAM errors with usable addresses. */
538 if (mce_is_memory_error(m) &&
539 !(m->status & MCI_STATUS_UC) &&
540 mce_usable_address(m))
541 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
547 static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
550 struct mce *m = (struct mce *)data;
558 /* Emit the trace record: */
561 set_bit(0, &mce_need_notify);
568 static struct notifier_block first_nb = {
569 .notifier_call = mce_first_notifier,
570 .priority = MCE_PRIO_FIRST,
573 static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
576 struct mce *mce = (struct mce *)data;
582 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
583 pfn = mce->addr >> PAGE_SHIFT;
584 memory_failure(pfn, MCE_VECTOR, 0);
589 static struct notifier_block mce_srao_nb = {
590 .notifier_call = srao_decode_notifier,
591 .priority = MCE_PRIO_SRAO,
594 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
597 struct mce *m = (struct mce *)data;
602 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
610 static struct notifier_block mce_default_nb = {
611 .notifier_call = mce_default_notifier,
612 /* lowest prio, we want it to run last. */
613 .priority = MCE_PRIO_LOWEST,
617 * Read ADDR and MISC registers.
619 static void mce_read_aux(struct mce *m, int i)
621 if (m->status & MCI_STATUS_MISCV)
622 m->misc = mce_rdmsrl(msr_ops.misc(i));
624 if (m->status & MCI_STATUS_ADDRV) {
625 m->addr = mce_rdmsrl(msr_ops.addr(i));
628 * Mask the reported address by the reported granularity.
630 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
631 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
637 * Extract [55:<lsb>] where lsb is the least significant
638 * *valid* bit of the address bits.
640 if (mce_flags.smca) {
641 u8 lsb = (m->addr >> 56) & 0x3f;
643 m->addr &= GENMASK_ULL(55, lsb);
647 if (mce_flags.smca) {
648 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
650 if (m->status & MCI_STATUS_SYNDV)
651 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
655 DEFINE_PER_CPU(unsigned, mce_poll_count);
658 * Poll for corrected events or events that happened before reset.
659 * Those are just logged through /dev/mcelog.
661 * This is executed in standard interrupt context.
663 * Note: spec recommends to panic for fatal unsignalled
664 * errors here. However this would be quite problematic --
665 * we would need to reimplement the Monarch handling and
666 * it would mess up the exclusion between exception handler
667 * and poll hander -- * so we skip this for now.
668 * These cases should not happen anyways, or only when the CPU
669 * is already totally * confused. In this case it's likely it will
670 * not fully execute the machine check handler either.
672 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
674 bool error_seen = false;
679 this_cpu_inc(mce_poll_count);
681 mce_gather_info(&m, NULL);
683 if (flags & MCP_TIMESTAMP)
686 for (i = 0; i < mca_cfg.banks; i++) {
687 if (!mce_banks[i].ctl || !test_bit(i, *b))
695 m.status = mce_rdmsrl(msr_ops.status(i));
696 if (!(m.status & MCI_STATUS_VAL))
700 * Uncorrected or signalled events are handled by the exception
701 * handler when it is enabled, so don't process those here.
703 * TBD do the same check for MCI_STATUS_EN here?
705 if (!(flags & MCP_UC) &&
706 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
713 severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
715 if (severity == MCE_DEFERRED_SEVERITY && mce_is_memory_error(&m))
716 if (m.status & MCI_STATUS_ADDRV)
717 m.severity = severity;
720 * Don't get the IP here because it's unlikely to
721 * have anything to do with the actual error location.
723 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
725 else if (mce_usable_address(&m)) {
727 * Although we skipped logging this, we still want
728 * to take action. Add to the pool so the registered
729 * notifiers will see it.
731 if (!mce_gen_pool_add(&m))
736 * Clear state for this bank.
738 mce_wrmsrl(msr_ops.status(i), 0);
742 * Don't clear MCG_STATUS here because it's only defined for
750 EXPORT_SYMBOL_GPL(machine_check_poll);
753 * Do a quick check if any of the events requires a panic.
754 * This decides if we keep the events around or clear them.
756 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
757 struct pt_regs *regs)
762 for (i = 0; i < mca_cfg.banks; i++) {
763 m->status = mce_rdmsrl(msr_ops.status(i));
764 if (m->status & MCI_STATUS_VAL) {
765 __set_bit(i, validp);
766 if (quirk_no_way_out)
767 quirk_no_way_out(i, m, regs);
770 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
779 * Variable to establish order between CPUs while scanning.
780 * Each CPU spins initially until executing is equal its number.
782 static atomic_t mce_executing;
785 * Defines order of CPUs on entry. First CPU becomes Monarch.
787 static atomic_t mce_callin;
790 * Check if a timeout waiting for other CPUs happened.
792 static int mce_timed_out(u64 *t, const char *msg)
795 * The others already did panic for some reason.
796 * Bail out like in a timeout.
797 * rmb() to tell the compiler that system_state
798 * might have been modified by someone else.
801 if (atomic_read(&mce_panicked))
803 if (!mca_cfg.monarch_timeout)
805 if ((s64)*t < SPINUNIT) {
806 if (mca_cfg.tolerant <= 1)
807 mce_panic(msg, NULL, NULL);
813 touch_nmi_watchdog();
818 * The Monarch's reign. The Monarch is the CPU who entered
819 * the machine check handler first. It waits for the others to
820 * raise the exception too and then grades them. When any
821 * error is fatal panic. Only then let the others continue.
823 * The other CPUs entering the MCE handler will be controlled by the
824 * Monarch. They are called Subjects.
826 * This way we prevent any potential data corruption in a unrecoverable case
827 * and also makes sure always all CPU's errors are examined.
829 * Also this detects the case of a machine check event coming from outer
830 * space (not detected by any CPUs) In this case some external agent wants
831 * us to shut down, so panic too.
833 * The other CPUs might still decide to panic if the handler happens
834 * in a unrecoverable place, but in this case the system is in a semi-stable
835 * state and won't corrupt anything by itself. It's ok to let the others
836 * continue for a bit first.
838 * All the spin loops have timeouts; when a timeout happens a CPU
839 * typically elects itself to be Monarch.
841 static void mce_reign(void)
844 struct mce *m = NULL;
845 int global_worst = 0;
850 * This CPU is the Monarch and the other CPUs have run
851 * through their handlers.
852 * Grade the severity of the errors of all the CPUs.
854 for_each_possible_cpu(cpu) {
855 int severity = mce_severity(&per_cpu(mces_seen, cpu),
858 if (severity > global_worst) {
860 global_worst = severity;
861 m = &per_cpu(mces_seen, cpu);
866 * Cannot recover? Panic here then.
867 * This dumps all the mces in the log buffer and stops the
870 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
871 mce_panic("Fatal machine check", m, msg);
874 * For UC somewhere we let the CPU who detects it handle it.
875 * Also must let continue the others, otherwise the handling
876 * CPU could deadlock on a lock.
880 * No machine check event found. Must be some external
881 * source or one CPU is hung. Panic.
883 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
884 mce_panic("Fatal machine check from unknown source", NULL, NULL);
887 * Now clear all the mces_seen so that they don't reappear on
890 for_each_possible_cpu(cpu)
891 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
894 static atomic_t global_nwo;
897 * Start of Monarch synchronization. This waits until all CPUs have
898 * entered the exception handler and then determines if any of them
899 * saw a fatal event that requires panic. Then it executes them
900 * in the entry order.
901 * TBD double check parallel CPU hotunplug
903 static int mce_start(int *no_way_out)
906 int cpus = num_online_cpus();
907 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
912 atomic_add(*no_way_out, &global_nwo);
914 * Rely on the implied barrier below, such that global_nwo
915 * is updated before mce_callin.
917 order = atomic_inc_return(&mce_callin);
922 while (atomic_read(&mce_callin) != cpus) {
923 if (mce_timed_out(&timeout,
924 "Timeout: Not all CPUs entered broadcast exception handler")) {
925 atomic_set(&global_nwo, 0);
932 * mce_callin should be read before global_nwo
938 * Monarch: Starts executing now, the others wait.
940 atomic_set(&mce_executing, 1);
943 * Subject: Now start the scanning loop one by one in
944 * the original callin order.
945 * This way when there are any shared banks it will be
946 * only seen by one CPU before cleared, avoiding duplicates.
948 while (atomic_read(&mce_executing) < order) {
949 if (mce_timed_out(&timeout,
950 "Timeout: Subject CPUs unable to finish machine check processing")) {
951 atomic_set(&global_nwo, 0);
959 * Cache the global no_way_out state.
961 *no_way_out = atomic_read(&global_nwo);
967 * Synchronize between CPUs after main scanning loop.
968 * This invokes the bulk of the Monarch processing.
970 static int mce_end(int order)
973 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
981 * Allow others to run.
983 atomic_inc(&mce_executing);
986 /* CHECKME: Can this race with a parallel hotplug? */
987 int cpus = num_online_cpus();
990 * Monarch: Wait for everyone to go through their scanning
993 while (atomic_read(&mce_executing) <= cpus) {
994 if (mce_timed_out(&timeout,
995 "Timeout: Monarch CPU unable to finish machine check processing"))
1005 * Subject: Wait for Monarch to finish.
1007 while (atomic_read(&mce_executing) != 0) {
1008 if (mce_timed_out(&timeout,
1009 "Timeout: Monarch CPU did not finish machine check processing"))
1015 * Don't reset anything. That's done by the Monarch.
1021 * Reset all global state.
1024 atomic_set(&global_nwo, 0);
1025 atomic_set(&mce_callin, 0);
1029 * Let others run again.
1031 atomic_set(&mce_executing, 0);
1035 static void mce_clear_state(unsigned long *toclear)
1039 for (i = 0; i < mca_cfg.banks; i++) {
1040 if (test_bit(i, toclear))
1041 mce_wrmsrl(msr_ops.status(i), 0);
1045 static int do_memory_failure(struct mce *m)
1047 int flags = MF_ACTION_REQUIRED;
1050 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1051 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1052 flags |= MF_MUST_KILL;
1053 ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags);
1055 pr_err("Memory error not recovered");
1060 * The actual machine check handler. This only handles real
1061 * exceptions when something got corrupted coming in through int 18.
1063 * This is executed in NMI context not subject to normal locking rules. This
1064 * implies that most kernel services cannot be safely used. Don't even
1065 * think about putting a printk in there!
1067 * On Intel systems this is entered on all CPUs in parallel through
1068 * MCE broadcast. However some CPUs might be broken beyond repair,
1069 * so be always careful when synchronizing with others.
1071 void do_machine_check(struct pt_regs *regs, long error_code)
1073 struct mca_config *cfg = &mca_cfg;
1074 struct mce m, *final;
1080 * Establish sequential order between the CPUs entering the machine
1085 * If no_way_out gets set, there is no safe way to recover from this
1086 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1090 * If kill_it gets set, there might be a way to recover from this
1094 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1095 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1096 char *msg = "Unknown";
1099 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1103 int cpu = smp_processor_id();
1106 * Cases where we avoid rendezvous handler timeout:
1107 * 1) If this CPU is offline.
1109 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1110 * skip those CPUs which remain looping in the 1st kernel - see
1111 * crash_nmi_callback().
1113 * Note: there still is a small window between kexec-ing and the new,
1114 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1115 * might not get handled properly.
1117 if (cpu_is_offline(cpu) ||
1118 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1121 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1122 if (mcgstatus & MCG_STATUS_RIPV) {
1123 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1130 this_cpu_inc(mce_exception_count);
1135 mce_gather_info(&m, regs);
1138 final = this_cpu_ptr(&mces_seen);
1141 memset(valid_banks, 0, sizeof(valid_banks));
1142 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1147 * When no restart IP might need to kill or panic.
1148 * Assume the worst for now, but if we find the
1149 * severity is MCE_AR_SEVERITY we have other options.
1151 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1155 * Check if this MCE is signaled to only this logical processor,
1158 if (m.cpuvendor == X86_VENDOR_INTEL)
1159 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1162 * Go through all banks in exclusion of the other CPUs. This way we
1163 * don't report duplicated events on shared banks because the first one
1164 * to see it will clear it. If this is a Local MCE, then no need to
1165 * perform rendezvous.
1168 order = mce_start(&no_way_out);
1170 for (i = 0; i < cfg->banks; i++) {
1171 __clear_bit(i, toclear);
1172 if (!test_bit(i, valid_banks))
1174 if (!mce_banks[i].ctl)
1181 m.status = mce_rdmsrl(msr_ops.status(i));
1182 if ((m.status & MCI_STATUS_VAL) == 0)
1186 * Non uncorrected or non signaled errors are handled by
1187 * machine_check_poll. Leave them alone, unless this panics.
1189 if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1194 * Set taint even when machine check was not enabled.
1196 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1198 severity = mce_severity(&m, cfg->tolerant, NULL, true);
1201 * When machine check was for corrected/deferred handler don't
1202 * touch, unless we're panicing.
1204 if ((severity == MCE_KEEP_SEVERITY ||
1205 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1207 __set_bit(i, toclear);
1208 if (severity == MCE_NO_SEVERITY) {
1210 * Machine check event was not enabled. Clear, but
1216 mce_read_aux(&m, i);
1218 /* assuming valid severity level != 0 */
1219 m.severity = severity;
1223 if (severity > worst) {
1229 /* mce_clear_state will clear *final, save locally for use later */
1233 mce_clear_state(toclear);
1236 * Do most of the synchronization with other CPUs.
1237 * When there's any problem use only local no_way_out state.
1240 if (mce_end(order) < 0)
1241 no_way_out = worst >= MCE_PANIC_SEVERITY;
1244 * Local MCE skipped calling mce_reign()
1245 * If we found a fatal error, we need to panic here.
1247 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
1248 mce_panic("Machine check from unknown source",
1253 * If tolerant is at an insane level we drop requests to kill
1254 * processes and continue even when there is no way out.
1256 if (cfg->tolerant == 3)
1258 else if (no_way_out)
1259 mce_panic("Fatal machine check on current CPU", &m, msg);
1262 mce_report_event(regs);
1263 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1267 if (worst != MCE_AR_SEVERITY && !kill_it)
1270 /* Fault was in user mode and we need to take some action */
1271 if ((m.cs & 3) == 3) {
1272 ist_begin_non_atomic(regs);
1275 if (kill_it || do_memory_failure(&m))
1276 force_sig(SIGBUS, current);
1277 local_irq_disable();
1278 ist_end_non_atomic();
1280 if (!fixup_exception(regs, X86_TRAP_MC))
1281 mce_panic("Failed kernel mode recovery", &m, NULL);
1287 EXPORT_SYMBOL_GPL(do_machine_check);
1289 #ifndef CONFIG_MEMORY_FAILURE
1290 int memory_failure(unsigned long pfn, int vector, int flags)
1292 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1293 BUG_ON(flags & MF_ACTION_REQUIRED);
1294 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1295 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1303 * Periodic polling timer for "silent" machine check errors. If the
1304 * poller finds an MCE, poll 2x faster. When the poller finds no more
1305 * errors, poll 2x slower (up to check_interval seconds).
1307 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1309 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1310 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1312 static unsigned long mce_adjust_timer_default(unsigned long interval)
1317 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1319 static void __start_timer(struct timer_list *t, unsigned long interval)
1321 unsigned long when = jiffies + interval;
1322 unsigned long flags;
1324 local_irq_save(flags);
1326 if (!timer_pending(t) || time_before(when, t->expires))
1327 mod_timer(t, round_jiffies(when));
1329 local_irq_restore(flags);
1332 static void mce_timer_fn(unsigned long data)
1334 struct timer_list *t = this_cpu_ptr(&mce_timer);
1335 int cpu = smp_processor_id();
1338 WARN_ON(cpu != data);
1340 iv = __this_cpu_read(mce_next_interval);
1342 if (mce_available(this_cpu_ptr(&cpu_info))) {
1343 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1345 if (mce_intel_cmci_poll()) {
1346 iv = mce_adjust_timer(iv);
1352 * Alert userspace if needed. If we logged an MCE, reduce the polling
1353 * interval, otherwise increase the polling interval.
1355 if (mce_notify_irq())
1356 iv = max(iv / 2, (unsigned long) HZ/100);
1358 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1361 __this_cpu_write(mce_next_interval, iv);
1362 __start_timer(t, iv);
1366 * Ensure that the timer is firing in @interval from now.
1368 void mce_timer_kick(unsigned long interval)
1370 struct timer_list *t = this_cpu_ptr(&mce_timer);
1371 unsigned long iv = __this_cpu_read(mce_next_interval);
1373 __start_timer(t, interval);
1376 __this_cpu_write(mce_next_interval, interval);
1379 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1380 static void mce_timer_delete_all(void)
1384 for_each_online_cpu(cpu)
1385 del_timer_sync(&per_cpu(mce_timer, cpu));
1389 * Notify the user(s) about new machine check events.
1390 * Can be called from interrupt context, but not from machine check/NMI
1393 int mce_notify_irq(void)
1395 /* Not more than two messages every minute */
1396 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1398 if (test_and_clear_bit(0, &mce_need_notify)) {
1401 if (__ratelimit(&ratelimit))
1402 pr_info(HW_ERR "Machine check events logged\n");
1408 EXPORT_SYMBOL_GPL(mce_notify_irq);
1410 static int __mcheck_cpu_mce_banks_init(void)
1413 u8 num_banks = mca_cfg.banks;
1415 mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL);
1419 for (i = 0; i < num_banks; i++) {
1420 struct mce_bank *b = &mce_banks[i];
1429 * Initialize Machine Checks for a CPU.
1431 static int __mcheck_cpu_cap_init(void)
1436 rdmsrl(MSR_IA32_MCG_CAP, cap);
1438 b = cap & MCG_BANKCNT_MASK;
1440 pr_info("CPU supports %d MCE banks\n", b);
1442 if (b > MAX_NR_BANKS) {
1443 pr_warn("Using only %u machine check banks out of %u\n",
1448 /* Don't support asymmetric configurations today */
1449 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1453 int err = __mcheck_cpu_mce_banks_init();
1459 /* Use accurate RIP reporting if available. */
1460 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1461 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1463 if (cap & MCG_SER_P)
1469 static void __mcheck_cpu_init_generic(void)
1471 enum mcp_flags m_fl = 0;
1472 mce_banks_t all_banks;
1475 if (!mca_cfg.bootlog)
1479 * Log the machine checks left over from the previous reset.
1481 bitmap_fill(all_banks, MAX_NR_BANKS);
1482 machine_check_poll(MCP_UC | m_fl, &all_banks);
1484 cr4_set_bits(X86_CR4_MCE);
1486 rdmsrl(MSR_IA32_MCG_CAP, cap);
1487 if (cap & MCG_CTL_P)
1488 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1491 static void __mcheck_cpu_init_clear_banks(void)
1495 for (i = 0; i < mca_cfg.banks; i++) {
1496 struct mce_bank *b = &mce_banks[i];
1500 wrmsrl(msr_ops.ctl(i), b->ctl);
1501 wrmsrl(msr_ops.status(i), 0);
1506 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1507 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1508 * Vol 3B Table 15-20). But this confuses both the code that determines
1509 * whether the machine check occurred in kernel or user mode, and also
1510 * the severity assessment code. Pretend that EIPV was set, and take the
1511 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1513 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1517 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1519 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1520 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1521 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1523 (MCI_STATUS_UC|MCI_STATUS_EN|
1524 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1525 MCI_STATUS_AR|MCACOD_INSTR))
1528 m->mcgstatus |= MCG_STATUS_EIPV;
1533 /* Add per CPU specific workarounds here */
1534 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1536 struct mca_config *cfg = &mca_cfg;
1538 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1539 pr_info("unknown CPU type - not enabling MCE support\n");
1543 /* This should be disabled by the BIOS, but isn't always */
1544 if (c->x86_vendor == X86_VENDOR_AMD) {
1545 if (c->x86 == 15 && cfg->banks > 4) {
1547 * disable GART TBL walk error reporting, which
1548 * trips off incorrectly with the IOMMU & 3ware
1551 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1553 if (c->x86 < 17 && cfg->bootlog < 0) {
1555 * Lots of broken BIOS around that don't clear them
1556 * by default and leave crap in there. Don't log:
1561 * Various K7s with broken bank 0 around. Always disable
1564 if (c->x86 == 6 && cfg->banks > 0)
1565 mce_banks[0].ctl = 0;
1568 * overflow_recov is supported for F15h Models 00h-0fh
1569 * even though we don't have a CPUID bit for it.
1571 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1572 mce_flags.overflow_recov = 1;
1575 * Turn off MC4_MISC thresholding banks on those models since
1576 * they're not supported there.
1578 if (c->x86 == 0x15 &&
1579 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1584 0x00000413, /* MC4_MISC0 */
1585 0xc0000408, /* MC4_MISC1 */
1588 rdmsrl(MSR_K7_HWCR, hwcr);
1590 /* McStatusWrEn has to be set */
1591 need_toggle = !(hwcr & BIT(18));
1594 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1596 /* Clear CntP bit safely */
1597 for (i = 0; i < ARRAY_SIZE(msrs); i++)
1598 msr_clear_bit(msrs[i], 62);
1600 /* restore old settings */
1602 wrmsrl(MSR_K7_HWCR, hwcr);
1606 if (c->x86_vendor == X86_VENDOR_INTEL) {
1608 * SDM documents that on family 6 bank 0 should not be written
1609 * because it aliases to another special BIOS controlled
1611 * But it's not aliased anymore on model 0x1a+
1612 * Don't ignore bank 0 completely because there could be a
1613 * valid event later, merely don't write CTL0.
1616 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1617 mce_banks[0].init = 0;
1620 * All newer Intel systems support MCE broadcasting. Enable
1621 * synchronization with a one second timeout.
1623 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1624 cfg->monarch_timeout < 0)
1625 cfg->monarch_timeout = USEC_PER_SEC;
1628 * There are also broken BIOSes on some Pentium M and
1631 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1634 if (c->x86 == 6 && c->x86_model == 45)
1635 quirk_no_way_out = quirk_sandybridge_ifu;
1637 if (cfg->monarch_timeout < 0)
1638 cfg->monarch_timeout = 0;
1639 if (cfg->bootlog != 0)
1640 cfg->panic_timeout = 30;
1645 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1650 switch (c->x86_vendor) {
1651 case X86_VENDOR_INTEL:
1652 intel_p5_mcheck_init(c);
1655 case X86_VENDOR_CENTAUR:
1656 winchip_mcheck_init(c);
1667 * Init basic CPU features needed for early decoding of MCEs.
1669 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1671 if (c->x86_vendor == X86_VENDOR_AMD) {
1672 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1673 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1674 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1676 if (mce_flags.smca) {
1677 msr_ops.ctl = smca_ctl_reg;
1678 msr_ops.status = smca_status_reg;
1679 msr_ops.addr = smca_addr_reg;
1680 msr_ops.misc = smca_misc_reg;
1685 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1687 switch (c->x86_vendor) {
1688 case X86_VENDOR_INTEL:
1689 mce_intel_feature_init(c);
1690 mce_adjust_timer = cmci_intel_adjust_timer;
1693 case X86_VENDOR_AMD: {
1694 mce_amd_feature_init(c);
1703 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1705 switch (c->x86_vendor) {
1706 case X86_VENDOR_INTEL:
1707 mce_intel_feature_clear(c);
1714 static void mce_start_timer(struct timer_list *t)
1716 unsigned long iv = check_interval * HZ;
1718 if (mca_cfg.ignore_ce || !iv)
1721 this_cpu_write(mce_next_interval, iv);
1722 __start_timer(t, iv);
1725 static void __mcheck_cpu_setup_timer(void)
1727 struct timer_list *t = this_cpu_ptr(&mce_timer);
1728 unsigned int cpu = smp_processor_id();
1730 setup_pinned_timer(t, mce_timer_fn, cpu);
1733 static void __mcheck_cpu_init_timer(void)
1735 struct timer_list *t = this_cpu_ptr(&mce_timer);
1736 unsigned int cpu = smp_processor_id();
1738 setup_pinned_timer(t, mce_timer_fn, cpu);
1742 /* Handle unconfigured int18 (should never happen) */
1743 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1745 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1746 smp_processor_id());
1749 /* Call the installed machine check handler for this CPU setup. */
1750 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1751 unexpected_machine_check;
1754 * Called for each booted CPU to set up machine checks.
1755 * Must be called with preempt off:
1757 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1759 if (mca_cfg.disabled)
1762 if (__mcheck_cpu_ancient_init(c))
1765 if (!mce_available(c))
1768 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1769 mca_cfg.disabled = true;
1773 if (mce_gen_pool_init()) {
1774 mca_cfg.disabled = true;
1775 pr_emerg("Couldn't allocate MCE records pool!\n");
1779 machine_check_vector = do_machine_check;
1781 __mcheck_cpu_init_early(c);
1782 __mcheck_cpu_init_generic();
1783 __mcheck_cpu_init_vendor(c);
1784 __mcheck_cpu_init_clear_banks();
1785 __mcheck_cpu_setup_timer();
1789 * Called for each booted CPU to clear some machine checks opt-ins
1791 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1793 if (mca_cfg.disabled)
1796 if (!mce_available(c))
1800 * Possibly to clear general settings generic to x86
1801 * __mcheck_cpu_clear_generic(c);
1803 __mcheck_cpu_clear_vendor(c);
1807 static void __mce_disable_bank(void *arg)
1809 int bank = *((int *)arg);
1810 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1811 cmci_disable_bank(bank);
1814 void mce_disable_bank(int bank)
1816 if (bank >= mca_cfg.banks) {
1818 "Ignoring request to disable invalid MCA bank %d.\n",
1822 set_bit(bank, mce_banks_ce_disabled);
1823 on_each_cpu(__mce_disable_bank, &bank, 1);
1827 * mce=off Disables machine check
1828 * mce=no_cmci Disables CMCI
1829 * mce=no_lmce Disables LMCE
1830 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1831 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1832 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1833 * monarchtimeout is how long to wait for other CPUs on machine
1834 * check, or 0 to not wait
1835 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1836 * mce=nobootlog Don't log MCEs from before booting.
1837 * mce=bios_cmci_threshold Don't program the CMCI threshold
1838 * mce=recovery force enable memcpy_mcsafe()
1840 static int __init mcheck_enable(char *str)
1842 struct mca_config *cfg = &mca_cfg;
1850 if (!strcmp(str, "off"))
1851 cfg->disabled = true;
1852 else if (!strcmp(str, "no_cmci"))
1853 cfg->cmci_disabled = true;
1854 else if (!strcmp(str, "no_lmce"))
1855 cfg->lmce_disabled = true;
1856 else if (!strcmp(str, "dont_log_ce"))
1857 cfg->dont_log_ce = true;
1858 else if (!strcmp(str, "ignore_ce"))
1859 cfg->ignore_ce = true;
1860 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1861 cfg->bootlog = (str[0] == 'b');
1862 else if (!strcmp(str, "bios_cmci_threshold"))
1863 cfg->bios_cmci_threshold = true;
1864 else if (!strcmp(str, "recovery"))
1865 cfg->recovery = true;
1866 else if (isdigit(str[0])) {
1867 if (get_option(&str, &cfg->tolerant) == 2)
1868 get_option(&str, &(cfg->monarch_timeout));
1870 pr_info("mce argument %s ignored. Please use /sys\n", str);
1875 __setup("mce", mcheck_enable);
1877 int __init mcheck_init(void)
1879 mcheck_intel_therm_init();
1880 mce_register_decode_chain(&first_nb);
1881 mce_register_decode_chain(&mce_srao_nb);
1882 mce_register_decode_chain(&mce_default_nb);
1883 mcheck_vendor_init_severity();
1885 INIT_WORK(&mce_work, mce_gen_pool_process);
1886 init_irq_work(&mce_irq_work, mce_irq_work_cb);
1892 * mce_syscore: PM support
1896 * Disable machine checks on suspend and shutdown. We can't really handle
1899 static void mce_disable_error_reporting(void)
1903 for (i = 0; i < mca_cfg.banks; i++) {
1904 struct mce_bank *b = &mce_banks[i];
1907 wrmsrl(msr_ops.ctl(i), 0);
1912 static void vendor_disable_error_reporting(void)
1915 * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
1916 * Disabling them for just a single offlined CPU is bad, since it will
1917 * inhibit reporting for all shared resources on the socket like the
1918 * last level cache (LLC), the integrated memory controller (iMC), etc.
1920 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1923 mce_disable_error_reporting();
1926 static int mce_syscore_suspend(void)
1928 vendor_disable_error_reporting();
1932 static void mce_syscore_shutdown(void)
1934 vendor_disable_error_reporting();
1938 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1939 * Only one CPU is active at this time, the others get re-added later using
1942 static void mce_syscore_resume(void)
1944 __mcheck_cpu_init_generic();
1945 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
1946 __mcheck_cpu_init_clear_banks();
1949 static struct syscore_ops mce_syscore_ops = {
1950 .suspend = mce_syscore_suspend,
1951 .shutdown = mce_syscore_shutdown,
1952 .resume = mce_syscore_resume,
1956 * mce_device: Sysfs support
1959 static void mce_cpu_restart(void *data)
1961 if (!mce_available(raw_cpu_ptr(&cpu_info)))
1963 __mcheck_cpu_init_generic();
1964 __mcheck_cpu_init_clear_banks();
1965 __mcheck_cpu_init_timer();
1968 /* Reinit MCEs after user configuration changes */
1969 static void mce_restart(void)
1971 mce_timer_delete_all();
1972 on_each_cpu(mce_cpu_restart, NULL, 1);
1975 /* Toggle features for corrected errors */
1976 static void mce_disable_cmci(void *data)
1978 if (!mce_available(raw_cpu_ptr(&cpu_info)))
1983 static void mce_enable_ce(void *all)
1985 if (!mce_available(raw_cpu_ptr(&cpu_info)))
1990 __mcheck_cpu_init_timer();
1993 static struct bus_type mce_subsys = {
1994 .name = "machinecheck",
1995 .dev_name = "machinecheck",
1998 DEFINE_PER_CPU(struct device *, mce_device);
2000 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2002 return container_of(attr, struct mce_bank, attr);
2005 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2008 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2011 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2012 const char *buf, size_t size)
2016 if (kstrtou64(buf, 0, &new) < 0)
2019 attr_to_bank(attr)->ctl = new;
2025 static ssize_t set_ignore_ce(struct device *s,
2026 struct device_attribute *attr,
2027 const char *buf, size_t size)
2031 if (kstrtou64(buf, 0, &new) < 0)
2034 if (mca_cfg.ignore_ce ^ !!new) {
2036 /* disable ce features */
2037 mce_timer_delete_all();
2038 on_each_cpu(mce_disable_cmci, NULL, 1);
2039 mca_cfg.ignore_ce = true;
2041 /* enable ce features */
2042 mca_cfg.ignore_ce = false;
2043 on_each_cpu(mce_enable_ce, (void *)1, 1);
2049 static ssize_t set_cmci_disabled(struct device *s,
2050 struct device_attribute *attr,
2051 const char *buf, size_t size)
2055 if (kstrtou64(buf, 0, &new) < 0)
2058 if (mca_cfg.cmci_disabled ^ !!new) {
2061 on_each_cpu(mce_disable_cmci, NULL, 1);
2062 mca_cfg.cmci_disabled = true;
2065 mca_cfg.cmci_disabled = false;
2066 on_each_cpu(mce_enable_ce, NULL, 1);
2072 static ssize_t store_int_with_restart(struct device *s,
2073 struct device_attribute *attr,
2074 const char *buf, size_t size)
2076 ssize_t ret = device_store_int(s, attr, buf, size);
2081 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2082 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2083 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2085 static struct dev_ext_attribute dev_attr_check_interval = {
2086 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2090 static struct dev_ext_attribute dev_attr_ignore_ce = {
2091 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2095 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2096 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2097 &mca_cfg.cmci_disabled
2100 static struct device_attribute *mce_device_attrs[] = {
2101 &dev_attr_tolerant.attr,
2102 &dev_attr_check_interval.attr,
2103 #ifdef CONFIG_X86_MCELOG_LEGACY
2106 &dev_attr_monarch_timeout.attr,
2107 &dev_attr_dont_log_ce.attr,
2108 &dev_attr_ignore_ce.attr,
2109 &dev_attr_cmci_disabled.attr,
2113 static cpumask_var_t mce_device_initialized;
2115 static void mce_device_release(struct device *dev)
2120 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2121 static int mce_device_create(unsigned int cpu)
2127 if (!mce_available(&boot_cpu_data))
2130 dev = per_cpu(mce_device, cpu);
2134 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2138 dev->bus = &mce_subsys;
2139 dev->release = &mce_device_release;
2141 err = device_register(dev);
2147 for (i = 0; mce_device_attrs[i]; i++) {
2148 err = device_create_file(dev, mce_device_attrs[i]);
2152 for (j = 0; j < mca_cfg.banks; j++) {
2153 err = device_create_file(dev, &mce_banks[j].attr);
2157 cpumask_set_cpu(cpu, mce_device_initialized);
2158 per_cpu(mce_device, cpu) = dev;
2163 device_remove_file(dev, &mce_banks[j].attr);
2166 device_remove_file(dev, mce_device_attrs[i]);
2168 device_unregister(dev);
2173 static void mce_device_remove(unsigned int cpu)
2175 struct device *dev = per_cpu(mce_device, cpu);
2178 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2181 for (i = 0; mce_device_attrs[i]; i++)
2182 device_remove_file(dev, mce_device_attrs[i]);
2184 for (i = 0; i < mca_cfg.banks; i++)
2185 device_remove_file(dev, &mce_banks[i].attr);
2187 device_unregister(dev);
2188 cpumask_clear_cpu(cpu, mce_device_initialized);
2189 per_cpu(mce_device, cpu) = NULL;
2192 /* Make sure there are no machine checks on offlined CPUs. */
2193 static void mce_disable_cpu(void)
2195 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2198 if (!cpuhp_tasks_frozen)
2201 vendor_disable_error_reporting();
2204 static void mce_reenable_cpu(void)
2208 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2211 if (!cpuhp_tasks_frozen)
2213 for (i = 0; i < mca_cfg.banks; i++) {
2214 struct mce_bank *b = &mce_banks[i];
2217 wrmsrl(msr_ops.ctl(i), b->ctl);
2221 static int mce_cpu_dead(unsigned int cpu)
2223 mce_intel_hcpu_update(cpu);
2225 /* intentionally ignoring frozen here */
2226 if (!cpuhp_tasks_frozen)
2231 static int mce_cpu_online(unsigned int cpu)
2233 struct timer_list *t = this_cpu_ptr(&mce_timer);
2236 mce_device_create(cpu);
2238 ret = mce_threshold_create_device(cpu);
2240 mce_device_remove(cpu);
2248 static int mce_cpu_pre_down(unsigned int cpu)
2250 struct timer_list *t = this_cpu_ptr(&mce_timer);
2254 mce_threshold_remove_device(cpu);
2255 mce_device_remove(cpu);
2259 static __init void mce_init_banks(void)
2263 for (i = 0; i < mca_cfg.banks; i++) {
2264 struct mce_bank *b = &mce_banks[i];
2265 struct device_attribute *a = &b->attr;
2267 sysfs_attr_init(&a->attr);
2268 a->attr.name = b->attrname;
2269 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2271 a->attr.mode = 0644;
2272 a->show = show_bank;
2273 a->store = set_bank;
2277 static __init int mcheck_init_device(void)
2281 if (!mce_available(&boot_cpu_data)) {
2286 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2293 err = subsys_system_register(&mce_subsys, NULL);
2297 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2302 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2303 mce_cpu_online, mce_cpu_pre_down);
2305 goto err_out_online;
2307 register_syscore_ops(&mce_syscore_ops);
2312 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2315 free_cpumask_var(mce_device_initialized);
2318 pr_err("Unable to init MCE device (rc: %d)\n", err);
2322 device_initcall_sync(mcheck_init_device);
2325 * Old style boot options parsing. Only for compatibility.
2327 static int __init mcheck_disable(char *str)
2329 mca_cfg.disabled = true;
2332 __setup("nomce", mcheck_disable);
2334 #ifdef CONFIG_DEBUG_FS
2335 struct dentry *mce_get_debugfs_dir(void)
2337 static struct dentry *dmce;
2340 dmce = debugfs_create_dir("mce", NULL);
2345 static void mce_reset(void)
2348 atomic_set(&mce_fake_panicked, 0);
2349 atomic_set(&mce_executing, 0);
2350 atomic_set(&mce_callin, 0);
2351 atomic_set(&global_nwo, 0);
2354 static int fake_panic_get(void *data, u64 *val)
2360 static int fake_panic_set(void *data, u64 val)
2367 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2368 fake_panic_set, "%llu\n");
2370 static int __init mcheck_debugfs_init(void)
2372 struct dentry *dmce, *ffake_panic;
2374 dmce = mce_get_debugfs_dir();
2377 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2385 static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2388 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2389 EXPORT_SYMBOL_GPL(mcsafe_key);
2391 static int __init mcheck_late_init(void)
2393 if (mca_cfg.recovery)
2394 static_branch_inc(&mcsafe_key);
2396 mcheck_debugfs_init();
2400 * Flush out everything that has been logged during early boot, now that
2401 * everything has been initialized (workqueues, decoders, ...).
2403 mce_schedule_work();
2407 late_initcall(mcheck_late_init);