2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
41 #include <asm/processor.h>
42 #include <asm/hw_irq.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
97 static DEFINE_PER_CPU(struct mce, mces_seen);
98 static int cpu_missing;
101 * CPU/chipset specific EDAC code can register a notifier call here to print
102 * MCE errors in a human-readable form.
104 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
105 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
107 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
110 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
111 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
116 static struct notifier_block mce_dec_nb = {
117 .notifier_call = default_decode_mce,
121 /* MCA banks polled by the period polling timer for corrected events */
122 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
123 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
126 static DEFINE_PER_CPU(struct work_struct, mce_work);
128 /* Do initial initialization of a struct mce */
129 void mce_setup(struct mce *m)
131 memset(m, 0, sizeof(struct mce));
132 m->cpu = m->extcpu = smp_processor_id();
134 /* We hope get_seconds stays lockless */
135 m->time = get_seconds();
136 m->cpuvendor = boot_cpu_data.x86_vendor;
137 m->cpuid = cpuid_eax(1);
139 m->socketid = cpu_data(m->extcpu).phys_proc_id;
141 m->apicid = cpu_data(m->extcpu).initial_apicid;
142 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
145 DEFINE_PER_CPU(struct mce, injectm);
146 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
149 * Lockless MCE logging infrastructure.
150 * This avoids deadlocks on printk locks without having to break locks. Also
151 * separate MCEs from kernel messages to avoid bogus bug reports.
154 static struct mce_log mcelog = {
155 .signature = MCE_LOG_SIGNATURE,
157 .recordlen = sizeof(struct mce),
160 void mce_log(struct mce *mce)
162 unsigned next, entry;
164 /* Emit the trace record: */
165 trace_mce_record(mce);
170 entry = rcu_dereference_check_mce(mcelog.next);
173 * If edac_mce is enabled, it will check the error type
174 * and will process it, if it is a known error.
175 * Otherwise, the error will be sent through mcelog
178 if (edac_mce_parse(mce))
182 * When the buffer fills up discard new entries.
183 * Assume that the earlier errors are the more
186 if (entry >= MCE_LOG_LEN) {
187 set_bit(MCE_OVERFLOW,
188 (unsigned long *)&mcelog.flags);
191 /* Old left over entry. Skip: */
192 if (mcelog.entry[entry].finished) {
200 if (cmpxchg(&mcelog.next, entry, next) == entry)
203 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
205 mcelog.entry[entry].finished = 1;
209 set_bit(0, &mce_need_notify);
212 static void print_mce(struct mce *m)
214 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
215 m->extcpu, m->mcgstatus, m->bank, m->status);
218 pr_emerg("RIP%s %02x:<%016Lx> ",
219 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
222 if (m->cs == __KERNEL_CS)
223 print_symbol("{%s}", m->ip);
227 pr_emerg("TSC %llx ", m->tsc);
229 pr_cont("ADDR %llx ", m->addr);
231 pr_cont("MISC %llx ", m->misc);
234 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
235 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
238 * Print out human-readable details about the MCE error,
239 * (if the CPU has an implementation for that)
241 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
244 static void print_mce_head(void)
246 pr_emerg("\nHARDWARE ERROR\n");
249 static void print_mce_tail(void)
251 pr_emerg("This is not a software problem!\n");
254 #define PANIC_TIMEOUT 5 /* 5 seconds */
256 static atomic_t mce_paniced;
258 static int fake_panic;
259 static atomic_t mce_fake_paniced;
261 /* Panic in progress. Enable interrupts and wait for final IPI */
262 static void wait_for_panic(void)
264 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
268 while (timeout-- > 0)
270 if (panic_timeout == 0)
271 panic_timeout = mce_panic_timeout;
272 panic("Panicing machine check CPU died");
275 static void mce_panic(char *msg, struct mce *final, char *exp)
281 * Make sure only one CPU runs in machine check panic
283 if (atomic_inc_return(&mce_paniced) > 1)
290 /* Don't log too much for fake panic */
291 if (atomic_inc_return(&mce_fake_paniced) > 1)
295 /* First print corrected ones that are still unlogged */
296 for (i = 0; i < MCE_LOG_LEN; i++) {
297 struct mce *m = &mcelog.entry[i];
298 if (!(m->status & MCI_STATUS_VAL))
300 if (!(m->status & MCI_STATUS_UC)) {
303 apei_err = apei_write_mce(m);
306 /* Now print uncorrected but with the final one last */
307 for (i = 0; i < MCE_LOG_LEN; i++) {
308 struct mce *m = &mcelog.entry[i];
309 if (!(m->status & MCI_STATUS_VAL))
311 if (!(m->status & MCI_STATUS_UC))
313 if (!final || memcmp(m, final, sizeof(struct mce))) {
316 apei_err = apei_write_mce(m);
322 apei_err = apei_write_mce(final);
325 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
328 printk(KERN_EMERG "Machine check: %s\n", exp);
330 if (panic_timeout == 0)
331 panic_timeout = mce_panic_timeout;
334 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
337 /* Support code for software error injection */
339 static int msr_to_offset(u32 msr)
341 unsigned bank = __get_cpu_var(injectm.bank);
344 return offsetof(struct mce, ip);
345 if (msr == MSR_IA32_MCx_STATUS(bank))
346 return offsetof(struct mce, status);
347 if (msr == MSR_IA32_MCx_ADDR(bank))
348 return offsetof(struct mce, addr);
349 if (msr == MSR_IA32_MCx_MISC(bank))
350 return offsetof(struct mce, misc);
351 if (msr == MSR_IA32_MCG_STATUS)
352 return offsetof(struct mce, mcgstatus);
356 /* MSR access wrappers used for error injection */
357 static u64 mce_rdmsrl(u32 msr)
361 if (__get_cpu_var(injectm).finished) {
362 int offset = msr_to_offset(msr);
366 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
369 if (rdmsrl_safe(msr, &v)) {
370 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
372 * Return zero in case the access faulted. This should
373 * not happen normally but can happen if the CPU does
374 * something weird, or if the code is buggy.
382 static void mce_wrmsrl(u32 msr, u64 v)
384 if (__get_cpu_var(injectm).finished) {
385 int offset = msr_to_offset(msr);
388 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
395 * Simple lockless ring to communicate PFNs from the exception handler with the
396 * process context work function. This is vastly simplified because there's
397 * only a single reader and a single writer.
399 #define MCE_RING_SIZE 16 /* we use one entry less */
402 unsigned short start;
404 unsigned long ring[MCE_RING_SIZE];
406 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
408 /* Runs with CPU affinity in workqueue */
409 static int mce_ring_empty(void)
411 struct mce_ring *r = &__get_cpu_var(mce_ring);
413 return r->start == r->end;
416 static int mce_ring_get(unsigned long *pfn)
423 r = &__get_cpu_var(mce_ring);
424 if (r->start == r->end)
426 *pfn = r->ring[r->start];
427 r->start = (r->start + 1) % MCE_RING_SIZE;
434 /* Always runs in MCE context with preempt off */
435 static int mce_ring_add(unsigned long pfn)
437 struct mce_ring *r = &__get_cpu_var(mce_ring);
440 next = (r->end + 1) % MCE_RING_SIZE;
441 if (next == r->start)
443 r->ring[r->end] = pfn;
449 int mce_available(struct cpuinfo_x86 *c)
453 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
456 static void mce_schedule_work(void)
458 if (!mce_ring_empty()) {
459 struct work_struct *work = &__get_cpu_var(mce_work);
460 if (!work_pending(work))
466 * Get the address of the instruction at the time of the machine check
469 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
472 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
480 m->ip = mce_rdmsrl(rip_msr);
483 #ifdef CONFIG_X86_LOCAL_APIC
485 * Called after interrupts have been reenabled again
486 * when a MCE happened during an interrupts off region
489 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
500 static void mce_report_event(struct pt_regs *regs)
502 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
505 * Triggering the work queue here is just an insurance
506 * policy in case the syscall exit notify handler
507 * doesn't run soon enough or ends up running on the
508 * wrong CPU (can happen when audit sleeps)
514 #ifdef CONFIG_X86_LOCAL_APIC
516 * Without APIC do not notify. The event will be picked
523 * When interrupts are disabled we cannot use
524 * kernel services safely. Trigger an self interrupt
525 * through the APIC to instead do the notification
526 * after interrupts are reenabled again.
528 apic->send_IPI_self(MCE_SELF_VECTOR);
531 * Wait for idle afterwards again so that we don't leave the
532 * APIC in a non idle state because the normal APIC writes
535 apic_wait_icr_idle();
539 DEFINE_PER_CPU(unsigned, mce_poll_count);
542 * Poll for corrected events or events that happened before reset.
543 * Those are just logged through /dev/mcelog.
545 * This is executed in standard interrupt context.
547 * Note: spec recommends to panic for fatal unsignalled
548 * errors here. However this would be quite problematic --
549 * we would need to reimplement the Monarch handling and
550 * it would mess up the exclusion between exception handler
551 * and poll hander -- * so we skip this for now.
552 * These cases should not happen anyways, or only when the CPU
553 * is already totally * confused. In this case it's likely it will
554 * not fully execute the machine check handler either.
556 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
561 percpu_inc(mce_poll_count);
565 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
566 for (i = 0; i < banks; i++) {
567 if (!mce_banks[i].ctl || !test_bit(i, *b))
576 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
577 if (!(m.status & MCI_STATUS_VAL))
581 * Uncorrected or signalled events are handled by the exception
582 * handler when it is enabled, so don't process those here.
584 * TBD do the same check for MCI_STATUS_EN here?
586 if (!(flags & MCP_UC) &&
587 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
590 if (m.status & MCI_STATUS_MISCV)
591 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
592 if (m.status & MCI_STATUS_ADDRV)
593 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
595 if (!(flags & MCP_TIMESTAMP))
598 * Don't get the IP here because it's unlikely to
599 * have anything to do with the actual error location.
601 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
603 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
604 add_taint(TAINT_MACHINE_CHECK);
608 * Clear state for this bank.
610 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
614 * Don't clear MCG_STATUS here because it's only defined for
620 EXPORT_SYMBOL_GPL(machine_check_poll);
623 * Do a quick check if any of the events requires a panic.
624 * This decides if we keep the events around or clear them.
626 static int mce_no_way_out(struct mce *m, char **msg)
630 for (i = 0; i < banks; i++) {
631 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
632 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
639 * Variable to establish order between CPUs while scanning.
640 * Each CPU spins initially until executing is equal its number.
642 static atomic_t mce_executing;
645 * Defines order of CPUs on entry. First CPU becomes Monarch.
647 static atomic_t mce_callin;
650 * Check if a timeout waiting for other CPUs happened.
652 static int mce_timed_out(u64 *t)
655 * The others already did panic for some reason.
656 * Bail out like in a timeout.
657 * rmb() to tell the compiler that system_state
658 * might have been modified by someone else.
661 if (atomic_read(&mce_paniced))
663 if (!monarch_timeout)
665 if ((s64)*t < SPINUNIT) {
666 /* CHECKME: Make panic default for 1 too? */
668 mce_panic("Timeout synchronizing machine check over CPUs",
675 touch_nmi_watchdog();
680 * The Monarch's reign. The Monarch is the CPU who entered
681 * the machine check handler first. It waits for the others to
682 * raise the exception too and then grades them. When any
683 * error is fatal panic. Only then let the others continue.
685 * The other CPUs entering the MCE handler will be controlled by the
686 * Monarch. They are called Subjects.
688 * This way we prevent any potential data corruption in a unrecoverable case
689 * and also makes sure always all CPU's errors are examined.
691 * Also this detects the case of a machine check event coming from outer
692 * space (not detected by any CPUs) In this case some external agent wants
693 * us to shut down, so panic too.
695 * The other CPUs might still decide to panic if the handler happens
696 * in a unrecoverable place, but in this case the system is in a semi-stable
697 * state and won't corrupt anything by itself. It's ok to let the others
698 * continue for a bit first.
700 * All the spin loops have timeouts; when a timeout happens a CPU
701 * typically elects itself to be Monarch.
703 static void mce_reign(void)
706 struct mce *m = NULL;
707 int global_worst = 0;
712 * This CPU is the Monarch and the other CPUs have run
713 * through their handlers.
714 * Grade the severity of the errors of all the CPUs.
716 for_each_possible_cpu(cpu) {
717 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
719 if (severity > global_worst) {
721 global_worst = severity;
722 m = &per_cpu(mces_seen, cpu);
727 * Cannot recover? Panic here then.
728 * This dumps all the mces in the log buffer and stops the
731 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
732 mce_panic("Fatal Machine check", m, msg);
735 * For UC somewhere we let the CPU who detects it handle it.
736 * Also must let continue the others, otherwise the handling
737 * CPU could deadlock on a lock.
741 * No machine check event found. Must be some external
742 * source or one CPU is hung. Panic.
744 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
745 mce_panic("Machine check from unknown source", NULL, NULL);
748 * Now clear all the mces_seen so that they don't reappear on
751 for_each_possible_cpu(cpu)
752 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
755 static atomic_t global_nwo;
758 * Start of Monarch synchronization. This waits until all CPUs have
759 * entered the exception handler and then determines if any of them
760 * saw a fatal event that requires panic. Then it executes them
761 * in the entry order.
762 * TBD double check parallel CPU hotunplug
764 static int mce_start(int *no_way_out)
767 int cpus = num_online_cpus();
768 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
773 atomic_add(*no_way_out, &global_nwo);
775 * global_nwo should be updated before mce_callin
778 order = atomic_inc_return(&mce_callin);
783 while (atomic_read(&mce_callin) != cpus) {
784 if (mce_timed_out(&timeout)) {
785 atomic_set(&global_nwo, 0);
792 * mce_callin should be read before global_nwo
798 * Monarch: Starts executing now, the others wait.
800 atomic_set(&mce_executing, 1);
803 * Subject: Now start the scanning loop one by one in
804 * the original callin order.
805 * This way when there are any shared banks it will be
806 * only seen by one CPU before cleared, avoiding duplicates.
808 while (atomic_read(&mce_executing) < order) {
809 if (mce_timed_out(&timeout)) {
810 atomic_set(&global_nwo, 0);
818 * Cache the global no_way_out state.
820 *no_way_out = atomic_read(&global_nwo);
826 * Synchronize between CPUs after main scanning loop.
827 * This invokes the bulk of the Monarch processing.
829 static int mce_end(int order)
832 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
840 * Allow others to run.
842 atomic_inc(&mce_executing);
845 /* CHECKME: Can this race with a parallel hotplug? */
846 int cpus = num_online_cpus();
849 * Monarch: Wait for everyone to go through their scanning
852 while (atomic_read(&mce_executing) <= cpus) {
853 if (mce_timed_out(&timeout))
863 * Subject: Wait for Monarch to finish.
865 while (atomic_read(&mce_executing) != 0) {
866 if (mce_timed_out(&timeout))
872 * Don't reset anything. That's done by the Monarch.
878 * Reset all global state.
881 atomic_set(&global_nwo, 0);
882 atomic_set(&mce_callin, 0);
886 * Let others run again.
888 atomic_set(&mce_executing, 0);
893 * Check if the address reported by the CPU is in a format we can parse.
894 * It would be possible to add code for most other cases, but all would
895 * be somewhat complicated (e.g. segment offset would require an instruction
896 * parser). So only support physical addresses upto page granuality for now.
898 static int mce_usable_address(struct mce *m)
900 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
902 if ((m->misc & 0x3f) > PAGE_SHIFT)
904 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
909 static void mce_clear_state(unsigned long *toclear)
913 for (i = 0; i < banks; i++) {
914 if (test_bit(i, toclear))
915 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
920 * The actual machine check handler. This only handles real
921 * exceptions when something got corrupted coming in through int 18.
923 * This is executed in NMI context not subject to normal locking rules. This
924 * implies that most kernel services cannot be safely used. Don't even
925 * think about putting a printk in there!
927 * On Intel systems this is entered on all CPUs in parallel through
928 * MCE broadcast. However some CPUs might be broken beyond repair,
929 * so be always careful when synchronizing with others.
931 void do_machine_check(struct pt_regs *regs, long error_code)
933 struct mce m, *final;
938 * Establish sequential order between the CPUs entering the machine
943 * If no_way_out gets set, there is no safe way to recover from this
944 * MCE. If tolerant is cranked up, we'll try anyway.
948 * If kill_it gets set, there might be a way to recover from this
952 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
953 char *msg = "Unknown";
955 atomic_inc(&mce_entry);
957 percpu_inc(mce_exception_count);
959 if (notify_die(DIE_NMI, "machine check", regs, error_code,
960 18, SIGKILL) == NOTIFY_STOP)
967 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
968 final = &__get_cpu_var(mces_seen);
971 no_way_out = mce_no_way_out(&m, &msg);
976 * When no restart IP must always kill or panic.
978 if (!(m.mcgstatus & MCG_STATUS_RIPV))
982 * Go through all the banks in exclusion of the other CPUs.
983 * This way we don't report duplicated events on shared banks
984 * because the first one to see it will clear it.
986 order = mce_start(&no_way_out);
987 for (i = 0; i < banks; i++) {
988 __clear_bit(i, toclear);
989 if (!mce_banks[i].ctl)
996 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
997 if ((m.status & MCI_STATUS_VAL) == 0)
1001 * Non uncorrected or non signaled errors are handled by
1002 * machine_check_poll. Leave them alone, unless this panics.
1004 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1009 * Set taint even when machine check was not enabled.
1011 add_taint(TAINT_MACHINE_CHECK);
1013 severity = mce_severity(&m, tolerant, NULL);
1016 * When machine check was for corrected handler don't touch,
1017 * unless we're panicing.
1019 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1021 __set_bit(i, toclear);
1022 if (severity == MCE_NO_SEVERITY) {
1024 * Machine check event was not enabled. Clear, but
1031 * Kill on action required.
1033 if (severity == MCE_AR_SEVERITY)
1036 if (m.status & MCI_STATUS_MISCV)
1037 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1038 if (m.status & MCI_STATUS_ADDRV)
1039 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1042 * Action optional error. Queue address for later processing.
1043 * When the ring overflows we just ignore the AO error.
1044 * RED-PEN add some logging mechanism when
1045 * usable_address or mce_add_ring fails.
1046 * RED-PEN don't ignore overflow for tolerant == 0
1048 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1049 mce_ring_add(m.addr >> PAGE_SHIFT);
1051 mce_get_rip(&m, regs);
1054 if (severity > worst) {
1061 mce_clear_state(toclear);
1064 * Do most of the synchronization with other CPUs.
1065 * When there's any problem use only local no_way_out state.
1067 if (mce_end(order) < 0)
1068 no_way_out = worst >= MCE_PANIC_SEVERITY;
1071 * If we have decided that we just CAN'T continue, and the user
1072 * has not set tolerant to an insane level, give up and die.
1074 * This is mainly used in the case when the system doesn't
1075 * support MCE broadcasting or it has been disabled.
1077 if (no_way_out && tolerant < 3)
1078 mce_panic("Fatal machine check on current CPU", final, msg);
1081 * If the error seems to be unrecoverable, something should be
1082 * done. Try to kill as little as possible. If we can kill just
1083 * one task, do that. If the user has set the tolerance very
1084 * high, don't try to do anything at all.
1087 if (kill_it && tolerant < 3)
1088 force_sig(SIGBUS, current);
1090 /* notify userspace ASAP */
1091 set_thread_flag(TIF_MCE_NOTIFY);
1094 mce_report_event(regs);
1095 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1097 atomic_dec(&mce_entry);
1100 EXPORT_SYMBOL_GPL(do_machine_check);
1102 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1103 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1105 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1109 * Called after mce notification in process context. This code
1110 * is allowed to sleep. Call the high level VM handler to process
1111 * any corrupted pages.
1112 * Assume that the work queue code only calls this one at a time
1114 * Note we don't disable preemption, so this code might run on the wrong
1115 * CPU. In this case the event is picked up by the scheduled work queue.
1116 * This is merely a fast path to expedite processing in some common
1119 void mce_notify_process(void)
1123 while (mce_ring_get(&pfn))
1124 memory_failure(pfn, MCE_VECTOR);
1127 static void mce_process_work(struct work_struct *dummy)
1129 mce_notify_process();
1132 #ifdef CONFIG_X86_MCE_INTEL
1134 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1135 * @cpu: The CPU on which the event occurred.
1136 * @status: Event status information
1138 * This function should be called by the thermal interrupt after the
1139 * event has been processed and the decision was made to log the event
1142 * The status parameter will be saved to the 'status' field of 'struct mce'
1143 * and historically has been the register value of the
1144 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1146 void mce_log_therm_throt_event(__u64 status)
1151 m.bank = MCE_THERMAL_BANK;
1155 #endif /* CONFIG_X86_MCE_INTEL */
1158 * Periodic polling timer for "silent" machine check errors. If the
1159 * poller finds an MCE, poll 2x faster. When the poller finds no more
1160 * errors, poll 2x slower (up to check_interval seconds).
1162 static int check_interval = 5 * 60; /* 5 minutes */
1164 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1165 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1167 static void mce_start_timer(unsigned long data)
1169 struct timer_list *t = &per_cpu(mce_timer, data);
1172 WARN_ON(smp_processor_id() != data);
1174 if (mce_available(¤t_cpu_data)) {
1175 machine_check_poll(MCP_TIMESTAMP,
1176 &__get_cpu_var(mce_poll_banks));
1180 * Alert userspace if needed. If we logged an MCE, reduce the
1181 * polling interval, otherwise increase the polling interval.
1183 n = &__get_cpu_var(mce_next_interval);
1184 if (mce_notify_irq())
1185 *n = max(*n/2, HZ/100);
1187 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1189 t->expires = jiffies + *n;
1190 add_timer_on(t, smp_processor_id());
1193 static void mce_do_trigger(struct work_struct *work)
1195 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1198 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1201 * Notify the user(s) about new machine check events.
1202 * Can be called from interrupt context, but not from machine check/NMI
1205 int mce_notify_irq(void)
1207 /* Not more than two messages every minute */
1208 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1210 clear_thread_flag(TIF_MCE_NOTIFY);
1212 if (test_and_clear_bit(0, &mce_need_notify)) {
1213 wake_up_interruptible(&mce_wait);
1216 * There is no risk of missing notifications because
1217 * work_pending is always cleared before the function is
1220 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1221 schedule_work(&mce_trigger_work);
1223 if (__ratelimit(&ratelimit))
1224 printk(KERN_INFO "Machine check events logged\n");
1230 EXPORT_SYMBOL_GPL(mce_notify_irq);
1232 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1236 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1239 for (i = 0; i < banks; i++) {
1240 struct mce_bank *b = &mce_banks[i];
1249 * Initialize Machine Checks for a CPU.
1251 static int __cpuinit __mcheck_cpu_cap_init(void)
1256 rdmsrl(MSR_IA32_MCG_CAP, cap);
1258 b = cap & MCG_BANKCNT_MASK;
1260 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1262 if (b > MAX_NR_BANKS) {
1264 "MCE: Using only %u machine check banks out of %u\n",
1269 /* Don't support asymmetric configurations today */
1270 WARN_ON(banks != 0 && b != banks);
1273 int err = __mcheck_cpu_mce_banks_init();
1279 /* Use accurate RIP reporting if available. */
1280 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1281 rip_msr = MSR_IA32_MCG_EIP;
1283 if (cap & MCG_SER_P)
1289 static void __mcheck_cpu_init_generic(void)
1291 mce_banks_t all_banks;
1296 * Log the machine checks left over from the previous reset.
1298 bitmap_fill(all_banks, MAX_NR_BANKS);
1299 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1301 set_in_cr4(X86_CR4_MCE);
1303 rdmsrl(MSR_IA32_MCG_CAP, cap);
1304 if (cap & MCG_CTL_P)
1305 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1307 for (i = 0; i < banks; i++) {
1308 struct mce_bank *b = &mce_banks[i];
1312 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1313 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1317 /* Add per CPU specific workarounds here */
1318 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1320 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1321 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1325 /* This should be disabled by the BIOS, but isn't always */
1326 if (c->x86_vendor == X86_VENDOR_AMD) {
1327 if (c->x86 == 15 && banks > 4) {
1329 * disable GART TBL walk error reporting, which
1330 * trips off incorrectly with the IOMMU & 3ware
1333 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1335 if (c->x86 <= 17 && mce_bootlog < 0) {
1337 * Lots of broken BIOS around that don't clear them
1338 * by default and leave crap in there. Don't log:
1343 * Various K7s with broken bank 0 around. Always disable
1346 if (c->x86 == 6 && banks > 0)
1347 mce_banks[0].ctl = 0;
1350 if (c->x86_vendor == X86_VENDOR_INTEL) {
1352 * SDM documents that on family 6 bank 0 should not be written
1353 * because it aliases to another special BIOS controlled
1355 * But it's not aliased anymore on model 0x1a+
1356 * Don't ignore bank 0 completely because there could be a
1357 * valid event later, merely don't write CTL0.
1360 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1361 mce_banks[0].init = 0;
1364 * All newer Intel systems support MCE broadcasting. Enable
1365 * synchronization with a one second timeout.
1367 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1368 monarch_timeout < 0)
1369 monarch_timeout = USEC_PER_SEC;
1372 * There are also broken BIOSes on some Pentium M and
1375 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1378 if (monarch_timeout < 0)
1379 monarch_timeout = 0;
1380 if (mce_bootlog != 0)
1381 mce_panic_timeout = 30;
1386 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1390 switch (c->x86_vendor) {
1391 case X86_VENDOR_INTEL:
1392 intel_p5_mcheck_init(c);
1394 case X86_VENDOR_CENTAUR:
1395 winchip_mcheck_init(c);
1400 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1402 switch (c->x86_vendor) {
1403 case X86_VENDOR_INTEL:
1404 mce_intel_feature_init(c);
1406 case X86_VENDOR_AMD:
1407 mce_amd_feature_init(c);
1414 static void __mcheck_cpu_init_timer(void)
1416 struct timer_list *t = &__get_cpu_var(mce_timer);
1417 int *n = &__get_cpu_var(mce_next_interval);
1419 setup_timer(t, mce_start_timer, smp_processor_id());
1424 *n = check_interval * HZ;
1427 t->expires = round_jiffies(jiffies + *n);
1428 add_timer_on(t, smp_processor_id());
1431 /* Handle unconfigured int18 (should never happen) */
1432 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1434 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1435 smp_processor_id());
1438 /* Call the installed machine check handler for this CPU setup. */
1439 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1440 unexpected_machine_check;
1443 * Called for each booted CPU to set up machine checks.
1444 * Must be called with preempt off:
1446 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1451 __mcheck_cpu_ancient_init(c);
1453 if (!mce_available(c))
1456 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1461 machine_check_vector = do_machine_check;
1463 __mcheck_cpu_init_generic();
1464 __mcheck_cpu_init_vendor(c);
1465 __mcheck_cpu_init_timer();
1466 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1471 * Character device to read and clear the MCE log.
1474 static DEFINE_SPINLOCK(mce_state_lock);
1475 static int open_count; /* #times opened */
1476 static int open_exclu; /* already open exclusive? */
1478 static int mce_open(struct inode *inode, struct file *file)
1480 spin_lock(&mce_state_lock);
1482 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1483 spin_unlock(&mce_state_lock);
1488 if (file->f_flags & O_EXCL)
1492 spin_unlock(&mce_state_lock);
1494 return nonseekable_open(inode, file);
1497 static int mce_release(struct inode *inode, struct file *file)
1499 spin_lock(&mce_state_lock);
1504 spin_unlock(&mce_state_lock);
1509 static void collect_tscs(void *data)
1511 unsigned long *cpu_tsc = (unsigned long *)data;
1513 rdtscll(cpu_tsc[smp_processor_id()]);
1516 static int mce_apei_read_done;
1518 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1519 static int __mce_read_apei(char __user **ubuf, size_t usize)
1525 if (usize < sizeof(struct mce))
1528 rc = apei_read_mce(&m, &record_id);
1529 /* Error or no more MCE record */
1531 mce_apei_read_done = 1;
1535 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1538 * In fact, we should have cleared the record after that has
1539 * been flushed to the disk or sent to network in
1540 * /sbin/mcelog, but we have no interface to support that now,
1541 * so just clear it to avoid duplication.
1543 rc = apei_clear_mce(record_id);
1545 mce_apei_read_done = 1;
1548 *ubuf += sizeof(struct mce);
1553 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1556 char __user *buf = ubuf;
1557 unsigned long *cpu_tsc;
1558 unsigned prev, next;
1561 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1565 mutex_lock(&mce_read_mutex);
1567 if (!mce_apei_read_done) {
1568 err = __mce_read_apei(&buf, usize);
1569 if (err || buf != ubuf)
1573 next = rcu_dereference_check_mce(mcelog.next);
1575 /* Only supports full reads right now */
1577 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1583 for (i = prev; i < next; i++) {
1584 unsigned long start = jiffies;
1586 while (!mcelog.entry[i].finished) {
1587 if (time_after_eq(jiffies, start + 2)) {
1588 memset(mcelog.entry + i, 0,
1589 sizeof(struct mce));
1595 err |= copy_to_user(buf, mcelog.entry + i,
1596 sizeof(struct mce));
1597 buf += sizeof(struct mce);
1602 memset(mcelog.entry + prev, 0,
1603 (next - prev) * sizeof(struct mce));
1605 next = cmpxchg(&mcelog.next, prev, 0);
1606 } while (next != prev);
1608 synchronize_sched();
1611 * Collect entries that were still getting written before the
1614 on_each_cpu(collect_tscs, cpu_tsc, 1);
1616 for (i = next; i < MCE_LOG_LEN; i++) {
1617 if (mcelog.entry[i].finished &&
1618 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1619 err |= copy_to_user(buf, mcelog.entry+i,
1620 sizeof(struct mce));
1622 buf += sizeof(struct mce);
1623 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1631 mutex_unlock(&mce_read_mutex);
1634 return err ? err : buf - ubuf;
1637 static unsigned int mce_poll(struct file *file, poll_table *wait)
1639 poll_wait(file, &mce_wait, wait);
1640 if (rcu_dereference_check_mce(mcelog.next))
1641 return POLLIN | POLLRDNORM;
1642 if (!mce_apei_read_done && apei_check_mce())
1643 return POLLIN | POLLRDNORM;
1647 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1649 int __user *p = (int __user *)arg;
1651 if (!capable(CAP_SYS_ADMIN))
1655 case MCE_GET_RECORD_LEN:
1656 return put_user(sizeof(struct mce), p);
1657 case MCE_GET_LOG_LEN:
1658 return put_user(MCE_LOG_LEN, p);
1659 case MCE_GETCLEAR_FLAGS: {
1663 flags = mcelog.flags;
1664 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1666 return put_user(flags, p);
1673 /* Modified in mce-inject.c, so not static or const */
1674 struct file_operations mce_chrdev_ops = {
1676 .release = mce_release,
1679 .unlocked_ioctl = mce_ioctl,
1681 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1683 static struct miscdevice mce_log_device = {
1690 * mce=off Disables machine check
1691 * mce=no_cmci Disables CMCI
1692 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1693 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1694 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1695 * monarchtimeout is how long to wait for other CPUs on machine
1696 * check, or 0 to not wait
1697 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1698 * mce=nobootlog Don't log MCEs from before booting.
1700 static int __init mcheck_enable(char *str)
1708 if (!strcmp(str, "off"))
1710 else if (!strcmp(str, "no_cmci"))
1711 mce_cmci_disabled = 1;
1712 else if (!strcmp(str, "dont_log_ce"))
1713 mce_dont_log_ce = 1;
1714 else if (!strcmp(str, "ignore_ce"))
1716 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1717 mce_bootlog = (str[0] == 'b');
1718 else if (isdigit(str[0])) {
1719 get_option(&str, &tolerant);
1722 get_option(&str, &monarch_timeout);
1725 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1731 __setup("mce", mcheck_enable);
1733 int __init mcheck_init(void)
1735 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1737 mcheck_intel_therm_init();
1747 * Disable machine checks on suspend and shutdown. We can't really handle
1750 static int mce_disable_error_reporting(void)
1754 for (i = 0; i < banks; i++) {
1755 struct mce_bank *b = &mce_banks[i];
1758 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1763 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1765 return mce_disable_error_reporting();
1768 static int mce_shutdown(struct sys_device *dev)
1770 return mce_disable_error_reporting();
1774 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1775 * Only one CPU is active at this time, the others get re-added later using
1778 static int mce_resume(struct sys_device *dev)
1780 __mcheck_cpu_init_generic();
1781 __mcheck_cpu_init_vendor(¤t_cpu_data);
1786 static void mce_cpu_restart(void *data)
1788 del_timer_sync(&__get_cpu_var(mce_timer));
1789 if (!mce_available(¤t_cpu_data))
1791 __mcheck_cpu_init_generic();
1792 __mcheck_cpu_init_timer();
1795 /* Reinit MCEs after user configuration changes */
1796 static void mce_restart(void)
1798 on_each_cpu(mce_cpu_restart, NULL, 1);
1801 /* Toggle features for corrected errors */
1802 static void mce_disable_ce(void *all)
1804 if (!mce_available(¤t_cpu_data))
1807 del_timer_sync(&__get_cpu_var(mce_timer));
1811 static void mce_enable_ce(void *all)
1813 if (!mce_available(¤t_cpu_data))
1818 __mcheck_cpu_init_timer();
1821 static struct sysdev_class mce_sysclass = {
1822 .suspend = mce_suspend,
1823 .shutdown = mce_shutdown,
1824 .resume = mce_resume,
1825 .name = "machinecheck",
1828 DEFINE_PER_CPU(struct sys_device, mce_dev);
1831 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1833 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1835 return container_of(attr, struct mce_bank, attr);
1838 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1841 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1844 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1845 const char *buf, size_t size)
1849 if (strict_strtoull(buf, 0, &new) < 0)
1852 attr_to_bank(attr)->ctl = new;
1859 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1861 strcpy(buf, mce_helper);
1863 return strlen(mce_helper) + 1;
1866 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1867 const char *buf, size_t siz)
1871 strncpy(mce_helper, buf, sizeof(mce_helper));
1872 mce_helper[sizeof(mce_helper)-1] = 0;
1873 p = strchr(mce_helper, '\n');
1878 return strlen(mce_helper) + !!p;
1881 static ssize_t set_ignore_ce(struct sys_device *s,
1882 struct sysdev_attribute *attr,
1883 const char *buf, size_t size)
1887 if (strict_strtoull(buf, 0, &new) < 0)
1890 if (mce_ignore_ce ^ !!new) {
1892 /* disable ce features */
1893 on_each_cpu(mce_disable_ce, (void *)1, 1);
1896 /* enable ce features */
1898 on_each_cpu(mce_enable_ce, (void *)1, 1);
1904 static ssize_t set_cmci_disabled(struct sys_device *s,
1905 struct sysdev_attribute *attr,
1906 const char *buf, size_t size)
1910 if (strict_strtoull(buf, 0, &new) < 0)
1913 if (mce_cmci_disabled ^ !!new) {
1916 on_each_cpu(mce_disable_ce, NULL, 1);
1917 mce_cmci_disabled = 1;
1920 mce_cmci_disabled = 0;
1921 on_each_cpu(mce_enable_ce, NULL, 1);
1927 static ssize_t store_int_with_restart(struct sys_device *s,
1928 struct sysdev_attribute *attr,
1929 const char *buf, size_t size)
1931 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1936 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1937 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1938 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1939 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1941 static struct sysdev_ext_attribute attr_check_interval = {
1942 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1943 store_int_with_restart),
1947 static struct sysdev_ext_attribute attr_ignore_ce = {
1948 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1952 static struct sysdev_ext_attribute attr_cmci_disabled = {
1953 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1957 static struct sysdev_attribute *mce_attrs[] = {
1958 &attr_tolerant.attr,
1959 &attr_check_interval.attr,
1961 &attr_monarch_timeout.attr,
1962 &attr_dont_log_ce.attr,
1963 &attr_ignore_ce.attr,
1964 &attr_cmci_disabled.attr,
1968 static cpumask_var_t mce_dev_initialized;
1970 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1971 static __cpuinit int mce_create_device(unsigned int cpu)
1976 if (!mce_available(&boot_cpu_data))
1979 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1980 per_cpu(mce_dev, cpu).id = cpu;
1981 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1983 err = sysdev_register(&per_cpu(mce_dev, cpu));
1987 for (i = 0; mce_attrs[i]; i++) {
1988 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1992 for (j = 0; j < banks; j++) {
1993 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1994 &mce_banks[j].attr);
1998 cpumask_set_cpu(cpu, mce_dev_initialized);
2003 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
2006 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2008 sysdev_unregister(&per_cpu(mce_dev, cpu));
2013 static __cpuinit void mce_remove_device(unsigned int cpu)
2017 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
2020 for (i = 0; mce_attrs[i]; i++)
2021 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2023 for (i = 0; i < banks; i++)
2024 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2026 sysdev_unregister(&per_cpu(mce_dev, cpu));
2027 cpumask_clear_cpu(cpu, mce_dev_initialized);
2030 /* Make sure there are no machine checks on offlined CPUs. */
2031 static void __cpuinit mce_disable_cpu(void *h)
2033 unsigned long action = *(unsigned long *)h;
2036 if (!mce_available(¤t_cpu_data))
2039 if (!(action & CPU_TASKS_FROZEN))
2041 for (i = 0; i < banks; i++) {
2042 struct mce_bank *b = &mce_banks[i];
2045 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2049 static void __cpuinit mce_reenable_cpu(void *h)
2051 unsigned long action = *(unsigned long *)h;
2054 if (!mce_available(¤t_cpu_data))
2057 if (!(action & CPU_TASKS_FROZEN))
2059 for (i = 0; i < banks; i++) {
2060 struct mce_bank *b = &mce_banks[i];
2063 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2067 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2068 static int __cpuinit
2069 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2071 unsigned int cpu = (unsigned long)hcpu;
2072 struct timer_list *t = &per_cpu(mce_timer, cpu);
2076 case CPU_ONLINE_FROZEN:
2077 mce_create_device(cpu);
2078 if (threshold_cpu_callback)
2079 threshold_cpu_callback(action, cpu);
2082 case CPU_DEAD_FROZEN:
2083 if (threshold_cpu_callback)
2084 threshold_cpu_callback(action, cpu);
2085 mce_remove_device(cpu);
2087 case CPU_DOWN_PREPARE:
2088 case CPU_DOWN_PREPARE_FROZEN:
2090 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2092 case CPU_DOWN_FAILED:
2093 case CPU_DOWN_FAILED_FROZEN:
2094 if (!mce_ignore_ce && check_interval) {
2095 t->expires = round_jiffies(jiffies +
2096 __get_cpu_var(mce_next_interval));
2097 add_timer_on(t, cpu);
2099 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2102 /* intentionally ignoring frozen here */
2103 cmci_rediscover(cpu);
2109 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2110 .notifier_call = mce_cpu_callback,
2113 static __init void mce_init_banks(void)
2117 for (i = 0; i < banks; i++) {
2118 struct mce_bank *b = &mce_banks[i];
2119 struct sysdev_attribute *a = &b->attr;
2121 sysfs_attr_init(&a->attr);
2122 a->attr.name = b->attrname;
2123 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2125 a->attr.mode = 0644;
2126 a->show = show_bank;
2127 a->store = set_bank;
2131 static __init int mcheck_init_device(void)
2136 if (!mce_available(&boot_cpu_data))
2139 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2143 err = sysdev_class_register(&mce_sysclass);
2147 for_each_online_cpu(i) {
2148 err = mce_create_device(i);
2153 register_hotcpu_notifier(&mce_cpu_notifier);
2154 misc_register(&mce_log_device);
2159 device_initcall(mcheck_init_device);
2162 * Old style boot options parsing. Only for compatibility.
2164 static int __init mcheck_disable(char *str)
2169 __setup("nomce", mcheck_disable);
2171 #ifdef CONFIG_DEBUG_FS
2172 struct dentry *mce_get_debugfs_dir(void)
2174 static struct dentry *dmce;
2177 dmce = debugfs_create_dir("mce", NULL);
2182 static void mce_reset(void)
2185 atomic_set(&mce_fake_paniced, 0);
2186 atomic_set(&mce_executing, 0);
2187 atomic_set(&mce_callin, 0);
2188 atomic_set(&global_nwo, 0);
2191 static int fake_panic_get(void *data, u64 *val)
2197 static int fake_panic_set(void *data, u64 val)
2204 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2205 fake_panic_set, "%llu\n");
2207 static int __init mcheck_debugfs_init(void)
2209 struct dentry *dmce, *ffake_panic;
2211 dmce = mce_get_debugfs_dir();
2214 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2221 late_initcall(mcheck_debugfs_init);