2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
40 #include <asm/processor.h>
41 #include <asm/hw_irq.h>
48 #include "mce-internal.h"
50 static DEFINE_MUTEX(mce_read_mutex);
52 #define rcu_dereference_check_mce(p) \
53 rcu_dereference_check((p), \
54 rcu_read_lock_sched_held() || \
55 lockdep_is_held(&mce_read_mutex))
57 #define CREATE_TRACE_POINTS
58 #include <trace/events/mce.h>
60 int mce_disabled __read_mostly;
62 #define MISC_MCELOG_MINOR 227
64 #define SPINUNIT 100 /* 100ns */
68 DEFINE_PER_CPU(unsigned, mce_exception_count);
72 * 0: always panic on uncorrected errors, log corrected errors
73 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
74 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
75 * 3: never panic or SIGBUS, log all errors (for testing only)
77 static int tolerant __read_mostly = 1;
78 static int banks __read_mostly;
79 static int rip_msr __read_mostly;
80 static int mce_bootlog __read_mostly = -1;
81 static int monarch_timeout __read_mostly = -1;
82 static int mce_panic_timeout __read_mostly;
83 static int mce_dont_log_ce __read_mostly;
84 int mce_cmci_disabled __read_mostly;
85 int mce_ignore_ce __read_mostly;
86 int mce_ser __read_mostly;
88 struct mce_bank *mce_banks __read_mostly;
90 /* User mode helper program triggered by machine check event */
91 static unsigned long mce_need_notify;
92 static char mce_helper[128];
93 static char *mce_helper_argv[2] = { mce_helper, NULL };
95 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
96 static DEFINE_PER_CPU(struct mce, mces_seen);
97 static int cpu_missing;
100 * CPU/chipset specific EDAC code can register a notifier call here to print
101 * MCE errors in a human-readable form.
103 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
104 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
106 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
109 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
110 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
115 static struct notifier_block mce_dec_nb = {
116 .notifier_call = default_decode_mce,
120 /* MCA banks polled by the period polling timer for corrected events */
121 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
122 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
125 static DEFINE_PER_CPU(struct work_struct, mce_work);
127 /* Do initial initialization of a struct mce */
128 void mce_setup(struct mce *m)
130 memset(m, 0, sizeof(struct mce));
131 m->cpu = m->extcpu = smp_processor_id();
133 /* We hope get_seconds stays lockless */
134 m->time = get_seconds();
135 m->cpuvendor = boot_cpu_data.x86_vendor;
136 m->cpuid = cpuid_eax(1);
138 m->socketid = cpu_data(m->extcpu).phys_proc_id;
140 m->apicid = cpu_data(m->extcpu).initial_apicid;
141 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
144 DEFINE_PER_CPU(struct mce, injectm);
145 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
148 * Lockless MCE logging infrastructure.
149 * This avoids deadlocks on printk locks without having to break locks. Also
150 * separate MCEs from kernel messages to avoid bogus bug reports.
153 static struct mce_log mcelog = {
154 .signature = MCE_LOG_SIGNATURE,
156 .recordlen = sizeof(struct mce),
159 void mce_log(struct mce *mce)
161 unsigned next, entry;
163 /* Emit the trace record: */
164 trace_mce_record(mce);
169 entry = rcu_dereference_check_mce(mcelog.next);
172 * When the buffer fills up discard new entries.
173 * Assume that the earlier errors are the more
176 if (entry >= MCE_LOG_LEN) {
177 set_bit(MCE_OVERFLOW,
178 (unsigned long *)&mcelog.flags);
181 /* Old left over entry. Skip: */
182 if (mcelog.entry[entry].finished) {
190 if (cmpxchg(&mcelog.next, entry, next) == entry)
193 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
195 mcelog.entry[entry].finished = 1;
199 set_bit(0, &mce_need_notify);
202 static void print_mce(struct mce *m)
204 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
205 m->extcpu, m->mcgstatus, m->bank, m->status);
208 pr_emerg("RIP%s %02x:<%016Lx> ",
209 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
212 if (m->cs == __KERNEL_CS)
213 print_symbol("{%s}", m->ip);
217 pr_emerg("TSC %llx ", m->tsc);
219 pr_cont("ADDR %llx ", m->addr);
221 pr_cont("MISC %llx ", m->misc);
224 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
225 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
228 * Print out human-readable details about the MCE error,
229 * (if the CPU has an implementation for that)
231 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
234 static void print_mce_head(void)
236 pr_emerg("\nHARDWARE ERROR\n");
239 static void print_mce_tail(void)
241 pr_emerg("This is not a software problem!\n");
244 #define PANIC_TIMEOUT 5 /* 5 seconds */
246 static atomic_t mce_paniced;
248 static int fake_panic;
249 static atomic_t mce_fake_paniced;
251 /* Panic in progress. Enable interrupts and wait for final IPI */
252 static void wait_for_panic(void)
254 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
258 while (timeout-- > 0)
260 if (panic_timeout == 0)
261 panic_timeout = mce_panic_timeout;
262 panic("Panicing machine check CPU died");
265 static void mce_panic(char *msg, struct mce *final, char *exp)
271 * Make sure only one CPU runs in machine check panic
273 if (atomic_inc_return(&mce_paniced) > 1)
280 /* Don't log too much for fake panic */
281 if (atomic_inc_return(&mce_fake_paniced) > 1)
285 /* First print corrected ones that are still unlogged */
286 for (i = 0; i < MCE_LOG_LEN; i++) {
287 struct mce *m = &mcelog.entry[i];
288 if (!(m->status & MCI_STATUS_VAL))
290 if (!(m->status & MCI_STATUS_UC))
293 /* Now print uncorrected but with the final one last */
294 for (i = 0; i < MCE_LOG_LEN; i++) {
295 struct mce *m = &mcelog.entry[i];
296 if (!(m->status & MCI_STATUS_VAL))
298 if (!(m->status & MCI_STATUS_UC))
300 if (!final || memcmp(m, final, sizeof(struct mce)))
306 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
309 printk(KERN_EMERG "Machine check: %s\n", exp);
311 if (panic_timeout == 0)
312 panic_timeout = mce_panic_timeout;
315 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
318 /* Support code for software error injection */
320 static int msr_to_offset(u32 msr)
322 unsigned bank = __get_cpu_var(injectm.bank);
325 return offsetof(struct mce, ip);
326 if (msr == MSR_IA32_MCx_STATUS(bank))
327 return offsetof(struct mce, status);
328 if (msr == MSR_IA32_MCx_ADDR(bank))
329 return offsetof(struct mce, addr);
330 if (msr == MSR_IA32_MCx_MISC(bank))
331 return offsetof(struct mce, misc);
332 if (msr == MSR_IA32_MCG_STATUS)
333 return offsetof(struct mce, mcgstatus);
337 /* MSR access wrappers used for error injection */
338 static u64 mce_rdmsrl(u32 msr)
342 if (__get_cpu_var(injectm).finished) {
343 int offset = msr_to_offset(msr);
347 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
350 if (rdmsrl_safe(msr, &v)) {
351 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
353 * Return zero in case the access faulted. This should
354 * not happen normally but can happen if the CPU does
355 * something weird, or if the code is buggy.
363 static void mce_wrmsrl(u32 msr, u64 v)
365 if (__get_cpu_var(injectm).finished) {
366 int offset = msr_to_offset(msr);
369 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
376 * Simple lockless ring to communicate PFNs from the exception handler with the
377 * process context work function. This is vastly simplified because there's
378 * only a single reader and a single writer.
380 #define MCE_RING_SIZE 16 /* we use one entry less */
383 unsigned short start;
385 unsigned long ring[MCE_RING_SIZE];
387 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
389 /* Runs with CPU affinity in workqueue */
390 static int mce_ring_empty(void)
392 struct mce_ring *r = &__get_cpu_var(mce_ring);
394 return r->start == r->end;
397 static int mce_ring_get(unsigned long *pfn)
404 r = &__get_cpu_var(mce_ring);
405 if (r->start == r->end)
407 *pfn = r->ring[r->start];
408 r->start = (r->start + 1) % MCE_RING_SIZE;
415 /* Always runs in MCE context with preempt off */
416 static int mce_ring_add(unsigned long pfn)
418 struct mce_ring *r = &__get_cpu_var(mce_ring);
421 next = (r->end + 1) % MCE_RING_SIZE;
422 if (next == r->start)
424 r->ring[r->end] = pfn;
430 int mce_available(struct cpuinfo_x86 *c)
434 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
437 static void mce_schedule_work(void)
439 if (!mce_ring_empty()) {
440 struct work_struct *work = &__get_cpu_var(mce_work);
441 if (!work_pending(work))
447 * Get the address of the instruction at the time of the machine check
450 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
453 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
461 m->ip = mce_rdmsrl(rip_msr);
464 #ifdef CONFIG_X86_LOCAL_APIC
466 * Called after interrupts have been reenabled again
467 * when a MCE happened during an interrupts off region
470 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
481 static void mce_report_event(struct pt_regs *regs)
483 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
486 * Triggering the work queue here is just an insurance
487 * policy in case the syscall exit notify handler
488 * doesn't run soon enough or ends up running on the
489 * wrong CPU (can happen when audit sleeps)
495 #ifdef CONFIG_X86_LOCAL_APIC
497 * Without APIC do not notify. The event will be picked
504 * When interrupts are disabled we cannot use
505 * kernel services safely. Trigger an self interrupt
506 * through the APIC to instead do the notification
507 * after interrupts are reenabled again.
509 apic->send_IPI_self(MCE_SELF_VECTOR);
512 * Wait for idle afterwards again so that we don't leave the
513 * APIC in a non idle state because the normal APIC writes
516 apic_wait_icr_idle();
520 DEFINE_PER_CPU(unsigned, mce_poll_count);
523 * Poll for corrected events or events that happened before reset.
524 * Those are just logged through /dev/mcelog.
526 * This is executed in standard interrupt context.
528 * Note: spec recommends to panic for fatal unsignalled
529 * errors here. However this would be quite problematic --
530 * we would need to reimplement the Monarch handling and
531 * it would mess up the exclusion between exception handler
532 * and poll hander -- * so we skip this for now.
533 * These cases should not happen anyways, or only when the CPU
534 * is already totally * confused. In this case it's likely it will
535 * not fully execute the machine check handler either.
537 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
542 percpu_inc(mce_poll_count);
546 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
547 for (i = 0; i < banks; i++) {
548 if (!mce_banks[i].ctl || !test_bit(i, *b))
557 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
558 if (!(m.status & MCI_STATUS_VAL))
562 * Uncorrected or signalled events are handled by the exception
563 * handler when it is enabled, so don't process those here.
565 * TBD do the same check for MCI_STATUS_EN here?
567 if (!(flags & MCP_UC) &&
568 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
571 if (m.status & MCI_STATUS_MISCV)
572 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
573 if (m.status & MCI_STATUS_ADDRV)
574 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
576 if (!(flags & MCP_TIMESTAMP))
579 * Don't get the IP here because it's unlikely to
580 * have anything to do with the actual error location.
582 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
584 add_taint(TAINT_MACHINE_CHECK);
588 * Clear state for this bank.
590 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
594 * Don't clear MCG_STATUS here because it's only defined for
600 EXPORT_SYMBOL_GPL(machine_check_poll);
603 * Do a quick check if any of the events requires a panic.
604 * This decides if we keep the events around or clear them.
606 static int mce_no_way_out(struct mce *m, char **msg)
610 for (i = 0; i < banks; i++) {
611 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
612 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
619 * Variable to establish order between CPUs while scanning.
620 * Each CPU spins initially until executing is equal its number.
622 static atomic_t mce_executing;
625 * Defines order of CPUs on entry. First CPU becomes Monarch.
627 static atomic_t mce_callin;
630 * Check if a timeout waiting for other CPUs happened.
632 static int mce_timed_out(u64 *t)
635 * The others already did panic for some reason.
636 * Bail out like in a timeout.
637 * rmb() to tell the compiler that system_state
638 * might have been modified by someone else.
641 if (atomic_read(&mce_paniced))
643 if (!monarch_timeout)
645 if ((s64)*t < SPINUNIT) {
646 /* CHECKME: Make panic default for 1 too? */
648 mce_panic("Timeout synchronizing machine check over CPUs",
655 touch_nmi_watchdog();
660 * The Monarch's reign. The Monarch is the CPU who entered
661 * the machine check handler first. It waits for the others to
662 * raise the exception too and then grades them. When any
663 * error is fatal panic. Only then let the others continue.
665 * The other CPUs entering the MCE handler will be controlled by the
666 * Monarch. They are called Subjects.
668 * This way we prevent any potential data corruption in a unrecoverable case
669 * and also makes sure always all CPU's errors are examined.
671 * Also this detects the case of a machine check event coming from outer
672 * space (not detected by any CPUs) In this case some external agent wants
673 * us to shut down, so panic too.
675 * The other CPUs might still decide to panic if the handler happens
676 * in a unrecoverable place, but in this case the system is in a semi-stable
677 * state and won't corrupt anything by itself. It's ok to let the others
678 * continue for a bit first.
680 * All the spin loops have timeouts; when a timeout happens a CPU
681 * typically elects itself to be Monarch.
683 static void mce_reign(void)
686 struct mce *m = NULL;
687 int global_worst = 0;
692 * This CPU is the Monarch and the other CPUs have run
693 * through their handlers.
694 * Grade the severity of the errors of all the CPUs.
696 for_each_possible_cpu(cpu) {
697 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
699 if (severity > global_worst) {
701 global_worst = severity;
702 m = &per_cpu(mces_seen, cpu);
707 * Cannot recover? Panic here then.
708 * This dumps all the mces in the log buffer and stops the
711 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
712 mce_panic("Fatal Machine check", m, msg);
715 * For UC somewhere we let the CPU who detects it handle it.
716 * Also must let continue the others, otherwise the handling
717 * CPU could deadlock on a lock.
721 * No machine check event found. Must be some external
722 * source or one CPU is hung. Panic.
724 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
725 mce_panic("Machine check from unknown source", NULL, NULL);
728 * Now clear all the mces_seen so that they don't reappear on
731 for_each_possible_cpu(cpu)
732 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
735 static atomic_t global_nwo;
738 * Start of Monarch synchronization. This waits until all CPUs have
739 * entered the exception handler and then determines if any of them
740 * saw a fatal event that requires panic. Then it executes them
741 * in the entry order.
742 * TBD double check parallel CPU hotunplug
744 static int mce_start(int *no_way_out)
747 int cpus = num_online_cpus();
748 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
753 atomic_add(*no_way_out, &global_nwo);
755 * global_nwo should be updated before mce_callin
758 order = atomic_inc_return(&mce_callin);
763 while (atomic_read(&mce_callin) != cpus) {
764 if (mce_timed_out(&timeout)) {
765 atomic_set(&global_nwo, 0);
772 * mce_callin should be read before global_nwo
778 * Monarch: Starts executing now, the others wait.
780 atomic_set(&mce_executing, 1);
783 * Subject: Now start the scanning loop one by one in
784 * the original callin order.
785 * This way when there are any shared banks it will be
786 * only seen by one CPU before cleared, avoiding duplicates.
788 while (atomic_read(&mce_executing) < order) {
789 if (mce_timed_out(&timeout)) {
790 atomic_set(&global_nwo, 0);
798 * Cache the global no_way_out state.
800 *no_way_out = atomic_read(&global_nwo);
806 * Synchronize between CPUs after main scanning loop.
807 * This invokes the bulk of the Monarch processing.
809 static int mce_end(int order)
812 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
820 * Allow others to run.
822 atomic_inc(&mce_executing);
825 /* CHECKME: Can this race with a parallel hotplug? */
826 int cpus = num_online_cpus();
829 * Monarch: Wait for everyone to go through their scanning
832 while (atomic_read(&mce_executing) <= cpus) {
833 if (mce_timed_out(&timeout))
843 * Subject: Wait for Monarch to finish.
845 while (atomic_read(&mce_executing) != 0) {
846 if (mce_timed_out(&timeout))
852 * Don't reset anything. That's done by the Monarch.
858 * Reset all global state.
861 atomic_set(&global_nwo, 0);
862 atomic_set(&mce_callin, 0);
866 * Let others run again.
868 atomic_set(&mce_executing, 0);
873 * Check if the address reported by the CPU is in a format we can parse.
874 * It would be possible to add code for most other cases, but all would
875 * be somewhat complicated (e.g. segment offset would require an instruction
876 * parser). So only support physical addresses upto page granuality for now.
878 static int mce_usable_address(struct mce *m)
880 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
882 if ((m->misc & 0x3f) > PAGE_SHIFT)
884 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
889 static void mce_clear_state(unsigned long *toclear)
893 for (i = 0; i < banks; i++) {
894 if (test_bit(i, toclear))
895 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
900 * The actual machine check handler. This only handles real
901 * exceptions when something got corrupted coming in through int 18.
903 * This is executed in NMI context not subject to normal locking rules. This
904 * implies that most kernel services cannot be safely used. Don't even
905 * think about putting a printk in there!
907 * On Intel systems this is entered on all CPUs in parallel through
908 * MCE broadcast. However some CPUs might be broken beyond repair,
909 * so be always careful when synchronizing with others.
911 void do_machine_check(struct pt_regs *regs, long error_code)
913 struct mce m, *final;
918 * Establish sequential order between the CPUs entering the machine
923 * If no_way_out gets set, there is no safe way to recover from this
924 * MCE. If tolerant is cranked up, we'll try anyway.
928 * If kill_it gets set, there might be a way to recover from this
932 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
933 char *msg = "Unknown";
935 atomic_inc(&mce_entry);
937 percpu_inc(mce_exception_count);
939 if (notify_die(DIE_NMI, "machine check", regs, error_code,
940 18, SIGKILL) == NOTIFY_STOP)
947 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
948 final = &__get_cpu_var(mces_seen);
951 no_way_out = mce_no_way_out(&m, &msg);
956 * When no restart IP must always kill or panic.
958 if (!(m.mcgstatus & MCG_STATUS_RIPV))
962 * Go through all the banks in exclusion of the other CPUs.
963 * This way we don't report duplicated events on shared banks
964 * because the first one to see it will clear it.
966 order = mce_start(&no_way_out);
967 for (i = 0; i < banks; i++) {
968 __clear_bit(i, toclear);
969 if (!mce_banks[i].ctl)
976 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
977 if ((m.status & MCI_STATUS_VAL) == 0)
981 * Non uncorrected or non signaled errors are handled by
982 * machine_check_poll. Leave them alone, unless this panics.
984 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
989 * Set taint even when machine check was not enabled.
991 add_taint(TAINT_MACHINE_CHECK);
993 severity = mce_severity(&m, tolerant, NULL);
996 * When machine check was for corrected handler don't touch,
997 * unless we're panicing.
999 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1001 __set_bit(i, toclear);
1002 if (severity == MCE_NO_SEVERITY) {
1004 * Machine check event was not enabled. Clear, but
1011 * Kill on action required.
1013 if (severity == MCE_AR_SEVERITY)
1016 if (m.status & MCI_STATUS_MISCV)
1017 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1018 if (m.status & MCI_STATUS_ADDRV)
1019 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1022 * Action optional error. Queue address for later processing.
1023 * When the ring overflows we just ignore the AO error.
1024 * RED-PEN add some logging mechanism when
1025 * usable_address or mce_add_ring fails.
1026 * RED-PEN don't ignore overflow for tolerant == 0
1028 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1029 mce_ring_add(m.addr >> PAGE_SHIFT);
1031 mce_get_rip(&m, regs);
1034 if (severity > worst) {
1041 mce_clear_state(toclear);
1044 * Do most of the synchronization with other CPUs.
1045 * When there's any problem use only local no_way_out state.
1047 if (mce_end(order) < 0)
1048 no_way_out = worst >= MCE_PANIC_SEVERITY;
1051 * If we have decided that we just CAN'T continue, and the user
1052 * has not set tolerant to an insane level, give up and die.
1054 * This is mainly used in the case when the system doesn't
1055 * support MCE broadcasting or it has been disabled.
1057 if (no_way_out && tolerant < 3)
1058 mce_panic("Fatal machine check on current CPU", final, msg);
1061 * If the error seems to be unrecoverable, something should be
1062 * done. Try to kill as little as possible. If we can kill just
1063 * one task, do that. If the user has set the tolerance very
1064 * high, don't try to do anything at all.
1067 if (kill_it && tolerant < 3)
1068 force_sig(SIGBUS, current);
1070 /* notify userspace ASAP */
1071 set_thread_flag(TIF_MCE_NOTIFY);
1074 mce_report_event(regs);
1075 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1077 atomic_dec(&mce_entry);
1080 EXPORT_SYMBOL_GPL(do_machine_check);
1082 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1083 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1085 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1089 * Called after mce notification in process context. This code
1090 * is allowed to sleep. Call the high level VM handler to process
1091 * any corrupted pages.
1092 * Assume that the work queue code only calls this one at a time
1094 * Note we don't disable preemption, so this code might run on the wrong
1095 * CPU. In this case the event is picked up by the scheduled work queue.
1096 * This is merely a fast path to expedite processing in some common
1099 void mce_notify_process(void)
1103 while (mce_ring_get(&pfn))
1104 memory_failure(pfn, MCE_VECTOR);
1107 static void mce_process_work(struct work_struct *dummy)
1109 mce_notify_process();
1112 #ifdef CONFIG_X86_MCE_INTEL
1114 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1115 * @cpu: The CPU on which the event occurred.
1116 * @status: Event status information
1118 * This function should be called by the thermal interrupt after the
1119 * event has been processed and the decision was made to log the event
1122 * The status parameter will be saved to the 'status' field of 'struct mce'
1123 * and historically has been the register value of the
1124 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1126 void mce_log_therm_throt_event(__u64 status)
1131 m.bank = MCE_THERMAL_BANK;
1135 #endif /* CONFIG_X86_MCE_INTEL */
1138 * Periodic polling timer for "silent" machine check errors. If the
1139 * poller finds an MCE, poll 2x faster. When the poller finds no more
1140 * errors, poll 2x slower (up to check_interval seconds).
1142 static int check_interval = 5 * 60; /* 5 minutes */
1144 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1145 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1147 static void mce_start_timer(unsigned long data)
1149 struct timer_list *t = &per_cpu(mce_timer, data);
1152 WARN_ON(smp_processor_id() != data);
1154 if (mce_available(¤t_cpu_data)) {
1155 machine_check_poll(MCP_TIMESTAMP,
1156 &__get_cpu_var(mce_poll_banks));
1160 * Alert userspace if needed. If we logged an MCE, reduce the
1161 * polling interval, otherwise increase the polling interval.
1163 n = &__get_cpu_var(mce_next_interval);
1164 if (mce_notify_irq())
1165 *n = max(*n/2, HZ/100);
1167 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1169 t->expires = jiffies + *n;
1170 add_timer_on(t, smp_processor_id());
1173 static void mce_do_trigger(struct work_struct *work)
1175 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1178 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1181 * Notify the user(s) about new machine check events.
1182 * Can be called from interrupt context, but not from machine check/NMI
1185 int mce_notify_irq(void)
1187 /* Not more than two messages every minute */
1188 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1190 clear_thread_flag(TIF_MCE_NOTIFY);
1192 if (test_and_clear_bit(0, &mce_need_notify)) {
1193 wake_up_interruptible(&mce_wait);
1196 * There is no risk of missing notifications because
1197 * work_pending is always cleared before the function is
1200 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1201 schedule_work(&mce_trigger_work);
1203 if (__ratelimit(&ratelimit))
1204 printk(KERN_INFO "Machine check events logged\n");
1210 EXPORT_SYMBOL_GPL(mce_notify_irq);
1212 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1216 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1219 for (i = 0; i < banks; i++) {
1220 struct mce_bank *b = &mce_banks[i];
1229 * Initialize Machine Checks for a CPU.
1231 static int __cpuinit __mcheck_cpu_cap_init(void)
1236 rdmsrl(MSR_IA32_MCG_CAP, cap);
1238 b = cap & MCG_BANKCNT_MASK;
1240 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1242 if (b > MAX_NR_BANKS) {
1244 "MCE: Using only %u machine check banks out of %u\n",
1249 /* Don't support asymmetric configurations today */
1250 WARN_ON(banks != 0 && b != banks);
1253 int err = __mcheck_cpu_mce_banks_init();
1259 /* Use accurate RIP reporting if available. */
1260 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1261 rip_msr = MSR_IA32_MCG_EIP;
1263 if (cap & MCG_SER_P)
1269 static void __mcheck_cpu_init_generic(void)
1271 mce_banks_t all_banks;
1276 * Log the machine checks left over from the previous reset.
1278 bitmap_fill(all_banks, MAX_NR_BANKS);
1279 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1281 set_in_cr4(X86_CR4_MCE);
1283 rdmsrl(MSR_IA32_MCG_CAP, cap);
1284 if (cap & MCG_CTL_P)
1285 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1287 for (i = 0; i < banks; i++) {
1288 struct mce_bank *b = &mce_banks[i];
1292 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1293 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1297 /* Add per CPU specific workarounds here */
1298 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1300 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1301 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1305 /* This should be disabled by the BIOS, but isn't always */
1306 if (c->x86_vendor == X86_VENDOR_AMD) {
1307 if (c->x86 == 15 && banks > 4) {
1309 * disable GART TBL walk error reporting, which
1310 * trips off incorrectly with the IOMMU & 3ware
1313 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1315 if (c->x86 <= 17 && mce_bootlog < 0) {
1317 * Lots of broken BIOS around that don't clear them
1318 * by default and leave crap in there. Don't log:
1323 * Various K7s with broken bank 0 around. Always disable
1326 if (c->x86 == 6 && banks > 0)
1327 mce_banks[0].ctl = 0;
1330 if (c->x86_vendor == X86_VENDOR_INTEL) {
1332 * SDM documents that on family 6 bank 0 should not be written
1333 * because it aliases to another special BIOS controlled
1335 * But it's not aliased anymore on model 0x1a+
1336 * Don't ignore bank 0 completely because there could be a
1337 * valid event later, merely don't write CTL0.
1340 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1341 mce_banks[0].init = 0;
1344 * All newer Intel systems support MCE broadcasting. Enable
1345 * synchronization with a one second timeout.
1347 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1348 monarch_timeout < 0)
1349 monarch_timeout = USEC_PER_SEC;
1352 * There are also broken BIOSes on some Pentium M and
1355 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1358 if (monarch_timeout < 0)
1359 monarch_timeout = 0;
1360 if (mce_bootlog != 0)
1361 mce_panic_timeout = 30;
1366 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1370 switch (c->x86_vendor) {
1371 case X86_VENDOR_INTEL:
1372 intel_p5_mcheck_init(c);
1374 case X86_VENDOR_CENTAUR:
1375 winchip_mcheck_init(c);
1380 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1382 switch (c->x86_vendor) {
1383 case X86_VENDOR_INTEL:
1384 mce_intel_feature_init(c);
1386 case X86_VENDOR_AMD:
1387 mce_amd_feature_init(c);
1394 static void __mcheck_cpu_init_timer(void)
1396 struct timer_list *t = &__get_cpu_var(mce_timer);
1397 int *n = &__get_cpu_var(mce_next_interval);
1399 setup_timer(t, mce_start_timer, smp_processor_id());
1404 *n = check_interval * HZ;
1407 t->expires = round_jiffies(jiffies + *n);
1408 add_timer_on(t, smp_processor_id());
1411 /* Handle unconfigured int18 (should never happen) */
1412 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1414 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1415 smp_processor_id());
1418 /* Call the installed machine check handler for this CPU setup. */
1419 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1420 unexpected_machine_check;
1423 * Called for each booted CPU to set up machine checks.
1424 * Must be called with preempt off:
1426 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1431 __mcheck_cpu_ancient_init(c);
1433 if (!mce_available(c))
1436 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1441 machine_check_vector = do_machine_check;
1443 __mcheck_cpu_init_generic();
1444 __mcheck_cpu_init_vendor(c);
1445 __mcheck_cpu_init_timer();
1446 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1451 * Character device to read and clear the MCE log.
1454 static DEFINE_SPINLOCK(mce_state_lock);
1455 static int open_count; /* #times opened */
1456 static int open_exclu; /* already open exclusive? */
1458 static int mce_open(struct inode *inode, struct file *file)
1460 spin_lock(&mce_state_lock);
1462 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1463 spin_unlock(&mce_state_lock);
1468 if (file->f_flags & O_EXCL)
1472 spin_unlock(&mce_state_lock);
1474 return nonseekable_open(inode, file);
1477 static int mce_release(struct inode *inode, struct file *file)
1479 spin_lock(&mce_state_lock);
1484 spin_unlock(&mce_state_lock);
1489 static void collect_tscs(void *data)
1491 unsigned long *cpu_tsc = (unsigned long *)data;
1493 rdtscll(cpu_tsc[smp_processor_id()]);
1496 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1499 char __user *buf = ubuf;
1500 unsigned long *cpu_tsc;
1501 unsigned prev, next;
1504 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1508 mutex_lock(&mce_read_mutex);
1509 next = rcu_dereference_check_mce(mcelog.next);
1511 /* Only supports full reads right now */
1512 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1513 mutex_unlock(&mce_read_mutex);
1522 for (i = prev; i < next; i++) {
1523 unsigned long start = jiffies;
1525 while (!mcelog.entry[i].finished) {
1526 if (time_after_eq(jiffies, start + 2)) {
1527 memset(mcelog.entry + i, 0,
1528 sizeof(struct mce));
1534 err |= copy_to_user(buf, mcelog.entry + i,
1535 sizeof(struct mce));
1536 buf += sizeof(struct mce);
1541 memset(mcelog.entry + prev, 0,
1542 (next - prev) * sizeof(struct mce));
1544 next = cmpxchg(&mcelog.next, prev, 0);
1545 } while (next != prev);
1547 synchronize_sched();
1550 * Collect entries that were still getting written before the
1553 on_each_cpu(collect_tscs, cpu_tsc, 1);
1555 for (i = next; i < MCE_LOG_LEN; i++) {
1556 if (mcelog.entry[i].finished &&
1557 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1558 err |= copy_to_user(buf, mcelog.entry+i,
1559 sizeof(struct mce));
1561 buf += sizeof(struct mce);
1562 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1565 mutex_unlock(&mce_read_mutex);
1568 return err ? -EFAULT : buf - ubuf;
1571 static unsigned int mce_poll(struct file *file, poll_table *wait)
1573 poll_wait(file, &mce_wait, wait);
1574 if (rcu_dereference_check_mce(mcelog.next))
1575 return POLLIN | POLLRDNORM;
1579 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1581 int __user *p = (int __user *)arg;
1583 if (!capable(CAP_SYS_ADMIN))
1587 case MCE_GET_RECORD_LEN:
1588 return put_user(sizeof(struct mce), p);
1589 case MCE_GET_LOG_LEN:
1590 return put_user(MCE_LOG_LEN, p);
1591 case MCE_GETCLEAR_FLAGS: {
1595 flags = mcelog.flags;
1596 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1598 return put_user(flags, p);
1605 /* Modified in mce-inject.c, so not static or const */
1606 struct file_operations mce_chrdev_ops = {
1608 .release = mce_release,
1611 .unlocked_ioctl = mce_ioctl,
1613 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1615 static struct miscdevice mce_log_device = {
1622 * mce=off Disables machine check
1623 * mce=no_cmci Disables CMCI
1624 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1625 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1626 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1627 * monarchtimeout is how long to wait for other CPUs on machine
1628 * check, or 0 to not wait
1629 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1630 * mce=nobootlog Don't log MCEs from before booting.
1632 static int __init mcheck_enable(char *str)
1640 if (!strcmp(str, "off"))
1642 else if (!strcmp(str, "no_cmci"))
1643 mce_cmci_disabled = 1;
1644 else if (!strcmp(str, "dont_log_ce"))
1645 mce_dont_log_ce = 1;
1646 else if (!strcmp(str, "ignore_ce"))
1648 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1649 mce_bootlog = (str[0] == 'b');
1650 else if (isdigit(str[0])) {
1651 get_option(&str, &tolerant);
1654 get_option(&str, &monarch_timeout);
1657 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1663 __setup("mce", mcheck_enable);
1665 int __init mcheck_init(void)
1667 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1669 mcheck_intel_therm_init();
1679 * Disable machine checks on suspend and shutdown. We can't really handle
1682 static int mce_disable_error_reporting(void)
1686 for (i = 0; i < banks; i++) {
1687 struct mce_bank *b = &mce_banks[i];
1690 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1695 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1697 return mce_disable_error_reporting();
1700 static int mce_shutdown(struct sys_device *dev)
1702 return mce_disable_error_reporting();
1706 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1707 * Only one CPU is active at this time, the others get re-added later using
1710 static int mce_resume(struct sys_device *dev)
1712 __mcheck_cpu_init_generic();
1713 __mcheck_cpu_init_vendor(¤t_cpu_data);
1718 static void mce_cpu_restart(void *data)
1720 del_timer_sync(&__get_cpu_var(mce_timer));
1721 if (!mce_available(¤t_cpu_data))
1723 __mcheck_cpu_init_generic();
1724 __mcheck_cpu_init_timer();
1727 /* Reinit MCEs after user configuration changes */
1728 static void mce_restart(void)
1730 on_each_cpu(mce_cpu_restart, NULL, 1);
1733 /* Toggle features for corrected errors */
1734 static void mce_disable_ce(void *all)
1736 if (!mce_available(¤t_cpu_data))
1739 del_timer_sync(&__get_cpu_var(mce_timer));
1743 static void mce_enable_ce(void *all)
1745 if (!mce_available(¤t_cpu_data))
1750 __mcheck_cpu_init_timer();
1753 static struct sysdev_class mce_sysclass = {
1754 .suspend = mce_suspend,
1755 .shutdown = mce_shutdown,
1756 .resume = mce_resume,
1757 .name = "machinecheck",
1760 DEFINE_PER_CPU(struct sys_device, mce_dev);
1763 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1765 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1767 return container_of(attr, struct mce_bank, attr);
1770 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1773 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1776 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1777 const char *buf, size_t size)
1781 if (strict_strtoull(buf, 0, &new) < 0)
1784 attr_to_bank(attr)->ctl = new;
1791 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1793 strcpy(buf, mce_helper);
1795 return strlen(mce_helper) + 1;
1798 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1799 const char *buf, size_t siz)
1803 strncpy(mce_helper, buf, sizeof(mce_helper));
1804 mce_helper[sizeof(mce_helper)-1] = 0;
1805 p = strchr(mce_helper, '\n');
1810 return strlen(mce_helper) + !!p;
1813 static ssize_t set_ignore_ce(struct sys_device *s,
1814 struct sysdev_attribute *attr,
1815 const char *buf, size_t size)
1819 if (strict_strtoull(buf, 0, &new) < 0)
1822 if (mce_ignore_ce ^ !!new) {
1824 /* disable ce features */
1825 on_each_cpu(mce_disable_ce, (void *)1, 1);
1828 /* enable ce features */
1830 on_each_cpu(mce_enable_ce, (void *)1, 1);
1836 static ssize_t set_cmci_disabled(struct sys_device *s,
1837 struct sysdev_attribute *attr,
1838 const char *buf, size_t size)
1842 if (strict_strtoull(buf, 0, &new) < 0)
1845 if (mce_cmci_disabled ^ !!new) {
1848 on_each_cpu(mce_disable_ce, NULL, 1);
1849 mce_cmci_disabled = 1;
1852 mce_cmci_disabled = 0;
1853 on_each_cpu(mce_enable_ce, NULL, 1);
1859 static ssize_t store_int_with_restart(struct sys_device *s,
1860 struct sysdev_attribute *attr,
1861 const char *buf, size_t size)
1863 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1868 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1869 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1870 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1871 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1873 static struct sysdev_ext_attribute attr_check_interval = {
1874 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1875 store_int_with_restart),
1879 static struct sysdev_ext_attribute attr_ignore_ce = {
1880 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1884 static struct sysdev_ext_attribute attr_cmci_disabled = {
1885 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1889 static struct sysdev_attribute *mce_attrs[] = {
1890 &attr_tolerant.attr,
1891 &attr_check_interval.attr,
1893 &attr_monarch_timeout.attr,
1894 &attr_dont_log_ce.attr,
1895 &attr_ignore_ce.attr,
1896 &attr_cmci_disabled.attr,
1900 static cpumask_var_t mce_dev_initialized;
1902 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1903 static __cpuinit int mce_create_device(unsigned int cpu)
1908 if (!mce_available(&boot_cpu_data))
1911 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1912 per_cpu(mce_dev, cpu).id = cpu;
1913 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1915 err = sysdev_register(&per_cpu(mce_dev, cpu));
1919 for (i = 0; mce_attrs[i]; i++) {
1920 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1924 for (j = 0; j < banks; j++) {
1925 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1926 &mce_banks[j].attr);
1930 cpumask_set_cpu(cpu, mce_dev_initialized);
1935 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1938 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1940 sysdev_unregister(&per_cpu(mce_dev, cpu));
1945 static __cpuinit void mce_remove_device(unsigned int cpu)
1949 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1952 for (i = 0; mce_attrs[i]; i++)
1953 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1955 for (i = 0; i < banks; i++)
1956 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1958 sysdev_unregister(&per_cpu(mce_dev, cpu));
1959 cpumask_clear_cpu(cpu, mce_dev_initialized);
1962 /* Make sure there are no machine checks on offlined CPUs. */
1963 static void __cpuinit mce_disable_cpu(void *h)
1965 unsigned long action = *(unsigned long *)h;
1968 if (!mce_available(¤t_cpu_data))
1971 if (!(action & CPU_TASKS_FROZEN))
1973 for (i = 0; i < banks; i++) {
1974 struct mce_bank *b = &mce_banks[i];
1977 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1981 static void __cpuinit mce_reenable_cpu(void *h)
1983 unsigned long action = *(unsigned long *)h;
1986 if (!mce_available(¤t_cpu_data))
1989 if (!(action & CPU_TASKS_FROZEN))
1991 for (i = 0; i < banks; i++) {
1992 struct mce_bank *b = &mce_banks[i];
1995 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1999 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2000 static int __cpuinit
2001 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2003 unsigned int cpu = (unsigned long)hcpu;
2004 struct timer_list *t = &per_cpu(mce_timer, cpu);
2008 case CPU_ONLINE_FROZEN:
2009 mce_create_device(cpu);
2010 if (threshold_cpu_callback)
2011 threshold_cpu_callback(action, cpu);
2014 case CPU_DEAD_FROZEN:
2015 if (threshold_cpu_callback)
2016 threshold_cpu_callback(action, cpu);
2017 mce_remove_device(cpu);
2019 case CPU_DOWN_PREPARE:
2020 case CPU_DOWN_PREPARE_FROZEN:
2022 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2024 case CPU_DOWN_FAILED:
2025 case CPU_DOWN_FAILED_FROZEN:
2026 if (!mce_ignore_ce && check_interval) {
2027 t->expires = round_jiffies(jiffies +
2028 __get_cpu_var(mce_next_interval));
2029 add_timer_on(t, cpu);
2031 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2034 /* intentionally ignoring frozen here */
2035 cmci_rediscover(cpu);
2041 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2042 .notifier_call = mce_cpu_callback,
2045 static __init void mce_init_banks(void)
2049 for (i = 0; i < banks; i++) {
2050 struct mce_bank *b = &mce_banks[i];
2051 struct sysdev_attribute *a = &b->attr;
2053 sysfs_attr_init(&a->attr);
2054 a->attr.name = b->attrname;
2055 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2057 a->attr.mode = 0644;
2058 a->show = show_bank;
2059 a->store = set_bank;
2063 static __init int mcheck_init_device(void)
2068 if (!mce_available(&boot_cpu_data))
2071 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2075 err = sysdev_class_register(&mce_sysclass);
2079 for_each_online_cpu(i) {
2080 err = mce_create_device(i);
2085 register_hotcpu_notifier(&mce_cpu_notifier);
2086 misc_register(&mce_log_device);
2091 device_initcall(mcheck_init_device);
2094 * Old style boot options parsing. Only for compatibility.
2096 static int __init mcheck_disable(char *str)
2101 __setup("nomce", mcheck_disable);
2103 #ifdef CONFIG_DEBUG_FS
2104 struct dentry *mce_get_debugfs_dir(void)
2106 static struct dentry *dmce;
2109 dmce = debugfs_create_dir("mce", NULL);
2114 static void mce_reset(void)
2117 atomic_set(&mce_fake_paniced, 0);
2118 atomic_set(&mce_executing, 0);
2119 atomic_set(&mce_callin, 0);
2120 atomic_set(&global_nwo, 0);
2123 static int fake_panic_get(void *data, u64 *val)
2129 static int fake_panic_set(void *data, u64 val)
2136 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2137 fake_panic_set, "%llu\n");
2139 static int __init mcheck_debugfs_init(void)
2141 struct dentry *dmce, *ffake_panic;
2143 dmce = mce_get_debugfs_dir();
2146 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2153 late_initcall(mcheck_debugfs_init);