2 * Performance counter x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
10 * For licencing details see kernel-base/COPYING
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
24 #include <asm/stacktrace.h>
27 static u64 perf_counter_mask __read_mostly;
29 struct cpu_hw_counters {
30 struct perf_counter *counters[X86_PMC_IDX_MAX];
31 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
32 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
33 unsigned long interrupts;
38 * struct x86_pmu - generic x86 pmu
43 int (*handle_irq)(struct pt_regs *, int);
44 void (*disable_all)(void);
45 void (*enable_all)(void);
46 void (*enable)(struct hw_perf_counter *, int);
47 void (*disable)(struct hw_perf_counter *, int);
50 u64 (*event_map)(int);
51 u64 (*raw_event)(u64);
54 int num_counters_fixed;
61 static struct x86_pmu x86_pmu __read_mostly;
63 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
68 * Intel PerfMon v3. Used on Core2 and later.
70 static const u64 intel_perfmon_event_map[] =
72 [PERF_COUNT_CPU_CYCLES] = 0x003c,
73 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
74 [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
75 [PERF_COUNT_CACHE_MISSES] = 0x412e,
76 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
77 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
78 [PERF_COUNT_BUS_CYCLES] = 0x013c,
81 static u64 intel_pmu_event_map(int event)
83 return intel_perfmon_event_map[event];
86 static u64 intel_pmu_raw_event(u64 event)
88 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
89 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
90 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
92 #define CORE_EVNTSEL_MASK \
93 (CORE_EVNTSEL_EVENT_MASK | \
94 CORE_EVNTSEL_UNIT_MASK | \
95 CORE_EVNTSEL_COUNTER_MASK)
97 return event & CORE_EVNTSEL_MASK;
101 * AMD Performance Monitor K7 and later.
103 static const u64 amd_perfmon_event_map[] =
105 [PERF_COUNT_CPU_CYCLES] = 0x0076,
106 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
107 [PERF_COUNT_CACHE_REFERENCES] = 0x0080,
108 [PERF_COUNT_CACHE_MISSES] = 0x0081,
109 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
110 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
113 static u64 amd_pmu_event_map(int event)
115 return amd_perfmon_event_map[event];
118 static u64 amd_pmu_raw_event(u64 event)
120 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
121 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
122 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
124 #define K7_EVNTSEL_MASK \
125 (K7_EVNTSEL_EVENT_MASK | \
126 K7_EVNTSEL_UNIT_MASK | \
127 K7_EVNTSEL_COUNTER_MASK)
129 return event & K7_EVNTSEL_MASK;
133 * Propagate counter elapsed time into the generic counter.
134 * Can only be executed on the CPU where the counter is active.
135 * Returns the delta events processed.
138 x86_perf_counter_update(struct perf_counter *counter,
139 struct hw_perf_counter *hwc, int idx)
141 int shift = 64 - x86_pmu.counter_bits;
142 u64 prev_raw_count, new_raw_count;
146 * Careful: an NMI might modify the previous counter value.
148 * Our tactic to handle this is to first atomically read and
149 * exchange a new raw count - then add that new-prev delta
150 * count to the generic counter atomically:
153 prev_raw_count = atomic64_read(&hwc->prev_count);
154 rdmsrl(hwc->counter_base + idx, new_raw_count);
156 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
157 new_raw_count) != prev_raw_count)
161 * Now we have the new raw value and have updated the prev
162 * timestamp already. We can now calculate the elapsed delta
163 * (counter-)time and add that to the generic counter.
165 * Careful, not all hw sign-extends above the physical width
168 delta = (new_raw_count << shift) - (prev_raw_count << shift);
171 atomic64_add(delta, &counter->count);
172 atomic64_sub(delta, &hwc->period_left);
174 return new_raw_count;
177 static atomic_t active_counters;
178 static DEFINE_MUTEX(pmc_reserve_mutex);
180 static bool reserve_pmc_hardware(void)
184 if (nmi_watchdog == NMI_LOCAL_APIC)
185 disable_lapic_nmi_watchdog();
187 for (i = 0; i < x86_pmu.num_counters; i++) {
188 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
192 for (i = 0; i < x86_pmu.num_counters; i++) {
193 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
200 for (i--; i >= 0; i--)
201 release_evntsel_nmi(x86_pmu.eventsel + i);
203 i = x86_pmu.num_counters;
206 for (i--; i >= 0; i--)
207 release_perfctr_nmi(x86_pmu.perfctr + i);
209 if (nmi_watchdog == NMI_LOCAL_APIC)
210 enable_lapic_nmi_watchdog();
215 static void release_pmc_hardware(void)
219 for (i = 0; i < x86_pmu.num_counters; i++) {
220 release_perfctr_nmi(x86_pmu.perfctr + i);
221 release_evntsel_nmi(x86_pmu.eventsel + i);
224 if (nmi_watchdog == NMI_LOCAL_APIC)
225 enable_lapic_nmi_watchdog();
228 static void hw_perf_counter_destroy(struct perf_counter *counter)
230 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
231 release_pmc_hardware();
232 mutex_unlock(&pmc_reserve_mutex);
236 static inline int x86_pmu_initialized(void)
238 return x86_pmu.handle_irq != NULL;
242 * Setup the hardware configuration for a given hw_event_type
244 static int __hw_perf_counter_init(struct perf_counter *counter)
246 struct perf_counter_hw_event *hw_event = &counter->hw_event;
247 struct hw_perf_counter *hwc = &counter->hw;
250 if (!x86_pmu_initialized())
254 if (!atomic_inc_not_zero(&active_counters)) {
255 mutex_lock(&pmc_reserve_mutex);
256 if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
259 atomic_inc(&active_counters);
260 mutex_unlock(&pmc_reserve_mutex);
267 * (keep 'enabled' bit clear for now)
269 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
272 * Count user and OS events unless requested not to.
274 if (!hw_event->exclude_user)
275 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
276 if (!hw_event->exclude_kernel)
277 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
280 * If privileged enough, allow NMI events:
284 if (sysctl_perf_counter_priv && !capable(CAP_SYS_ADMIN))
289 hwc->irq_period = hw_event->irq_period;
290 if ((s64)hwc->irq_period <= 0 || hwc->irq_period > x86_pmu.max_period)
291 hwc->irq_period = x86_pmu.max_period;
293 atomic64_set(&hwc->period_left, hwc->irq_period);
296 * Raw event type provide the config in the event structure
298 if (perf_event_raw(hw_event)) {
299 hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event));
301 if (perf_event_id(hw_event) >= x86_pmu.max_events)
306 hwc->config |= x86_pmu.event_map(perf_event_id(hw_event));
309 counter->destroy = hw_perf_counter_destroy;
314 static void intel_pmu_disable_all(void)
316 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
319 static void amd_pmu_disable_all(void)
321 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
329 * ensure we write the disable before we start disabling the
330 * counters proper, so that amd_pmu_enable_counter() does the
335 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
338 if (!test_bit(idx, cpuc->active_mask))
340 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
341 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
343 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
344 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
348 void hw_perf_disable(void)
350 if (!x86_pmu_initialized())
352 return x86_pmu.disable_all();
355 static void intel_pmu_enable_all(void)
357 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
360 static void amd_pmu_enable_all(void)
362 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
371 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
374 if (!test_bit(idx, cpuc->active_mask))
376 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
377 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
379 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
380 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
384 void hw_perf_enable(void)
386 if (!x86_pmu_initialized())
388 x86_pmu.enable_all();
391 static inline u64 intel_pmu_get_status(void)
395 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
400 static inline void intel_pmu_ack_status(u64 ack)
402 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
405 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
408 err = checking_wrmsrl(hwc->config_base + idx,
409 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
412 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
415 err = checking_wrmsrl(hwc->config_base + idx,
420 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
422 int idx = __idx - X86_PMC_IDX_FIXED;
426 mask = 0xfULL << (idx * 4);
428 rdmsrl(hwc->config_base, ctrl_val);
430 err = checking_wrmsrl(hwc->config_base, ctrl_val);
434 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
436 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
437 intel_pmu_disable_fixed(hwc, idx);
441 x86_pmu_disable_counter(hwc, idx);
445 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
447 x86_pmu_disable_counter(hwc, idx);
450 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
453 * Set the next IRQ period, based on the hwc->period_left value.
454 * To be called with the counter disabled in hw:
457 x86_perf_counter_set_period(struct perf_counter *counter,
458 struct hw_perf_counter *hwc, int idx)
460 s64 left = atomic64_read(&hwc->period_left);
461 s64 period = hwc->irq_period;
465 * If we are way outside a reasoable range then just skip forward:
467 if (unlikely(left <= -period)) {
469 atomic64_set(&hwc->period_left, left);
472 if (unlikely(left <= 0)) {
474 atomic64_set(&hwc->period_left, left);
477 * Quirk: certain CPUs dont like it if just 1 event is left:
479 if (unlikely(left < 2))
482 per_cpu(prev_left[idx], smp_processor_id()) = left;
485 * The hw counter starts counting from this counter offset,
486 * mark it to be able to extra future deltas:
488 atomic64_set(&hwc->prev_count, (u64)-left);
490 err = checking_wrmsrl(hwc->counter_base + idx,
491 (u64)(-left) & x86_pmu.counter_mask);
495 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
497 int idx = __idx - X86_PMC_IDX_FIXED;
498 u64 ctrl_val, bits, mask;
502 * Enable IRQ generation (0x8),
503 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
507 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
509 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
512 mask = 0xfULL << (idx * 4);
514 rdmsrl(hwc->config_base, ctrl_val);
517 err = checking_wrmsrl(hwc->config_base, ctrl_val);
520 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
522 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
523 intel_pmu_enable_fixed(hwc, idx);
527 x86_pmu_enable_counter(hwc, idx);
530 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
532 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
535 x86_pmu_enable_counter(hwc, idx);
537 x86_pmu_disable_counter(hwc, idx);
541 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
545 if (!x86_pmu.num_counters_fixed)
548 if (unlikely(hwc->nmi))
551 event = hwc->config & ARCH_PERFMON_EVENT_MASK;
553 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
554 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
555 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES)))
556 return X86_PMC_IDX_FIXED_CPU_CYCLES;
557 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES)))
558 return X86_PMC_IDX_FIXED_BUS_CYCLES;
564 * Find a PMC slot for the freshly enabled / scheduled in counter:
566 static int x86_pmu_enable(struct perf_counter *counter)
568 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
569 struct hw_perf_counter *hwc = &counter->hw;
572 idx = fixed_mode_idx(counter, hwc);
575 * Try to get the fixed counter, if that is already taken
576 * then try to get a generic counter:
578 if (test_and_set_bit(idx, cpuc->used_mask))
581 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
583 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
584 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
587 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
591 /* Try to get the previous generic counter again */
592 if (test_and_set_bit(idx, cpuc->used_mask)) {
594 idx = find_first_zero_bit(cpuc->used_mask,
595 x86_pmu.num_counters);
596 if (idx == x86_pmu.num_counters)
599 set_bit(idx, cpuc->used_mask);
602 hwc->config_base = x86_pmu.eventsel;
603 hwc->counter_base = x86_pmu.perfctr;
606 perf_counters_lapic_init(hwc->nmi);
608 x86_pmu.disable(hwc, idx);
610 cpuc->counters[idx] = counter;
611 set_bit(idx, cpuc->active_mask);
613 x86_perf_counter_set_period(counter, hwc, idx);
614 x86_pmu.enable(hwc, idx);
619 void perf_counter_print_debug(void)
621 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
622 struct cpu_hw_counters *cpuc;
626 if (!x86_pmu.num_counters)
629 local_irq_save(flags);
631 cpu = smp_processor_id();
632 cpuc = &per_cpu(cpu_hw_counters, cpu);
634 if (x86_pmu.version >= 2) {
635 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
636 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
637 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
638 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
641 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
642 pr_info("CPU#%d: status: %016llx\n", cpu, status);
643 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
644 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
646 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
648 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
649 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
650 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
652 prev_left = per_cpu(prev_left[idx], cpu);
654 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
656 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
657 cpu, idx, pmc_count);
658 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
659 cpu, idx, prev_left);
661 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
662 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
664 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
665 cpu, idx, pmc_count);
667 local_irq_restore(flags);
670 static void x86_pmu_disable(struct perf_counter *counter)
672 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
673 struct hw_perf_counter *hwc = &counter->hw;
677 * Must be done before we disable, otherwise the nmi handler
678 * could reenable again:
680 clear_bit(idx, cpuc->active_mask);
681 x86_pmu.disable(hwc, idx);
684 * Make sure the cleared pointer becomes visible before we
685 * (potentially) free the counter:
690 * Drain the remaining delta count out of a counter
691 * that we are disabling:
693 x86_perf_counter_update(counter, hwc, idx);
694 cpuc->counters[idx] = NULL;
695 clear_bit(idx, cpuc->used_mask);
699 * Save and restart an expired counter. Called by NMI contexts,
700 * so it has to be careful about preempting normal counter ops:
702 static void intel_pmu_save_and_restart(struct perf_counter *counter)
704 struct hw_perf_counter *hwc = &counter->hw;
707 x86_perf_counter_update(counter, hwc, idx);
708 x86_perf_counter_set_period(counter, hwc, idx);
710 if (counter->state == PERF_COUNTER_STATE_ACTIVE)
711 intel_pmu_enable_counter(hwc, idx);
715 * Maximum interrupt frequency of 100KHz per CPU
717 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
720 * This handler is triggered by the local APIC, so the APIC IRQ handling
723 static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
725 int bit, cpu = smp_processor_id();
727 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
730 status = intel_pmu_get_status();
737 inc_irq_stat(apic_perf_irqs);
739 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
740 struct perf_counter *counter = cpuc->counters[bit];
742 clear_bit(bit, (unsigned long *) &status);
743 if (!test_bit(bit, cpuc->active_mask))
746 intel_pmu_save_and_restart(counter);
747 if (perf_counter_overflow(counter, nmi, regs, 0))
748 intel_pmu_disable_counter(&counter->hw, bit);
751 intel_pmu_ack_status(ack);
754 * Repeat if there is more work to be done:
756 status = intel_pmu_get_status();
760 if (++cpuc->interrupts != PERFMON_MAX_INTERRUPTS)
766 static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
768 int cpu = smp_processor_id();
769 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
772 struct perf_counter *counter;
773 struct hw_perf_counter *hwc;
774 int idx, throttle = 0;
776 if (++cpuc->interrupts == PERFMON_MAX_INTERRUPTS) {
783 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
786 if (!test_bit(idx, cpuc->active_mask))
789 counter = cpuc->counters[idx];
792 if (counter->hw_event.nmi != nmi)
795 val = x86_perf_counter_update(counter, hwc, idx);
796 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
799 /* counter overflow */
800 x86_perf_counter_set_period(counter, hwc, idx);
802 inc_irq_stat(apic_perf_irqs);
803 disable = perf_counter_overflow(counter, nmi, regs, 0);
806 if (disable || throttle)
807 amd_pmu_disable_counter(hwc, idx);
813 void perf_counter_unthrottle(void)
815 struct cpu_hw_counters *cpuc;
817 if (!x86_pmu_initialized())
820 cpuc = &__get_cpu_var(cpu_hw_counters);
821 if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
823 * Clear them before re-enabling irqs/NMIs again:
825 cpuc->interrupts = 0;
828 cpuc->interrupts = 0;
832 void smp_perf_counter_interrupt(struct pt_regs *regs)
835 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
837 x86_pmu.handle_irq(regs, 0);
841 void smp_perf_pending_interrupt(struct pt_regs *regs)
845 inc_irq_stat(apic_pending_irqs);
846 perf_counter_do_pending();
850 void set_perf_counter_pending(void)
852 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
855 void perf_counters_lapic_init(int nmi)
859 if (!x86_pmu_initialized())
863 * Enable the performance counter vector in the APIC LVT:
865 apic_val = apic_read(APIC_LVTERR);
867 apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
869 apic_write(APIC_LVTPC, APIC_DM_NMI);
871 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
872 apic_write(APIC_LVTERR, apic_val);
876 perf_counter_nmi_handler(struct notifier_block *self,
877 unsigned long cmd, void *__args)
879 struct die_args *args = __args;
880 struct pt_regs *regs;
882 if (!atomic_read(&active_counters))
896 apic_write(APIC_LVTPC, APIC_DM_NMI);
898 * Can't rely on the handled return value to say it was our NMI, two
899 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
901 * If the first NMI handles both, the latter will be empty and daze
904 x86_pmu.handle_irq(regs, 1);
909 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
910 .notifier_call = perf_counter_nmi_handler,
915 static struct x86_pmu intel_pmu = {
917 .handle_irq = intel_pmu_handle_irq,
918 .disable_all = intel_pmu_disable_all,
919 .enable_all = intel_pmu_enable_all,
920 .enable = intel_pmu_enable_counter,
921 .disable = intel_pmu_disable_counter,
922 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
923 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
924 .event_map = intel_pmu_event_map,
925 .raw_event = intel_pmu_raw_event,
926 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
928 * Intel PMCs cannot be accessed sanely above 32 bit width,
929 * so we install an artificial 1<<31 period regardless of
930 * the generic counter period:
932 .max_period = (1ULL << 31) - 1,
935 static struct x86_pmu amd_pmu = {
937 .handle_irq = amd_pmu_handle_irq,
938 .disable_all = amd_pmu_disable_all,
939 .enable_all = amd_pmu_enable_all,
940 .enable = amd_pmu_enable_counter,
941 .disable = amd_pmu_disable_counter,
942 .eventsel = MSR_K7_EVNTSEL0,
943 .perfctr = MSR_K7_PERFCTR0,
944 .event_map = amd_pmu_event_map,
945 .raw_event = amd_pmu_raw_event,
946 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
949 .counter_mask = (1ULL << 48) - 1,
950 /* use highest bit to detect overflow */
951 .max_period = (1ULL << 47) - 1,
954 static int intel_pmu_init(void)
956 union cpuid10_edx edx;
957 union cpuid10_eax eax;
962 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
966 * Check whether the Architectural PerfMon supports
967 * Branch Misses Retired Event or not.
969 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
970 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
973 version = eax.split.version_id;
978 x86_pmu.version = version;
979 x86_pmu.num_counters = eax.split.num_counters;
982 * Quirk: v2 perfmon does not report fixed-purpose counters, so
983 * assume at least 3 counters:
985 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
987 x86_pmu.counter_bits = eax.split.bit_width;
988 x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
990 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
995 static int amd_pmu_init(void)
1001 void __init init_hw_perf_counters(void)
1005 switch (boot_cpu_data.x86_vendor) {
1006 case X86_VENDOR_INTEL:
1007 err = intel_pmu_init();
1009 case X86_VENDOR_AMD:
1010 err = amd_pmu_init();
1018 pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name);
1019 pr_info("... version: %d\n", x86_pmu.version);
1020 pr_info("... bit width: %d\n", x86_pmu.counter_bits);
1022 pr_info("... num counters: %d\n", x86_pmu.num_counters);
1023 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1024 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1025 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
1026 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1028 perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
1029 perf_max_counters = x86_pmu.num_counters;
1031 pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask);
1032 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1034 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1035 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1036 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1037 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1039 pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed);
1041 perf_counter_mask |=
1042 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1044 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
1046 perf_counters_lapic_init(0);
1047 register_die_notifier(&perf_counter_nmi_notifier);
1050 static inline void x86_pmu_read(struct perf_counter *counter)
1052 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1055 static const struct pmu pmu = {
1056 .enable = x86_pmu_enable,
1057 .disable = x86_pmu_disable,
1058 .read = x86_pmu_read,
1061 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1065 err = __hw_perf_counter_init(counter);
1067 return ERR_PTR(err);
1077 void callchain_store(struct perf_callchain_entry *entry, unsigned long ip)
1079 if (entry->nr < MAX_STACK_DEPTH)
1080 entry->ip[entry->nr++] = ip;
1083 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1084 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1088 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1090 /* Ignore warnings */
1093 static void backtrace_warning(void *data, char *msg)
1095 /* Ignore warnings */
1098 static int backtrace_stack(void *data, char *name)
1100 /* Don't bother with IRQ stacks for now */
1104 static void backtrace_address(void *data, unsigned long addr, int reliable)
1106 struct perf_callchain_entry *entry = data;
1109 callchain_store(entry, addr);
1112 static const struct stacktrace_ops backtrace_ops = {
1113 .warning = backtrace_warning,
1114 .warning_symbol = backtrace_warning_symbol,
1115 .stack = backtrace_stack,
1116 .address = backtrace_address,
1120 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1126 callchain_store(entry, instruction_pointer(regs));
1128 stack = ((char *)regs + sizeof(struct pt_regs));
1129 #ifdef CONFIG_FRAME_POINTER
1130 bp = frame_pointer(regs);
1135 dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry);
1137 entry->kernel = entry->nr - nr;
1141 struct stack_frame {
1142 const void __user *next_fp;
1143 unsigned long return_address;
1146 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1150 if (!access_ok(VERIFY_READ, fp, sizeof(*frame)))
1154 pagefault_disable();
1155 if (__copy_from_user_inatomic(frame, fp, sizeof(*frame)))
1163 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1165 struct stack_frame frame;
1166 const void __user *fp;
1169 regs = (struct pt_regs *)current->thread.sp0 - 1;
1170 fp = (void __user *)regs->bp;
1172 callchain_store(entry, regs->ip);
1174 while (entry->nr < MAX_STACK_DEPTH) {
1175 frame.next_fp = NULL;
1176 frame.return_address = 0;
1178 if (!copy_stack_frame(fp, &frame))
1181 if ((unsigned long)fp < user_stack_pointer(regs))
1184 callchain_store(entry, frame.return_address);
1188 entry->user = entry->nr - nr;
1192 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1199 is_user = user_mode(regs);
1201 if (!current || current->pid == 0)
1204 if (is_user && current->state != TASK_RUNNING)
1208 perf_callchain_kernel(regs, entry);
1211 perf_callchain_user(regs, entry);
1214 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1216 struct perf_callchain_entry *entry;
1219 entry = &__get_cpu_var(nmi_entry);
1221 entry = &__get_cpu_var(irq_entry);
1228 perf_do_callchain(regs, entry);