2 * Performance counter x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
10 * For licencing details see kernel-base/COPYING
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
24 #include <asm/stacktrace.h>
27 static u64 perf_counter_mask __read_mostly;
29 struct cpu_hw_counters {
30 struct perf_counter *counters[X86_PMC_IDX_MAX];
31 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
32 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
33 unsigned long interrupts;
39 * struct x86_pmu - generic x86 pmu
44 int (*handle_irq)(struct pt_regs *, int);
45 u64 (*save_disable_all)(void);
46 void (*restore_all)(u64);
47 void (*enable)(struct hw_perf_counter *, int);
48 void (*disable)(struct hw_perf_counter *, int);
51 u64 (*event_map)(int);
52 u64 (*raw_event)(u64);
55 int num_counters_fixed;
61 static struct x86_pmu x86_pmu __read_mostly;
63 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
68 * Intel PerfMon v3. Used on Core2 and later.
70 static const u64 intel_perfmon_event_map[] =
72 [PERF_COUNT_CPU_CYCLES] = 0x003c,
73 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
74 [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
75 [PERF_COUNT_CACHE_MISSES] = 0x412e,
76 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
77 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
78 [PERF_COUNT_BUS_CYCLES] = 0x013c,
81 static u64 intel_pmu_event_map(int event)
83 return intel_perfmon_event_map[event];
86 static u64 intel_pmu_raw_event(u64 event)
88 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
89 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
90 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
92 #define CORE_EVNTSEL_MASK \
93 (CORE_EVNTSEL_EVENT_MASK | \
94 CORE_EVNTSEL_UNIT_MASK | \
95 CORE_EVNTSEL_COUNTER_MASK)
97 return event & CORE_EVNTSEL_MASK;
101 * AMD Performance Monitor K7 and later.
103 static const u64 amd_perfmon_event_map[] =
105 [PERF_COUNT_CPU_CYCLES] = 0x0076,
106 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
107 [PERF_COUNT_CACHE_REFERENCES] = 0x0080,
108 [PERF_COUNT_CACHE_MISSES] = 0x0081,
109 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
110 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
113 static u64 amd_pmu_event_map(int event)
115 return amd_perfmon_event_map[event];
118 static u64 amd_pmu_raw_event(u64 event)
120 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
121 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
122 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
124 #define K7_EVNTSEL_MASK \
125 (K7_EVNTSEL_EVENT_MASK | \
126 K7_EVNTSEL_UNIT_MASK | \
127 K7_EVNTSEL_COUNTER_MASK)
129 return event & K7_EVNTSEL_MASK;
133 * Propagate counter elapsed time into the generic counter.
134 * Can only be executed on the CPU where the counter is active.
135 * Returns the delta events processed.
138 x86_perf_counter_update(struct perf_counter *counter,
139 struct hw_perf_counter *hwc, int idx)
141 u64 prev_raw_count, new_raw_count, delta;
144 * Careful: an NMI might modify the previous counter value.
146 * Our tactic to handle this is to first atomically read and
147 * exchange a new raw count - then add that new-prev delta
148 * count to the generic counter atomically:
151 prev_raw_count = atomic64_read(&hwc->prev_count);
152 rdmsrl(hwc->counter_base + idx, new_raw_count);
154 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
155 new_raw_count) != prev_raw_count)
159 * Now we have the new raw value and have updated the prev
160 * timestamp already. We can now calculate the elapsed delta
161 * (counter-)time and add that to the generic counter.
163 * Careful, not all hw sign-extends above the physical width
164 * of the count, so we do that by clipping the delta to 32 bits:
166 delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count);
168 atomic64_add(delta, &counter->count);
169 atomic64_sub(delta, &hwc->period_left);
171 return new_raw_count;
174 static atomic_t active_counters;
175 static DEFINE_MUTEX(pmc_reserve_mutex);
177 static bool reserve_pmc_hardware(void)
181 if (nmi_watchdog == NMI_LOCAL_APIC)
182 disable_lapic_nmi_watchdog();
184 for (i = 0; i < x86_pmu.num_counters; i++) {
185 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
189 for (i = 0; i < x86_pmu.num_counters; i++) {
190 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
197 for (i--; i >= 0; i--)
198 release_evntsel_nmi(x86_pmu.eventsel + i);
200 i = x86_pmu.num_counters;
203 for (i--; i >= 0; i--)
204 release_perfctr_nmi(x86_pmu.perfctr + i);
206 if (nmi_watchdog == NMI_LOCAL_APIC)
207 enable_lapic_nmi_watchdog();
212 static void release_pmc_hardware(void)
216 for (i = 0; i < x86_pmu.num_counters; i++) {
217 release_perfctr_nmi(x86_pmu.perfctr + i);
218 release_evntsel_nmi(x86_pmu.eventsel + i);
221 if (nmi_watchdog == NMI_LOCAL_APIC)
222 enable_lapic_nmi_watchdog();
225 static void hw_perf_counter_destroy(struct perf_counter *counter)
227 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
228 release_pmc_hardware();
229 mutex_unlock(&pmc_reserve_mutex);
233 static inline int x86_pmu_initialized(void)
235 return x86_pmu.handle_irq != NULL;
239 * Setup the hardware configuration for a given hw_event_type
241 static int __hw_perf_counter_init(struct perf_counter *counter)
243 struct perf_counter_hw_event *hw_event = &counter->hw_event;
244 struct hw_perf_counter *hwc = &counter->hw;
247 if (!x86_pmu_initialized())
251 if (!atomic_inc_not_zero(&active_counters)) {
252 mutex_lock(&pmc_reserve_mutex);
253 if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
256 atomic_inc(&active_counters);
257 mutex_unlock(&pmc_reserve_mutex);
264 * (keep 'enabled' bit clear for now)
266 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
269 * Count user and OS events unless requested not to.
271 if (!hw_event->exclude_user)
272 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
273 if (!hw_event->exclude_kernel)
274 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
277 * If privileged enough, allow NMI events:
280 if (capable(CAP_SYS_ADMIN) && hw_event->nmi)
283 hwc->irq_period = hw_event->irq_period;
284 if ((s64)hwc->irq_period <= 0 || hwc->irq_period > x86_pmu.max_period)
285 hwc->irq_period = x86_pmu.max_period;
287 atomic64_set(&hwc->period_left, hwc->irq_period);
290 * Raw event type provide the config in the event structure
292 if (perf_event_raw(hw_event)) {
293 hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event));
295 if (perf_event_id(hw_event) >= x86_pmu.max_events)
300 hwc->config |= x86_pmu.event_map(perf_event_id(hw_event));
303 counter->destroy = hw_perf_counter_destroy;
308 static u64 intel_pmu_save_disable_all(void)
312 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
313 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
318 static u64 amd_pmu_save_disable_all(void)
320 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
323 enabled = cpuc->enabled;
326 * ensure we write the disable before we start disabling the
327 * counters proper, so that amd_pmu_enable_counter() does the
332 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
335 if (!test_bit(idx, cpuc->active_mask))
337 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
338 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
340 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
341 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
347 u64 hw_perf_save_disable(void)
349 if (!x86_pmu_initialized())
351 return x86_pmu.save_disable_all();
354 * Exported because of ACPI idle
356 EXPORT_SYMBOL_GPL(hw_perf_save_disable);
358 static void intel_pmu_restore_all(u64 ctrl)
360 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
363 static void amd_pmu_restore_all(u64 ctrl)
365 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
368 cpuc->enabled = ctrl;
373 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
376 if (!test_bit(idx, cpuc->active_mask))
378 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
379 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
381 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
382 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
386 void hw_perf_restore(u64 ctrl)
388 if (!x86_pmu_initialized())
390 x86_pmu.restore_all(ctrl);
393 * Exported because of ACPI idle
395 EXPORT_SYMBOL_GPL(hw_perf_restore);
397 static inline u64 intel_pmu_get_status(void)
401 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
406 static inline void intel_pmu_ack_status(u64 ack)
408 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
411 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
414 err = checking_wrmsrl(hwc->config_base + idx,
415 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
418 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
421 err = checking_wrmsrl(hwc->config_base + idx,
426 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
428 int idx = __idx - X86_PMC_IDX_FIXED;
432 mask = 0xfULL << (idx * 4);
434 rdmsrl(hwc->config_base, ctrl_val);
436 err = checking_wrmsrl(hwc->config_base, ctrl_val);
440 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
442 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
443 intel_pmu_disable_fixed(hwc, idx);
447 x86_pmu_disable_counter(hwc, idx);
451 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
453 x86_pmu_disable_counter(hwc, idx);
456 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
459 * Set the next IRQ period, based on the hwc->period_left value.
460 * To be called with the counter disabled in hw:
463 x86_perf_counter_set_period(struct perf_counter *counter,
464 struct hw_perf_counter *hwc, int idx)
466 s64 left = atomic64_read(&hwc->period_left);
467 s64 period = hwc->irq_period;
471 * If we are way outside a reasoable range then just skip forward:
473 if (unlikely(left <= -period)) {
475 atomic64_set(&hwc->period_left, left);
478 if (unlikely(left <= 0)) {
480 atomic64_set(&hwc->period_left, left);
483 per_cpu(prev_left[idx], smp_processor_id()) = left;
486 * The hw counter starts counting from this counter offset,
487 * mark it to be able to extra future deltas:
489 atomic64_set(&hwc->prev_count, (u64)-left);
491 err = checking_wrmsrl(hwc->counter_base + idx,
492 (u64)(-left) & x86_pmu.counter_mask);
496 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
498 int idx = __idx - X86_PMC_IDX_FIXED;
499 u64 ctrl_val, bits, mask;
503 * Enable IRQ generation (0x8),
504 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
508 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
510 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
513 mask = 0xfULL << (idx * 4);
515 rdmsrl(hwc->config_base, ctrl_val);
518 err = checking_wrmsrl(hwc->config_base, ctrl_val);
521 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
523 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
524 intel_pmu_enable_fixed(hwc, idx);
528 x86_pmu_enable_counter(hwc, idx);
531 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
533 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
536 x86_pmu_enable_counter(hwc, idx);
538 x86_pmu_disable_counter(hwc, idx);
542 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
546 if (!x86_pmu.num_counters_fixed)
549 if (unlikely(hwc->nmi))
552 event = hwc->config & ARCH_PERFMON_EVENT_MASK;
554 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
555 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
556 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES)))
557 return X86_PMC_IDX_FIXED_CPU_CYCLES;
558 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES)))
559 return X86_PMC_IDX_FIXED_BUS_CYCLES;
565 * Find a PMC slot for the freshly enabled / scheduled in counter:
567 static int x86_pmu_enable(struct perf_counter *counter)
569 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
570 struct hw_perf_counter *hwc = &counter->hw;
573 idx = fixed_mode_idx(counter, hwc);
576 * Try to get the fixed counter, if that is already taken
577 * then try to get a generic counter:
579 if (test_and_set_bit(idx, cpuc->used_mask))
582 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
584 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
585 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
588 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
592 /* Try to get the previous generic counter again */
593 if (test_and_set_bit(idx, cpuc->used_mask)) {
595 idx = find_first_zero_bit(cpuc->used_mask,
596 x86_pmu.num_counters);
597 if (idx == x86_pmu.num_counters)
600 set_bit(idx, cpuc->used_mask);
603 hwc->config_base = x86_pmu.eventsel;
604 hwc->counter_base = x86_pmu.perfctr;
607 perf_counters_lapic_init(hwc->nmi);
609 x86_pmu.disable(hwc, idx);
611 cpuc->counters[idx] = counter;
612 set_bit(idx, cpuc->active_mask);
614 x86_perf_counter_set_period(counter, hwc, idx);
615 x86_pmu.enable(hwc, idx);
620 void perf_counter_print_debug(void)
622 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
623 struct cpu_hw_counters *cpuc;
627 if (!x86_pmu.num_counters)
630 local_irq_save(flags);
632 cpu = smp_processor_id();
633 cpuc = &per_cpu(cpu_hw_counters, cpu);
635 if (x86_pmu.version >= 2) {
636 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
637 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
638 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
639 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
642 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
643 pr_info("CPU#%d: status: %016llx\n", cpu, status);
644 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
645 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
647 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
649 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
650 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
651 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
653 prev_left = per_cpu(prev_left[idx], cpu);
655 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
657 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
658 cpu, idx, pmc_count);
659 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
660 cpu, idx, prev_left);
662 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
663 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
665 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
666 cpu, idx, pmc_count);
668 local_irq_restore(flags);
671 static void x86_pmu_disable(struct perf_counter *counter)
673 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
674 struct hw_perf_counter *hwc = &counter->hw;
678 * Must be done before we disable, otherwise the nmi handler
679 * could reenable again:
681 clear_bit(idx, cpuc->active_mask);
682 x86_pmu.disable(hwc, idx);
685 * Make sure the cleared pointer becomes visible before we
686 * (potentially) free the counter:
691 * Drain the remaining delta count out of a counter
692 * that we are disabling:
694 x86_perf_counter_update(counter, hwc, idx);
695 cpuc->counters[idx] = NULL;
696 clear_bit(idx, cpuc->used_mask);
700 * Save and restart an expired counter. Called by NMI contexts,
701 * so it has to be careful about preempting normal counter ops:
703 static void intel_pmu_save_and_restart(struct perf_counter *counter)
705 struct hw_perf_counter *hwc = &counter->hw;
708 x86_perf_counter_update(counter, hwc, idx);
709 x86_perf_counter_set_period(counter, hwc, idx);
711 if (counter->state == PERF_COUNTER_STATE_ACTIVE)
712 intel_pmu_enable_counter(hwc, idx);
716 * Maximum interrupt frequency of 100KHz per CPU
718 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
721 * This handler is triggered by the local APIC, so the APIC IRQ handling
724 static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
726 int bit, cpu = smp_processor_id();
728 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
731 cpuc->throttle_ctrl = intel_pmu_save_disable_all();
733 status = intel_pmu_get_status();
739 inc_irq_stat(apic_perf_irqs);
741 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
742 struct perf_counter *counter = cpuc->counters[bit];
744 clear_bit(bit, (unsigned long *) &status);
745 if (!test_bit(bit, cpuc->active_mask))
748 intel_pmu_save_and_restart(counter);
749 if (perf_counter_overflow(counter, nmi, regs, 0))
750 intel_pmu_disable_counter(&counter->hw, bit);
753 intel_pmu_ack_status(ack);
756 * Repeat if there is more work to be done:
758 status = intel_pmu_get_status();
763 * Restore - do not reenable when global enable is off or throttled:
765 if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS)
766 intel_pmu_restore_all(cpuc->throttle_ctrl);
771 static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
773 int cpu = smp_processor_id();
774 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
777 struct perf_counter *counter;
778 struct hw_perf_counter *hwc;
782 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
783 if (!test_bit(idx, cpuc->active_mask))
785 counter = cpuc->counters[idx];
787 val = x86_perf_counter_update(counter, hwc, idx);
788 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
790 /* counter overflow */
791 x86_perf_counter_set_period(counter, hwc, idx);
793 inc_irq_stat(apic_perf_irqs);
794 if (perf_counter_overflow(counter, nmi, regs, 0))
795 amd_pmu_disable_counter(hwc, idx);
796 else if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS)
798 * do not reenable when throttled, but reload
801 amd_pmu_disable_counter(hwc, idx);
802 else if (counter->state == PERF_COUNTER_STATE_ACTIVE)
803 amd_pmu_enable_counter(hwc, idx);
808 void perf_counter_unthrottle(void)
810 struct cpu_hw_counters *cpuc;
812 if (!x86_pmu_initialized())
815 cpuc = &__get_cpu_var(cpu_hw_counters);
816 if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
817 if (printk_ratelimit())
818 printk(KERN_WARNING "perfcounters: max interrupts exceeded!\n");
819 hw_perf_restore(cpuc->throttle_ctrl);
821 cpuc->interrupts = 0;
824 void smp_perf_counter_interrupt(struct pt_regs *regs)
827 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
829 x86_pmu.handle_irq(regs, 0);
833 void smp_perf_pending_interrupt(struct pt_regs *regs)
837 inc_irq_stat(apic_pending_irqs);
838 perf_counter_do_pending();
842 void set_perf_counter_pending(void)
844 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
847 void perf_counters_lapic_init(int nmi)
851 if (!x86_pmu_initialized())
855 * Enable the performance counter vector in the APIC LVT:
857 apic_val = apic_read(APIC_LVTERR);
859 apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
861 apic_write(APIC_LVTPC, APIC_DM_NMI);
863 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
864 apic_write(APIC_LVTERR, apic_val);
868 perf_counter_nmi_handler(struct notifier_block *self,
869 unsigned long cmd, void *__args)
871 struct die_args *args = __args;
872 struct pt_regs *regs;
875 if (!atomic_read(&active_counters))
889 apic_write(APIC_LVTPC, APIC_DM_NMI);
890 ret = x86_pmu.handle_irq(regs, 1);
892 return ret ? NOTIFY_STOP : NOTIFY_OK;
895 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
896 .notifier_call = perf_counter_nmi_handler,
901 static struct x86_pmu intel_pmu = {
903 .handle_irq = intel_pmu_handle_irq,
904 .save_disable_all = intel_pmu_save_disable_all,
905 .restore_all = intel_pmu_restore_all,
906 .enable = intel_pmu_enable_counter,
907 .disable = intel_pmu_disable_counter,
908 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
909 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
910 .event_map = intel_pmu_event_map,
911 .raw_event = intel_pmu_raw_event,
912 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
914 * Intel PMCs cannot be accessed sanely above 32 bit width,
915 * so we install an artificial 1<<31 period regardless of
916 * the generic counter period:
918 .max_period = (1ULL << 31) - 1,
921 static struct x86_pmu amd_pmu = {
923 .handle_irq = amd_pmu_handle_irq,
924 .save_disable_all = amd_pmu_save_disable_all,
925 .restore_all = amd_pmu_restore_all,
926 .enable = amd_pmu_enable_counter,
927 .disable = amd_pmu_disable_counter,
928 .eventsel = MSR_K7_EVNTSEL0,
929 .perfctr = MSR_K7_PERFCTR0,
930 .event_map = amd_pmu_event_map,
931 .raw_event = amd_pmu_raw_event,
932 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
935 .counter_mask = (1ULL << 48) - 1,
936 /* use highest bit to detect overflow */
937 .max_period = (1ULL << 47) - 1,
940 static int intel_pmu_init(void)
942 union cpuid10_edx edx;
943 union cpuid10_eax eax;
948 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
952 * Check whether the Architectural PerfMon supports
953 * Branch Misses Retired Event or not.
955 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
956 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
959 version = eax.split.version_id;
964 x86_pmu.version = version;
965 x86_pmu.num_counters = eax.split.num_counters;
968 * Quirk: v2 perfmon does not report fixed-purpose counters, so
969 * assume at least 3 counters:
971 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
973 x86_pmu.counter_bits = eax.split.bit_width;
974 x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
979 static int amd_pmu_init(void)
985 void __init init_hw_perf_counters(void)
989 switch (boot_cpu_data.x86_vendor) {
990 case X86_VENDOR_INTEL:
991 err = intel_pmu_init();
994 err = amd_pmu_init();
1002 pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name);
1003 pr_info("... version: %d\n", x86_pmu.version);
1004 pr_info("... bit width: %d\n", x86_pmu.counter_bits);
1006 pr_info("... num counters: %d\n", x86_pmu.num_counters);
1007 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1008 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1009 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
1010 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1012 perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
1013 perf_max_counters = x86_pmu.num_counters;
1015 pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask);
1016 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1018 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1019 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1020 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1021 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1023 pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed);
1025 perf_counter_mask |=
1026 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1028 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
1030 perf_counters_lapic_init(0);
1031 register_die_notifier(&perf_counter_nmi_notifier);
1034 static inline void x86_pmu_read(struct perf_counter *counter)
1036 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1039 static const struct pmu pmu = {
1040 .enable = x86_pmu_enable,
1041 .disable = x86_pmu_disable,
1042 .read = x86_pmu_read,
1045 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1049 err = __hw_perf_counter_init(counter);
1051 return ERR_PTR(err);
1061 void callchain_store(struct perf_callchain_entry *entry, unsigned long ip)
1063 if (entry->nr < MAX_STACK_DEPTH)
1064 entry->ip[entry->nr++] = ip;
1067 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1068 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1072 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1074 /* Ignore warnings */
1077 static void backtrace_warning(void *data, char *msg)
1079 /* Ignore warnings */
1082 static int backtrace_stack(void *data, char *name)
1084 /* Don't bother with IRQ stacks for now */
1088 static void backtrace_address(void *data, unsigned long addr, int reliable)
1090 struct perf_callchain_entry *entry = data;
1093 callchain_store(entry, addr);
1096 static const struct stacktrace_ops backtrace_ops = {
1097 .warning = backtrace_warning,
1098 .warning_symbol = backtrace_warning_symbol,
1099 .stack = backtrace_stack,
1100 .address = backtrace_address,
1104 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1110 callchain_store(entry, instruction_pointer(regs));
1112 stack = ((char *)regs + sizeof(struct pt_regs));
1113 #ifdef CONFIG_FRAME_POINTER
1114 bp = frame_pointer(regs);
1119 dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry);
1121 entry->kernel = entry->nr - nr;
1125 struct stack_frame {
1126 const void __user *next_fp;
1127 unsigned long return_address;
1130 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1134 if (!access_ok(VERIFY_READ, fp, sizeof(*frame)))
1138 pagefault_disable();
1139 if (__copy_from_user_inatomic(frame, fp, sizeof(*frame)))
1147 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1149 struct stack_frame frame;
1150 const void __user *fp;
1153 regs = (struct pt_regs *)current->thread.sp0 - 1;
1154 fp = (void __user *)regs->bp;
1156 callchain_store(entry, regs->ip);
1158 while (entry->nr < MAX_STACK_DEPTH) {
1159 frame.next_fp = NULL;
1160 frame.return_address = 0;
1162 if (!copy_stack_frame(fp, &frame))
1165 if ((unsigned long)fp < user_stack_pointer(regs))
1168 callchain_store(entry, frame.return_address);
1172 entry->user = entry->nr - nr;
1176 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1183 is_user = user_mode(regs);
1185 if (!current || current->pid == 0)
1188 if (is_user && current->state != TASK_RUNNING)
1192 perf_callchain_kernel(regs, entry);
1195 perf_callchain_user(regs, entry);
1198 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1200 struct perf_callchain_entry *entry;
1203 entry = &__get_cpu_var(nmi_entry);
1205 entry = &__get_cpu_var(irq_entry);
1212 perf_do_callchain(regs, entry);