2 * Performance counter x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
10 * For licencing details see kernel-base/COPYING
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
24 #include <asm/stacktrace.h>
27 static u64 perf_counter_mask __read_mostly;
29 struct cpu_hw_counters {
30 struct perf_counter *counters[X86_PMC_IDX_MAX];
31 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
32 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
33 unsigned long interrupts;
39 * struct x86_pmu - generic x86 pmu
44 int (*handle_irq)(struct pt_regs *, int);
45 u64 (*save_disable_all)(void);
46 void (*restore_all)(u64);
47 void (*enable)(struct hw_perf_counter *, int);
48 void (*disable)(struct hw_perf_counter *, int);
51 u64 (*event_map)(int);
52 u64 (*raw_event)(u64);
55 int num_counters_fixed;
61 static struct x86_pmu x86_pmu __read_mostly;
63 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
68 * Intel PerfMon v3. Used on Core2 and later.
70 static const u64 intel_perfmon_event_map[] =
72 [PERF_COUNT_CPU_CYCLES] = 0x003c,
73 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
74 [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
75 [PERF_COUNT_CACHE_MISSES] = 0x412e,
76 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
77 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
78 [PERF_COUNT_BUS_CYCLES] = 0x013c,
81 static u64 intel_pmu_event_map(int event)
83 return intel_perfmon_event_map[event];
86 static u64 intel_pmu_raw_event(u64 event)
88 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
89 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
90 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
92 #define CORE_EVNTSEL_MASK \
93 (CORE_EVNTSEL_EVENT_MASK | \
94 CORE_EVNTSEL_UNIT_MASK | \
95 CORE_EVNTSEL_COUNTER_MASK)
97 return event & CORE_EVNTSEL_MASK;
101 * AMD Performance Monitor K7 and later.
103 static const u64 amd_perfmon_event_map[] =
105 [PERF_COUNT_CPU_CYCLES] = 0x0076,
106 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
107 [PERF_COUNT_CACHE_REFERENCES] = 0x0080,
108 [PERF_COUNT_CACHE_MISSES] = 0x0081,
109 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
110 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
113 static u64 amd_pmu_event_map(int event)
115 return amd_perfmon_event_map[event];
118 static u64 amd_pmu_raw_event(u64 event)
120 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
121 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
122 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
124 #define K7_EVNTSEL_MASK \
125 (K7_EVNTSEL_EVENT_MASK | \
126 K7_EVNTSEL_UNIT_MASK | \
127 K7_EVNTSEL_COUNTER_MASK)
129 return event & K7_EVNTSEL_MASK;
133 * Propagate counter elapsed time into the generic counter.
134 * Can only be executed on the CPU where the counter is active.
135 * Returns the delta events processed.
138 x86_perf_counter_update(struct perf_counter *counter,
139 struct hw_perf_counter *hwc, int idx)
141 int shift = 64 - x86_pmu.counter_bits;
142 u64 prev_raw_count, new_raw_count;
146 * Careful: an NMI might modify the previous counter value.
148 * Our tactic to handle this is to first atomically read and
149 * exchange a new raw count - then add that new-prev delta
150 * count to the generic counter atomically:
153 prev_raw_count = atomic64_read(&hwc->prev_count);
154 rdmsrl(hwc->counter_base + idx, new_raw_count);
156 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
157 new_raw_count) != prev_raw_count)
161 * Now we have the new raw value and have updated the prev
162 * timestamp already. We can now calculate the elapsed delta
163 * (counter-)time and add that to the generic counter.
165 * Careful, not all hw sign-extends above the physical width
168 delta = (new_raw_count << shift) - (prev_raw_count << shift);
171 atomic64_add(delta, &counter->count);
172 atomic64_sub(delta, &hwc->period_left);
174 return new_raw_count;
177 static atomic_t active_counters;
178 static DEFINE_MUTEX(pmc_reserve_mutex);
180 static bool reserve_pmc_hardware(void)
184 if (nmi_watchdog == NMI_LOCAL_APIC)
185 disable_lapic_nmi_watchdog();
187 for (i = 0; i < x86_pmu.num_counters; i++) {
188 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
192 for (i = 0; i < x86_pmu.num_counters; i++) {
193 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
200 for (i--; i >= 0; i--)
201 release_evntsel_nmi(x86_pmu.eventsel + i);
203 i = x86_pmu.num_counters;
206 for (i--; i >= 0; i--)
207 release_perfctr_nmi(x86_pmu.perfctr + i);
209 if (nmi_watchdog == NMI_LOCAL_APIC)
210 enable_lapic_nmi_watchdog();
215 static void release_pmc_hardware(void)
219 for (i = 0; i < x86_pmu.num_counters; i++) {
220 release_perfctr_nmi(x86_pmu.perfctr + i);
221 release_evntsel_nmi(x86_pmu.eventsel + i);
224 if (nmi_watchdog == NMI_LOCAL_APIC)
225 enable_lapic_nmi_watchdog();
228 static void hw_perf_counter_destroy(struct perf_counter *counter)
230 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
231 release_pmc_hardware();
232 mutex_unlock(&pmc_reserve_mutex);
236 static inline int x86_pmu_initialized(void)
238 return x86_pmu.handle_irq != NULL;
242 * Setup the hardware configuration for a given hw_event_type
244 static int __hw_perf_counter_init(struct perf_counter *counter)
246 struct perf_counter_hw_event *hw_event = &counter->hw_event;
247 struct hw_perf_counter *hwc = &counter->hw;
250 if (!x86_pmu_initialized())
254 if (!atomic_inc_not_zero(&active_counters)) {
255 mutex_lock(&pmc_reserve_mutex);
256 if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
259 atomic_inc(&active_counters);
260 mutex_unlock(&pmc_reserve_mutex);
267 * (keep 'enabled' bit clear for now)
269 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
272 * Count user and OS events unless requested not to.
274 if (!hw_event->exclude_user)
275 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
276 if (!hw_event->exclude_kernel)
277 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
280 * If privileged enough, allow NMI events:
284 if (sysctl_perf_counter_priv && !capable(CAP_SYS_ADMIN))
289 hwc->irq_period = hw_event->irq_period;
290 if ((s64)hwc->irq_period <= 0 || hwc->irq_period > x86_pmu.max_period)
291 hwc->irq_period = x86_pmu.max_period;
293 atomic64_set(&hwc->period_left, hwc->irq_period);
296 * Raw event type provide the config in the event structure
298 if (perf_event_raw(hw_event)) {
299 hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event));
301 if (perf_event_id(hw_event) >= x86_pmu.max_events)
306 hwc->config |= x86_pmu.event_map(perf_event_id(hw_event));
309 counter->destroy = hw_perf_counter_destroy;
314 static u64 intel_pmu_save_disable_all(void)
318 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
319 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
324 static u64 amd_pmu_save_disable_all(void)
326 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
329 enabled = cpuc->enabled;
332 * ensure we write the disable before we start disabling the
333 * counters proper, so that amd_pmu_enable_counter() does the
340 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
343 if (!test_bit(idx, cpuc->active_mask))
345 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
346 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
348 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
349 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
356 u64 hw_perf_save_disable(void)
358 if (!x86_pmu_initialized())
360 return x86_pmu.save_disable_all();
363 * Exported because of ACPI idle
365 EXPORT_SYMBOL_GPL(hw_perf_save_disable);
367 static void intel_pmu_restore_all(u64 ctrl)
369 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
372 static void amd_pmu_restore_all(u64 ctrl)
374 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
377 cpuc->enabled = ctrl;
382 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
385 if (!test_bit(idx, cpuc->active_mask))
387 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
388 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
390 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
391 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
395 void hw_perf_restore(u64 ctrl)
397 if (!x86_pmu_initialized())
399 x86_pmu.restore_all(ctrl);
402 * Exported because of ACPI idle
404 EXPORT_SYMBOL_GPL(hw_perf_restore);
406 static inline u64 intel_pmu_get_status(void)
410 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
415 static inline void intel_pmu_ack_status(u64 ack)
417 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
420 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
423 err = checking_wrmsrl(hwc->config_base + idx,
424 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
427 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
430 err = checking_wrmsrl(hwc->config_base + idx,
435 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
437 int idx = __idx - X86_PMC_IDX_FIXED;
441 mask = 0xfULL << (idx * 4);
443 rdmsrl(hwc->config_base, ctrl_val);
445 err = checking_wrmsrl(hwc->config_base, ctrl_val);
449 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
451 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
452 intel_pmu_disable_fixed(hwc, idx);
456 x86_pmu_disable_counter(hwc, idx);
460 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
462 x86_pmu_disable_counter(hwc, idx);
465 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
468 * Set the next IRQ period, based on the hwc->period_left value.
469 * To be called with the counter disabled in hw:
472 x86_perf_counter_set_period(struct perf_counter *counter,
473 struct hw_perf_counter *hwc, int idx)
475 s64 left = atomic64_read(&hwc->period_left);
476 s64 period = hwc->irq_period;
480 * If we are way outside a reasoable range then just skip forward:
482 if (unlikely(left <= -period)) {
484 atomic64_set(&hwc->period_left, left);
487 if (unlikely(left <= 0)) {
489 atomic64_set(&hwc->period_left, left);
492 per_cpu(prev_left[idx], smp_processor_id()) = left;
495 * The hw counter starts counting from this counter offset,
496 * mark it to be able to extra future deltas:
498 atomic64_set(&hwc->prev_count, (u64)-left);
500 err = checking_wrmsrl(hwc->counter_base + idx,
501 (u64)(-left) & x86_pmu.counter_mask);
505 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
507 int idx = __idx - X86_PMC_IDX_FIXED;
508 u64 ctrl_val, bits, mask;
512 * Enable IRQ generation (0x8),
513 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
517 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
519 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
522 mask = 0xfULL << (idx * 4);
524 rdmsrl(hwc->config_base, ctrl_val);
527 err = checking_wrmsrl(hwc->config_base, ctrl_val);
530 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
532 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
533 intel_pmu_enable_fixed(hwc, idx);
537 x86_pmu_enable_counter(hwc, idx);
540 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
542 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
545 x86_pmu_enable_counter(hwc, idx);
547 x86_pmu_disable_counter(hwc, idx);
551 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
555 if (!x86_pmu.num_counters_fixed)
558 if (unlikely(hwc->nmi))
561 event = hwc->config & ARCH_PERFMON_EVENT_MASK;
563 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
564 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
565 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES)))
566 return X86_PMC_IDX_FIXED_CPU_CYCLES;
567 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES)))
568 return X86_PMC_IDX_FIXED_BUS_CYCLES;
574 * Find a PMC slot for the freshly enabled / scheduled in counter:
576 static int x86_pmu_enable(struct perf_counter *counter)
578 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
579 struct hw_perf_counter *hwc = &counter->hw;
582 idx = fixed_mode_idx(counter, hwc);
585 * Try to get the fixed counter, if that is already taken
586 * then try to get a generic counter:
588 if (test_and_set_bit(idx, cpuc->used_mask))
591 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
593 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
594 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
597 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
601 /* Try to get the previous generic counter again */
602 if (test_and_set_bit(idx, cpuc->used_mask)) {
604 idx = find_first_zero_bit(cpuc->used_mask,
605 x86_pmu.num_counters);
606 if (idx == x86_pmu.num_counters)
609 set_bit(idx, cpuc->used_mask);
612 hwc->config_base = x86_pmu.eventsel;
613 hwc->counter_base = x86_pmu.perfctr;
616 perf_counters_lapic_init(hwc->nmi);
618 x86_pmu.disable(hwc, idx);
620 cpuc->counters[idx] = counter;
621 set_bit(idx, cpuc->active_mask);
623 x86_perf_counter_set_period(counter, hwc, idx);
624 x86_pmu.enable(hwc, idx);
629 void perf_counter_print_debug(void)
631 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
632 struct cpu_hw_counters *cpuc;
636 if (!x86_pmu.num_counters)
639 local_irq_save(flags);
641 cpu = smp_processor_id();
642 cpuc = &per_cpu(cpu_hw_counters, cpu);
644 if (x86_pmu.version >= 2) {
645 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
646 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
647 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
648 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
651 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
652 pr_info("CPU#%d: status: %016llx\n", cpu, status);
653 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
654 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
656 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
658 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
659 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
660 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
662 prev_left = per_cpu(prev_left[idx], cpu);
664 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
666 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
667 cpu, idx, pmc_count);
668 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
669 cpu, idx, prev_left);
671 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
672 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
674 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
675 cpu, idx, pmc_count);
677 local_irq_restore(flags);
680 static void x86_pmu_disable(struct perf_counter *counter)
682 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
683 struct hw_perf_counter *hwc = &counter->hw;
687 * Must be done before we disable, otherwise the nmi handler
688 * could reenable again:
690 clear_bit(idx, cpuc->active_mask);
691 x86_pmu.disable(hwc, idx);
694 * Make sure the cleared pointer becomes visible before we
695 * (potentially) free the counter:
700 * Drain the remaining delta count out of a counter
701 * that we are disabling:
703 x86_perf_counter_update(counter, hwc, idx);
704 cpuc->counters[idx] = NULL;
705 clear_bit(idx, cpuc->used_mask);
709 * Save and restart an expired counter. Called by NMI contexts,
710 * so it has to be careful about preempting normal counter ops:
712 static void intel_pmu_save_and_restart(struct perf_counter *counter)
714 struct hw_perf_counter *hwc = &counter->hw;
717 x86_perf_counter_update(counter, hwc, idx);
718 x86_perf_counter_set_period(counter, hwc, idx);
720 if (counter->state == PERF_COUNTER_STATE_ACTIVE)
721 intel_pmu_enable_counter(hwc, idx);
725 * Maximum interrupt frequency of 100KHz per CPU
727 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
730 * This handler is triggered by the local APIC, so the APIC IRQ handling
733 static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
735 int bit, cpu = smp_processor_id();
737 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
740 cpuc->throttle_ctrl = intel_pmu_save_disable_all();
742 status = intel_pmu_get_status();
748 inc_irq_stat(apic_perf_irqs);
750 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
751 struct perf_counter *counter = cpuc->counters[bit];
753 clear_bit(bit, (unsigned long *) &status);
754 if (!test_bit(bit, cpuc->active_mask))
757 intel_pmu_save_and_restart(counter);
758 if (perf_counter_overflow(counter, nmi, regs, 0))
759 intel_pmu_disable_counter(&counter->hw, bit);
762 intel_pmu_ack_status(ack);
765 * Repeat if there is more work to be done:
767 status = intel_pmu_get_status();
772 * Restore - do not reenable when global enable is off or throttled:
774 if (cpuc->throttle_ctrl) {
775 if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS) {
776 intel_pmu_restore_all(cpuc->throttle_ctrl);
778 pr_info("CPU#%d: perfcounters: max interrupt rate exceeded! Throttle on.\n", smp_processor_id());
785 static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
787 int cpu = smp_processor_id();
788 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
791 struct perf_counter *counter;
792 struct hw_perf_counter *hwc;
793 int idx, throttle = 0;
795 cpuc->throttle_ctrl = cpuc->enabled;
799 if (cpuc->throttle_ctrl) {
800 if (++cpuc->interrupts >= PERFMON_MAX_INTERRUPTS)
804 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
807 if (!test_bit(idx, cpuc->active_mask))
810 counter = cpuc->counters[idx];
812 val = x86_perf_counter_update(counter, hwc, idx);
813 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
816 /* counter overflow */
817 x86_perf_counter_set_period(counter, hwc, idx);
819 inc_irq_stat(apic_perf_irqs);
820 disable = perf_counter_overflow(counter, nmi, regs, 0);
823 if (disable || throttle)
824 amd_pmu_disable_counter(hwc, idx);
827 if (cpuc->throttle_ctrl && !throttle)
833 void perf_counter_unthrottle(void)
835 struct cpu_hw_counters *cpuc;
837 if (!x86_pmu_initialized())
840 cpuc = &__get_cpu_var(cpu_hw_counters);
841 if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
842 pr_info("CPU#%d: perfcounters: throttle off.\n", smp_processor_id());
845 * Clear them before re-enabling irqs/NMIs again:
847 cpuc->interrupts = 0;
848 hw_perf_restore(cpuc->throttle_ctrl);
850 cpuc->interrupts = 0;
854 void smp_perf_counter_interrupt(struct pt_regs *regs)
857 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
859 x86_pmu.handle_irq(regs, 0);
863 void smp_perf_pending_interrupt(struct pt_regs *regs)
867 inc_irq_stat(apic_pending_irqs);
868 perf_counter_do_pending();
872 void set_perf_counter_pending(void)
874 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
877 void perf_counters_lapic_init(int nmi)
881 if (!x86_pmu_initialized())
885 * Enable the performance counter vector in the APIC LVT:
887 apic_val = apic_read(APIC_LVTERR);
889 apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
891 apic_write(APIC_LVTPC, APIC_DM_NMI);
893 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
894 apic_write(APIC_LVTERR, apic_val);
898 perf_counter_nmi_handler(struct notifier_block *self,
899 unsigned long cmd, void *__args)
901 struct die_args *args = __args;
902 struct pt_regs *regs;
905 if (!atomic_read(&active_counters))
919 apic_write(APIC_LVTPC, APIC_DM_NMI);
920 ret = x86_pmu.handle_irq(regs, 1);
922 return ret ? NOTIFY_STOP : NOTIFY_OK;
925 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
926 .notifier_call = perf_counter_nmi_handler,
931 static struct x86_pmu intel_pmu = {
933 .handle_irq = intel_pmu_handle_irq,
934 .save_disable_all = intel_pmu_save_disable_all,
935 .restore_all = intel_pmu_restore_all,
936 .enable = intel_pmu_enable_counter,
937 .disable = intel_pmu_disable_counter,
938 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
939 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
940 .event_map = intel_pmu_event_map,
941 .raw_event = intel_pmu_raw_event,
942 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
944 * Intel PMCs cannot be accessed sanely above 32 bit width,
945 * so we install an artificial 1<<31 period regardless of
946 * the generic counter period:
948 .max_period = (1ULL << 31) - 1,
951 static struct x86_pmu amd_pmu = {
953 .handle_irq = amd_pmu_handle_irq,
954 .save_disable_all = amd_pmu_save_disable_all,
955 .restore_all = amd_pmu_restore_all,
956 .enable = amd_pmu_enable_counter,
957 .disable = amd_pmu_disable_counter,
958 .eventsel = MSR_K7_EVNTSEL0,
959 .perfctr = MSR_K7_PERFCTR0,
960 .event_map = amd_pmu_event_map,
961 .raw_event = amd_pmu_raw_event,
962 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
965 .counter_mask = (1ULL << 48) - 1,
966 /* use highest bit to detect overflow */
967 .max_period = (1ULL << 47) - 1,
970 static int intel_pmu_init(void)
972 union cpuid10_edx edx;
973 union cpuid10_eax eax;
978 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
982 * Check whether the Architectural PerfMon supports
983 * Branch Misses Retired Event or not.
985 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
986 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
989 version = eax.split.version_id;
994 x86_pmu.version = version;
995 x86_pmu.num_counters = eax.split.num_counters;
998 * Quirk: v2 perfmon does not report fixed-purpose counters, so
999 * assume at least 3 counters:
1001 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
1003 x86_pmu.counter_bits = eax.split.bit_width;
1004 x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
1009 static int amd_pmu_init(void)
1015 void __init init_hw_perf_counters(void)
1019 switch (boot_cpu_data.x86_vendor) {
1020 case X86_VENDOR_INTEL:
1021 err = intel_pmu_init();
1023 case X86_VENDOR_AMD:
1024 err = amd_pmu_init();
1032 pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name);
1033 pr_info("... version: %d\n", x86_pmu.version);
1034 pr_info("... bit width: %d\n", x86_pmu.counter_bits);
1036 pr_info("... num counters: %d\n", x86_pmu.num_counters);
1037 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1038 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1039 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
1040 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1042 perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
1043 perf_max_counters = x86_pmu.num_counters;
1045 pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask);
1046 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1048 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1049 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1050 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1051 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1053 pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed);
1055 perf_counter_mask |=
1056 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1058 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
1060 perf_counters_lapic_init(0);
1061 register_die_notifier(&perf_counter_nmi_notifier);
1064 static inline void x86_pmu_read(struct perf_counter *counter)
1066 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1069 static const struct pmu pmu = {
1070 .enable = x86_pmu_enable,
1071 .disable = x86_pmu_disable,
1072 .read = x86_pmu_read,
1075 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1079 err = __hw_perf_counter_init(counter);
1081 return ERR_PTR(err);
1091 void callchain_store(struct perf_callchain_entry *entry, unsigned long ip)
1093 if (entry->nr < MAX_STACK_DEPTH)
1094 entry->ip[entry->nr++] = ip;
1097 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1098 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1102 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1104 /* Ignore warnings */
1107 static void backtrace_warning(void *data, char *msg)
1109 /* Ignore warnings */
1112 static int backtrace_stack(void *data, char *name)
1114 /* Don't bother with IRQ stacks for now */
1118 static void backtrace_address(void *data, unsigned long addr, int reliable)
1120 struct perf_callchain_entry *entry = data;
1123 callchain_store(entry, addr);
1126 static const struct stacktrace_ops backtrace_ops = {
1127 .warning = backtrace_warning,
1128 .warning_symbol = backtrace_warning_symbol,
1129 .stack = backtrace_stack,
1130 .address = backtrace_address,
1134 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1140 callchain_store(entry, instruction_pointer(regs));
1142 stack = ((char *)regs + sizeof(struct pt_regs));
1143 #ifdef CONFIG_FRAME_POINTER
1144 bp = frame_pointer(regs);
1149 dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry);
1151 entry->kernel = entry->nr - nr;
1155 struct stack_frame {
1156 const void __user *next_fp;
1157 unsigned long return_address;
1160 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1164 if (!access_ok(VERIFY_READ, fp, sizeof(*frame)))
1168 pagefault_disable();
1169 if (__copy_from_user_inatomic(frame, fp, sizeof(*frame)))
1177 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1179 struct stack_frame frame;
1180 const void __user *fp;
1183 regs = (struct pt_regs *)current->thread.sp0 - 1;
1184 fp = (void __user *)regs->bp;
1186 callchain_store(entry, regs->ip);
1188 while (entry->nr < MAX_STACK_DEPTH) {
1189 frame.next_fp = NULL;
1190 frame.return_address = 0;
1192 if (!copy_stack_frame(fp, &frame))
1195 if ((unsigned long)fp < user_stack_pointer(regs))
1198 callchain_store(entry, frame.return_address);
1202 entry->user = entry->nr - nr;
1206 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1213 is_user = user_mode(regs);
1215 if (!current || current->pid == 0)
1218 if (is_user && current->state != TASK_RUNNING)
1222 perf_callchain_kernel(regs, entry);
1225 perf_callchain_user(regs, entry);
1228 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1230 struct perf_callchain_entry *entry;
1233 entry = &__get_cpu_var(nmi_entry);
1235 entry = &__get_cpu_var(irq_entry);
1242 perf_do_callchain(regs, entry);