2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
51 unsigned long offset, addr = (unsigned long)from;
52 int type = in_nmi() ? KM_NMI : KM_IRQ0;
53 unsigned long size, len = 0;
59 ret = __get_user_pages_fast(addr, 1, 0, &page);
63 offset = addr & (PAGE_SIZE - 1);
64 size = min(PAGE_SIZE - offset, n - len);
66 map = kmap_atomic(page, type);
67 memcpy(to, map+offset, size);
68 kunmap_atomic(map, type);
80 struct event_constraint {
82 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
91 int nb_id; /* NorthBridge id */
92 int refcnt; /* reference count */
93 struct perf_event *owners[X86_PMC_IDX_MAX];
94 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
97 #define MAX_LBR_ENTRIES 16
99 struct cpu_hw_events {
101 * Generic x86 PMC bits
103 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
104 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
105 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
111 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
112 u64 tags[X86_PMC_IDX_MAX];
113 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
115 unsigned int group_flag;
118 * Intel DebugStore bits
120 struct debug_store *ds;
128 struct perf_branch_stack lbr_stack;
129 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
134 struct amd_nb *amd_nb;
137 #define __EVENT_CONSTRAINT(c, n, m, w) {\
138 { .idxmsk64 = (n) }, \
144 #define EVENT_CONSTRAINT(c, n, m) \
145 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
148 * Constraint on the Event code.
150 #define INTEL_EVENT_CONSTRAINT(c, n) \
151 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
154 * Constraint on the Event code + UMask + fixed-mask
156 * filter mask to validate fixed counter events.
157 * the following filters disqualify for fixed counters:
161 * The other filters are supported by fixed counters.
162 * The any-thread option is supported starting with v3.
164 #define FIXED_EVENT_CONSTRAINT(c, n) \
165 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
168 * Constraint on the Event code + UMask
170 #define PEBS_EVENT_CONSTRAINT(c, n) \
171 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
173 #define EVENT_CONSTRAINT_END \
174 EVENT_CONSTRAINT(0, 0, 0)
176 #define for_each_event_constraint(e, c) \
177 for ((e) = (c); (e)->weight; (e)++)
179 union perf_capabilities {
183 u64 pebs_arch_reg : 1;
191 * struct x86_pmu - generic x86 pmu
195 * Generic x86 PMC bits
199 int (*handle_irq)(struct pt_regs *);
200 void (*disable_all)(void);
201 void (*enable_all)(int added);
202 void (*enable)(struct perf_event *);
203 void (*disable)(struct perf_event *);
204 int (*hw_config)(struct perf_event *event);
205 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
208 u64 (*event_map)(int);
211 int num_counters_fixed;
216 struct event_constraint *
217 (*get_event_constraints)(struct cpu_hw_events *cpuc,
218 struct perf_event *event);
220 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
221 struct perf_event *event);
222 struct event_constraint *event_constraints;
223 void (*quirks)(void);
224 int perfctr_second_write;
226 int (*cpu_prepare)(int cpu);
227 void (*cpu_starting)(int cpu);
228 void (*cpu_dying)(int cpu);
229 void (*cpu_dead)(int cpu);
232 * Intel Arch Perfmon v2+
235 union perf_capabilities intel_cap;
238 * Intel DebugStore bits
241 int pebs_record_size;
242 void (*drain_pebs)(struct pt_regs *regs);
243 struct event_constraint *pebs_constraints;
248 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
249 int lbr_nr; /* hardware stack size */
252 static struct x86_pmu x86_pmu __read_mostly;
254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
258 static int x86_perf_event_set_period(struct perf_event *event);
261 * Generalized hw caching related hw_event table, filled
262 * in on a per model basis. A value of 0 means
263 * 'not supported', -1 means 'hw_event makes no sense on
264 * this CPU', any other value means the raw hw_event
268 #define C(x) PERF_COUNT_HW_CACHE_##x
270 static u64 __read_mostly hw_cache_event_ids
271 [PERF_COUNT_HW_CACHE_MAX]
272 [PERF_COUNT_HW_CACHE_OP_MAX]
273 [PERF_COUNT_HW_CACHE_RESULT_MAX];
276 * Propagate event elapsed time into the generic event.
277 * Can only be executed on the CPU where the event is active.
278 * Returns the delta events processed.
281 x86_perf_event_update(struct perf_event *event)
283 struct hw_perf_event *hwc = &event->hw;
284 int shift = 64 - x86_pmu.cntval_bits;
285 u64 prev_raw_count, new_raw_count;
289 if (idx == X86_PMC_IDX_FIXED_BTS)
293 * Careful: an NMI might modify the previous event value.
295 * Our tactic to handle this is to first atomically read and
296 * exchange a new raw count - then add that new-prev delta
297 * count to the generic event atomically:
300 prev_raw_count = local64_read(&hwc->prev_count);
301 rdmsrl(hwc->event_base + idx, new_raw_count);
303 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
304 new_raw_count) != prev_raw_count)
308 * Now we have the new raw value and have updated the prev
309 * timestamp already. We can now calculate the elapsed delta
310 * (event-)time and add that to the generic event.
312 * Careful, not all hw sign-extends above the physical width
315 delta = (new_raw_count << shift) - (prev_raw_count << shift);
318 local64_add(delta, &event->count);
319 local64_sub(delta, &hwc->period_left);
321 return new_raw_count;
324 static atomic_t active_events;
325 static DEFINE_MUTEX(pmc_reserve_mutex);
327 #ifdef CONFIG_X86_LOCAL_APIC
329 static bool reserve_pmc_hardware(void)
333 if (nmi_watchdog == NMI_LOCAL_APIC)
334 disable_lapic_nmi_watchdog();
336 for (i = 0; i < x86_pmu.num_counters; i++) {
337 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
341 for (i = 0; i < x86_pmu.num_counters; i++) {
342 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
349 for (i--; i >= 0; i--)
350 release_evntsel_nmi(x86_pmu.eventsel + i);
352 i = x86_pmu.num_counters;
355 for (i--; i >= 0; i--)
356 release_perfctr_nmi(x86_pmu.perfctr + i);
358 if (nmi_watchdog == NMI_LOCAL_APIC)
359 enable_lapic_nmi_watchdog();
364 static void release_pmc_hardware(void)
368 for (i = 0; i < x86_pmu.num_counters; i++) {
369 release_perfctr_nmi(x86_pmu.perfctr + i);
370 release_evntsel_nmi(x86_pmu.eventsel + i);
373 if (nmi_watchdog == NMI_LOCAL_APIC)
374 enable_lapic_nmi_watchdog();
379 static bool reserve_pmc_hardware(void) { return true; }
380 static void release_pmc_hardware(void) {}
384 static int reserve_ds_buffers(void);
385 static void release_ds_buffers(void);
387 static void hw_perf_event_destroy(struct perf_event *event)
389 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
390 release_pmc_hardware();
391 release_ds_buffers();
392 mutex_unlock(&pmc_reserve_mutex);
396 static inline int x86_pmu_initialized(void)
398 return x86_pmu.handle_irq != NULL;
402 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
404 unsigned int cache_type, cache_op, cache_result;
407 config = attr->config;
409 cache_type = (config >> 0) & 0xff;
410 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
413 cache_op = (config >> 8) & 0xff;
414 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
417 cache_result = (config >> 16) & 0xff;
418 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
421 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
434 static int x86_setup_perfctr(struct perf_event *event)
436 struct perf_event_attr *attr = &event->attr;
437 struct hw_perf_event *hwc = &event->hw;
440 if (!hwc->sample_period) {
441 hwc->sample_period = x86_pmu.max_period;
442 hwc->last_period = hwc->sample_period;
443 local64_set(&hwc->period_left, hwc->sample_period);
446 * If we have a PMU initialized but no APIC
447 * interrupts, we cannot sample hardware
448 * events (user-space has to fall back and
449 * sample via a hrtimer based software event):
455 if (attr->type == PERF_TYPE_RAW)
458 if (attr->type == PERF_TYPE_HW_CACHE)
459 return set_ext_hw_attr(hwc, attr);
461 if (attr->config >= x86_pmu.max_events)
467 config = x86_pmu.event_map(attr->config);
478 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
479 (hwc->sample_period == 1)) {
480 /* BTS is not supported by this architecture. */
484 /* BTS is currently only allowed for user-mode. */
485 if (!attr->exclude_kernel)
489 hwc->config |= config;
494 static int x86_pmu_hw_config(struct perf_event *event)
496 if (event->attr.precise_ip) {
499 /* Support for constant skid */
503 /* Support for IP fixup */
507 if (event->attr.precise_ip > precise)
513 * (keep 'enabled' bit clear for now)
515 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
518 * Count user and OS events unless requested not to
520 if (!event->attr.exclude_user)
521 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
522 if (!event->attr.exclude_kernel)
523 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
525 if (event->attr.type == PERF_TYPE_RAW)
526 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
528 return x86_setup_perfctr(event);
532 * Setup the hardware configuration for a given attr_type
534 static int __hw_perf_event_init(struct perf_event *event)
538 if (!x86_pmu_initialized())
542 if (!atomic_inc_not_zero(&active_events)) {
543 mutex_lock(&pmc_reserve_mutex);
544 if (atomic_read(&active_events) == 0) {
545 if (!reserve_pmc_hardware())
548 err = reserve_ds_buffers();
550 release_pmc_hardware();
554 atomic_inc(&active_events);
555 mutex_unlock(&pmc_reserve_mutex);
560 event->destroy = hw_perf_event_destroy;
563 event->hw.last_cpu = -1;
564 event->hw.last_tag = ~0ULL;
566 return x86_pmu.hw_config(event);
569 static void x86_pmu_disable_all(void)
571 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
574 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
577 if (!test_bit(idx, cpuc->active_mask))
579 rdmsrl(x86_pmu.eventsel + idx, val);
580 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
582 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
583 wrmsrl(x86_pmu.eventsel + idx, val);
587 void hw_perf_disable(void)
589 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
591 if (!x86_pmu_initialized())
601 x86_pmu.disable_all();
604 static void x86_pmu_enable_all(int added)
606 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
609 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
610 struct perf_event *event = cpuc->events[idx];
613 if (!test_bit(idx, cpuc->active_mask))
616 val = event->hw.config;
617 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
618 wrmsrl(x86_pmu.eventsel + idx, val);
622 static const struct pmu pmu;
624 static inline int is_x86_event(struct perf_event *event)
626 return event->pmu == &pmu;
629 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
631 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
632 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
633 int i, j, w, wmax, num = 0;
634 struct hw_perf_event *hwc;
636 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
638 for (i = 0; i < n; i++) {
639 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
644 * fastpath, try to reuse previous register
646 for (i = 0; i < n; i++) {
647 hwc = &cpuc->event_list[i]->hw;
654 /* constraint still honored */
655 if (!test_bit(hwc->idx, c->idxmsk))
658 /* not already used */
659 if (test_bit(hwc->idx, used_mask))
662 __set_bit(hwc->idx, used_mask);
664 assign[i] = hwc->idx;
673 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
676 * weight = number of possible counters
678 * 1 = most constrained, only works on one counter
679 * wmax = least constrained, works on any counter
681 * assign events to counters starting with most
682 * constrained events.
684 wmax = x86_pmu.num_counters;
687 * when fixed event counters are present,
688 * wmax is incremented by 1 to account
689 * for one more choice
691 if (x86_pmu.num_counters_fixed)
694 for (w = 1, num = n; num && w <= wmax; w++) {
696 for (i = 0; num && i < n; i++) {
698 hwc = &cpuc->event_list[i]->hw;
703 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
704 if (!test_bit(j, used_mask))
708 if (j == X86_PMC_IDX_MAX)
711 __set_bit(j, used_mask);
720 * scheduling failed or is just a simulation,
721 * free resources if necessary
723 if (!assign || num) {
724 for (i = 0; i < n; i++) {
725 if (x86_pmu.put_event_constraints)
726 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
729 return num ? -ENOSPC : 0;
733 * dogrp: true if must collect siblings events (group)
734 * returns total number of events and error code
736 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
738 struct perf_event *event;
741 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
743 /* current number of events already accepted */
746 if (is_x86_event(leader)) {
749 cpuc->event_list[n] = leader;
755 list_for_each_entry(event, &leader->sibling_list, group_entry) {
756 if (!is_x86_event(event) ||
757 event->state <= PERF_EVENT_STATE_OFF)
763 cpuc->event_list[n] = event;
769 static inline void x86_assign_hw_event(struct perf_event *event,
770 struct cpu_hw_events *cpuc, int i)
772 struct hw_perf_event *hwc = &event->hw;
774 hwc->idx = cpuc->assign[i];
775 hwc->last_cpu = smp_processor_id();
776 hwc->last_tag = ++cpuc->tags[i];
778 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
779 hwc->config_base = 0;
781 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
782 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
784 * We set it so that event_base + idx in wrmsr/rdmsr maps to
785 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
788 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
790 hwc->config_base = x86_pmu.eventsel;
791 hwc->event_base = x86_pmu.perfctr;
795 static inline int match_prev_assignment(struct hw_perf_event *hwc,
796 struct cpu_hw_events *cpuc,
799 return hwc->idx == cpuc->assign[i] &&
800 hwc->last_cpu == smp_processor_id() &&
801 hwc->last_tag == cpuc->tags[i];
804 static int x86_pmu_start(struct perf_event *event);
805 static void x86_pmu_stop(struct perf_event *event);
807 void hw_perf_enable(void)
809 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
810 struct perf_event *event;
811 struct hw_perf_event *hwc;
812 int i, added = cpuc->n_added;
814 if (!x86_pmu_initialized())
821 int n_running = cpuc->n_events - cpuc->n_added;
823 * apply assignment obtained either from
824 * hw_perf_group_sched_in() or x86_pmu_enable()
826 * step1: save events moving to new counters
827 * step2: reprogram moved events into new counters
829 for (i = 0; i < n_running; i++) {
830 event = cpuc->event_list[i];
834 * we can avoid reprogramming counter if:
835 * - assigned same counter as last time
836 * - running on same CPU as last time
837 * - no other event has used the counter since
839 if (hwc->idx == -1 ||
840 match_prev_assignment(hwc, cpuc, i))
846 for (i = 0; i < cpuc->n_events; i++) {
847 event = cpuc->event_list[i];
850 if (!match_prev_assignment(hwc, cpuc, i))
851 x86_assign_hw_event(event, cpuc, i);
852 else if (i < n_running)
855 x86_pmu_start(event);
858 perf_events_lapic_init();
864 x86_pmu.enable_all(added);
867 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
870 wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
873 static inline void x86_pmu_disable_event(struct perf_event *event)
875 struct hw_perf_event *hwc = &event->hw;
877 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
880 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
883 * Set the next IRQ period, based on the hwc->period_left value.
884 * To be called with the event disabled in hw:
887 x86_perf_event_set_period(struct perf_event *event)
889 struct hw_perf_event *hwc = &event->hw;
890 s64 left = local64_read(&hwc->period_left);
891 s64 period = hwc->sample_period;
892 int ret = 0, idx = hwc->idx;
894 if (idx == X86_PMC_IDX_FIXED_BTS)
898 * If we are way outside a reasonable range then just skip forward:
900 if (unlikely(left <= -period)) {
902 local64_set(&hwc->period_left, left);
903 hwc->last_period = period;
907 if (unlikely(left <= 0)) {
909 local64_set(&hwc->period_left, left);
910 hwc->last_period = period;
914 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
916 if (unlikely(left < 2))
919 if (left > x86_pmu.max_period)
920 left = x86_pmu.max_period;
922 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
925 * The hw event starts counting from this event offset,
926 * mark it to be able to extra future deltas:
928 local64_set(&hwc->prev_count, (u64)-left);
930 wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
933 * Due to erratum on certan cpu we need
934 * a second write to be sure the register
935 * is updated properly
937 if (x86_pmu.perfctr_second_write) {
938 wrmsrl(hwc->event_base + idx,
939 (u64)(-left) & x86_pmu.cntval_mask);
942 perf_event_update_userpage(event);
947 static void x86_pmu_enable_event(struct perf_event *event)
949 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
951 __x86_pmu_enable_event(&event->hw,
952 ARCH_PERFMON_EVENTSEL_ENABLE);
956 * activate a single event
958 * The event is added to the group of enabled events
959 * but only if it can be scehduled with existing events.
961 * Called with PMU disabled. If successful and return value 1,
962 * then guaranteed to call perf_enable() and hw_perf_enable()
964 static int x86_pmu_enable(struct perf_event *event)
966 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
967 struct hw_perf_event *hwc;
968 int assign[X86_PMC_IDX_MAX];
974 n = collect_events(cpuc, event, false);
979 * If group events scheduling transaction was started,
980 * skip the schedulability test here, it will be peformed
981 * at commit time(->commit_txn) as a whole
983 if (cpuc->group_flag & PERF_EVENT_TXN)
986 ret = x86_pmu.schedule_events(cpuc, n, assign);
990 * copy new assignment, now we know it is possible
991 * will be used by hw_perf_enable()
993 memcpy(cpuc->assign, assign, n*sizeof(int));
997 cpuc->n_added += n - n0;
998 cpuc->n_txn += n - n0;
1003 static int x86_pmu_start(struct perf_event *event)
1005 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1006 int idx = event->hw.idx;
1011 x86_perf_event_set_period(event);
1012 cpuc->events[idx] = event;
1013 __set_bit(idx, cpuc->active_mask);
1014 __set_bit(idx, cpuc->running);
1015 x86_pmu.enable(event);
1016 perf_event_update_userpage(event);
1021 static void x86_pmu_unthrottle(struct perf_event *event)
1023 int ret = x86_pmu_start(event);
1027 void perf_event_print_debug(void)
1029 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1031 struct cpu_hw_events *cpuc;
1032 unsigned long flags;
1035 if (!x86_pmu.num_counters)
1038 local_irq_save(flags);
1040 cpu = smp_processor_id();
1041 cpuc = &per_cpu(cpu_hw_events, cpu);
1043 if (x86_pmu.version >= 2) {
1044 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1045 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1046 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1047 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1048 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1051 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1052 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1053 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1054 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1055 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1057 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1059 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1060 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1061 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1063 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1065 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1066 cpu, idx, pmc_ctrl);
1067 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1068 cpu, idx, pmc_count);
1069 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1070 cpu, idx, prev_left);
1072 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1073 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1075 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1076 cpu, idx, pmc_count);
1078 local_irq_restore(flags);
1081 static void x86_pmu_stop(struct perf_event *event)
1083 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1084 struct hw_perf_event *hwc = &event->hw;
1087 if (!__test_and_clear_bit(idx, cpuc->active_mask))
1090 x86_pmu.disable(event);
1093 * Drain the remaining delta count out of a event
1094 * that we are disabling:
1096 x86_perf_event_update(event);
1098 cpuc->events[idx] = NULL;
1101 static void x86_pmu_disable(struct perf_event *event)
1103 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1107 * If we're called during a txn, we don't need to do anything.
1108 * The events never got scheduled and ->cancel_txn will truncate
1111 if (cpuc->group_flag & PERF_EVENT_TXN)
1114 x86_pmu_stop(event);
1116 for (i = 0; i < cpuc->n_events; i++) {
1117 if (event == cpuc->event_list[i]) {
1119 if (x86_pmu.put_event_constraints)
1120 x86_pmu.put_event_constraints(cpuc, event);
1122 while (++i < cpuc->n_events)
1123 cpuc->event_list[i-1] = cpuc->event_list[i];
1129 perf_event_update_userpage(event);
1132 static int x86_pmu_handle_irq(struct pt_regs *regs)
1134 struct perf_sample_data data;
1135 struct cpu_hw_events *cpuc;
1136 struct perf_event *event;
1137 struct hw_perf_event *hwc;
1138 int idx, handled = 0;
1141 perf_sample_data_init(&data, 0);
1143 cpuc = &__get_cpu_var(cpu_hw_events);
1145 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1146 if (!test_bit(idx, cpuc->active_mask)) {
1148 * Though we deactivated the counter some cpus
1149 * might still deliver spurious interrupts still
1150 * in flight. Catch them:
1152 if (__test_and_clear_bit(idx, cpuc->running))
1157 event = cpuc->events[idx];
1160 val = x86_perf_event_update(event);
1161 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1168 data.period = event->hw.last_period;
1170 if (!x86_perf_event_set_period(event))
1173 if (perf_event_overflow(event, 1, &data, regs))
1174 x86_pmu_stop(event);
1178 inc_irq_stat(apic_perf_irqs);
1183 void smp_perf_pending_interrupt(struct pt_regs *regs)
1187 inc_irq_stat(apic_pending_irqs);
1188 perf_event_do_pending();
1192 void set_perf_event_pending(void)
1194 #ifdef CONFIG_X86_LOCAL_APIC
1195 if (!x86_pmu.apic || !x86_pmu_initialized())
1198 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1202 void perf_events_lapic_init(void)
1204 if (!x86_pmu.apic || !x86_pmu_initialized())
1208 * Always use NMI for PMU
1210 apic_write(APIC_LVTPC, APIC_DM_NMI);
1213 struct pmu_nmi_state {
1214 unsigned int marked;
1218 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1220 static int __kprobes
1221 perf_event_nmi_handler(struct notifier_block *self,
1222 unsigned long cmd, void *__args)
1224 struct die_args *args = __args;
1225 unsigned int this_nmi;
1228 if (!atomic_read(&active_events))
1235 case DIE_NMIUNKNOWN:
1236 this_nmi = percpu_read(irq_stat.__nmi_count);
1237 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1238 /* let the kernel handle the unknown nmi */
1241 * This one is a PMU back-to-back nmi. Two events
1242 * trigger 'simultaneously' raising two back-to-back
1243 * NMIs. If the first NMI handles both, the latter
1244 * will be empty and daze the CPU. So, we drop it to
1245 * avoid false-positive 'unknown nmi' messages.
1252 apic_write(APIC_LVTPC, APIC_DM_NMI);
1254 handled = x86_pmu.handle_irq(args->regs);
1258 this_nmi = percpu_read(irq_stat.__nmi_count);
1259 if ((handled > 1) ||
1260 /* the next nmi could be a back-to-back nmi */
1261 ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1262 (__get_cpu_var(pmu_nmi).handled > 1))) {
1264 * We could have two subsequent back-to-back nmis: The
1265 * first handles more than one counter, the 2nd
1266 * handles only one counter and the 3rd handles no
1269 * This is the 2nd nmi because the previous was
1270 * handling more than one counter. We will mark the
1271 * next (3rd) and then drop it if unhandled.
1273 __get_cpu_var(pmu_nmi).marked = this_nmi + 1;
1274 __get_cpu_var(pmu_nmi).handled = handled;
1280 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1281 .notifier_call = perf_event_nmi_handler,
1286 static struct event_constraint unconstrained;
1287 static struct event_constraint emptyconstraint;
1289 static struct event_constraint *
1290 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1292 struct event_constraint *c;
1294 if (x86_pmu.event_constraints) {
1295 for_each_event_constraint(c, x86_pmu.event_constraints) {
1296 if ((event->hw.config & c->cmask) == c->code)
1301 return &unconstrained;
1304 #include "perf_event_amd.c"
1305 #include "perf_event_p6.c"
1306 #include "perf_event_p4.c"
1307 #include "perf_event_intel_lbr.c"
1308 #include "perf_event_intel_ds.c"
1309 #include "perf_event_intel.c"
1311 static int __cpuinit
1312 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1314 unsigned int cpu = (long)hcpu;
1315 int ret = NOTIFY_OK;
1317 switch (action & ~CPU_TASKS_FROZEN) {
1318 case CPU_UP_PREPARE:
1319 if (x86_pmu.cpu_prepare)
1320 ret = x86_pmu.cpu_prepare(cpu);
1324 if (x86_pmu.cpu_starting)
1325 x86_pmu.cpu_starting(cpu);
1329 if (x86_pmu.cpu_dying)
1330 x86_pmu.cpu_dying(cpu);
1333 case CPU_UP_CANCELED:
1335 if (x86_pmu.cpu_dead)
1336 x86_pmu.cpu_dead(cpu);
1346 static void __init pmu_check_apic(void)
1352 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1353 pr_info("no hardware sampling interrupt available.\n");
1356 void __init init_hw_perf_events(void)
1358 struct event_constraint *c;
1361 pr_info("Performance Events: ");
1363 switch (boot_cpu_data.x86_vendor) {
1364 case X86_VENDOR_INTEL:
1365 err = intel_pmu_init();
1367 case X86_VENDOR_AMD:
1368 err = amd_pmu_init();
1374 pr_cont("no PMU driver, software events only.\n");
1380 pr_cont("%s PMU driver.\n", x86_pmu.name);
1385 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1386 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1387 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1388 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1390 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1391 perf_max_events = x86_pmu.num_counters;
1393 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1394 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1395 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1396 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1399 x86_pmu.intel_ctrl |=
1400 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1402 perf_events_lapic_init();
1403 register_die_notifier(&perf_event_nmi_notifier);
1405 unconstrained = (struct event_constraint)
1406 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1407 0, x86_pmu.num_counters);
1409 if (x86_pmu.event_constraints) {
1410 for_each_event_constraint(c, x86_pmu.event_constraints) {
1411 if (c->cmask != X86_RAW_EVENT_MASK)
1414 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1415 c->weight += x86_pmu.num_counters;
1419 pr_info("... version: %d\n", x86_pmu.version);
1420 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1421 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1422 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1423 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1424 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1425 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1427 perf_cpu_notifier(x86_pmu_notifier);
1430 static inline void x86_pmu_read(struct perf_event *event)
1432 x86_perf_event_update(event);
1436 * Start group events scheduling transaction
1437 * Set the flag to make pmu::enable() not perform the
1438 * schedulability test, it will be performed at commit time
1440 static void x86_pmu_start_txn(const struct pmu *pmu)
1442 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1444 cpuc->group_flag |= PERF_EVENT_TXN;
1449 * Stop group events scheduling transaction
1450 * Clear the flag and pmu::enable() will perform the
1451 * schedulability test.
1453 static void x86_pmu_cancel_txn(const struct pmu *pmu)
1455 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1457 cpuc->group_flag &= ~PERF_EVENT_TXN;
1459 * Truncate the collected events.
1461 cpuc->n_added -= cpuc->n_txn;
1462 cpuc->n_events -= cpuc->n_txn;
1466 * Commit group events scheduling transaction
1467 * Perform the group schedulability test as a whole
1468 * Return 0 if success
1470 static int x86_pmu_commit_txn(const struct pmu *pmu)
1472 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1473 int assign[X86_PMC_IDX_MAX];
1478 if (!x86_pmu_initialized())
1481 ret = x86_pmu.schedule_events(cpuc, n, assign);
1486 * copy new assignment, now we know it is possible
1487 * will be used by hw_perf_enable()
1489 memcpy(cpuc->assign, assign, n*sizeof(int));
1491 cpuc->group_flag &= ~PERF_EVENT_TXN;
1496 static const struct pmu pmu = {
1497 .enable = x86_pmu_enable,
1498 .disable = x86_pmu_disable,
1499 .start = x86_pmu_start,
1500 .stop = x86_pmu_stop,
1501 .read = x86_pmu_read,
1502 .unthrottle = x86_pmu_unthrottle,
1503 .start_txn = x86_pmu_start_txn,
1504 .cancel_txn = x86_pmu_cancel_txn,
1505 .commit_txn = x86_pmu_commit_txn,
1509 * validate that we can schedule this event
1511 static int validate_event(struct perf_event *event)
1513 struct cpu_hw_events *fake_cpuc;
1514 struct event_constraint *c;
1517 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1521 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1523 if (!c || !c->weight)
1526 if (x86_pmu.put_event_constraints)
1527 x86_pmu.put_event_constraints(fake_cpuc, event);
1535 * validate a single event group
1537 * validation include:
1538 * - check events are compatible which each other
1539 * - events do not compete for the same counter
1540 * - number of events <= number of counters
1542 * validation ensures the group can be loaded onto the
1543 * PMU if it was the only group available.
1545 static int validate_group(struct perf_event *event)
1547 struct perf_event *leader = event->group_leader;
1548 struct cpu_hw_events *fake_cpuc;
1552 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1557 * the event is not yet connected with its
1558 * siblings therefore we must first collect
1559 * existing siblings, then add the new event
1560 * before we can simulate the scheduling
1563 n = collect_events(fake_cpuc, leader, true);
1567 fake_cpuc->n_events = n;
1568 n = collect_events(fake_cpuc, event, false);
1572 fake_cpuc->n_events = n;
1574 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1582 const struct pmu *hw_perf_event_init(struct perf_event *event)
1584 const struct pmu *tmp;
1587 err = __hw_perf_event_init(event);
1590 * we temporarily connect event to its pmu
1591 * such that validate_group() can classify
1592 * it as an x86 event using is_x86_event()
1597 if (event->group_leader != event)
1598 err = validate_group(event);
1600 err = validate_event(event);
1606 event->destroy(event);
1607 return ERR_PTR(err);
1618 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1620 if (entry->nr < PERF_MAX_STACK_DEPTH)
1621 entry->ip[entry->nr++] = ip;
1624 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1625 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1629 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1631 /* Ignore warnings */
1634 static void backtrace_warning(void *data, char *msg)
1636 /* Ignore warnings */
1639 static int backtrace_stack(void *data, char *name)
1644 static void backtrace_address(void *data, unsigned long addr, int reliable)
1646 struct perf_callchain_entry *entry = data;
1648 callchain_store(entry, addr);
1651 static const struct stacktrace_ops backtrace_ops = {
1652 .warning = backtrace_warning,
1653 .warning_symbol = backtrace_warning_symbol,
1654 .stack = backtrace_stack,
1655 .address = backtrace_address,
1656 .walk_stack = print_context_stack_bp,
1660 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1662 callchain_store(entry, PERF_CONTEXT_KERNEL);
1663 callchain_store(entry, regs->ip);
1665 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1668 #ifdef CONFIG_COMPAT
1670 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1672 /* 32-bit process in 64-bit kernel. */
1673 struct stack_frame_ia32 frame;
1674 const void __user *fp;
1676 if (!test_thread_flag(TIF_IA32))
1679 fp = compat_ptr(regs->bp);
1680 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1681 unsigned long bytes;
1682 frame.next_frame = 0;
1683 frame.return_address = 0;
1685 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1686 if (bytes != sizeof(frame))
1689 if (fp < compat_ptr(regs->sp))
1692 callchain_store(entry, frame.return_address);
1693 fp = compat_ptr(frame.next_frame);
1699 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1706 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1708 struct stack_frame frame;
1709 const void __user *fp;
1711 if (!user_mode(regs))
1712 regs = task_pt_regs(current);
1714 fp = (void __user *)regs->bp;
1716 callchain_store(entry, PERF_CONTEXT_USER);
1717 callchain_store(entry, regs->ip);
1719 if (perf_callchain_user32(regs, entry))
1722 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1723 unsigned long bytes;
1724 frame.next_frame = NULL;
1725 frame.return_address = 0;
1727 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1728 if (bytes != sizeof(frame))
1731 if ((unsigned long)fp < regs->sp)
1734 callchain_store(entry, frame.return_address);
1735 fp = frame.next_frame;
1740 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1747 is_user = user_mode(regs);
1749 if (is_user && current->state != TASK_RUNNING)
1753 perf_callchain_kernel(regs, entry);
1756 perf_callchain_user(regs, entry);
1759 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1761 struct perf_callchain_entry *entry;
1763 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1764 /* TODO: We don't support guest os callchain now */
1769 entry = &__get_cpu_var(pmc_nmi_entry);
1771 entry = &__get_cpu_var(pmc_irq_entry);
1775 perf_do_callchain(regs, entry);
1780 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1784 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1785 ip = perf_guest_cbs->get_guest_ip();
1787 ip = instruction_pointer(regs);
1792 unsigned long perf_misc_flags(struct pt_regs *regs)
1796 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1797 if (perf_guest_cbs->is_user_mode())
1798 misc |= PERF_RECORD_MISC_GUEST_USER;
1800 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1802 if (user_mode(regs))
1803 misc |= PERF_RECORD_MISC_USER;
1805 misc |= PERF_RECORD_MISC_KERNEL;
1808 if (regs->flags & PERF_EFLAGS_EXACT)
1809 misc |= PERF_RECORD_MISC_EXACT_IP;