2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
51 unsigned long offset, addr = (unsigned long)from;
52 int type = in_nmi() ? KM_NMI : KM_IRQ0;
53 unsigned long size, len = 0;
59 ret = __get_user_pages_fast(addr, 1, 0, &page);
63 offset = addr & (PAGE_SIZE - 1);
64 size = min(PAGE_SIZE - offset, n - len);
66 map = kmap_atomic(page, type);
67 memcpy(to, map+offset, size);
68 kunmap_atomic(map, type);
80 struct event_constraint {
82 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
91 int nb_id; /* NorthBridge id */
92 int refcnt; /* reference count */
93 struct perf_event *owners[X86_PMC_IDX_MAX];
94 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
97 #define MAX_LBR_ENTRIES 16
99 struct cpu_hw_events {
101 * Generic x86 PMC bits
103 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
104 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
110 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
111 u64 tags[X86_PMC_IDX_MAX];
112 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
114 unsigned int group_flag;
117 * Intel DebugStore bits
119 struct debug_store *ds;
127 struct perf_branch_stack lbr_stack;
128 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
133 struct amd_nb *amd_nb;
136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
137 { .idxmsk64 = (n) }, \
143 #define EVENT_CONSTRAINT(c, n, m) \
144 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
147 * Constraint on the Event code.
149 #define INTEL_EVENT_CONSTRAINT(c, n) \
150 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
153 * Constraint on the Event code + UMask + fixed-mask
155 * filter mask to validate fixed counter events.
156 * the following filters disqualify for fixed counters:
160 * The other filters are supported by fixed counters.
161 * The any-thread option is supported starting with v3.
163 #define FIXED_EVENT_CONSTRAINT(c, n) \
164 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
167 * Constraint on the Event code + UMask
169 #define PEBS_EVENT_CONSTRAINT(c, n) \
170 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
172 #define EVENT_CONSTRAINT_END \
173 EVENT_CONSTRAINT(0, 0, 0)
175 #define for_each_event_constraint(e, c) \
176 for ((e) = (c); (e)->weight; (e)++)
178 union perf_capabilities {
182 u64 pebs_arch_reg : 1;
190 * struct x86_pmu - generic x86 pmu
194 * Generic x86 PMC bits
198 int (*handle_irq)(struct pt_regs *);
199 void (*disable_all)(void);
200 void (*enable_all)(int added);
201 void (*enable)(struct perf_event *);
202 void (*disable)(struct perf_event *);
203 int (*hw_config)(struct perf_event *event);
204 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
207 u64 (*event_map)(int);
210 int num_counters_fixed;
215 struct event_constraint *
216 (*get_event_constraints)(struct cpu_hw_events *cpuc,
217 struct perf_event *event);
219 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
220 struct perf_event *event);
221 struct event_constraint *event_constraints;
222 void (*quirks)(void);
223 int perfctr_second_write;
225 int (*cpu_prepare)(int cpu);
226 void (*cpu_starting)(int cpu);
227 void (*cpu_dying)(int cpu);
228 void (*cpu_dead)(int cpu);
231 * Intel Arch Perfmon v2+
234 union perf_capabilities intel_cap;
237 * Intel DebugStore bits
240 int pebs_record_size;
241 void (*drain_pebs)(struct pt_regs *regs);
242 struct event_constraint *pebs_constraints;
247 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
248 int lbr_nr; /* hardware stack size */
251 static struct x86_pmu x86_pmu __read_mostly;
253 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
257 static int x86_perf_event_set_period(struct perf_event *event);
260 * Generalized hw caching related hw_event table, filled
261 * in on a per model basis. A value of 0 means
262 * 'not supported', -1 means 'hw_event makes no sense on
263 * this CPU', any other value means the raw hw_event
267 #define C(x) PERF_COUNT_HW_CACHE_##x
269 static u64 __read_mostly hw_cache_event_ids
270 [PERF_COUNT_HW_CACHE_MAX]
271 [PERF_COUNT_HW_CACHE_OP_MAX]
272 [PERF_COUNT_HW_CACHE_RESULT_MAX];
275 * Propagate event elapsed time into the generic event.
276 * Can only be executed on the CPU where the event is active.
277 * Returns the delta events processed.
280 x86_perf_event_update(struct perf_event *event)
282 struct hw_perf_event *hwc = &event->hw;
283 int shift = 64 - x86_pmu.cntval_bits;
284 u64 prev_raw_count, new_raw_count;
288 if (idx == X86_PMC_IDX_FIXED_BTS)
292 * Careful: an NMI might modify the previous event value.
294 * Our tactic to handle this is to first atomically read and
295 * exchange a new raw count - then add that new-prev delta
296 * count to the generic event atomically:
299 prev_raw_count = local64_read(&hwc->prev_count);
300 rdmsrl(hwc->event_base + idx, new_raw_count);
302 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
303 new_raw_count) != prev_raw_count)
307 * Now we have the new raw value and have updated the prev
308 * timestamp already. We can now calculate the elapsed delta
309 * (event-)time and add that to the generic event.
311 * Careful, not all hw sign-extends above the physical width
314 delta = (new_raw_count << shift) - (prev_raw_count << shift);
317 local64_add(delta, &event->count);
318 local64_sub(delta, &hwc->period_left);
320 return new_raw_count;
323 static atomic_t active_events;
324 static DEFINE_MUTEX(pmc_reserve_mutex);
326 #ifdef CONFIG_X86_LOCAL_APIC
328 static bool reserve_pmc_hardware(void)
332 if (nmi_watchdog == NMI_LOCAL_APIC)
333 disable_lapic_nmi_watchdog();
335 for (i = 0; i < x86_pmu.num_counters; i++) {
336 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
340 for (i = 0; i < x86_pmu.num_counters; i++) {
341 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
348 for (i--; i >= 0; i--)
349 release_evntsel_nmi(x86_pmu.eventsel + i);
351 i = x86_pmu.num_counters;
354 for (i--; i >= 0; i--)
355 release_perfctr_nmi(x86_pmu.perfctr + i);
357 if (nmi_watchdog == NMI_LOCAL_APIC)
358 enable_lapic_nmi_watchdog();
363 static void release_pmc_hardware(void)
367 for (i = 0; i < x86_pmu.num_counters; i++) {
368 release_perfctr_nmi(x86_pmu.perfctr + i);
369 release_evntsel_nmi(x86_pmu.eventsel + i);
372 if (nmi_watchdog == NMI_LOCAL_APIC)
373 enable_lapic_nmi_watchdog();
378 static bool reserve_pmc_hardware(void) { return true; }
379 static void release_pmc_hardware(void) {}
383 static int reserve_ds_buffers(void);
384 static void release_ds_buffers(void);
386 static void hw_perf_event_destroy(struct perf_event *event)
388 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
389 release_pmc_hardware();
390 release_ds_buffers();
391 mutex_unlock(&pmc_reserve_mutex);
395 static inline int x86_pmu_initialized(void)
397 return x86_pmu.handle_irq != NULL;
401 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
403 unsigned int cache_type, cache_op, cache_result;
406 config = attr->config;
408 cache_type = (config >> 0) & 0xff;
409 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
412 cache_op = (config >> 8) & 0xff;
413 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
416 cache_result = (config >> 16) & 0xff;
417 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
420 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
433 static int x86_setup_perfctr(struct perf_event *event)
435 struct perf_event_attr *attr = &event->attr;
436 struct hw_perf_event *hwc = &event->hw;
439 if (!hwc->sample_period) {
440 hwc->sample_period = x86_pmu.max_period;
441 hwc->last_period = hwc->sample_period;
442 local64_set(&hwc->period_left, hwc->sample_period);
445 * If we have a PMU initialized but no APIC
446 * interrupts, we cannot sample hardware
447 * events (user-space has to fall back and
448 * sample via a hrtimer based software event):
454 if (attr->type == PERF_TYPE_RAW)
457 if (attr->type == PERF_TYPE_HW_CACHE)
458 return set_ext_hw_attr(hwc, attr);
460 if (attr->config >= x86_pmu.max_events)
466 config = x86_pmu.event_map(attr->config);
477 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
478 (hwc->sample_period == 1)) {
479 /* BTS is not supported by this architecture. */
483 /* BTS is currently only allowed for user-mode. */
484 if (!attr->exclude_kernel)
488 hwc->config |= config;
493 static int x86_pmu_hw_config(struct perf_event *event)
495 if (event->attr.precise_ip) {
498 /* Support for constant skid */
502 /* Support for IP fixup */
506 if (event->attr.precise_ip > precise)
512 * (keep 'enabled' bit clear for now)
514 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
517 * Count user and OS events unless requested not to
519 if (!event->attr.exclude_user)
520 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
521 if (!event->attr.exclude_kernel)
522 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
524 if (event->attr.type == PERF_TYPE_RAW)
525 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
527 return x86_setup_perfctr(event);
531 * Setup the hardware configuration for a given attr_type
533 static int __x86_pmu_event_init(struct perf_event *event)
537 if (!x86_pmu_initialized())
541 if (!atomic_inc_not_zero(&active_events)) {
542 mutex_lock(&pmc_reserve_mutex);
543 if (atomic_read(&active_events) == 0) {
544 if (!reserve_pmc_hardware())
547 err = reserve_ds_buffers();
549 release_pmc_hardware();
553 atomic_inc(&active_events);
554 mutex_unlock(&pmc_reserve_mutex);
559 event->destroy = hw_perf_event_destroy;
562 event->hw.last_cpu = -1;
563 event->hw.last_tag = ~0ULL;
565 return x86_pmu.hw_config(event);
568 static void x86_pmu_disable_all(void)
570 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
573 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
576 if (!test_bit(idx, cpuc->active_mask))
578 rdmsrl(x86_pmu.eventsel + idx, val);
579 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
581 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
582 wrmsrl(x86_pmu.eventsel + idx, val);
586 static void x86_pmu_pmu_disable(struct pmu *pmu)
588 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
590 if (!x86_pmu_initialized())
600 x86_pmu.disable_all();
603 static void x86_pmu_enable_all(int added)
605 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
608 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
609 struct perf_event *event = cpuc->events[idx];
612 if (!test_bit(idx, cpuc->active_mask))
615 val = event->hw.config;
616 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
617 wrmsrl(x86_pmu.eventsel + idx, val);
621 static struct pmu pmu;
623 static inline int is_x86_event(struct perf_event *event)
625 return event->pmu == &pmu;
628 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
630 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
631 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
632 int i, j, w, wmax, num = 0;
633 struct hw_perf_event *hwc;
635 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
637 for (i = 0; i < n; i++) {
638 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
643 * fastpath, try to reuse previous register
645 for (i = 0; i < n; i++) {
646 hwc = &cpuc->event_list[i]->hw;
653 /* constraint still honored */
654 if (!test_bit(hwc->idx, c->idxmsk))
657 /* not already used */
658 if (test_bit(hwc->idx, used_mask))
661 __set_bit(hwc->idx, used_mask);
663 assign[i] = hwc->idx;
672 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
675 * weight = number of possible counters
677 * 1 = most constrained, only works on one counter
678 * wmax = least constrained, works on any counter
680 * assign events to counters starting with most
681 * constrained events.
683 wmax = x86_pmu.num_counters;
686 * when fixed event counters are present,
687 * wmax is incremented by 1 to account
688 * for one more choice
690 if (x86_pmu.num_counters_fixed)
693 for (w = 1, num = n; num && w <= wmax; w++) {
695 for (i = 0; num && i < n; i++) {
697 hwc = &cpuc->event_list[i]->hw;
702 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
703 if (!test_bit(j, used_mask))
707 if (j == X86_PMC_IDX_MAX)
710 __set_bit(j, used_mask);
719 * scheduling failed or is just a simulation,
720 * free resources if necessary
722 if (!assign || num) {
723 for (i = 0; i < n; i++) {
724 if (x86_pmu.put_event_constraints)
725 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
728 return num ? -ENOSPC : 0;
732 * dogrp: true if must collect siblings events (group)
733 * returns total number of events and error code
735 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
737 struct perf_event *event;
740 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
742 /* current number of events already accepted */
745 if (is_x86_event(leader)) {
748 cpuc->event_list[n] = leader;
754 list_for_each_entry(event, &leader->sibling_list, group_entry) {
755 if (!is_x86_event(event) ||
756 event->state <= PERF_EVENT_STATE_OFF)
762 cpuc->event_list[n] = event;
768 static inline void x86_assign_hw_event(struct perf_event *event,
769 struct cpu_hw_events *cpuc, int i)
771 struct hw_perf_event *hwc = &event->hw;
773 hwc->idx = cpuc->assign[i];
774 hwc->last_cpu = smp_processor_id();
775 hwc->last_tag = ++cpuc->tags[i];
777 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
778 hwc->config_base = 0;
780 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
781 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
783 * We set it so that event_base + idx in wrmsr/rdmsr maps to
784 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
787 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
789 hwc->config_base = x86_pmu.eventsel;
790 hwc->event_base = x86_pmu.perfctr;
794 static inline int match_prev_assignment(struct hw_perf_event *hwc,
795 struct cpu_hw_events *cpuc,
798 return hwc->idx == cpuc->assign[i] &&
799 hwc->last_cpu == smp_processor_id() &&
800 hwc->last_tag == cpuc->tags[i];
803 static int x86_pmu_start(struct perf_event *event);
804 static void x86_pmu_stop(struct perf_event *event);
806 static void x86_pmu_pmu_enable(struct pmu *pmu)
808 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
809 struct perf_event *event;
810 struct hw_perf_event *hwc;
811 int i, added = cpuc->n_added;
813 if (!x86_pmu_initialized())
820 int n_running = cpuc->n_events - cpuc->n_added;
822 * apply assignment obtained either from
823 * hw_perf_group_sched_in() or x86_pmu_enable()
825 * step1: save events moving to new counters
826 * step2: reprogram moved events into new counters
828 for (i = 0; i < n_running; i++) {
829 event = cpuc->event_list[i];
833 * we can avoid reprogramming counter if:
834 * - assigned same counter as last time
835 * - running on same CPU as last time
836 * - no other event has used the counter since
838 if (hwc->idx == -1 ||
839 match_prev_assignment(hwc, cpuc, i))
845 for (i = 0; i < cpuc->n_events; i++) {
846 event = cpuc->event_list[i];
849 if (!match_prev_assignment(hwc, cpuc, i))
850 x86_assign_hw_event(event, cpuc, i);
851 else if (i < n_running)
854 x86_pmu_start(event);
857 perf_events_lapic_init();
863 x86_pmu.enable_all(added);
866 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
869 wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
872 static inline void x86_pmu_disable_event(struct perf_event *event)
874 struct hw_perf_event *hwc = &event->hw;
876 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
879 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
882 * Set the next IRQ period, based on the hwc->period_left value.
883 * To be called with the event disabled in hw:
886 x86_perf_event_set_period(struct perf_event *event)
888 struct hw_perf_event *hwc = &event->hw;
889 s64 left = local64_read(&hwc->period_left);
890 s64 period = hwc->sample_period;
891 int ret = 0, idx = hwc->idx;
893 if (idx == X86_PMC_IDX_FIXED_BTS)
897 * If we are way outside a reasonable range then just skip forward:
899 if (unlikely(left <= -period)) {
901 local64_set(&hwc->period_left, left);
902 hwc->last_period = period;
906 if (unlikely(left <= 0)) {
908 local64_set(&hwc->period_left, left);
909 hwc->last_period = period;
913 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
915 if (unlikely(left < 2))
918 if (left > x86_pmu.max_period)
919 left = x86_pmu.max_period;
921 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
924 * The hw event starts counting from this event offset,
925 * mark it to be able to extra future deltas:
927 local64_set(&hwc->prev_count, (u64)-left);
929 wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
932 * Due to erratum on certan cpu we need
933 * a second write to be sure the register
934 * is updated properly
936 if (x86_pmu.perfctr_second_write) {
937 wrmsrl(hwc->event_base + idx,
938 (u64)(-left) & x86_pmu.cntval_mask);
941 perf_event_update_userpage(event);
946 static void x86_pmu_enable_event(struct perf_event *event)
948 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
950 __x86_pmu_enable_event(&event->hw,
951 ARCH_PERFMON_EVENTSEL_ENABLE);
955 * activate a single event
957 * The event is added to the group of enabled events
958 * but only if it can be scehduled with existing events.
960 * Called with PMU disabled. If successful and return value 1,
961 * then guaranteed to call perf_enable() and hw_perf_enable()
963 static int x86_pmu_enable(struct perf_event *event)
965 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
966 struct hw_perf_event *hwc;
967 int assign[X86_PMC_IDX_MAX];
972 perf_pmu_disable(event->pmu);
974 ret = n = collect_events(cpuc, event, false);
979 * If group events scheduling transaction was started,
980 * skip the schedulability test here, it will be peformed
981 * at commit time(->commit_txn) as a whole
983 if (cpuc->group_flag & PERF_EVENT_TXN)
986 ret = x86_pmu.schedule_events(cpuc, n, assign);
990 * copy new assignment, now we know it is possible
991 * will be used by hw_perf_enable()
993 memcpy(cpuc->assign, assign, n*sizeof(int));
997 cpuc->n_added += n - n0;
998 cpuc->n_txn += n - n0;
1002 perf_pmu_enable(event->pmu);
1006 static int x86_pmu_start(struct perf_event *event)
1008 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1009 int idx = event->hw.idx;
1014 x86_perf_event_set_period(event);
1015 cpuc->events[idx] = event;
1016 __set_bit(idx, cpuc->active_mask);
1017 x86_pmu.enable(event);
1018 perf_event_update_userpage(event);
1023 static void x86_pmu_unthrottle(struct perf_event *event)
1025 int ret = x86_pmu_start(event);
1029 void perf_event_print_debug(void)
1031 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1033 struct cpu_hw_events *cpuc;
1034 unsigned long flags;
1037 if (!x86_pmu.num_counters)
1040 local_irq_save(flags);
1042 cpu = smp_processor_id();
1043 cpuc = &per_cpu(cpu_hw_events, cpu);
1045 if (x86_pmu.version >= 2) {
1046 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1047 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1048 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1049 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1050 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1053 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1054 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1055 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1056 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1057 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1059 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1061 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1062 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1063 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1065 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1067 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1068 cpu, idx, pmc_ctrl);
1069 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1070 cpu, idx, pmc_count);
1071 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1072 cpu, idx, prev_left);
1074 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1075 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1077 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1078 cpu, idx, pmc_count);
1080 local_irq_restore(flags);
1083 static void x86_pmu_stop(struct perf_event *event)
1085 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1086 struct hw_perf_event *hwc = &event->hw;
1089 if (!__test_and_clear_bit(idx, cpuc->active_mask))
1092 x86_pmu.disable(event);
1095 * Drain the remaining delta count out of a event
1096 * that we are disabling:
1098 x86_perf_event_update(event);
1100 cpuc->events[idx] = NULL;
1103 static void x86_pmu_disable(struct perf_event *event)
1105 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1109 * If we're called during a txn, we don't need to do anything.
1110 * The events never got scheduled and ->cancel_txn will truncate
1113 if (cpuc->group_flag & PERF_EVENT_TXN)
1116 x86_pmu_stop(event);
1118 for (i = 0; i < cpuc->n_events; i++) {
1119 if (event == cpuc->event_list[i]) {
1121 if (x86_pmu.put_event_constraints)
1122 x86_pmu.put_event_constraints(cpuc, event);
1124 while (++i < cpuc->n_events)
1125 cpuc->event_list[i-1] = cpuc->event_list[i];
1131 perf_event_update_userpage(event);
1134 static int x86_pmu_handle_irq(struct pt_regs *regs)
1136 struct perf_sample_data data;
1137 struct cpu_hw_events *cpuc;
1138 struct perf_event *event;
1139 struct hw_perf_event *hwc;
1140 int idx, handled = 0;
1143 perf_sample_data_init(&data, 0);
1145 cpuc = &__get_cpu_var(cpu_hw_events);
1147 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1148 if (!test_bit(idx, cpuc->active_mask))
1151 event = cpuc->events[idx];
1154 val = x86_perf_event_update(event);
1155 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1162 data.period = event->hw.last_period;
1164 if (!x86_perf_event_set_period(event))
1167 if (perf_event_overflow(event, 1, &data, regs))
1168 x86_pmu_stop(event);
1172 inc_irq_stat(apic_perf_irqs);
1177 void smp_perf_pending_interrupt(struct pt_regs *regs)
1181 inc_irq_stat(apic_pending_irqs);
1182 perf_event_do_pending();
1186 void set_perf_event_pending(void)
1188 #ifdef CONFIG_X86_LOCAL_APIC
1189 if (!x86_pmu.apic || !x86_pmu_initialized())
1192 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1196 void perf_events_lapic_init(void)
1198 if (!x86_pmu.apic || !x86_pmu_initialized())
1202 * Always use NMI for PMU
1204 apic_write(APIC_LVTPC, APIC_DM_NMI);
1207 struct pmu_nmi_state {
1208 unsigned int marked;
1212 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1214 static int __kprobes
1215 perf_event_nmi_handler(struct notifier_block *self,
1216 unsigned long cmd, void *__args)
1218 struct die_args *args = __args;
1219 unsigned int this_nmi;
1222 if (!atomic_read(&active_events))
1229 case DIE_NMIUNKNOWN:
1230 this_nmi = percpu_read(irq_stat.__nmi_count);
1231 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1232 /* let the kernel handle the unknown nmi */
1235 * This one is a PMU back-to-back nmi. Two events
1236 * trigger 'simultaneously' raising two back-to-back
1237 * NMIs. If the first NMI handles both, the latter
1238 * will be empty and daze the CPU. So, we drop it to
1239 * avoid false-positive 'unknown nmi' messages.
1246 apic_write(APIC_LVTPC, APIC_DM_NMI);
1248 handled = x86_pmu.handle_irq(args->regs);
1252 this_nmi = percpu_read(irq_stat.__nmi_count);
1253 if ((handled > 1) ||
1254 /* the next nmi could be a back-to-back nmi */
1255 ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1256 (__get_cpu_var(pmu_nmi).handled > 1))) {
1258 * We could have two subsequent back-to-back nmis: The
1259 * first handles more than one counter, the 2nd
1260 * handles only one counter and the 3rd handles no
1263 * This is the 2nd nmi because the previous was
1264 * handling more than one counter. We will mark the
1265 * next (3rd) and then drop it if unhandled.
1267 __get_cpu_var(pmu_nmi).marked = this_nmi + 1;
1268 __get_cpu_var(pmu_nmi).handled = handled;
1274 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1275 .notifier_call = perf_event_nmi_handler,
1280 static struct event_constraint unconstrained;
1281 static struct event_constraint emptyconstraint;
1283 static struct event_constraint *
1284 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1286 struct event_constraint *c;
1288 if (x86_pmu.event_constraints) {
1289 for_each_event_constraint(c, x86_pmu.event_constraints) {
1290 if ((event->hw.config & c->cmask) == c->code)
1295 return &unconstrained;
1298 #include "perf_event_amd.c"
1299 #include "perf_event_p6.c"
1300 #include "perf_event_p4.c"
1301 #include "perf_event_intel_lbr.c"
1302 #include "perf_event_intel_ds.c"
1303 #include "perf_event_intel.c"
1305 static int __cpuinit
1306 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1308 unsigned int cpu = (long)hcpu;
1309 int ret = NOTIFY_OK;
1311 switch (action & ~CPU_TASKS_FROZEN) {
1312 case CPU_UP_PREPARE:
1313 if (x86_pmu.cpu_prepare)
1314 ret = x86_pmu.cpu_prepare(cpu);
1318 if (x86_pmu.cpu_starting)
1319 x86_pmu.cpu_starting(cpu);
1323 if (x86_pmu.cpu_dying)
1324 x86_pmu.cpu_dying(cpu);
1327 case CPU_UP_CANCELED:
1329 if (x86_pmu.cpu_dead)
1330 x86_pmu.cpu_dead(cpu);
1340 static void __init pmu_check_apic(void)
1346 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1347 pr_info("no hardware sampling interrupt available.\n");
1350 void __init init_hw_perf_events(void)
1352 struct event_constraint *c;
1355 pr_info("Performance Events: ");
1357 switch (boot_cpu_data.x86_vendor) {
1358 case X86_VENDOR_INTEL:
1359 err = intel_pmu_init();
1361 case X86_VENDOR_AMD:
1362 err = amd_pmu_init();
1368 pr_cont("no PMU driver, software events only.\n");
1374 pr_cont("%s PMU driver.\n", x86_pmu.name);
1379 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1380 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1381 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1382 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1384 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1385 perf_max_events = x86_pmu.num_counters;
1387 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1388 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1389 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1390 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1393 x86_pmu.intel_ctrl |=
1394 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1396 perf_events_lapic_init();
1397 register_die_notifier(&perf_event_nmi_notifier);
1399 unconstrained = (struct event_constraint)
1400 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1401 0, x86_pmu.num_counters);
1403 if (x86_pmu.event_constraints) {
1404 for_each_event_constraint(c, x86_pmu.event_constraints) {
1405 if (c->cmask != X86_RAW_EVENT_MASK)
1408 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1409 c->weight += x86_pmu.num_counters;
1413 pr_info("... version: %d\n", x86_pmu.version);
1414 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1415 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1416 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1417 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1418 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1419 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1421 perf_pmu_register(&pmu);
1422 perf_cpu_notifier(x86_pmu_notifier);
1425 static inline void x86_pmu_read(struct perf_event *event)
1427 x86_perf_event_update(event);
1431 * Start group events scheduling transaction
1432 * Set the flag to make pmu::enable() not perform the
1433 * schedulability test, it will be performed at commit time
1435 static void x86_pmu_start_txn(struct pmu *pmu)
1437 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1439 perf_pmu_disable(pmu);
1440 cpuc->group_flag |= PERF_EVENT_TXN;
1445 * Stop group events scheduling transaction
1446 * Clear the flag and pmu::enable() will perform the
1447 * schedulability test.
1449 static void x86_pmu_cancel_txn(struct pmu *pmu)
1451 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1453 cpuc->group_flag &= ~PERF_EVENT_TXN;
1455 * Truncate the collected events.
1457 cpuc->n_added -= cpuc->n_txn;
1458 cpuc->n_events -= cpuc->n_txn;
1459 perf_pmu_enable(pmu);
1463 * Commit group events scheduling transaction
1464 * Perform the group schedulability test as a whole
1465 * Return 0 if success
1467 static int x86_pmu_commit_txn(struct pmu *pmu)
1469 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1470 int assign[X86_PMC_IDX_MAX];
1475 if (!x86_pmu_initialized())
1478 ret = x86_pmu.schedule_events(cpuc, n, assign);
1483 * copy new assignment, now we know it is possible
1484 * will be used by hw_perf_enable()
1486 memcpy(cpuc->assign, assign, n*sizeof(int));
1488 cpuc->group_flag &= ~PERF_EVENT_TXN;
1489 perf_pmu_enable(pmu);
1494 * validate that we can schedule this event
1496 static int validate_event(struct perf_event *event)
1498 struct cpu_hw_events *fake_cpuc;
1499 struct event_constraint *c;
1502 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1506 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1508 if (!c || !c->weight)
1511 if (x86_pmu.put_event_constraints)
1512 x86_pmu.put_event_constraints(fake_cpuc, event);
1520 * validate a single event group
1522 * validation include:
1523 * - check events are compatible which each other
1524 * - events do not compete for the same counter
1525 * - number of events <= number of counters
1527 * validation ensures the group can be loaded onto the
1528 * PMU if it was the only group available.
1530 static int validate_group(struct perf_event *event)
1532 struct perf_event *leader = event->group_leader;
1533 struct cpu_hw_events *fake_cpuc;
1537 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1542 * the event is not yet connected with its
1543 * siblings therefore we must first collect
1544 * existing siblings, then add the new event
1545 * before we can simulate the scheduling
1548 n = collect_events(fake_cpuc, leader, true);
1552 fake_cpuc->n_events = n;
1553 n = collect_events(fake_cpuc, event, false);
1557 fake_cpuc->n_events = n;
1559 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1567 int x86_pmu_event_init(struct perf_event *event)
1572 switch (event->attr.type) {
1574 case PERF_TYPE_HARDWARE:
1575 case PERF_TYPE_HW_CACHE:
1582 err = __x86_pmu_event_init(event);
1585 * we temporarily connect event to its pmu
1586 * such that validate_group() can classify
1587 * it as an x86 event using is_x86_event()
1592 if (event->group_leader != event)
1593 err = validate_group(event);
1595 err = validate_event(event);
1601 event->destroy(event);
1607 static struct pmu pmu = {
1608 .pmu_enable = x86_pmu_pmu_enable,
1609 .pmu_disable = x86_pmu_pmu_disable,
1610 .event_init = x86_pmu_event_init,
1611 .enable = x86_pmu_enable,
1612 .disable = x86_pmu_disable,
1613 .start = x86_pmu_start,
1614 .stop = x86_pmu_stop,
1615 .read = x86_pmu_read,
1616 .unthrottle = x86_pmu_unthrottle,
1617 .start_txn = x86_pmu_start_txn,
1618 .cancel_txn = x86_pmu_cancel_txn,
1619 .commit_txn = x86_pmu_commit_txn,
1627 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1629 /* Ignore warnings */
1632 static void backtrace_warning(void *data, char *msg)
1634 /* Ignore warnings */
1637 static int backtrace_stack(void *data, char *name)
1642 static void backtrace_address(void *data, unsigned long addr, int reliable)
1644 struct perf_callchain_entry *entry = data;
1646 perf_callchain_store(entry, addr);
1649 static const struct stacktrace_ops backtrace_ops = {
1650 .warning = backtrace_warning,
1651 .warning_symbol = backtrace_warning_symbol,
1652 .stack = backtrace_stack,
1653 .address = backtrace_address,
1654 .walk_stack = print_context_stack_bp,
1658 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1660 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1661 /* TODO: We don't support guest os callchain now */
1665 perf_callchain_store(entry, regs->ip);
1667 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1670 #ifdef CONFIG_COMPAT
1672 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1674 /* 32-bit process in 64-bit kernel. */
1675 struct stack_frame_ia32 frame;
1676 const void __user *fp;
1678 if (!test_thread_flag(TIF_IA32))
1681 fp = compat_ptr(regs->bp);
1682 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1683 unsigned long bytes;
1684 frame.next_frame = 0;
1685 frame.return_address = 0;
1687 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1688 if (bytes != sizeof(frame))
1691 if (fp < compat_ptr(regs->sp))
1694 perf_callchain_store(entry, frame.return_address);
1695 fp = compat_ptr(frame.next_frame);
1701 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1708 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1710 struct stack_frame frame;
1711 const void __user *fp;
1713 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1714 /* TODO: We don't support guest os callchain now */
1718 fp = (void __user *)regs->bp;
1720 perf_callchain_store(entry, regs->ip);
1722 if (perf_callchain_user32(regs, entry))
1725 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1726 unsigned long bytes;
1727 frame.next_frame = NULL;
1728 frame.return_address = 0;
1730 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1731 if (bytes != sizeof(frame))
1734 if ((unsigned long)fp < regs->sp)
1737 perf_callchain_store(entry, frame.return_address);
1738 fp = frame.next_frame;
1742 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1746 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1747 ip = perf_guest_cbs->get_guest_ip();
1749 ip = instruction_pointer(regs);
1754 unsigned long perf_misc_flags(struct pt_regs *regs)
1758 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1759 if (perf_guest_cbs->is_user_mode())
1760 misc |= PERF_RECORD_MISC_GUEST_USER;
1762 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1764 if (user_mode(regs))
1765 misc |= PERF_RECORD_MISC_USER;
1767 misc |= PERF_RECORD_MISC_KERNEL;
1770 if (regs->flags & PERF_EFLAGS_EXACT)
1771 misc |= PERF_RECORD_MISC_EXACT_IP;