2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
34 #include <asm/alternative.h>
38 #define wrmsrl(msr, val) \
40 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
41 (unsigned long)(val)); \
42 native_write_msr((msr), (u32)((u64)(val)), \
43 (u32)((u64)(val) >> 32)); \
49 * register -------------------------------
50 * | HT | no HT | HT | no HT |
51 *-----------------------------------------
52 * offcore | core | core | cpu | core |
53 * lbr_sel | core | core | cpu | core |
54 * ld_lat | cpu | core | cpu | core |
55 *-----------------------------------------
57 * Given that there is a small number of shared regs,
58 * we can pre-allocate their slot in the per-cpu
59 * per-core reg tables.
62 EXTRA_REG_NONE = -1, /* not used */
64 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
65 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
67 EXTRA_REG_MAX /* number of entries needed */
71 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
74 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
76 unsigned long offset, addr = (unsigned long)from;
77 unsigned long size, len = 0;
83 ret = __get_user_pages_fast(addr, 1, 0, &page);
87 offset = addr & (PAGE_SIZE - 1);
88 size = min(PAGE_SIZE - offset, n - len);
90 map = kmap_atomic(page);
91 memcpy(to, map+offset, size);
104 struct event_constraint {
106 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
115 int nb_id; /* NorthBridge id */
116 int refcnt; /* reference count */
117 struct perf_event *owners[X86_PMC_IDX_MAX];
118 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
121 struct intel_percore;
123 #define MAX_LBR_ENTRIES 16
125 struct cpu_hw_events {
127 * Generic x86 PMC bits
129 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
130 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
131 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
137 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
138 u64 tags[X86_PMC_IDX_MAX];
139 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
141 unsigned int group_flag;
144 * Intel DebugStore bits
146 struct debug_store *ds;
154 struct perf_branch_stack lbr_stack;
155 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
158 * manage shared (per-core, per-cpu) registers
159 * used on Intel NHM/WSM/SNB
161 struct intel_shared_regs *shared_regs;
166 struct amd_nb *amd_nb;
169 #define __EVENT_CONSTRAINT(c, n, m, w) {\
170 { .idxmsk64 = (n) }, \
176 #define EVENT_CONSTRAINT(c, n, m) \
177 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
180 * Constraint on the Event code.
182 #define INTEL_EVENT_CONSTRAINT(c, n) \
183 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
186 * Constraint on the Event code + UMask + fixed-mask
188 * filter mask to validate fixed counter events.
189 * the following filters disqualify for fixed counters:
193 * The other filters are supported by fixed counters.
194 * The any-thread option is supported starting with v3.
196 #define FIXED_EVENT_CONSTRAINT(c, n) \
197 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
200 * Constraint on the Event code + UMask
202 #define INTEL_UEVENT_CONSTRAINT(c, n) \
203 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
205 #define EVENT_CONSTRAINT_END \
206 EVENT_CONSTRAINT(0, 0, 0)
208 #define for_each_event_constraint(e, c) \
209 for ((e) = (c); (e)->weight; (e)++)
212 * Per register state.
215 raw_spinlock_t lock; /* per-core: protect structure */
216 u64 config; /* extra MSR config */
217 u64 reg; /* extra MSR number */
218 atomic_t ref; /* reference count */
222 * Extra registers for specific events.
224 * Some events need large masks and require external MSRs.
225 * Those extra MSRs end up being shared for all events on
226 * a PMU and sometimes between PMU of sibling HT threads.
227 * In either case, the kernel needs to handle conflicting
228 * accesses to those extra, shared, regs. The data structure
229 * to manage those registers is stored in cpu_hw_event.
236 int idx; /* per_xxx->regs[] reg index */
239 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
242 .config_mask = (m), \
243 .valid_mask = (vm), \
244 .idx = EXTRA_REG_##i \
247 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
248 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
250 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
252 union perf_capabilities {
256 u64 pebs_arch_reg : 1;
264 * struct x86_pmu - generic x86 pmu
268 * Generic x86 PMC bits
272 int (*handle_irq)(struct pt_regs *);
273 void (*disable_all)(void);
274 void (*enable_all)(int added);
275 void (*enable)(struct perf_event *);
276 void (*disable)(struct perf_event *);
277 int (*hw_config)(struct perf_event *event);
278 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
281 u64 (*event_map)(int);
284 int num_counters_fixed;
289 struct event_constraint *
290 (*get_event_constraints)(struct cpu_hw_events *cpuc,
291 struct perf_event *event);
293 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
294 struct perf_event *event);
295 struct event_constraint *event_constraints;
296 void (*quirks)(void);
297 int perfctr_second_write;
299 int (*cpu_prepare)(int cpu);
300 void (*cpu_starting)(int cpu);
301 void (*cpu_dying)(int cpu);
302 void (*cpu_dead)(int cpu);
305 * Intel Arch Perfmon v2+
308 union perf_capabilities intel_cap;
311 * Intel DebugStore bits
314 int bts_active, pebs_active;
315 int pebs_record_size;
316 void (*drain_pebs)(struct pt_regs *regs);
317 struct event_constraint *pebs_constraints;
322 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
323 int lbr_nr; /* hardware stack size */
326 * Extra registers for events
328 struct extra_reg *extra_regs;
329 unsigned int er_flags;
332 #define ERF_NO_HT_SHARING 1
333 #define ERF_HAS_RSP_1 2
335 static struct x86_pmu x86_pmu __read_mostly;
337 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
341 static int x86_perf_event_set_period(struct perf_event *event);
344 * Generalized hw caching related hw_event table, filled
345 * in on a per model basis. A value of 0 means
346 * 'not supported', -1 means 'hw_event makes no sense on
347 * this CPU', any other value means the raw hw_event
351 #define C(x) PERF_COUNT_HW_CACHE_##x
353 static u64 __read_mostly hw_cache_event_ids
354 [PERF_COUNT_HW_CACHE_MAX]
355 [PERF_COUNT_HW_CACHE_OP_MAX]
356 [PERF_COUNT_HW_CACHE_RESULT_MAX];
357 static u64 __read_mostly hw_cache_extra_regs
358 [PERF_COUNT_HW_CACHE_MAX]
359 [PERF_COUNT_HW_CACHE_OP_MAX]
360 [PERF_COUNT_HW_CACHE_RESULT_MAX];
363 * Propagate event elapsed time into the generic event.
364 * Can only be executed on the CPU where the event is active.
365 * Returns the delta events processed.
368 x86_perf_event_update(struct perf_event *event)
370 struct hw_perf_event *hwc = &event->hw;
371 int shift = 64 - x86_pmu.cntval_bits;
372 u64 prev_raw_count, new_raw_count;
376 if (idx == X86_PMC_IDX_FIXED_BTS)
380 * Careful: an NMI might modify the previous event value.
382 * Our tactic to handle this is to first atomically read and
383 * exchange a new raw count - then add that new-prev delta
384 * count to the generic event atomically:
387 prev_raw_count = local64_read(&hwc->prev_count);
388 rdmsrl(hwc->event_base, new_raw_count);
390 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
391 new_raw_count) != prev_raw_count)
395 * Now we have the new raw value and have updated the prev
396 * timestamp already. We can now calculate the elapsed delta
397 * (event-)time and add that to the generic event.
399 * Careful, not all hw sign-extends above the physical width
402 delta = (new_raw_count << shift) - (prev_raw_count << shift);
405 local64_add(delta, &event->count);
406 local64_sub(delta, &hwc->period_left);
408 return new_raw_count;
411 static inline int x86_pmu_addr_offset(int index)
415 /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
416 alternative_io(ASM_NOP2,
418 X86_FEATURE_PERFCTR_CORE,
425 static inline unsigned int x86_pmu_config_addr(int index)
427 return x86_pmu.eventsel + x86_pmu_addr_offset(index);
430 static inline unsigned int x86_pmu_event_addr(int index)
432 return x86_pmu.perfctr + x86_pmu_addr_offset(index);
436 * Find and validate any extra registers to set up.
438 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
440 struct hw_perf_event_extra *reg;
441 struct extra_reg *er;
443 reg = &event->hw.extra_reg;
445 if (!x86_pmu.extra_regs)
448 for (er = x86_pmu.extra_regs; er->msr; er++) {
449 if (er->event != (config & er->config_mask))
451 if (event->attr.config1 & ~er->valid_mask)
455 reg->config = event->attr.config1;
462 static atomic_t active_events;
463 static DEFINE_MUTEX(pmc_reserve_mutex);
465 #ifdef CONFIG_X86_LOCAL_APIC
467 static bool reserve_pmc_hardware(void)
471 for (i = 0; i < x86_pmu.num_counters; i++) {
472 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
476 for (i = 0; i < x86_pmu.num_counters; i++) {
477 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
484 for (i--; i >= 0; i--)
485 release_evntsel_nmi(x86_pmu_config_addr(i));
487 i = x86_pmu.num_counters;
490 for (i--; i >= 0; i--)
491 release_perfctr_nmi(x86_pmu_event_addr(i));
496 static void release_pmc_hardware(void)
500 for (i = 0; i < x86_pmu.num_counters; i++) {
501 release_perfctr_nmi(x86_pmu_event_addr(i));
502 release_evntsel_nmi(x86_pmu_config_addr(i));
508 static bool reserve_pmc_hardware(void) { return true; }
509 static void release_pmc_hardware(void) {}
513 static bool check_hw_exists(void)
515 u64 val, val_new = 0;
519 * Check to see if the BIOS enabled any of the counters, if so
522 for (i = 0; i < x86_pmu.num_counters; i++) {
523 reg = x86_pmu_config_addr(i);
524 ret = rdmsrl_safe(reg, &val);
527 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
531 if (x86_pmu.num_counters_fixed) {
532 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
533 ret = rdmsrl_safe(reg, &val);
536 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
537 if (val & (0x03 << i*4))
543 * Now write a value and read it back to see if it matches,
544 * this is needed to detect certain hardware emulators (qemu/kvm)
545 * that don't trap on the MSR access and always return 0s.
548 ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
549 ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
550 if (ret || val != val_new)
557 * We still allow the PMU driver to operate:
559 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
560 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
565 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
570 static void reserve_ds_buffers(void);
571 static void release_ds_buffers(void);
573 static void hw_perf_event_destroy(struct perf_event *event)
575 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
576 release_pmc_hardware();
577 release_ds_buffers();
578 mutex_unlock(&pmc_reserve_mutex);
582 static inline int x86_pmu_initialized(void)
584 return x86_pmu.handle_irq != NULL;
588 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
590 struct perf_event_attr *attr = &event->attr;
591 unsigned int cache_type, cache_op, cache_result;
594 config = attr->config;
596 cache_type = (config >> 0) & 0xff;
597 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
600 cache_op = (config >> 8) & 0xff;
601 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
604 cache_result = (config >> 16) & 0xff;
605 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
608 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
617 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
618 return x86_pmu_extra_regs(val, event);
621 static int x86_setup_perfctr(struct perf_event *event)
623 struct perf_event_attr *attr = &event->attr;
624 struct hw_perf_event *hwc = &event->hw;
627 if (!is_sampling_event(event)) {
628 hwc->sample_period = x86_pmu.max_period;
629 hwc->last_period = hwc->sample_period;
630 local64_set(&hwc->period_left, hwc->sample_period);
633 * If we have a PMU initialized but no APIC
634 * interrupts, we cannot sample hardware
635 * events (user-space has to fall back and
636 * sample via a hrtimer based software event):
643 * Do not allow config1 (extended registers) to propagate,
644 * there's no sane user-space generalization yet:
646 if (attr->type == PERF_TYPE_RAW)
649 if (attr->type == PERF_TYPE_HW_CACHE)
650 return set_ext_hw_attr(hwc, event);
652 if (attr->config >= x86_pmu.max_events)
658 config = x86_pmu.event_map(attr->config);
669 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
670 !attr->freq && hwc->sample_period == 1) {
671 /* BTS is not supported by this architecture. */
672 if (!x86_pmu.bts_active)
675 /* BTS is currently only allowed for user-mode. */
676 if (!attr->exclude_kernel)
680 hwc->config |= config;
685 static int x86_pmu_hw_config(struct perf_event *event)
687 if (event->attr.precise_ip) {
690 /* Support for constant skid */
691 if (x86_pmu.pebs_active) {
694 /* Support for IP fixup */
699 if (event->attr.precise_ip > precise)
705 * (keep 'enabled' bit clear for now)
707 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
710 * Count user and OS events unless requested not to
712 if (!event->attr.exclude_user)
713 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
714 if (!event->attr.exclude_kernel)
715 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
717 if (event->attr.type == PERF_TYPE_RAW)
718 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
720 return x86_setup_perfctr(event);
724 * Setup the hardware configuration for a given attr_type
726 static int __x86_pmu_event_init(struct perf_event *event)
730 if (!x86_pmu_initialized())
734 if (!atomic_inc_not_zero(&active_events)) {
735 mutex_lock(&pmc_reserve_mutex);
736 if (atomic_read(&active_events) == 0) {
737 if (!reserve_pmc_hardware())
740 reserve_ds_buffers();
743 atomic_inc(&active_events);
744 mutex_unlock(&pmc_reserve_mutex);
749 event->destroy = hw_perf_event_destroy;
752 event->hw.last_cpu = -1;
753 event->hw.last_tag = ~0ULL;
756 event->hw.extra_reg.idx = EXTRA_REG_NONE;
758 return x86_pmu.hw_config(event);
761 static void x86_pmu_disable_all(void)
763 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
766 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
769 if (!test_bit(idx, cpuc->active_mask))
771 rdmsrl(x86_pmu_config_addr(idx), val);
772 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
774 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
775 wrmsrl(x86_pmu_config_addr(idx), val);
779 static void x86_pmu_disable(struct pmu *pmu)
781 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
783 if (!x86_pmu_initialized())
793 x86_pmu.disable_all();
796 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
799 if (hwc->extra_reg.reg)
800 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
801 wrmsrl(hwc->config_base, hwc->config | enable_mask);
804 static void x86_pmu_enable_all(int added)
806 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
809 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
810 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
812 if (!test_bit(idx, cpuc->active_mask))
815 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
819 static struct pmu pmu;
821 static inline int is_x86_event(struct perf_event *event)
823 return event->pmu == &pmu;
826 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
828 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
829 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
830 int i, j, w, wmax, num = 0;
831 struct hw_perf_event *hwc;
833 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
835 for (i = 0; i < n; i++) {
836 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
841 * fastpath, try to reuse previous register
843 for (i = 0; i < n; i++) {
844 hwc = &cpuc->event_list[i]->hw;
851 /* constraint still honored */
852 if (!test_bit(hwc->idx, c->idxmsk))
855 /* not already used */
856 if (test_bit(hwc->idx, used_mask))
859 __set_bit(hwc->idx, used_mask);
861 assign[i] = hwc->idx;
870 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
873 * weight = number of possible counters
875 * 1 = most constrained, only works on one counter
876 * wmax = least constrained, works on any counter
878 * assign events to counters starting with most
879 * constrained events.
881 wmax = x86_pmu.num_counters;
884 * when fixed event counters are present,
885 * wmax is incremented by 1 to account
886 * for one more choice
888 if (x86_pmu.num_counters_fixed)
891 for (w = 1, num = n; num && w <= wmax; w++) {
893 for (i = 0; num && i < n; i++) {
895 hwc = &cpuc->event_list[i]->hw;
900 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
901 if (!test_bit(j, used_mask))
905 if (j == X86_PMC_IDX_MAX)
908 __set_bit(j, used_mask);
917 * scheduling failed or is just a simulation,
918 * free resources if necessary
920 if (!assign || num) {
921 for (i = 0; i < n; i++) {
922 if (x86_pmu.put_event_constraints)
923 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
926 return num ? -ENOSPC : 0;
930 * dogrp: true if must collect siblings events (group)
931 * returns total number of events and error code
933 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
935 struct perf_event *event;
938 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
940 /* current number of events already accepted */
943 if (is_x86_event(leader)) {
946 cpuc->event_list[n] = leader;
952 list_for_each_entry(event, &leader->sibling_list, group_entry) {
953 if (!is_x86_event(event) ||
954 event->state <= PERF_EVENT_STATE_OFF)
960 cpuc->event_list[n] = event;
966 static inline void x86_assign_hw_event(struct perf_event *event,
967 struct cpu_hw_events *cpuc, int i)
969 struct hw_perf_event *hwc = &event->hw;
971 hwc->idx = cpuc->assign[i];
972 hwc->last_cpu = smp_processor_id();
973 hwc->last_tag = ++cpuc->tags[i];
975 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
976 hwc->config_base = 0;
978 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
979 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
980 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
982 hwc->config_base = x86_pmu_config_addr(hwc->idx);
983 hwc->event_base = x86_pmu_event_addr(hwc->idx);
987 static inline int match_prev_assignment(struct hw_perf_event *hwc,
988 struct cpu_hw_events *cpuc,
991 return hwc->idx == cpuc->assign[i] &&
992 hwc->last_cpu == smp_processor_id() &&
993 hwc->last_tag == cpuc->tags[i];
996 static void x86_pmu_start(struct perf_event *event, int flags);
997 static void x86_pmu_stop(struct perf_event *event, int flags);
999 static void x86_pmu_enable(struct pmu *pmu)
1001 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1002 struct perf_event *event;
1003 struct hw_perf_event *hwc;
1004 int i, added = cpuc->n_added;
1006 if (!x86_pmu_initialized())
1012 if (cpuc->n_added) {
1013 int n_running = cpuc->n_events - cpuc->n_added;
1015 * apply assignment obtained either from
1016 * hw_perf_group_sched_in() or x86_pmu_enable()
1018 * step1: save events moving to new counters
1019 * step2: reprogram moved events into new counters
1021 for (i = 0; i < n_running; i++) {
1022 event = cpuc->event_list[i];
1026 * we can avoid reprogramming counter if:
1027 * - assigned same counter as last time
1028 * - running on same CPU as last time
1029 * - no other event has used the counter since
1031 if (hwc->idx == -1 ||
1032 match_prev_assignment(hwc, cpuc, i))
1036 * Ensure we don't accidentally enable a stopped
1037 * counter simply because we rescheduled.
1039 if (hwc->state & PERF_HES_STOPPED)
1040 hwc->state |= PERF_HES_ARCH;
1042 x86_pmu_stop(event, PERF_EF_UPDATE);
1045 for (i = 0; i < cpuc->n_events; i++) {
1046 event = cpuc->event_list[i];
1049 if (!match_prev_assignment(hwc, cpuc, i))
1050 x86_assign_hw_event(event, cpuc, i);
1051 else if (i < n_running)
1054 if (hwc->state & PERF_HES_ARCH)
1057 x86_pmu_start(event, PERF_EF_RELOAD);
1060 perf_events_lapic_init();
1066 x86_pmu.enable_all(added);
1069 static inline void x86_pmu_disable_event(struct perf_event *event)
1071 struct hw_perf_event *hwc = &event->hw;
1073 wrmsrl(hwc->config_base, hwc->config);
1076 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1079 * Set the next IRQ period, based on the hwc->period_left value.
1080 * To be called with the event disabled in hw:
1083 x86_perf_event_set_period(struct perf_event *event)
1085 struct hw_perf_event *hwc = &event->hw;
1086 s64 left = local64_read(&hwc->period_left);
1087 s64 period = hwc->sample_period;
1088 int ret = 0, idx = hwc->idx;
1090 if (idx == X86_PMC_IDX_FIXED_BTS)
1094 * If we are way outside a reasonable range then just skip forward:
1096 if (unlikely(left <= -period)) {
1098 local64_set(&hwc->period_left, left);
1099 hwc->last_period = period;
1103 if (unlikely(left <= 0)) {
1105 local64_set(&hwc->period_left, left);
1106 hwc->last_period = period;
1110 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1112 if (unlikely(left < 2))
1115 if (left > x86_pmu.max_period)
1116 left = x86_pmu.max_period;
1118 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1121 * The hw event starts counting from this event offset,
1122 * mark it to be able to extra future deltas:
1124 local64_set(&hwc->prev_count, (u64)-left);
1126 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1129 * Due to erratum on certan cpu we need
1130 * a second write to be sure the register
1131 * is updated properly
1133 if (x86_pmu.perfctr_second_write) {
1134 wrmsrl(hwc->event_base,
1135 (u64)(-left) & x86_pmu.cntval_mask);
1138 perf_event_update_userpage(event);
1143 static void x86_pmu_enable_event(struct perf_event *event)
1145 if (__this_cpu_read(cpu_hw_events.enabled))
1146 __x86_pmu_enable_event(&event->hw,
1147 ARCH_PERFMON_EVENTSEL_ENABLE);
1151 * Add a single event to the PMU.
1153 * The event is added to the group of enabled events
1154 * but only if it can be scehduled with existing events.
1156 static int x86_pmu_add(struct perf_event *event, int flags)
1158 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1159 struct hw_perf_event *hwc;
1160 int assign[X86_PMC_IDX_MAX];
1165 perf_pmu_disable(event->pmu);
1166 n0 = cpuc->n_events;
1167 ret = n = collect_events(cpuc, event, false);
1171 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1172 if (!(flags & PERF_EF_START))
1173 hwc->state |= PERF_HES_ARCH;
1176 * If group events scheduling transaction was started,
1177 * skip the schedulability test here, it will be performed
1178 * at commit time (->commit_txn) as a whole
1180 if (cpuc->group_flag & PERF_EVENT_TXN)
1183 ret = x86_pmu.schedule_events(cpuc, n, assign);
1187 * copy new assignment, now we know it is possible
1188 * will be used by hw_perf_enable()
1190 memcpy(cpuc->assign, assign, n*sizeof(int));
1194 cpuc->n_added += n - n0;
1195 cpuc->n_txn += n - n0;
1199 perf_pmu_enable(event->pmu);
1203 static void x86_pmu_start(struct perf_event *event, int flags)
1205 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1206 int idx = event->hw.idx;
1208 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1211 if (WARN_ON_ONCE(idx == -1))
1214 if (flags & PERF_EF_RELOAD) {
1215 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1216 x86_perf_event_set_period(event);
1219 event->hw.state = 0;
1221 cpuc->events[idx] = event;
1222 __set_bit(idx, cpuc->active_mask);
1223 __set_bit(idx, cpuc->running);
1224 x86_pmu.enable(event);
1225 perf_event_update_userpage(event);
1228 void perf_event_print_debug(void)
1230 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1232 struct cpu_hw_events *cpuc;
1233 unsigned long flags;
1236 if (!x86_pmu.num_counters)
1239 local_irq_save(flags);
1241 cpu = smp_processor_id();
1242 cpuc = &per_cpu(cpu_hw_events, cpu);
1244 if (x86_pmu.version >= 2) {
1245 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1246 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1247 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1248 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1249 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1252 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1253 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1254 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1255 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1256 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1258 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1260 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1261 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1262 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1264 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1266 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1267 cpu, idx, pmc_ctrl);
1268 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1269 cpu, idx, pmc_count);
1270 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1271 cpu, idx, prev_left);
1273 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1274 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1276 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1277 cpu, idx, pmc_count);
1279 local_irq_restore(flags);
1282 static void x86_pmu_stop(struct perf_event *event, int flags)
1284 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1285 struct hw_perf_event *hwc = &event->hw;
1287 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1288 x86_pmu.disable(event);
1289 cpuc->events[hwc->idx] = NULL;
1290 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1291 hwc->state |= PERF_HES_STOPPED;
1294 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1296 * Drain the remaining delta count out of a event
1297 * that we are disabling:
1299 x86_perf_event_update(event);
1300 hwc->state |= PERF_HES_UPTODATE;
1304 static void x86_pmu_del(struct perf_event *event, int flags)
1306 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1310 * If we're called during a txn, we don't need to do anything.
1311 * The events never got scheduled and ->cancel_txn will truncate
1314 if (cpuc->group_flag & PERF_EVENT_TXN)
1317 x86_pmu_stop(event, PERF_EF_UPDATE);
1319 for (i = 0; i < cpuc->n_events; i++) {
1320 if (event == cpuc->event_list[i]) {
1322 if (x86_pmu.put_event_constraints)
1323 x86_pmu.put_event_constraints(cpuc, event);
1325 while (++i < cpuc->n_events)
1326 cpuc->event_list[i-1] = cpuc->event_list[i];
1332 perf_event_update_userpage(event);
1335 static int x86_pmu_handle_irq(struct pt_regs *regs)
1337 struct perf_sample_data data;
1338 struct cpu_hw_events *cpuc;
1339 struct perf_event *event;
1340 int idx, handled = 0;
1343 perf_sample_data_init(&data, 0);
1345 cpuc = &__get_cpu_var(cpu_hw_events);
1348 * Some chipsets need to unmask the LVTPC in a particular spot
1349 * inside the nmi handler. As a result, the unmasking was pushed
1350 * into all the nmi handlers.
1352 * This generic handler doesn't seem to have any issues where the
1353 * unmasking occurs so it was left at the top.
1355 apic_write(APIC_LVTPC, APIC_DM_NMI);
1357 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1358 if (!test_bit(idx, cpuc->active_mask)) {
1360 * Though we deactivated the counter some cpus
1361 * might still deliver spurious interrupts still
1362 * in flight. Catch them:
1364 if (__test_and_clear_bit(idx, cpuc->running))
1369 event = cpuc->events[idx];
1371 val = x86_perf_event_update(event);
1372 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1379 data.period = event->hw.last_period;
1381 if (!x86_perf_event_set_period(event))
1384 if (perf_event_overflow(event, &data, regs))
1385 x86_pmu_stop(event, 0);
1389 inc_irq_stat(apic_perf_irqs);
1394 void perf_events_lapic_init(void)
1396 if (!x86_pmu.apic || !x86_pmu_initialized())
1400 * Always use NMI for PMU
1402 apic_write(APIC_LVTPC, APIC_DM_NMI);
1405 struct pmu_nmi_state {
1406 unsigned int marked;
1410 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1412 static int __kprobes
1413 perf_event_nmi_handler(struct notifier_block *self,
1414 unsigned long cmd, void *__args)
1416 struct die_args *args = __args;
1417 unsigned int this_nmi;
1420 if (!atomic_read(&active_events))
1426 case DIE_NMIUNKNOWN:
1427 this_nmi = percpu_read(irq_stat.__nmi_count);
1428 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1429 /* let the kernel handle the unknown nmi */
1432 * This one is a PMU back-to-back nmi. Two events
1433 * trigger 'simultaneously' raising two back-to-back
1434 * NMIs. If the first NMI handles both, the latter
1435 * will be empty and daze the CPU. So, we drop it to
1436 * avoid false-positive 'unknown nmi' messages.
1443 handled = x86_pmu.handle_irq(args->regs);
1447 this_nmi = percpu_read(irq_stat.__nmi_count);
1448 if ((handled > 1) ||
1449 /* the next nmi could be a back-to-back nmi */
1450 ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1451 (__this_cpu_read(pmu_nmi.handled) > 1))) {
1453 * We could have two subsequent back-to-back nmis: The
1454 * first handles more than one counter, the 2nd
1455 * handles only one counter and the 3rd handles no
1458 * This is the 2nd nmi because the previous was
1459 * handling more than one counter. We will mark the
1460 * next (3rd) and then drop it if unhandled.
1462 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1463 __this_cpu_write(pmu_nmi.handled, handled);
1469 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1470 .notifier_call = perf_event_nmi_handler,
1472 .priority = NMI_LOCAL_LOW_PRIOR,
1475 static struct event_constraint unconstrained;
1476 static struct event_constraint emptyconstraint;
1478 static struct event_constraint *
1479 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1481 struct event_constraint *c;
1483 if (x86_pmu.event_constraints) {
1484 for_each_event_constraint(c, x86_pmu.event_constraints) {
1485 if ((event->hw.config & c->cmask) == c->code)
1490 return &unconstrained;
1493 #include "perf_event_amd.c"
1494 #include "perf_event_p6.c"
1495 #include "perf_event_p4.c"
1496 #include "perf_event_intel_lbr.c"
1497 #include "perf_event_intel_ds.c"
1498 #include "perf_event_intel.c"
1500 static int __cpuinit
1501 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1503 unsigned int cpu = (long)hcpu;
1504 int ret = NOTIFY_OK;
1506 switch (action & ~CPU_TASKS_FROZEN) {
1507 case CPU_UP_PREPARE:
1508 if (x86_pmu.cpu_prepare)
1509 ret = x86_pmu.cpu_prepare(cpu);
1513 if (x86_pmu.cpu_starting)
1514 x86_pmu.cpu_starting(cpu);
1518 if (x86_pmu.cpu_dying)
1519 x86_pmu.cpu_dying(cpu);
1522 case CPU_UP_CANCELED:
1524 if (x86_pmu.cpu_dead)
1525 x86_pmu.cpu_dead(cpu);
1535 static void __init pmu_check_apic(void)
1541 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1542 pr_info("no hardware sampling interrupt available.\n");
1545 static int __init init_hw_perf_events(void)
1547 struct event_constraint *c;
1550 pr_info("Performance Events: ");
1552 switch (boot_cpu_data.x86_vendor) {
1553 case X86_VENDOR_INTEL:
1554 err = intel_pmu_init();
1556 case X86_VENDOR_AMD:
1557 err = amd_pmu_init();
1563 pr_cont("no PMU driver, software events only.\n");
1569 /* sanity check that the hardware exists or is emulated */
1570 if (!check_hw_exists())
1573 pr_cont("%s PMU driver.\n", x86_pmu.name);
1578 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1579 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1580 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1581 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1583 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1585 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1586 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1587 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1588 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1591 x86_pmu.intel_ctrl |=
1592 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1594 perf_events_lapic_init();
1595 register_die_notifier(&perf_event_nmi_notifier);
1597 unconstrained = (struct event_constraint)
1598 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1599 0, x86_pmu.num_counters);
1601 if (x86_pmu.event_constraints) {
1602 for_each_event_constraint(c, x86_pmu.event_constraints) {
1603 if (c->cmask != X86_RAW_EVENT_MASK)
1606 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1607 c->weight += x86_pmu.num_counters;
1611 pr_info("... version: %d\n", x86_pmu.version);
1612 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1613 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1614 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1615 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1616 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1617 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1619 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1620 perf_cpu_notifier(x86_pmu_notifier);
1624 early_initcall(init_hw_perf_events);
1626 static inline void x86_pmu_read(struct perf_event *event)
1628 x86_perf_event_update(event);
1632 * Start group events scheduling transaction
1633 * Set the flag to make pmu::enable() not perform the
1634 * schedulability test, it will be performed at commit time
1636 static void x86_pmu_start_txn(struct pmu *pmu)
1638 perf_pmu_disable(pmu);
1639 __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1640 __this_cpu_write(cpu_hw_events.n_txn, 0);
1644 * Stop group events scheduling transaction
1645 * Clear the flag and pmu::enable() will perform the
1646 * schedulability test.
1648 static void x86_pmu_cancel_txn(struct pmu *pmu)
1650 __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1652 * Truncate the collected events.
1654 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1655 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1656 perf_pmu_enable(pmu);
1660 * Commit group events scheduling transaction
1661 * Perform the group schedulability test as a whole
1662 * Return 0 if success
1664 static int x86_pmu_commit_txn(struct pmu *pmu)
1666 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1667 int assign[X86_PMC_IDX_MAX];
1672 if (!x86_pmu_initialized())
1675 ret = x86_pmu.schedule_events(cpuc, n, assign);
1680 * copy new assignment, now we know it is possible
1681 * will be used by hw_perf_enable()
1683 memcpy(cpuc->assign, assign, n*sizeof(int));
1685 cpuc->group_flag &= ~PERF_EVENT_TXN;
1686 perf_pmu_enable(pmu);
1690 * a fake_cpuc is used to validate event groups. Due to
1691 * the extra reg logic, we need to also allocate a fake
1692 * per_core and per_cpu structure. Otherwise, group events
1693 * using extra reg may conflict without the kernel being
1694 * able to catch this when the last event gets added to
1697 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1699 kfree(cpuc->shared_regs);
1703 static struct cpu_hw_events *allocate_fake_cpuc(void)
1705 struct cpu_hw_events *cpuc;
1706 int cpu = raw_smp_processor_id();
1708 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1710 return ERR_PTR(-ENOMEM);
1712 /* only needed, if we have extra_regs */
1713 if (x86_pmu.extra_regs) {
1714 cpuc->shared_regs = allocate_shared_regs(cpu);
1715 if (!cpuc->shared_regs)
1720 free_fake_cpuc(cpuc);
1721 return ERR_PTR(-ENOMEM);
1725 * validate that we can schedule this event
1727 static int validate_event(struct perf_event *event)
1729 struct cpu_hw_events *fake_cpuc;
1730 struct event_constraint *c;
1733 fake_cpuc = allocate_fake_cpuc();
1734 if (IS_ERR(fake_cpuc))
1735 return PTR_ERR(fake_cpuc);
1737 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1739 if (!c || !c->weight)
1742 if (x86_pmu.put_event_constraints)
1743 x86_pmu.put_event_constraints(fake_cpuc, event);
1745 free_fake_cpuc(fake_cpuc);
1751 * validate a single event group
1753 * validation include:
1754 * - check events are compatible which each other
1755 * - events do not compete for the same counter
1756 * - number of events <= number of counters
1758 * validation ensures the group can be loaded onto the
1759 * PMU if it was the only group available.
1761 static int validate_group(struct perf_event *event)
1763 struct perf_event *leader = event->group_leader;
1764 struct cpu_hw_events *fake_cpuc;
1765 int ret = -ENOSPC, n;
1767 fake_cpuc = allocate_fake_cpuc();
1768 if (IS_ERR(fake_cpuc))
1769 return PTR_ERR(fake_cpuc);
1771 * the event is not yet connected with its
1772 * siblings therefore we must first collect
1773 * existing siblings, then add the new event
1774 * before we can simulate the scheduling
1776 n = collect_events(fake_cpuc, leader, true);
1780 fake_cpuc->n_events = n;
1781 n = collect_events(fake_cpuc, event, false);
1785 fake_cpuc->n_events = n;
1787 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1790 free_fake_cpuc(fake_cpuc);
1794 static int x86_pmu_event_init(struct perf_event *event)
1799 switch (event->attr.type) {
1801 case PERF_TYPE_HARDWARE:
1802 case PERF_TYPE_HW_CACHE:
1809 err = __x86_pmu_event_init(event);
1812 * we temporarily connect event to its pmu
1813 * such that validate_group() can classify
1814 * it as an x86 event using is_x86_event()
1819 if (event->group_leader != event)
1820 err = validate_group(event);
1822 err = validate_event(event);
1828 event->destroy(event);
1834 static struct pmu pmu = {
1835 .pmu_enable = x86_pmu_enable,
1836 .pmu_disable = x86_pmu_disable,
1838 .event_init = x86_pmu_event_init,
1842 .start = x86_pmu_start,
1843 .stop = x86_pmu_stop,
1844 .read = x86_pmu_read,
1846 .start_txn = x86_pmu_start_txn,
1847 .cancel_txn = x86_pmu_cancel_txn,
1848 .commit_txn = x86_pmu_commit_txn,
1855 static int backtrace_stack(void *data, char *name)
1860 static void backtrace_address(void *data, unsigned long addr, int reliable)
1862 struct perf_callchain_entry *entry = data;
1864 perf_callchain_store(entry, addr);
1867 static const struct stacktrace_ops backtrace_ops = {
1868 .stack = backtrace_stack,
1869 .address = backtrace_address,
1870 .walk_stack = print_context_stack_bp,
1874 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1876 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1877 /* TODO: We don't support guest os callchain now */
1881 perf_callchain_store(entry, regs->ip);
1883 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1886 #ifdef CONFIG_COMPAT
1888 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1890 /* 32-bit process in 64-bit kernel. */
1891 struct stack_frame_ia32 frame;
1892 const void __user *fp;
1894 if (!test_thread_flag(TIF_IA32))
1897 fp = compat_ptr(regs->bp);
1898 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1899 unsigned long bytes;
1900 frame.next_frame = 0;
1901 frame.return_address = 0;
1903 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1904 if (bytes != sizeof(frame))
1907 if (fp < compat_ptr(regs->sp))
1910 perf_callchain_store(entry, frame.return_address);
1911 fp = compat_ptr(frame.next_frame);
1917 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1924 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1926 struct stack_frame frame;
1927 const void __user *fp;
1929 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1930 /* TODO: We don't support guest os callchain now */
1934 fp = (void __user *)regs->bp;
1936 perf_callchain_store(entry, regs->ip);
1938 if (perf_callchain_user32(regs, entry))
1941 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1942 unsigned long bytes;
1943 frame.next_frame = NULL;
1944 frame.return_address = 0;
1946 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1947 if (bytes != sizeof(frame))
1950 if ((unsigned long)fp < regs->sp)
1953 perf_callchain_store(entry, frame.return_address);
1954 fp = frame.next_frame;
1958 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1962 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1963 ip = perf_guest_cbs->get_guest_ip();
1965 ip = instruction_pointer(regs);
1970 unsigned long perf_misc_flags(struct pt_regs *regs)
1974 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1975 if (perf_guest_cbs->is_user_mode())
1976 misc |= PERF_RECORD_MISC_GUEST_USER;
1978 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1980 if (user_mode(regs))
1981 misc |= PERF_RECORD_MISC_USER;
1983 misc |= PERF_RECORD_MISC_KERNEL;
1986 if (regs->flags & PERF_EFLAGS_EXACT)
1987 misc |= PERF_RECORD_MISC_EXACT_IP;