2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
51 unsigned long offset, addr = (unsigned long)from;
52 int type = in_nmi() ? KM_NMI : KM_IRQ0;
53 unsigned long size, len = 0;
59 ret = __get_user_pages_fast(addr, 1, 0, &page);
63 offset = addr & (PAGE_SIZE - 1);
64 size = min(PAGE_SIZE - offset, n - len);
66 map = kmap_atomic(page, type);
67 memcpy(to, map+offset, size);
68 kunmap_atomic(map, type);
80 struct event_constraint {
82 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
91 int nb_id; /* NorthBridge id */
92 int refcnt; /* reference count */
93 struct perf_event *owners[X86_PMC_IDX_MAX];
94 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
97 #define MAX_LBR_ENTRIES 16
99 struct cpu_hw_events {
101 * Generic x86 PMC bits
103 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
104 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
109 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
110 u64 tags[X86_PMC_IDX_MAX];
111 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
113 unsigned int group_flag;
116 * Intel DebugStore bits
118 struct debug_store *ds;
126 struct perf_branch_stack lbr_stack;
127 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
132 struct amd_nb *amd_nb;
135 #define __EVENT_CONSTRAINT(c, n, m, w) {\
136 { .idxmsk64 = (n) }, \
142 #define EVENT_CONSTRAINT(c, n, m) \
143 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
146 * Constraint on the Event code.
148 #define INTEL_EVENT_CONSTRAINT(c, n) \
149 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
152 * Constraint on the Event code + UMask + fixed-mask
154 * filter mask to validate fixed counter events.
155 * the following filters disqualify for fixed counters:
159 * The other filters are supported by fixed counters.
160 * The any-thread option is supported starting with v3.
162 #define FIXED_EVENT_CONSTRAINT(c, n) \
163 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
166 * Constraint on the Event code + UMask
168 #define PEBS_EVENT_CONSTRAINT(c, n) \
169 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
171 #define EVENT_CONSTRAINT_END \
172 EVENT_CONSTRAINT(0, 0, 0)
174 #define for_each_event_constraint(e, c) \
175 for ((e) = (c); (e)->weight; (e)++)
177 union perf_capabilities {
181 u64 pebs_arch_reg : 1;
189 * struct x86_pmu - generic x86 pmu
193 * Generic x86 PMC bits
197 int (*handle_irq)(struct pt_regs *);
198 void (*disable_all)(void);
199 void (*enable_all)(int added);
200 void (*enable)(struct perf_event *);
201 void (*disable)(struct perf_event *);
202 int (*hw_config)(struct perf_event *event);
203 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
206 u64 (*event_map)(int);
209 int num_counters_fixed;
214 struct event_constraint *
215 (*get_event_constraints)(struct cpu_hw_events *cpuc,
216 struct perf_event *event);
218 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
219 struct perf_event *event);
220 struct event_constraint *event_constraints;
221 void (*quirks)(void);
223 int (*cpu_prepare)(int cpu);
224 void (*cpu_starting)(int cpu);
225 void (*cpu_dying)(int cpu);
226 void (*cpu_dead)(int cpu);
229 * Intel Arch Perfmon v2+
232 union perf_capabilities intel_cap;
235 * Intel DebugStore bits
238 int pebs_record_size;
239 void (*drain_pebs)(struct pt_regs *regs);
240 struct event_constraint *pebs_constraints;
245 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
246 int lbr_nr; /* hardware stack size */
249 static struct x86_pmu x86_pmu __read_mostly;
251 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
255 static int x86_perf_event_set_period(struct perf_event *event);
258 * Generalized hw caching related hw_event table, filled
259 * in on a per model basis. A value of 0 means
260 * 'not supported', -1 means 'hw_event makes no sense on
261 * this CPU', any other value means the raw hw_event
265 #define C(x) PERF_COUNT_HW_CACHE_##x
267 static u64 __read_mostly hw_cache_event_ids
268 [PERF_COUNT_HW_CACHE_MAX]
269 [PERF_COUNT_HW_CACHE_OP_MAX]
270 [PERF_COUNT_HW_CACHE_RESULT_MAX];
273 * Propagate event elapsed time into the generic event.
274 * Can only be executed on the CPU where the event is active.
275 * Returns the delta events processed.
278 x86_perf_event_update(struct perf_event *event)
280 struct hw_perf_event *hwc = &event->hw;
281 int shift = 64 - x86_pmu.cntval_bits;
282 u64 prev_raw_count, new_raw_count;
286 if (idx == X86_PMC_IDX_FIXED_BTS)
290 * Careful: an NMI might modify the previous event value.
292 * Our tactic to handle this is to first atomically read and
293 * exchange a new raw count - then add that new-prev delta
294 * count to the generic event atomically:
297 prev_raw_count = atomic64_read(&hwc->prev_count);
298 rdmsrl(hwc->event_base + idx, new_raw_count);
300 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
301 new_raw_count) != prev_raw_count)
305 * Now we have the new raw value and have updated the prev
306 * timestamp already. We can now calculate the elapsed delta
307 * (event-)time and add that to the generic event.
309 * Careful, not all hw sign-extends above the physical width
312 delta = (new_raw_count << shift) - (prev_raw_count << shift);
315 atomic64_add(delta, &event->count);
316 atomic64_sub(delta, &hwc->period_left);
318 return new_raw_count;
321 static atomic_t active_events;
322 static DEFINE_MUTEX(pmc_reserve_mutex);
324 #ifdef CONFIG_X86_LOCAL_APIC
326 static bool reserve_pmc_hardware(void)
330 if (nmi_watchdog == NMI_LOCAL_APIC)
331 disable_lapic_nmi_watchdog();
333 for (i = 0; i < x86_pmu.num_counters; i++) {
334 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
338 for (i = 0; i < x86_pmu.num_counters; i++) {
339 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
346 for (i--; i >= 0; i--)
347 release_evntsel_nmi(x86_pmu.eventsel + i);
349 i = x86_pmu.num_counters;
352 for (i--; i >= 0; i--)
353 release_perfctr_nmi(x86_pmu.perfctr + i);
355 if (nmi_watchdog == NMI_LOCAL_APIC)
356 enable_lapic_nmi_watchdog();
361 static void release_pmc_hardware(void)
365 for (i = 0; i < x86_pmu.num_counters; i++) {
366 release_perfctr_nmi(x86_pmu.perfctr + i);
367 release_evntsel_nmi(x86_pmu.eventsel + i);
370 if (nmi_watchdog == NMI_LOCAL_APIC)
371 enable_lapic_nmi_watchdog();
376 static bool reserve_pmc_hardware(void) { return true; }
377 static void release_pmc_hardware(void) {}
381 static int reserve_ds_buffers(void);
382 static void release_ds_buffers(void);
384 static void hw_perf_event_destroy(struct perf_event *event)
386 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
387 release_pmc_hardware();
388 release_ds_buffers();
389 mutex_unlock(&pmc_reserve_mutex);
393 static inline int x86_pmu_initialized(void)
395 return x86_pmu.handle_irq != NULL;
399 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
401 unsigned int cache_type, cache_op, cache_result;
404 config = attr->config;
406 cache_type = (config >> 0) & 0xff;
407 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
410 cache_op = (config >> 8) & 0xff;
411 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
414 cache_result = (config >> 16) & 0xff;
415 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
418 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
431 static int x86_setup_perfctr(struct perf_event *event)
433 struct perf_event_attr *attr = &event->attr;
434 struct hw_perf_event *hwc = &event->hw;
437 if (!hwc->sample_period) {
438 hwc->sample_period = x86_pmu.max_period;
439 hwc->last_period = hwc->sample_period;
440 atomic64_set(&hwc->period_left, hwc->sample_period);
443 * If we have a PMU initialized but no APIC
444 * interrupts, we cannot sample hardware
445 * events (user-space has to fall back and
446 * sample via a hrtimer based software event):
452 if (attr->type == PERF_TYPE_RAW)
455 if (attr->type == PERF_TYPE_HW_CACHE)
456 return set_ext_hw_attr(hwc, attr);
458 if (attr->config >= x86_pmu.max_events)
464 config = x86_pmu.event_map(attr->config);
475 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
476 (hwc->sample_period == 1)) {
477 /* BTS is not supported by this architecture. */
481 /* BTS is currently only allowed for user-mode. */
482 if (!attr->exclude_kernel)
486 hwc->config |= config;
491 static int x86_pmu_hw_config(struct perf_event *event)
493 if (event->attr.precise_ip) {
496 /* Support for constant skid */
500 /* Support for IP fixup */
504 if (event->attr.precise_ip > precise)
510 * (keep 'enabled' bit clear for now)
512 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
515 * Count user and OS events unless requested not to
517 if (!event->attr.exclude_user)
518 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
519 if (!event->attr.exclude_kernel)
520 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
522 if (event->attr.type == PERF_TYPE_RAW)
523 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
525 return x86_setup_perfctr(event);
529 * Setup the hardware configuration for a given attr_type
531 static int __hw_perf_event_init(struct perf_event *event)
535 if (!x86_pmu_initialized())
539 if (!atomic_inc_not_zero(&active_events)) {
540 mutex_lock(&pmc_reserve_mutex);
541 if (atomic_read(&active_events) == 0) {
542 if (!reserve_pmc_hardware())
545 err = reserve_ds_buffers();
547 release_pmc_hardware();
551 atomic_inc(&active_events);
552 mutex_unlock(&pmc_reserve_mutex);
557 event->destroy = hw_perf_event_destroy;
560 event->hw.last_cpu = -1;
561 event->hw.last_tag = ~0ULL;
563 return x86_pmu.hw_config(event);
566 static void x86_pmu_disable_all(void)
568 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
571 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
574 if (!test_bit(idx, cpuc->active_mask))
576 rdmsrl(x86_pmu.eventsel + idx, val);
577 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
579 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
580 wrmsrl(x86_pmu.eventsel + idx, val);
584 void hw_perf_disable(void)
586 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
588 if (!x86_pmu_initialized())
598 x86_pmu.disable_all();
601 static void x86_pmu_enable_all(int added)
603 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
606 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
607 struct perf_event *event = cpuc->events[idx];
610 if (!test_bit(idx, cpuc->active_mask))
613 val = event->hw.config;
614 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
615 wrmsrl(x86_pmu.eventsel + idx, val);
619 static const struct pmu pmu;
621 static inline int is_x86_event(struct perf_event *event)
623 return event->pmu == &pmu;
626 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
628 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
629 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
630 int i, j, w, wmax, num = 0;
631 struct hw_perf_event *hwc;
633 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
635 for (i = 0; i < n; i++) {
636 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
641 * fastpath, try to reuse previous register
643 for (i = 0; i < n; i++) {
644 hwc = &cpuc->event_list[i]->hw;
651 /* constraint still honored */
652 if (!test_bit(hwc->idx, c->idxmsk))
655 /* not already used */
656 if (test_bit(hwc->idx, used_mask))
659 __set_bit(hwc->idx, used_mask);
661 assign[i] = hwc->idx;
670 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
673 * weight = number of possible counters
675 * 1 = most constrained, only works on one counter
676 * wmax = least constrained, works on any counter
678 * assign events to counters starting with most
679 * constrained events.
681 wmax = x86_pmu.num_counters;
684 * when fixed event counters are present,
685 * wmax is incremented by 1 to account
686 * for one more choice
688 if (x86_pmu.num_counters_fixed)
691 for (w = 1, num = n; num && w <= wmax; w++) {
693 for (i = 0; num && i < n; i++) {
695 hwc = &cpuc->event_list[i]->hw;
700 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
701 if (!test_bit(j, used_mask))
705 if (j == X86_PMC_IDX_MAX)
708 __set_bit(j, used_mask);
717 * scheduling failed or is just a simulation,
718 * free resources if necessary
720 if (!assign || num) {
721 for (i = 0; i < n; i++) {
722 if (x86_pmu.put_event_constraints)
723 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
726 return num ? -ENOSPC : 0;
730 * dogrp: true if must collect siblings events (group)
731 * returns total number of events and error code
733 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
735 struct perf_event *event;
738 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
740 /* current number of events already accepted */
743 if (is_x86_event(leader)) {
746 cpuc->event_list[n] = leader;
752 list_for_each_entry(event, &leader->sibling_list, group_entry) {
753 if (!is_x86_event(event) ||
754 event->state <= PERF_EVENT_STATE_OFF)
760 cpuc->event_list[n] = event;
766 static inline void x86_assign_hw_event(struct perf_event *event,
767 struct cpu_hw_events *cpuc, int i)
769 struct hw_perf_event *hwc = &event->hw;
771 hwc->idx = cpuc->assign[i];
772 hwc->last_cpu = smp_processor_id();
773 hwc->last_tag = ++cpuc->tags[i];
775 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
776 hwc->config_base = 0;
778 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
779 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
781 * We set it so that event_base + idx in wrmsr/rdmsr maps to
782 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
785 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
787 hwc->config_base = x86_pmu.eventsel;
788 hwc->event_base = x86_pmu.perfctr;
792 static inline int match_prev_assignment(struct hw_perf_event *hwc,
793 struct cpu_hw_events *cpuc,
796 return hwc->idx == cpuc->assign[i] &&
797 hwc->last_cpu == smp_processor_id() &&
798 hwc->last_tag == cpuc->tags[i];
801 static int x86_pmu_start(struct perf_event *event);
802 static void x86_pmu_stop(struct perf_event *event);
804 void hw_perf_enable(void)
806 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
807 struct perf_event *event;
808 struct hw_perf_event *hwc;
809 int i, added = cpuc->n_added;
811 if (!x86_pmu_initialized())
818 int n_running = cpuc->n_events - cpuc->n_added;
820 * apply assignment obtained either from
821 * hw_perf_group_sched_in() or x86_pmu_enable()
823 * step1: save events moving to new counters
824 * step2: reprogram moved events into new counters
826 for (i = 0; i < n_running; i++) {
827 event = cpuc->event_list[i];
831 * we can avoid reprogramming counter if:
832 * - assigned same counter as last time
833 * - running on same CPU as last time
834 * - no other event has used the counter since
836 if (hwc->idx == -1 ||
837 match_prev_assignment(hwc, cpuc, i))
843 for (i = 0; i < cpuc->n_events; i++) {
844 event = cpuc->event_list[i];
847 if (!match_prev_assignment(hwc, cpuc, i))
848 x86_assign_hw_event(event, cpuc, i);
849 else if (i < n_running)
852 x86_pmu_start(event);
855 perf_events_lapic_init();
861 x86_pmu.enable_all(added);
864 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
867 wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
870 static inline void x86_pmu_disable_event(struct perf_event *event)
872 struct hw_perf_event *hwc = &event->hw;
874 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
877 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
880 * Set the next IRQ period, based on the hwc->period_left value.
881 * To be called with the event disabled in hw:
884 x86_perf_event_set_period(struct perf_event *event)
886 struct hw_perf_event *hwc = &event->hw;
887 s64 left = atomic64_read(&hwc->period_left);
888 s64 period = hwc->sample_period;
889 int ret = 0, idx = hwc->idx;
891 if (idx == X86_PMC_IDX_FIXED_BTS)
895 * If we are way outside a reasonable range then just skip forward:
897 if (unlikely(left <= -period)) {
899 atomic64_set(&hwc->period_left, left);
900 hwc->last_period = period;
904 if (unlikely(left <= 0)) {
906 atomic64_set(&hwc->period_left, left);
907 hwc->last_period = period;
911 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
913 if (unlikely(left < 2))
916 if (left > x86_pmu.max_period)
917 left = x86_pmu.max_period;
919 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
922 * The hw event starts counting from this event offset,
923 * mark it to be able to extra future deltas:
925 atomic64_set(&hwc->prev_count, (u64)-left);
927 wrmsrl(hwc->event_base + idx,
928 (u64)(-left) & x86_pmu.cntval_mask);
930 perf_event_update_userpage(event);
935 static void x86_pmu_enable_event(struct perf_event *event)
937 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
939 __x86_pmu_enable_event(&event->hw,
940 ARCH_PERFMON_EVENTSEL_ENABLE);
944 * activate a single event
946 * The event is added to the group of enabled events
947 * but only if it can be scehduled with existing events.
949 * Called with PMU disabled. If successful and return value 1,
950 * then guaranteed to call perf_enable() and hw_perf_enable()
952 static int x86_pmu_enable(struct perf_event *event)
954 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
955 struct hw_perf_event *hwc;
956 int assign[X86_PMC_IDX_MAX];
962 n = collect_events(cpuc, event, false);
967 * If group events scheduling transaction was started,
968 * skip the schedulability test here, it will be peformed
969 * at commit time(->commit_txn) as a whole
971 if (cpuc->group_flag & PERF_EVENT_TXN_STARTED)
974 ret = x86_pmu.schedule_events(cpuc, n, assign);
978 * copy new assignment, now we know it is possible
979 * will be used by hw_perf_enable()
981 memcpy(cpuc->assign, assign, n*sizeof(int));
985 cpuc->n_added += n - n0;
990 static int x86_pmu_start(struct perf_event *event)
992 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
993 int idx = event->hw.idx;
998 x86_perf_event_set_period(event);
999 cpuc->events[idx] = event;
1000 __set_bit(idx, cpuc->active_mask);
1001 x86_pmu.enable(event);
1002 perf_event_update_userpage(event);
1007 static void x86_pmu_unthrottle(struct perf_event *event)
1009 int ret = x86_pmu_start(event);
1013 void perf_event_print_debug(void)
1015 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1017 struct cpu_hw_events *cpuc;
1018 unsigned long flags;
1021 if (!x86_pmu.num_counters)
1024 local_irq_save(flags);
1026 cpu = smp_processor_id();
1027 cpuc = &per_cpu(cpu_hw_events, cpu);
1029 if (x86_pmu.version >= 2) {
1030 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1031 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1032 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1033 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1034 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1037 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1038 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1039 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1040 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1041 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1043 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1045 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1046 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1047 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1049 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1051 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1052 cpu, idx, pmc_ctrl);
1053 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1054 cpu, idx, pmc_count);
1055 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1056 cpu, idx, prev_left);
1058 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1059 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1061 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1062 cpu, idx, pmc_count);
1064 local_irq_restore(flags);
1067 static void x86_pmu_stop(struct perf_event *event)
1069 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1070 struct hw_perf_event *hwc = &event->hw;
1073 if (!__test_and_clear_bit(idx, cpuc->active_mask))
1076 x86_pmu.disable(event);
1079 * Drain the remaining delta count out of a event
1080 * that we are disabling:
1082 x86_perf_event_update(event);
1084 cpuc->events[idx] = NULL;
1087 static void x86_pmu_disable(struct perf_event *event)
1089 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1092 x86_pmu_stop(event);
1094 for (i = 0; i < cpuc->n_events; i++) {
1095 if (event == cpuc->event_list[i]) {
1097 if (x86_pmu.put_event_constraints)
1098 x86_pmu.put_event_constraints(cpuc, event);
1100 while (++i < cpuc->n_events)
1101 cpuc->event_list[i-1] = cpuc->event_list[i];
1107 perf_event_update_userpage(event);
1110 static int x86_pmu_handle_irq(struct pt_regs *regs)
1112 struct perf_sample_data data;
1113 struct cpu_hw_events *cpuc;
1114 struct perf_event *event;
1115 struct hw_perf_event *hwc;
1116 int idx, handled = 0;
1119 perf_sample_data_init(&data, 0);
1121 cpuc = &__get_cpu_var(cpu_hw_events);
1123 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1124 if (!test_bit(idx, cpuc->active_mask))
1127 event = cpuc->events[idx];
1130 val = x86_perf_event_update(event);
1131 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1138 data.period = event->hw.last_period;
1140 if (!x86_perf_event_set_period(event))
1143 if (perf_event_overflow(event, 1, &data, regs))
1144 x86_pmu_stop(event);
1148 inc_irq_stat(apic_perf_irqs);
1153 void smp_perf_pending_interrupt(struct pt_regs *regs)
1157 inc_irq_stat(apic_pending_irqs);
1158 perf_event_do_pending();
1162 void set_perf_event_pending(void)
1164 #ifdef CONFIG_X86_LOCAL_APIC
1165 if (!x86_pmu.apic || !x86_pmu_initialized())
1168 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1172 void perf_events_lapic_init(void)
1174 if (!x86_pmu.apic || !x86_pmu_initialized())
1178 * Always use NMI for PMU
1180 apic_write(APIC_LVTPC, APIC_DM_NMI);
1183 static int __kprobes
1184 perf_event_nmi_handler(struct notifier_block *self,
1185 unsigned long cmd, void *__args)
1187 struct die_args *args = __args;
1188 struct pt_regs *regs;
1190 if (!atomic_read(&active_events))
1204 apic_write(APIC_LVTPC, APIC_DM_NMI);
1206 * Can't rely on the handled return value to say it was our NMI, two
1207 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1209 * If the first NMI handles both, the latter will be empty and daze
1212 x86_pmu.handle_irq(regs);
1217 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1218 .notifier_call = perf_event_nmi_handler,
1223 static struct event_constraint unconstrained;
1224 static struct event_constraint emptyconstraint;
1226 static struct event_constraint *
1227 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1229 struct event_constraint *c;
1231 if (x86_pmu.event_constraints) {
1232 for_each_event_constraint(c, x86_pmu.event_constraints) {
1233 if ((event->hw.config & c->cmask) == c->code)
1238 return &unconstrained;
1241 #include "perf_event_amd.c"
1242 #include "perf_event_p6.c"
1243 #include "perf_event_p4.c"
1244 #include "perf_event_intel_lbr.c"
1245 #include "perf_event_intel_ds.c"
1246 #include "perf_event_intel.c"
1248 static int __cpuinit
1249 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1251 unsigned int cpu = (long)hcpu;
1252 int ret = NOTIFY_OK;
1254 switch (action & ~CPU_TASKS_FROZEN) {
1255 case CPU_UP_PREPARE:
1256 if (x86_pmu.cpu_prepare)
1257 ret = x86_pmu.cpu_prepare(cpu);
1261 if (x86_pmu.cpu_starting)
1262 x86_pmu.cpu_starting(cpu);
1266 if (x86_pmu.cpu_dying)
1267 x86_pmu.cpu_dying(cpu);
1270 case CPU_UP_CANCELED:
1272 if (x86_pmu.cpu_dead)
1273 x86_pmu.cpu_dead(cpu);
1283 static void __init pmu_check_apic(void)
1289 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1290 pr_info("no hardware sampling interrupt available.\n");
1293 void __init init_hw_perf_events(void)
1295 struct event_constraint *c;
1298 pr_info("Performance Events: ");
1300 switch (boot_cpu_data.x86_vendor) {
1301 case X86_VENDOR_INTEL:
1302 err = intel_pmu_init();
1304 case X86_VENDOR_AMD:
1305 err = amd_pmu_init();
1311 pr_cont("no PMU driver, software events only.\n");
1317 pr_cont("%s PMU driver.\n", x86_pmu.name);
1322 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1323 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1324 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1325 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1327 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1328 perf_max_events = x86_pmu.num_counters;
1330 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1331 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1332 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1333 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1336 x86_pmu.intel_ctrl |=
1337 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1339 perf_events_lapic_init();
1340 register_die_notifier(&perf_event_nmi_notifier);
1342 unconstrained = (struct event_constraint)
1343 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1344 0, x86_pmu.num_counters);
1346 if (x86_pmu.event_constraints) {
1347 for_each_event_constraint(c, x86_pmu.event_constraints) {
1348 if (c->cmask != X86_RAW_EVENT_MASK)
1351 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1352 c->weight += x86_pmu.num_counters;
1356 pr_info("... version: %d\n", x86_pmu.version);
1357 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1358 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1359 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1360 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1361 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1362 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1364 perf_cpu_notifier(x86_pmu_notifier);
1367 static inline void x86_pmu_read(struct perf_event *event)
1369 x86_perf_event_update(event);
1373 * Start group events scheduling transaction
1374 * Set the flag to make pmu::enable() not perform the
1375 * schedulability test, it will be performed at commit time
1377 static void x86_pmu_start_txn(const struct pmu *pmu)
1379 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1381 cpuc->group_flag |= PERF_EVENT_TXN_STARTED;
1385 * Stop group events scheduling transaction
1386 * Clear the flag and pmu::enable() will perform the
1387 * schedulability test.
1389 static void x86_pmu_cancel_txn(const struct pmu *pmu)
1391 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1393 cpuc->group_flag &= ~PERF_EVENT_TXN_STARTED;
1397 * Commit group events scheduling transaction
1398 * Perform the group schedulability test as a whole
1399 * Return 0 if success
1401 static int x86_pmu_commit_txn(const struct pmu *pmu)
1403 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1404 int assign[X86_PMC_IDX_MAX];
1409 if (!x86_pmu_initialized())
1412 ret = x86_pmu.schedule_events(cpuc, n, assign);
1417 * copy new assignment, now we know it is possible
1418 * will be used by hw_perf_enable()
1420 memcpy(cpuc->assign, assign, n*sizeof(int));
1425 static const struct pmu pmu = {
1426 .enable = x86_pmu_enable,
1427 .disable = x86_pmu_disable,
1428 .start = x86_pmu_start,
1429 .stop = x86_pmu_stop,
1430 .read = x86_pmu_read,
1431 .unthrottle = x86_pmu_unthrottle,
1432 .start_txn = x86_pmu_start_txn,
1433 .cancel_txn = x86_pmu_cancel_txn,
1434 .commit_txn = x86_pmu_commit_txn,
1438 * validate that we can schedule this event
1440 static int validate_event(struct perf_event *event)
1442 struct cpu_hw_events *fake_cpuc;
1443 struct event_constraint *c;
1446 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1450 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1452 if (!c || !c->weight)
1455 if (x86_pmu.put_event_constraints)
1456 x86_pmu.put_event_constraints(fake_cpuc, event);
1464 * validate a single event group
1466 * validation include:
1467 * - check events are compatible which each other
1468 * - events do not compete for the same counter
1469 * - number of events <= number of counters
1471 * validation ensures the group can be loaded onto the
1472 * PMU if it was the only group available.
1474 static int validate_group(struct perf_event *event)
1476 struct perf_event *leader = event->group_leader;
1477 struct cpu_hw_events *fake_cpuc;
1481 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1486 * the event is not yet connected with its
1487 * siblings therefore we must first collect
1488 * existing siblings, then add the new event
1489 * before we can simulate the scheduling
1492 n = collect_events(fake_cpuc, leader, true);
1496 fake_cpuc->n_events = n;
1497 n = collect_events(fake_cpuc, event, false);
1501 fake_cpuc->n_events = n;
1503 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1511 const struct pmu *hw_perf_event_init(struct perf_event *event)
1513 const struct pmu *tmp;
1516 err = __hw_perf_event_init(event);
1519 * we temporarily connect event to its pmu
1520 * such that validate_group() can classify
1521 * it as an x86 event using is_x86_event()
1526 if (event->group_leader != event)
1527 err = validate_group(event);
1529 err = validate_event(event);
1535 event->destroy(event);
1536 return ERR_PTR(err);
1547 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1549 if (entry->nr < PERF_MAX_STACK_DEPTH)
1550 entry->ip[entry->nr++] = ip;
1553 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1554 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1558 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1560 /* Ignore warnings */
1563 static void backtrace_warning(void *data, char *msg)
1565 /* Ignore warnings */
1568 static int backtrace_stack(void *data, char *name)
1573 static void backtrace_address(void *data, unsigned long addr, int reliable)
1575 struct perf_callchain_entry *entry = data;
1577 callchain_store(entry, addr);
1580 static const struct stacktrace_ops backtrace_ops = {
1581 .warning = backtrace_warning,
1582 .warning_symbol = backtrace_warning_symbol,
1583 .stack = backtrace_stack,
1584 .address = backtrace_address,
1585 .walk_stack = print_context_stack_bp,
1588 #include "../dumpstack.h"
1591 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1593 callchain_store(entry, PERF_CONTEXT_KERNEL);
1594 callchain_store(entry, regs->ip);
1596 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1599 #ifdef CONFIG_COMPAT
1601 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1603 /* 32-bit process in 64-bit kernel. */
1604 struct stack_frame_ia32 frame;
1605 const void __user *fp;
1607 if (!test_thread_flag(TIF_IA32))
1610 fp = compat_ptr(regs->bp);
1611 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1612 unsigned long bytes;
1613 frame.next_frame = 0;
1614 frame.return_address = 0;
1616 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1617 if (bytes != sizeof(frame))
1620 if (fp < compat_ptr(regs->sp))
1623 callchain_store(entry, frame.return_address);
1624 fp = compat_ptr(frame.next_frame);
1630 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1637 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1639 struct stack_frame frame;
1640 const void __user *fp;
1642 if (!user_mode(regs))
1643 regs = task_pt_regs(current);
1645 fp = (void __user *)regs->bp;
1647 callchain_store(entry, PERF_CONTEXT_USER);
1648 callchain_store(entry, regs->ip);
1650 if (perf_callchain_user32(regs, entry))
1653 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1654 unsigned long bytes;
1655 frame.next_frame = NULL;
1656 frame.return_address = 0;
1658 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1659 if (bytes != sizeof(frame))
1662 if ((unsigned long)fp < regs->sp)
1665 callchain_store(entry, frame.return_address);
1666 fp = frame.next_frame;
1671 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1678 is_user = user_mode(regs);
1680 if (is_user && current->state != TASK_RUNNING)
1684 perf_callchain_kernel(regs, entry);
1687 perf_callchain_user(regs, entry);
1690 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1692 struct perf_callchain_entry *entry;
1694 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1695 /* TODO: We don't support guest os callchain now */
1700 entry = &__get_cpu_var(pmc_nmi_entry);
1702 entry = &__get_cpu_var(pmc_irq_entry);
1706 perf_do_callchain(regs, entry);
1711 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1715 * perf_arch_fetch_caller_regs adds another call, we need to increment
1718 regs->bp = rewind_frame_pointer(skip + 1);
1719 regs->cs = __KERNEL_CS;
1721 * We abuse bit 3 to pass exact information, see perf_misc_flags
1722 * and the comment with PERF_EFLAGS_EXACT.
1727 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1731 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1732 ip = perf_guest_cbs->get_guest_ip();
1734 ip = instruction_pointer(regs);
1739 unsigned long perf_misc_flags(struct pt_regs *regs)
1743 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1744 if (perf_guest_cbs->is_user_mode())
1745 misc |= PERF_RECORD_MISC_GUEST_USER;
1747 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1749 if (user_mode(regs))
1750 misc |= PERF_RECORD_MISC_USER;
1752 misc |= PERF_RECORD_MISC_KERNEL;
1755 if (regs->flags & PERF_EFLAGS_EXACT)
1756 misc |= PERF_RECORD_MISC_EXACT_IP;