2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
51 unsigned long offset, addr = (unsigned long)from;
52 unsigned long size, len = 0;
58 ret = __get_user_pages_fast(addr, 1, 0, &page);
62 offset = addr & (PAGE_SIZE - 1);
63 size = min(PAGE_SIZE - offset, n - len);
65 map = kmap_atomic(page);
66 memcpy(to, map+offset, size);
79 struct event_constraint {
81 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
90 int nb_id; /* NorthBridge id */
91 int refcnt; /* reference count */
92 struct perf_event *owners[X86_PMC_IDX_MAX];
93 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
96 #define MAX_LBR_ENTRIES 16
98 struct cpu_hw_events {
100 * Generic x86 PMC bits
102 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
103 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
104 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
110 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
111 u64 tags[X86_PMC_IDX_MAX];
112 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
114 unsigned int group_flag;
117 * Intel DebugStore bits
119 struct debug_store *ds;
127 struct perf_branch_stack lbr_stack;
128 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
133 struct amd_nb *amd_nb;
136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
137 { .idxmsk64 = (n) }, \
143 #define EVENT_CONSTRAINT(c, n, m) \
144 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
147 * Constraint on the Event code.
149 #define INTEL_EVENT_CONSTRAINT(c, n) \
150 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
153 * Constraint on the Event code + UMask + fixed-mask
155 * filter mask to validate fixed counter events.
156 * the following filters disqualify for fixed counters:
160 * The other filters are supported by fixed counters.
161 * The any-thread option is supported starting with v3.
163 #define FIXED_EVENT_CONSTRAINT(c, n) \
164 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
167 * Constraint on the Event code + UMask
169 #define PEBS_EVENT_CONSTRAINT(c, n) \
170 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
172 #define EVENT_CONSTRAINT_END \
173 EVENT_CONSTRAINT(0, 0, 0)
175 #define for_each_event_constraint(e, c) \
176 for ((e) = (c); (e)->weight; (e)++)
178 union perf_capabilities {
182 u64 pebs_arch_reg : 1;
190 * struct x86_pmu - generic x86 pmu
194 * Generic x86 PMC bits
198 int (*handle_irq)(struct pt_regs *);
199 void (*disable_all)(void);
200 void (*enable_all)(int added);
201 void (*enable)(struct perf_event *);
202 void (*disable)(struct perf_event *);
203 int (*hw_config)(struct perf_event *event);
204 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
207 u64 (*event_map)(int);
210 int num_counters_fixed;
215 struct event_constraint *
216 (*get_event_constraints)(struct cpu_hw_events *cpuc,
217 struct perf_event *event);
219 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
220 struct perf_event *event);
221 struct event_constraint *event_constraints;
222 void (*quirks)(void);
223 int perfctr_second_write;
225 int (*cpu_prepare)(int cpu);
226 void (*cpu_starting)(int cpu);
227 void (*cpu_dying)(int cpu);
228 void (*cpu_dead)(int cpu);
231 * Intel Arch Perfmon v2+
234 union perf_capabilities intel_cap;
237 * Intel DebugStore bits
240 int bts_active, pebs_active;
241 int pebs_record_size;
242 void (*drain_pebs)(struct pt_regs *regs);
243 struct event_constraint *pebs_constraints;
248 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
249 int lbr_nr; /* hardware stack size */
252 static struct x86_pmu x86_pmu __read_mostly;
254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
258 static int x86_perf_event_set_period(struct perf_event *event);
261 * Generalized hw caching related hw_event table, filled
262 * in on a per model basis. A value of 0 means
263 * 'not supported', -1 means 'hw_event makes no sense on
264 * this CPU', any other value means the raw hw_event
268 #define C(x) PERF_COUNT_HW_CACHE_##x
270 static u64 __read_mostly hw_cache_event_ids
271 [PERF_COUNT_HW_CACHE_MAX]
272 [PERF_COUNT_HW_CACHE_OP_MAX]
273 [PERF_COUNT_HW_CACHE_RESULT_MAX];
276 * Propagate event elapsed time into the generic event.
277 * Can only be executed on the CPU where the event is active.
278 * Returns the delta events processed.
281 x86_perf_event_update(struct perf_event *event)
283 struct hw_perf_event *hwc = &event->hw;
284 int shift = 64 - x86_pmu.cntval_bits;
285 u64 prev_raw_count, new_raw_count;
289 if (idx == X86_PMC_IDX_FIXED_BTS)
293 * Careful: an NMI might modify the previous event value.
295 * Our tactic to handle this is to first atomically read and
296 * exchange a new raw count - then add that new-prev delta
297 * count to the generic event atomically:
300 prev_raw_count = local64_read(&hwc->prev_count);
301 rdmsrl(hwc->event_base + idx, new_raw_count);
303 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
304 new_raw_count) != prev_raw_count)
308 * Now we have the new raw value and have updated the prev
309 * timestamp already. We can now calculate the elapsed delta
310 * (event-)time and add that to the generic event.
312 * Careful, not all hw sign-extends above the physical width
315 delta = (new_raw_count << shift) - (prev_raw_count << shift);
318 local64_add(delta, &event->count);
319 local64_sub(delta, &hwc->period_left);
321 return new_raw_count;
324 static atomic_t active_events;
325 static DEFINE_MUTEX(pmc_reserve_mutex);
327 #ifdef CONFIG_X86_LOCAL_APIC
329 static bool reserve_pmc_hardware(void)
333 if (nmi_watchdog == NMI_LOCAL_APIC)
334 disable_lapic_nmi_watchdog();
336 for (i = 0; i < x86_pmu.num_counters; i++) {
337 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
341 for (i = 0; i < x86_pmu.num_counters; i++) {
342 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
349 for (i--; i >= 0; i--)
350 release_evntsel_nmi(x86_pmu.eventsel + i);
352 i = x86_pmu.num_counters;
355 for (i--; i >= 0; i--)
356 release_perfctr_nmi(x86_pmu.perfctr + i);
358 if (nmi_watchdog == NMI_LOCAL_APIC)
359 enable_lapic_nmi_watchdog();
364 static void release_pmc_hardware(void)
368 for (i = 0; i < x86_pmu.num_counters; i++) {
369 release_perfctr_nmi(x86_pmu.perfctr + i);
370 release_evntsel_nmi(x86_pmu.eventsel + i);
373 if (nmi_watchdog == NMI_LOCAL_APIC)
374 enable_lapic_nmi_watchdog();
379 static bool reserve_pmc_hardware(void) { return true; }
380 static void release_pmc_hardware(void) {}
384 static void reserve_ds_buffers(void);
385 static void release_ds_buffers(void);
387 static void hw_perf_event_destroy(struct perf_event *event)
389 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
390 release_pmc_hardware();
391 release_ds_buffers();
392 mutex_unlock(&pmc_reserve_mutex);
396 static inline int x86_pmu_initialized(void)
398 return x86_pmu.handle_irq != NULL;
402 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
404 unsigned int cache_type, cache_op, cache_result;
407 config = attr->config;
409 cache_type = (config >> 0) & 0xff;
410 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
413 cache_op = (config >> 8) & 0xff;
414 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
417 cache_result = (config >> 16) & 0xff;
418 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
421 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
434 static int x86_setup_perfctr(struct perf_event *event)
436 struct perf_event_attr *attr = &event->attr;
437 struct hw_perf_event *hwc = &event->hw;
440 if (!hwc->sample_period) {
441 hwc->sample_period = x86_pmu.max_period;
442 hwc->last_period = hwc->sample_period;
443 local64_set(&hwc->period_left, hwc->sample_period);
446 * If we have a PMU initialized but no APIC
447 * interrupts, we cannot sample hardware
448 * events (user-space has to fall back and
449 * sample via a hrtimer based software event):
455 if (attr->type == PERF_TYPE_RAW)
458 if (attr->type == PERF_TYPE_HW_CACHE)
459 return set_ext_hw_attr(hwc, attr);
461 if (attr->config >= x86_pmu.max_events)
467 config = x86_pmu.event_map(attr->config);
478 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
479 (hwc->sample_period == 1)) {
480 /* BTS is not supported by this architecture. */
481 if (!x86_pmu.bts_active)
484 /* BTS is currently only allowed for user-mode. */
485 if (!attr->exclude_kernel)
489 hwc->config |= config;
494 static int x86_pmu_hw_config(struct perf_event *event)
496 if (event->attr.precise_ip) {
499 /* Support for constant skid */
500 if (x86_pmu.pebs_active) {
503 /* Support for IP fixup */
508 if (event->attr.precise_ip > precise)
514 * (keep 'enabled' bit clear for now)
516 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
519 * Count user and OS events unless requested not to
521 if (!event->attr.exclude_user)
522 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
523 if (!event->attr.exclude_kernel)
524 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
526 if (event->attr.type == PERF_TYPE_RAW)
527 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
529 return x86_setup_perfctr(event);
533 * Setup the hardware configuration for a given attr_type
535 static int __x86_pmu_event_init(struct perf_event *event)
539 if (!x86_pmu_initialized())
543 if (!atomic_inc_not_zero(&active_events)) {
544 mutex_lock(&pmc_reserve_mutex);
545 if (atomic_read(&active_events) == 0) {
546 if (!reserve_pmc_hardware())
549 reserve_ds_buffers();
552 atomic_inc(&active_events);
553 mutex_unlock(&pmc_reserve_mutex);
558 event->destroy = hw_perf_event_destroy;
561 event->hw.last_cpu = -1;
562 event->hw.last_tag = ~0ULL;
564 return x86_pmu.hw_config(event);
567 static void x86_pmu_disable_all(void)
569 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
572 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
575 if (!test_bit(idx, cpuc->active_mask))
577 rdmsrl(x86_pmu.eventsel + idx, val);
578 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
580 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
581 wrmsrl(x86_pmu.eventsel + idx, val);
585 static void x86_pmu_disable(struct pmu *pmu)
587 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
589 if (!x86_pmu_initialized())
599 x86_pmu.disable_all();
602 static void x86_pmu_enable_all(int added)
604 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
607 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
608 struct perf_event *event = cpuc->events[idx];
611 if (!test_bit(idx, cpuc->active_mask))
614 val = event->hw.config;
615 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
616 wrmsrl(x86_pmu.eventsel + idx, val);
620 static struct pmu pmu;
622 static inline int is_x86_event(struct perf_event *event)
624 return event->pmu == &pmu;
627 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
629 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
630 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
631 int i, j, w, wmax, num = 0;
632 struct hw_perf_event *hwc;
634 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
636 for (i = 0; i < n; i++) {
637 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
642 * fastpath, try to reuse previous register
644 for (i = 0; i < n; i++) {
645 hwc = &cpuc->event_list[i]->hw;
652 /* constraint still honored */
653 if (!test_bit(hwc->idx, c->idxmsk))
656 /* not already used */
657 if (test_bit(hwc->idx, used_mask))
660 __set_bit(hwc->idx, used_mask);
662 assign[i] = hwc->idx;
671 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
674 * weight = number of possible counters
676 * 1 = most constrained, only works on one counter
677 * wmax = least constrained, works on any counter
679 * assign events to counters starting with most
680 * constrained events.
682 wmax = x86_pmu.num_counters;
685 * when fixed event counters are present,
686 * wmax is incremented by 1 to account
687 * for one more choice
689 if (x86_pmu.num_counters_fixed)
692 for (w = 1, num = n; num && w <= wmax; w++) {
694 for (i = 0; num && i < n; i++) {
696 hwc = &cpuc->event_list[i]->hw;
701 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
702 if (!test_bit(j, used_mask))
706 if (j == X86_PMC_IDX_MAX)
709 __set_bit(j, used_mask);
718 * scheduling failed or is just a simulation,
719 * free resources if necessary
721 if (!assign || num) {
722 for (i = 0; i < n; i++) {
723 if (x86_pmu.put_event_constraints)
724 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
727 return num ? -ENOSPC : 0;
731 * dogrp: true if must collect siblings events (group)
732 * returns total number of events and error code
734 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
736 struct perf_event *event;
739 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
741 /* current number of events already accepted */
744 if (is_x86_event(leader)) {
747 cpuc->event_list[n] = leader;
753 list_for_each_entry(event, &leader->sibling_list, group_entry) {
754 if (!is_x86_event(event) ||
755 event->state <= PERF_EVENT_STATE_OFF)
761 cpuc->event_list[n] = event;
767 static inline void x86_assign_hw_event(struct perf_event *event,
768 struct cpu_hw_events *cpuc, int i)
770 struct hw_perf_event *hwc = &event->hw;
772 hwc->idx = cpuc->assign[i];
773 hwc->last_cpu = smp_processor_id();
774 hwc->last_tag = ++cpuc->tags[i];
776 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
777 hwc->config_base = 0;
779 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
780 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
782 * We set it so that event_base + idx in wrmsr/rdmsr maps to
783 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
786 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
788 hwc->config_base = x86_pmu.eventsel;
789 hwc->event_base = x86_pmu.perfctr;
793 static inline int match_prev_assignment(struct hw_perf_event *hwc,
794 struct cpu_hw_events *cpuc,
797 return hwc->idx == cpuc->assign[i] &&
798 hwc->last_cpu == smp_processor_id() &&
799 hwc->last_tag == cpuc->tags[i];
802 static void x86_pmu_start(struct perf_event *event, int flags);
803 static void x86_pmu_stop(struct perf_event *event, int flags);
805 static void x86_pmu_enable(struct pmu *pmu)
807 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
808 struct perf_event *event;
809 struct hw_perf_event *hwc;
810 int i, added = cpuc->n_added;
812 if (!x86_pmu_initialized())
819 int n_running = cpuc->n_events - cpuc->n_added;
821 * apply assignment obtained either from
822 * hw_perf_group_sched_in() or x86_pmu_enable()
824 * step1: save events moving to new counters
825 * step2: reprogram moved events into new counters
827 for (i = 0; i < n_running; i++) {
828 event = cpuc->event_list[i];
832 * we can avoid reprogramming counter if:
833 * - assigned same counter as last time
834 * - running on same CPU as last time
835 * - no other event has used the counter since
837 if (hwc->idx == -1 ||
838 match_prev_assignment(hwc, cpuc, i))
842 * Ensure we don't accidentally enable a stopped
843 * counter simply because we rescheduled.
845 if (hwc->state & PERF_HES_STOPPED)
846 hwc->state |= PERF_HES_ARCH;
848 x86_pmu_stop(event, PERF_EF_UPDATE);
851 for (i = 0; i < cpuc->n_events; i++) {
852 event = cpuc->event_list[i];
855 if (!match_prev_assignment(hwc, cpuc, i))
856 x86_assign_hw_event(event, cpuc, i);
857 else if (i < n_running)
860 if (hwc->state & PERF_HES_ARCH)
863 x86_pmu_start(event, PERF_EF_RELOAD);
866 perf_events_lapic_init();
872 x86_pmu.enable_all(added);
875 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
878 wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
881 static inline void x86_pmu_disable_event(struct perf_event *event)
883 struct hw_perf_event *hwc = &event->hw;
885 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
888 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
891 * Set the next IRQ period, based on the hwc->period_left value.
892 * To be called with the event disabled in hw:
895 x86_perf_event_set_period(struct perf_event *event)
897 struct hw_perf_event *hwc = &event->hw;
898 s64 left = local64_read(&hwc->period_left);
899 s64 period = hwc->sample_period;
900 int ret = 0, idx = hwc->idx;
902 if (idx == X86_PMC_IDX_FIXED_BTS)
906 * If we are way outside a reasonable range then just skip forward:
908 if (unlikely(left <= -period)) {
910 local64_set(&hwc->period_left, left);
911 hwc->last_period = period;
915 if (unlikely(left <= 0)) {
917 local64_set(&hwc->period_left, left);
918 hwc->last_period = period;
922 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
924 if (unlikely(left < 2))
927 if (left > x86_pmu.max_period)
928 left = x86_pmu.max_period;
930 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
933 * The hw event starts counting from this event offset,
934 * mark it to be able to extra future deltas:
936 local64_set(&hwc->prev_count, (u64)-left);
938 wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
941 * Due to erratum on certan cpu we need
942 * a second write to be sure the register
943 * is updated properly
945 if (x86_pmu.perfctr_second_write) {
946 wrmsrl(hwc->event_base + idx,
947 (u64)(-left) & x86_pmu.cntval_mask);
950 perf_event_update_userpage(event);
955 static void x86_pmu_enable_event(struct perf_event *event)
957 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
959 __x86_pmu_enable_event(&event->hw,
960 ARCH_PERFMON_EVENTSEL_ENABLE);
964 * Add a single event to the PMU.
966 * The event is added to the group of enabled events
967 * but only if it can be scehduled with existing events.
969 static int x86_pmu_add(struct perf_event *event, int flags)
971 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
972 struct hw_perf_event *hwc;
973 int assign[X86_PMC_IDX_MAX];
978 perf_pmu_disable(event->pmu);
980 ret = n = collect_events(cpuc, event, false);
984 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
985 if (!(flags & PERF_EF_START))
986 hwc->state |= PERF_HES_ARCH;
989 * If group events scheduling transaction was started,
990 * skip the schedulability test here, it will be peformed
991 * at commit time (->commit_txn) as a whole
993 if (cpuc->group_flag & PERF_EVENT_TXN)
996 ret = x86_pmu.schedule_events(cpuc, n, assign);
1000 * copy new assignment, now we know it is possible
1001 * will be used by hw_perf_enable()
1003 memcpy(cpuc->assign, assign, n*sizeof(int));
1007 cpuc->n_added += n - n0;
1008 cpuc->n_txn += n - n0;
1012 perf_pmu_enable(event->pmu);
1016 static void x86_pmu_start(struct perf_event *event, int flags)
1018 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1019 int idx = event->hw.idx;
1021 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1024 if (WARN_ON_ONCE(idx == -1))
1027 if (flags & PERF_EF_RELOAD) {
1028 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1029 x86_perf_event_set_period(event);
1032 event->hw.state = 0;
1034 cpuc->events[idx] = event;
1035 __set_bit(idx, cpuc->active_mask);
1036 __set_bit(idx, cpuc->running);
1037 x86_pmu.enable(event);
1038 perf_event_update_userpage(event);
1041 void perf_event_print_debug(void)
1043 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1045 struct cpu_hw_events *cpuc;
1046 unsigned long flags;
1049 if (!x86_pmu.num_counters)
1052 local_irq_save(flags);
1054 cpu = smp_processor_id();
1055 cpuc = &per_cpu(cpu_hw_events, cpu);
1057 if (x86_pmu.version >= 2) {
1058 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1059 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1060 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1061 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1062 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1065 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1066 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1067 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1068 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1069 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1071 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1073 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1074 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1075 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1077 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1079 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1080 cpu, idx, pmc_ctrl);
1081 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1082 cpu, idx, pmc_count);
1083 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1084 cpu, idx, prev_left);
1086 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1087 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1089 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1090 cpu, idx, pmc_count);
1092 local_irq_restore(flags);
1095 static void x86_pmu_stop(struct perf_event *event, int flags)
1097 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1098 struct hw_perf_event *hwc = &event->hw;
1100 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1101 x86_pmu.disable(event);
1102 cpuc->events[hwc->idx] = NULL;
1103 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1104 hwc->state |= PERF_HES_STOPPED;
1107 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1109 * Drain the remaining delta count out of a event
1110 * that we are disabling:
1112 x86_perf_event_update(event);
1113 hwc->state |= PERF_HES_UPTODATE;
1117 static void x86_pmu_del(struct perf_event *event, int flags)
1119 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1123 * If we're called during a txn, we don't need to do anything.
1124 * The events never got scheduled and ->cancel_txn will truncate
1127 if (cpuc->group_flag & PERF_EVENT_TXN)
1130 x86_pmu_stop(event, PERF_EF_UPDATE);
1132 for (i = 0; i < cpuc->n_events; i++) {
1133 if (event == cpuc->event_list[i]) {
1135 if (x86_pmu.put_event_constraints)
1136 x86_pmu.put_event_constraints(cpuc, event);
1138 while (++i < cpuc->n_events)
1139 cpuc->event_list[i-1] = cpuc->event_list[i];
1145 perf_event_update_userpage(event);
1148 static int x86_pmu_handle_irq(struct pt_regs *regs)
1150 struct perf_sample_data data;
1151 struct cpu_hw_events *cpuc;
1152 struct perf_event *event;
1153 int idx, handled = 0;
1156 perf_sample_data_init(&data, 0);
1158 cpuc = &__get_cpu_var(cpu_hw_events);
1160 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1161 if (!test_bit(idx, cpuc->active_mask)) {
1163 * Though we deactivated the counter some cpus
1164 * might still deliver spurious interrupts still
1165 * in flight. Catch them:
1167 if (__test_and_clear_bit(idx, cpuc->running))
1172 event = cpuc->events[idx];
1174 val = x86_perf_event_update(event);
1175 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1182 data.period = event->hw.last_period;
1184 if (!x86_perf_event_set_period(event))
1187 if (perf_event_overflow(event, 1, &data, regs))
1188 x86_pmu_stop(event, 0);
1192 inc_irq_stat(apic_perf_irqs);
1197 void perf_events_lapic_init(void)
1199 if (!x86_pmu.apic || !x86_pmu_initialized())
1203 * Always use NMI for PMU
1205 apic_write(APIC_LVTPC, APIC_DM_NMI);
1208 struct pmu_nmi_state {
1209 unsigned int marked;
1213 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1215 static int __kprobes
1216 perf_event_nmi_handler(struct notifier_block *self,
1217 unsigned long cmd, void *__args)
1219 struct die_args *args = __args;
1220 unsigned int this_nmi;
1223 if (!atomic_read(&active_events))
1230 case DIE_NMIUNKNOWN:
1231 this_nmi = percpu_read(irq_stat.__nmi_count);
1232 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1233 /* let the kernel handle the unknown nmi */
1236 * This one is a PMU back-to-back nmi. Two events
1237 * trigger 'simultaneously' raising two back-to-back
1238 * NMIs. If the first NMI handles both, the latter
1239 * will be empty and daze the CPU. So, we drop it to
1240 * avoid false-positive 'unknown nmi' messages.
1247 apic_write(APIC_LVTPC, APIC_DM_NMI);
1249 handled = x86_pmu.handle_irq(args->regs);
1253 this_nmi = percpu_read(irq_stat.__nmi_count);
1254 if ((handled > 1) ||
1255 /* the next nmi could be a back-to-back nmi */
1256 ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1257 (__get_cpu_var(pmu_nmi).handled > 1))) {
1259 * We could have two subsequent back-to-back nmis: The
1260 * first handles more than one counter, the 2nd
1261 * handles only one counter and the 3rd handles no
1264 * This is the 2nd nmi because the previous was
1265 * handling more than one counter. We will mark the
1266 * next (3rd) and then drop it if unhandled.
1268 __get_cpu_var(pmu_nmi).marked = this_nmi + 1;
1269 __get_cpu_var(pmu_nmi).handled = handled;
1275 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1276 .notifier_call = perf_event_nmi_handler,
1281 static struct event_constraint unconstrained;
1282 static struct event_constraint emptyconstraint;
1284 static struct event_constraint *
1285 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1287 struct event_constraint *c;
1289 if (x86_pmu.event_constraints) {
1290 for_each_event_constraint(c, x86_pmu.event_constraints) {
1291 if ((event->hw.config & c->cmask) == c->code)
1296 return &unconstrained;
1299 #include "perf_event_amd.c"
1300 #include "perf_event_p6.c"
1301 #include "perf_event_p4.c"
1302 #include "perf_event_intel_lbr.c"
1303 #include "perf_event_intel_ds.c"
1304 #include "perf_event_intel.c"
1306 static int __cpuinit
1307 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1309 unsigned int cpu = (long)hcpu;
1310 int ret = NOTIFY_OK;
1312 switch (action & ~CPU_TASKS_FROZEN) {
1313 case CPU_UP_PREPARE:
1314 if (x86_pmu.cpu_prepare)
1315 ret = x86_pmu.cpu_prepare(cpu);
1319 if (x86_pmu.cpu_starting)
1320 x86_pmu.cpu_starting(cpu);
1324 if (x86_pmu.cpu_dying)
1325 x86_pmu.cpu_dying(cpu);
1328 case CPU_UP_CANCELED:
1330 if (x86_pmu.cpu_dead)
1331 x86_pmu.cpu_dead(cpu);
1341 static void __init pmu_check_apic(void)
1347 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1348 pr_info("no hardware sampling interrupt available.\n");
1351 void __init init_hw_perf_events(void)
1353 struct event_constraint *c;
1356 pr_info("Performance Events: ");
1358 switch (boot_cpu_data.x86_vendor) {
1359 case X86_VENDOR_INTEL:
1360 err = intel_pmu_init();
1362 case X86_VENDOR_AMD:
1363 err = amd_pmu_init();
1369 pr_cont("no PMU driver, software events only.\n");
1375 pr_cont("%s PMU driver.\n", x86_pmu.name);
1380 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1381 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1382 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1383 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1385 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1387 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1388 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1389 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1390 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1393 x86_pmu.intel_ctrl |=
1394 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1396 perf_events_lapic_init();
1397 register_die_notifier(&perf_event_nmi_notifier);
1399 unconstrained = (struct event_constraint)
1400 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1401 0, x86_pmu.num_counters);
1403 if (x86_pmu.event_constraints) {
1404 for_each_event_constraint(c, x86_pmu.event_constraints) {
1405 if (c->cmask != X86_RAW_EVENT_MASK)
1408 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1409 c->weight += x86_pmu.num_counters;
1413 pr_info("... version: %d\n", x86_pmu.version);
1414 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1415 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1416 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1417 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1418 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1419 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1421 perf_pmu_register(&pmu);
1422 perf_cpu_notifier(x86_pmu_notifier);
1425 static inline void x86_pmu_read(struct perf_event *event)
1427 x86_perf_event_update(event);
1431 * Start group events scheduling transaction
1432 * Set the flag to make pmu::enable() not perform the
1433 * schedulability test, it will be performed at commit time
1435 static void x86_pmu_start_txn(struct pmu *pmu)
1437 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1439 perf_pmu_disable(pmu);
1440 cpuc->group_flag |= PERF_EVENT_TXN;
1445 * Stop group events scheduling transaction
1446 * Clear the flag and pmu::enable() will perform the
1447 * schedulability test.
1449 static void x86_pmu_cancel_txn(struct pmu *pmu)
1451 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1453 cpuc->group_flag &= ~PERF_EVENT_TXN;
1455 * Truncate the collected events.
1457 cpuc->n_added -= cpuc->n_txn;
1458 cpuc->n_events -= cpuc->n_txn;
1459 perf_pmu_enable(pmu);
1463 * Commit group events scheduling transaction
1464 * Perform the group schedulability test as a whole
1465 * Return 0 if success
1467 static int x86_pmu_commit_txn(struct pmu *pmu)
1469 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1470 int assign[X86_PMC_IDX_MAX];
1475 if (!x86_pmu_initialized())
1478 ret = x86_pmu.schedule_events(cpuc, n, assign);
1483 * copy new assignment, now we know it is possible
1484 * will be used by hw_perf_enable()
1486 memcpy(cpuc->assign, assign, n*sizeof(int));
1488 cpuc->group_flag &= ~PERF_EVENT_TXN;
1489 perf_pmu_enable(pmu);
1494 * validate that we can schedule this event
1496 static int validate_event(struct perf_event *event)
1498 struct cpu_hw_events *fake_cpuc;
1499 struct event_constraint *c;
1502 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1506 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1508 if (!c || !c->weight)
1511 if (x86_pmu.put_event_constraints)
1512 x86_pmu.put_event_constraints(fake_cpuc, event);
1520 * validate a single event group
1522 * validation include:
1523 * - check events are compatible which each other
1524 * - events do not compete for the same counter
1525 * - number of events <= number of counters
1527 * validation ensures the group can be loaded onto the
1528 * PMU if it was the only group available.
1530 static int validate_group(struct perf_event *event)
1532 struct perf_event *leader = event->group_leader;
1533 struct cpu_hw_events *fake_cpuc;
1537 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1542 * the event is not yet connected with its
1543 * siblings therefore we must first collect
1544 * existing siblings, then add the new event
1545 * before we can simulate the scheduling
1548 n = collect_events(fake_cpuc, leader, true);
1552 fake_cpuc->n_events = n;
1553 n = collect_events(fake_cpuc, event, false);
1557 fake_cpuc->n_events = n;
1559 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1567 int x86_pmu_event_init(struct perf_event *event)
1572 switch (event->attr.type) {
1574 case PERF_TYPE_HARDWARE:
1575 case PERF_TYPE_HW_CACHE:
1582 err = __x86_pmu_event_init(event);
1585 * we temporarily connect event to its pmu
1586 * such that validate_group() can classify
1587 * it as an x86 event using is_x86_event()
1592 if (event->group_leader != event)
1593 err = validate_group(event);
1595 err = validate_event(event);
1601 event->destroy(event);
1607 static struct pmu pmu = {
1608 .pmu_enable = x86_pmu_enable,
1609 .pmu_disable = x86_pmu_disable,
1611 .event_init = x86_pmu_event_init,
1615 .start = x86_pmu_start,
1616 .stop = x86_pmu_stop,
1617 .read = x86_pmu_read,
1619 .start_txn = x86_pmu_start_txn,
1620 .cancel_txn = x86_pmu_cancel_txn,
1621 .commit_txn = x86_pmu_commit_txn,
1629 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1631 /* Ignore warnings */
1634 static void backtrace_warning(void *data, char *msg)
1636 /* Ignore warnings */
1639 static int backtrace_stack(void *data, char *name)
1644 static void backtrace_address(void *data, unsigned long addr, int reliable)
1646 struct perf_callchain_entry *entry = data;
1648 perf_callchain_store(entry, addr);
1651 static const struct stacktrace_ops backtrace_ops = {
1652 .warning = backtrace_warning,
1653 .warning_symbol = backtrace_warning_symbol,
1654 .stack = backtrace_stack,
1655 .address = backtrace_address,
1656 .walk_stack = print_context_stack_bp,
1660 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1662 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1663 /* TODO: We don't support guest os callchain now */
1667 perf_callchain_store(entry, regs->ip);
1669 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1672 #ifdef CONFIG_COMPAT
1674 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1676 /* 32-bit process in 64-bit kernel. */
1677 struct stack_frame_ia32 frame;
1678 const void __user *fp;
1680 if (!test_thread_flag(TIF_IA32))
1683 fp = compat_ptr(regs->bp);
1684 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1685 unsigned long bytes;
1686 frame.next_frame = 0;
1687 frame.return_address = 0;
1689 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1690 if (bytes != sizeof(frame))
1693 if (fp < compat_ptr(regs->sp))
1696 perf_callchain_store(entry, frame.return_address);
1697 fp = compat_ptr(frame.next_frame);
1703 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1710 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1712 struct stack_frame frame;
1713 const void __user *fp;
1715 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1716 /* TODO: We don't support guest os callchain now */
1720 fp = (void __user *)regs->bp;
1722 perf_callchain_store(entry, regs->ip);
1724 if (perf_callchain_user32(regs, entry))
1727 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1728 unsigned long bytes;
1729 frame.next_frame = NULL;
1730 frame.return_address = 0;
1732 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1733 if (bytes != sizeof(frame))
1736 if ((unsigned long)fp < regs->sp)
1739 perf_callchain_store(entry, frame.return_address);
1740 fp = frame.next_frame;
1744 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1748 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1749 ip = perf_guest_cbs->get_guest_ip();
1751 ip = instruction_pointer(regs);
1756 unsigned long perf_misc_flags(struct pt_regs *regs)
1760 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1761 if (perf_guest_cbs->is_user_mode())
1762 misc |= PERF_RECORD_MISC_GUEST_USER;
1764 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1766 if (user_mode(regs))
1767 misc |= PERF_RECORD_MISC_USER;
1769 misc |= PERF_RECORD_MISC_KERNEL;
1772 if (regs->flags & PERF_EFLAGS_EXACT)
1773 misc |= PERF_RECORD_MISC_EXACT_IP;