2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
11 * For licencing details see kernel-base/COPYING
14 #include <linux/perf_event.h>
15 #include <linux/capability.h>
16 #include <linux/notifier.h>
17 #include <linux/hardirq.h>
18 #include <linux/kprobes.h>
19 #include <linux/module.h>
20 #include <linux/kdebug.h>
21 #include <linux/sched.h>
22 #include <linux/uaccess.h>
23 #include <linux/highmem.h>
24 #include <linux/cpu.h>
27 #include <asm/stacktrace.h>
30 static u64 perf_event_mask __read_mostly;
32 /* The maximal number of PEBS events: */
33 #define MAX_PEBS_EVENTS 4
35 /* The size of a BTS record in bytes: */
36 #define BTS_RECORD_SIZE 24
38 /* The size of a per-cpu BTS buffer in bytes: */
39 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048)
41 /* The BTS overflow threshold in bytes from the end of the buffer: */
42 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128)
46 * Bits in the debugctlmsr controlling branch tracing.
48 #define X86_DEBUGCTL_TR (1 << 6)
49 #define X86_DEBUGCTL_BTS (1 << 7)
50 #define X86_DEBUGCTL_BTINT (1 << 8)
51 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
52 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
55 * A debug store configuration.
57 * We only support architectures that use 64bit fields.
62 u64 bts_absolute_maximum;
63 u64 bts_interrupt_threshold;
66 u64 pebs_absolute_maximum;
67 u64 pebs_interrupt_threshold;
68 u64 pebs_event_reset[MAX_PEBS_EVENTS];
71 struct cpu_hw_events {
72 struct perf_event *events[X86_PMC_IDX_MAX];
73 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
74 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
75 unsigned long interrupts;
77 struct debug_store *ds;
81 * struct x86_pmu - generic x86 pmu
86 int (*handle_irq)(struct pt_regs *);
87 void (*disable_all)(void);
88 void (*enable_all)(void);
89 void (*enable)(struct hw_perf_event *, int);
90 void (*disable)(struct hw_perf_event *, int);
93 u64 (*event_map)(int);
94 u64 (*raw_event)(u64);
103 void (*enable_bts)(u64 config);
104 void (*disable_bts)(void);
107 static struct x86_pmu x86_pmu __read_mostly;
109 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
114 * Not sure about some of these
116 static const u64 p6_perfmon_event_map[] =
118 [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
119 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
120 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
121 [PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
122 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
123 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
124 [PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
127 static u64 p6_pmu_event_map(int hw_event)
129 return p6_perfmon_event_map[hw_event];
133 * Event setting that is specified not to count anything.
134 * We use this to effectively disable a counter.
136 * L2_RQSTS with 0 MESI unit mask.
138 #define P6_NOP_EVENT 0x0000002EULL
140 static u64 p6_pmu_raw_event(u64 hw_event)
142 #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
143 #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
144 #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
145 #define P6_EVNTSEL_INV_MASK 0x00800000ULL
146 #define P6_EVNTSEL_REG_MASK 0xFF000000ULL
148 #define P6_EVNTSEL_MASK \
149 (P6_EVNTSEL_EVENT_MASK | \
150 P6_EVNTSEL_UNIT_MASK | \
151 P6_EVNTSEL_EDGE_MASK | \
152 P6_EVNTSEL_INV_MASK | \
155 return hw_event & P6_EVNTSEL_MASK;
160 * Intel PerfMon v3. Used on Core2 and later.
162 static const u64 intel_perfmon_event_map[] =
164 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
165 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
166 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
167 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
168 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
169 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
170 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
173 static u64 intel_pmu_event_map(int hw_event)
175 return intel_perfmon_event_map[hw_event];
179 * Generalized hw caching related hw_event table, filled
180 * in on a per model basis. A value of 0 means
181 * 'not supported', -1 means 'hw_event makes no sense on
182 * this CPU', any other value means the raw hw_event
186 #define C(x) PERF_COUNT_HW_CACHE_##x
188 static u64 __read_mostly hw_cache_event_ids
189 [PERF_COUNT_HW_CACHE_MAX]
190 [PERF_COUNT_HW_CACHE_OP_MAX]
191 [PERF_COUNT_HW_CACHE_RESULT_MAX];
193 static const u64 nehalem_hw_cache_event_ids
194 [PERF_COUNT_HW_CACHE_MAX]
195 [PERF_COUNT_HW_CACHE_OP_MAX]
196 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
200 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
201 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
204 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
205 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
207 [ C(OP_PREFETCH) ] = {
208 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
209 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
214 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
215 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
218 [ C(RESULT_ACCESS) ] = -1,
219 [ C(RESULT_MISS) ] = -1,
221 [ C(OP_PREFETCH) ] = {
222 [ C(RESULT_ACCESS) ] = 0x0,
223 [ C(RESULT_MISS) ] = 0x0,
228 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
229 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
232 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
233 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
235 [ C(OP_PREFETCH) ] = {
236 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
237 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
242 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
243 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
246 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
247 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
249 [ C(OP_PREFETCH) ] = {
250 [ C(RESULT_ACCESS) ] = 0x0,
251 [ C(RESULT_MISS) ] = 0x0,
256 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
257 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
260 [ C(RESULT_ACCESS) ] = -1,
261 [ C(RESULT_MISS) ] = -1,
263 [ C(OP_PREFETCH) ] = {
264 [ C(RESULT_ACCESS) ] = -1,
265 [ C(RESULT_MISS) ] = -1,
270 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
271 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
274 [ C(RESULT_ACCESS) ] = -1,
275 [ C(RESULT_MISS) ] = -1,
277 [ C(OP_PREFETCH) ] = {
278 [ C(RESULT_ACCESS) ] = -1,
279 [ C(RESULT_MISS) ] = -1,
284 static const u64 core2_hw_cache_event_ids
285 [PERF_COUNT_HW_CACHE_MAX]
286 [PERF_COUNT_HW_CACHE_OP_MAX]
287 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
291 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
292 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
295 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
296 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
298 [ C(OP_PREFETCH) ] = {
299 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
300 [ C(RESULT_MISS) ] = 0,
305 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
306 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
309 [ C(RESULT_ACCESS) ] = -1,
310 [ C(RESULT_MISS) ] = -1,
312 [ C(OP_PREFETCH) ] = {
313 [ C(RESULT_ACCESS) ] = 0,
314 [ C(RESULT_MISS) ] = 0,
319 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
320 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
323 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
324 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
326 [ C(OP_PREFETCH) ] = {
327 [ C(RESULT_ACCESS) ] = 0,
328 [ C(RESULT_MISS) ] = 0,
333 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
334 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
337 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
338 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
340 [ C(OP_PREFETCH) ] = {
341 [ C(RESULT_ACCESS) ] = 0,
342 [ C(RESULT_MISS) ] = 0,
347 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
348 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
351 [ C(RESULT_ACCESS) ] = -1,
352 [ C(RESULT_MISS) ] = -1,
354 [ C(OP_PREFETCH) ] = {
355 [ C(RESULT_ACCESS) ] = -1,
356 [ C(RESULT_MISS) ] = -1,
361 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
362 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
365 [ C(RESULT_ACCESS) ] = -1,
366 [ C(RESULT_MISS) ] = -1,
368 [ C(OP_PREFETCH) ] = {
369 [ C(RESULT_ACCESS) ] = -1,
370 [ C(RESULT_MISS) ] = -1,
375 static const u64 atom_hw_cache_event_ids
376 [PERF_COUNT_HW_CACHE_MAX]
377 [PERF_COUNT_HW_CACHE_OP_MAX]
378 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
382 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
383 [ C(RESULT_MISS) ] = 0,
386 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
387 [ C(RESULT_MISS) ] = 0,
389 [ C(OP_PREFETCH) ] = {
390 [ C(RESULT_ACCESS) ] = 0x0,
391 [ C(RESULT_MISS) ] = 0,
396 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
397 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
400 [ C(RESULT_ACCESS) ] = -1,
401 [ C(RESULT_MISS) ] = -1,
403 [ C(OP_PREFETCH) ] = {
404 [ C(RESULT_ACCESS) ] = 0,
405 [ C(RESULT_MISS) ] = 0,
410 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
411 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
414 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
415 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
417 [ C(OP_PREFETCH) ] = {
418 [ C(RESULT_ACCESS) ] = 0,
419 [ C(RESULT_MISS) ] = 0,
424 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
425 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
428 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
429 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
431 [ C(OP_PREFETCH) ] = {
432 [ C(RESULT_ACCESS) ] = 0,
433 [ C(RESULT_MISS) ] = 0,
438 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
439 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
442 [ C(RESULT_ACCESS) ] = -1,
443 [ C(RESULT_MISS) ] = -1,
445 [ C(OP_PREFETCH) ] = {
446 [ C(RESULT_ACCESS) ] = -1,
447 [ C(RESULT_MISS) ] = -1,
452 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
453 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
456 [ C(RESULT_ACCESS) ] = -1,
457 [ C(RESULT_MISS) ] = -1,
459 [ C(OP_PREFETCH) ] = {
460 [ C(RESULT_ACCESS) ] = -1,
461 [ C(RESULT_MISS) ] = -1,
466 static u64 intel_pmu_raw_event(u64 hw_event)
468 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
469 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
470 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
471 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
472 #define CORE_EVNTSEL_REG_MASK 0xFF000000ULL
474 #define CORE_EVNTSEL_MASK \
475 (CORE_EVNTSEL_EVENT_MASK | \
476 CORE_EVNTSEL_UNIT_MASK | \
477 CORE_EVNTSEL_EDGE_MASK | \
478 CORE_EVNTSEL_INV_MASK | \
479 CORE_EVNTSEL_REG_MASK)
481 return hw_event & CORE_EVNTSEL_MASK;
484 static const u64 amd_hw_cache_event_ids
485 [PERF_COUNT_HW_CACHE_MAX]
486 [PERF_COUNT_HW_CACHE_OP_MAX]
487 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
491 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
492 [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
495 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
496 [ C(RESULT_MISS) ] = 0,
498 [ C(OP_PREFETCH) ] = {
499 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
500 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
505 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
506 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
509 [ C(RESULT_ACCESS) ] = -1,
510 [ C(RESULT_MISS) ] = -1,
512 [ C(OP_PREFETCH) ] = {
513 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
514 [ C(RESULT_MISS) ] = 0,
519 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
520 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
523 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
524 [ C(RESULT_MISS) ] = 0,
526 [ C(OP_PREFETCH) ] = {
527 [ C(RESULT_ACCESS) ] = 0,
528 [ C(RESULT_MISS) ] = 0,
533 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
534 [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
537 [ C(RESULT_ACCESS) ] = 0,
538 [ C(RESULT_MISS) ] = 0,
540 [ C(OP_PREFETCH) ] = {
541 [ C(RESULT_ACCESS) ] = 0,
542 [ C(RESULT_MISS) ] = 0,
547 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
548 [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
551 [ C(RESULT_ACCESS) ] = -1,
552 [ C(RESULT_MISS) ] = -1,
554 [ C(OP_PREFETCH) ] = {
555 [ C(RESULT_ACCESS) ] = -1,
556 [ C(RESULT_MISS) ] = -1,
561 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
562 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
565 [ C(RESULT_ACCESS) ] = -1,
566 [ C(RESULT_MISS) ] = -1,
568 [ C(OP_PREFETCH) ] = {
569 [ C(RESULT_ACCESS) ] = -1,
570 [ C(RESULT_MISS) ] = -1,
576 * AMD Performance Monitor K7 and later.
578 static const u64 amd_perfmon_event_map[] =
580 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
581 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
582 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
583 [PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
584 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
585 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
588 static u64 amd_pmu_event_map(int hw_event)
590 return amd_perfmon_event_map[hw_event];
593 static u64 amd_pmu_raw_event(u64 hw_event)
595 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
596 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
597 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
598 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
599 #define K7_EVNTSEL_REG_MASK 0x0FF000000ULL
601 #define K7_EVNTSEL_MASK \
602 (K7_EVNTSEL_EVENT_MASK | \
603 K7_EVNTSEL_UNIT_MASK | \
604 K7_EVNTSEL_EDGE_MASK | \
605 K7_EVNTSEL_INV_MASK | \
608 return hw_event & K7_EVNTSEL_MASK;
612 * Propagate event elapsed time into the generic event.
613 * Can only be executed on the CPU where the event is active.
614 * Returns the delta events processed.
617 x86_perf_event_update(struct perf_event *event,
618 struct hw_perf_event *hwc, int idx)
620 int shift = 64 - x86_pmu.event_bits;
621 u64 prev_raw_count, new_raw_count;
624 if (idx == X86_PMC_IDX_FIXED_BTS)
628 * Careful: an NMI might modify the previous event value.
630 * Our tactic to handle this is to first atomically read and
631 * exchange a new raw count - then add that new-prev delta
632 * count to the generic event atomically:
635 prev_raw_count = atomic64_read(&hwc->prev_count);
636 rdmsrl(hwc->event_base + idx, new_raw_count);
638 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
639 new_raw_count) != prev_raw_count)
643 * Now we have the new raw value and have updated the prev
644 * timestamp already. We can now calculate the elapsed delta
645 * (event-)time and add that to the generic event.
647 * Careful, not all hw sign-extends above the physical width
650 delta = (new_raw_count << shift) - (prev_raw_count << shift);
653 atomic64_add(delta, &event->count);
654 atomic64_sub(delta, &hwc->period_left);
656 return new_raw_count;
659 static atomic_t active_events;
660 static DEFINE_MUTEX(pmc_reserve_mutex);
662 static bool reserve_pmc_hardware(void)
664 #ifdef CONFIG_X86_LOCAL_APIC
667 if (nmi_watchdog == NMI_LOCAL_APIC)
668 disable_lapic_nmi_watchdog();
670 for (i = 0; i < x86_pmu.num_events; i++) {
671 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
675 for (i = 0; i < x86_pmu.num_events; i++) {
676 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
683 #ifdef CONFIG_X86_LOCAL_APIC
685 for (i--; i >= 0; i--)
686 release_evntsel_nmi(x86_pmu.eventsel + i);
688 i = x86_pmu.num_events;
691 for (i--; i >= 0; i--)
692 release_perfctr_nmi(x86_pmu.perfctr + i);
694 if (nmi_watchdog == NMI_LOCAL_APIC)
695 enable_lapic_nmi_watchdog();
701 static void release_pmc_hardware(void)
703 #ifdef CONFIG_X86_LOCAL_APIC
706 for (i = 0; i < x86_pmu.num_events; i++) {
707 release_perfctr_nmi(x86_pmu.perfctr + i);
708 release_evntsel_nmi(x86_pmu.eventsel + i);
711 if (nmi_watchdog == NMI_LOCAL_APIC)
712 enable_lapic_nmi_watchdog();
716 static inline bool bts_available(void)
718 return x86_pmu.enable_bts != NULL;
721 static inline void init_debug_store_on_cpu(int cpu)
723 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
728 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
729 (u32)((u64)(unsigned long)ds),
730 (u32)((u64)(unsigned long)ds >> 32));
733 static inline void fini_debug_store_on_cpu(int cpu)
735 if (!per_cpu(cpu_hw_events, cpu).ds)
738 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
741 static void release_bts_hardware(void)
745 if (!bts_available())
750 for_each_online_cpu(cpu)
751 fini_debug_store_on_cpu(cpu);
753 for_each_possible_cpu(cpu) {
754 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
759 per_cpu(cpu_hw_events, cpu).ds = NULL;
761 kfree((void *)(unsigned long)ds->bts_buffer_base);
768 static int reserve_bts_hardware(void)
772 if (!bts_available())
777 for_each_possible_cpu(cpu) {
778 struct debug_store *ds;
782 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
783 if (unlikely(!buffer))
786 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
792 ds->bts_buffer_base = (u64)(unsigned long)buffer;
793 ds->bts_index = ds->bts_buffer_base;
794 ds->bts_absolute_maximum =
795 ds->bts_buffer_base + BTS_BUFFER_SIZE;
796 ds->bts_interrupt_threshold =
797 ds->bts_absolute_maximum - BTS_OVFL_TH;
799 per_cpu(cpu_hw_events, cpu).ds = ds;
804 release_bts_hardware();
806 for_each_online_cpu(cpu)
807 init_debug_store_on_cpu(cpu);
815 static void hw_perf_event_destroy(struct perf_event *event)
817 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
818 release_pmc_hardware();
819 release_bts_hardware();
820 mutex_unlock(&pmc_reserve_mutex);
824 static inline int x86_pmu_initialized(void)
826 return x86_pmu.handle_irq != NULL;
830 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
832 unsigned int cache_type, cache_op, cache_result;
835 config = attr->config;
837 cache_type = (config >> 0) & 0xff;
838 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
841 cache_op = (config >> 8) & 0xff;
842 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
845 cache_result = (config >> 16) & 0xff;
846 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
849 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
862 static void intel_pmu_enable_bts(u64 config)
864 unsigned long debugctlmsr;
866 debugctlmsr = get_debugctlmsr();
868 debugctlmsr |= X86_DEBUGCTL_TR;
869 debugctlmsr |= X86_DEBUGCTL_BTS;
870 debugctlmsr |= X86_DEBUGCTL_BTINT;
872 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
873 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
875 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
876 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
878 update_debugctlmsr(debugctlmsr);
881 static void intel_pmu_disable_bts(void)
883 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
884 unsigned long debugctlmsr;
889 debugctlmsr = get_debugctlmsr();
892 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
893 X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
895 update_debugctlmsr(debugctlmsr);
899 * Setup the hardware configuration for a given attr_type
901 static int __hw_perf_event_init(struct perf_event *event)
903 struct perf_event_attr *attr = &event->attr;
904 struct hw_perf_event *hwc = &event->hw;
908 if (!x86_pmu_initialized())
912 if (!atomic_inc_not_zero(&active_events)) {
913 mutex_lock(&pmc_reserve_mutex);
914 if (atomic_read(&active_events) == 0) {
915 if (!reserve_pmc_hardware())
918 err = reserve_bts_hardware();
921 atomic_inc(&active_events);
922 mutex_unlock(&pmc_reserve_mutex);
927 event->destroy = hw_perf_event_destroy;
931 * (keep 'enabled' bit clear for now)
933 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
936 * Count user and OS events unless requested not to.
938 if (!attr->exclude_user)
939 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
940 if (!attr->exclude_kernel)
941 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
943 if (!hwc->sample_period) {
944 hwc->sample_period = x86_pmu.max_period;
945 hwc->last_period = hwc->sample_period;
946 atomic64_set(&hwc->period_left, hwc->sample_period);
949 * If we have a PMU initialized but no APIC
950 * interrupts, we cannot sample hardware
951 * events (user-space has to fall back and
952 * sample via a hrtimer based software event):
959 * Raw hw_event type provide the config in the hw_event structure
961 if (attr->type == PERF_TYPE_RAW) {
962 hwc->config |= x86_pmu.raw_event(attr->config);
966 if (attr->type == PERF_TYPE_HW_CACHE)
967 return set_ext_hw_attr(hwc, attr);
969 if (attr->config >= x86_pmu.max_events)
975 config = x86_pmu.event_map(attr->config);
986 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
987 (hwc->sample_period == 1)) {
988 /* BTS is not supported by this architecture. */
989 if (!bts_available())
992 /* BTS is currently only allowed for user-mode. */
993 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
997 hwc->config |= config;
1002 static void p6_pmu_disable_all(void)
1004 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1013 /* p6 only has one enable register */
1014 rdmsrl(MSR_P6_EVNTSEL0, val);
1015 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1016 wrmsrl(MSR_P6_EVNTSEL0, val);
1019 static void intel_pmu_disable_all(void)
1021 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1029 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1031 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1032 intel_pmu_disable_bts();
1035 static void amd_pmu_disable_all(void)
1037 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1045 * ensure we write the disable before we start disabling the
1046 * events proper, so that amd_pmu_enable_event() does the
1051 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1054 if (!test_bit(idx, cpuc->active_mask))
1056 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
1057 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
1059 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1060 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1064 void hw_perf_disable(void)
1066 if (!x86_pmu_initialized())
1068 return x86_pmu.disable_all();
1071 static void p6_pmu_enable_all(void)
1073 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1082 /* p6 only has one enable register */
1083 rdmsrl(MSR_P6_EVNTSEL0, val);
1084 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1085 wrmsrl(MSR_P6_EVNTSEL0, val);
1088 static void intel_pmu_enable_all(void)
1090 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1098 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1100 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1101 struct perf_event *event =
1102 cpuc->events[X86_PMC_IDX_FIXED_BTS];
1104 if (WARN_ON_ONCE(!event))
1107 intel_pmu_enable_bts(event->hw.config);
1111 static void amd_pmu_enable_all(void)
1113 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1122 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1123 struct perf_event *event = cpuc->events[idx];
1126 if (!test_bit(idx, cpuc->active_mask))
1129 val = event->hw.config;
1130 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1131 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1135 void hw_perf_enable(void)
1137 if (!x86_pmu_initialized())
1139 x86_pmu.enable_all();
1142 static inline u64 intel_pmu_get_status(void)
1146 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1151 static inline void intel_pmu_ack_status(u64 ack)
1153 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1156 static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1158 (void)checking_wrmsrl(hwc->config_base + idx,
1159 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
1162 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1164 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
1168 intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
1170 int idx = __idx - X86_PMC_IDX_FIXED;
1173 mask = 0xfULL << (idx * 4);
1175 rdmsrl(hwc->config_base, ctrl_val);
1177 (void)checking_wrmsrl(hwc->config_base, ctrl_val);
1181 p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1183 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1184 u64 val = P6_NOP_EVENT;
1187 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1189 (void)checking_wrmsrl(hwc->config_base + idx, val);
1193 intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1195 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1196 intel_pmu_disable_bts();
1200 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1201 intel_pmu_disable_fixed(hwc, idx);
1205 x86_pmu_disable_event(hwc, idx);
1209 amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1211 x86_pmu_disable_event(hwc, idx);
1214 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1217 * Set the next IRQ period, based on the hwc->period_left value.
1218 * To be called with the event disabled in hw:
1221 x86_perf_event_set_period(struct perf_event *event,
1222 struct hw_perf_event *hwc, int idx)
1224 s64 left = atomic64_read(&hwc->period_left);
1225 s64 period = hwc->sample_period;
1228 if (idx == X86_PMC_IDX_FIXED_BTS)
1232 * If we are way outside a reasoable range then just skip forward:
1234 if (unlikely(left <= -period)) {
1236 atomic64_set(&hwc->period_left, left);
1237 hwc->last_period = period;
1241 if (unlikely(left <= 0)) {
1243 atomic64_set(&hwc->period_left, left);
1244 hwc->last_period = period;
1248 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1250 if (unlikely(left < 2))
1253 if (left > x86_pmu.max_period)
1254 left = x86_pmu.max_period;
1256 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1259 * The hw event starts counting from this event offset,
1260 * mark it to be able to extra future deltas:
1262 atomic64_set(&hwc->prev_count, (u64)-left);
1264 err = checking_wrmsrl(hwc->event_base + idx,
1265 (u64)(-left) & x86_pmu.event_mask);
1267 perf_event_update_userpage(event);
1273 intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
1275 int idx = __idx - X86_PMC_IDX_FIXED;
1276 u64 ctrl_val, bits, mask;
1280 * Enable IRQ generation (0x8),
1281 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1285 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1287 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1290 mask = 0xfULL << (idx * 4);
1292 rdmsrl(hwc->config_base, ctrl_val);
1295 err = checking_wrmsrl(hwc->config_base, ctrl_val);
1298 static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1300 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1305 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1307 (void)checking_wrmsrl(hwc->config_base + idx, val);
1311 static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1313 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1314 if (!__get_cpu_var(cpu_hw_events).enabled)
1317 intel_pmu_enable_bts(hwc->config);
1321 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1322 intel_pmu_enable_fixed(hwc, idx);
1326 x86_pmu_enable_event(hwc, idx);
1329 static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1331 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1334 x86_pmu_enable_event(hwc, idx);
1338 fixed_mode_idx(struct perf_event *event, struct hw_perf_event *hwc)
1340 unsigned int hw_event;
1342 hw_event = hwc->config & ARCH_PERFMON_EVENT_MASK;
1344 if (unlikely((hw_event ==
1345 x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
1346 (hwc->sample_period == 1)))
1347 return X86_PMC_IDX_FIXED_BTS;
1349 if (!x86_pmu.num_events_fixed)
1352 if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
1353 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
1354 if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
1355 return X86_PMC_IDX_FIXED_CPU_CYCLES;
1356 if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES)))
1357 return X86_PMC_IDX_FIXED_BUS_CYCLES;
1363 * Find a PMC slot for the freshly enabled / scheduled in event:
1365 static int x86_pmu_enable(struct perf_event *event)
1367 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1368 struct hw_perf_event *hwc = &event->hw;
1371 idx = fixed_mode_idx(event, hwc);
1372 if (idx == X86_PMC_IDX_FIXED_BTS) {
1373 /* BTS is already occupied. */
1374 if (test_and_set_bit(idx, cpuc->used_mask))
1377 hwc->config_base = 0;
1378 hwc->event_base = 0;
1380 } else if (idx >= 0) {
1382 * Try to get the fixed event, if that is already taken
1383 * then try to get a generic event:
1385 if (test_and_set_bit(idx, cpuc->used_mask))
1388 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1390 * We set it so that event_base + idx in wrmsr/rdmsr maps to
1391 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1394 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1398 /* Try to get the previous generic event again */
1399 if (test_and_set_bit(idx, cpuc->used_mask)) {
1401 idx = find_first_zero_bit(cpuc->used_mask,
1402 x86_pmu.num_events);
1403 if (idx == x86_pmu.num_events)
1406 set_bit(idx, cpuc->used_mask);
1409 hwc->config_base = x86_pmu.eventsel;
1410 hwc->event_base = x86_pmu.perfctr;
1413 perf_events_lapic_init();
1415 x86_pmu.disable(hwc, idx);
1417 cpuc->events[idx] = event;
1418 set_bit(idx, cpuc->active_mask);
1420 x86_perf_event_set_period(event, hwc, idx);
1421 x86_pmu.enable(hwc, idx);
1423 perf_event_update_userpage(event);
1428 static void x86_pmu_unthrottle(struct perf_event *event)
1430 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1431 struct hw_perf_event *hwc = &event->hw;
1433 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1434 cpuc->events[hwc->idx] != event))
1437 x86_pmu.enable(hwc, hwc->idx);
1440 void perf_event_print_debug(void)
1442 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1443 struct cpu_hw_events *cpuc;
1444 unsigned long flags;
1447 if (!x86_pmu.num_events)
1450 local_irq_save(flags);
1452 cpu = smp_processor_id();
1453 cpuc = &per_cpu(cpu_hw_events, cpu);
1455 if (x86_pmu.version >= 2) {
1456 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1457 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1458 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1459 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1462 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1463 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1464 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1465 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1467 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
1469 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1470 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1471 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1473 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1475 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1476 cpu, idx, pmc_ctrl);
1477 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1478 cpu, idx, pmc_count);
1479 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1480 cpu, idx, prev_left);
1482 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1483 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1485 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1486 cpu, idx, pmc_count);
1488 local_irq_restore(flags);
1491 static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
1493 struct debug_store *ds = cpuc->ds;
1499 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
1500 struct bts_record *at, *top;
1501 struct perf_output_handle handle;
1502 struct perf_event_header header;
1503 struct perf_sample_data data;
1504 struct pt_regs regs;
1512 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
1513 top = (struct bts_record *)(unsigned long)ds->bts_index;
1518 ds->bts_index = ds->bts_buffer_base;
1521 data.period = event->hw.last_period;
1526 * Prepare a generic sample, i.e. fill in the invariant fields.
1527 * We will overwrite the from and to address before we output
1530 perf_prepare_sample(&header, &data, event, ®s);
1532 if (perf_output_begin(&handle, event,
1533 header.size * (top - at), 1, 1))
1536 for (; at < top; at++) {
1540 perf_output_sample(&handle, &header, &data, event);
1543 perf_output_end(&handle);
1545 /* There's new data available. */
1546 event->hw.interrupts++;
1547 event->pending_kill = POLL_IN;
1550 static void x86_pmu_disable(struct perf_event *event)
1552 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1553 struct hw_perf_event *hwc = &event->hw;
1557 * Must be done before we disable, otherwise the nmi handler
1558 * could reenable again:
1560 clear_bit(idx, cpuc->active_mask);
1561 x86_pmu.disable(hwc, idx);
1564 * Make sure the cleared pointer becomes visible before we
1565 * (potentially) free the event:
1570 * Drain the remaining delta count out of a event
1571 * that we are disabling:
1573 x86_perf_event_update(event, hwc, idx);
1575 /* Drain the remaining BTS records. */
1576 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS))
1577 intel_pmu_drain_bts_buffer(cpuc);
1579 cpuc->events[idx] = NULL;
1580 clear_bit(idx, cpuc->used_mask);
1582 perf_event_update_userpage(event);
1586 * Save and restart an expired event. Called by NMI contexts,
1587 * so it has to be careful about preempting normal event ops:
1589 static int intel_pmu_save_and_restart(struct perf_event *event)
1591 struct hw_perf_event *hwc = &event->hw;
1595 x86_perf_event_update(event, hwc, idx);
1596 ret = x86_perf_event_set_period(event, hwc, idx);
1598 if (event->state == PERF_EVENT_STATE_ACTIVE)
1599 intel_pmu_enable_event(hwc, idx);
1604 static void intel_pmu_reset(void)
1606 struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
1607 unsigned long flags;
1610 if (!x86_pmu.num_events)
1613 local_irq_save(flags);
1615 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1617 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1618 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1619 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
1621 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1622 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1625 ds->bts_index = ds->bts_buffer_base;
1627 local_irq_restore(flags);
1630 static int p6_pmu_handle_irq(struct pt_regs *regs)
1632 struct perf_sample_data data;
1633 struct cpu_hw_events *cpuc;
1634 struct perf_event *event;
1635 struct hw_perf_event *hwc;
1636 int idx, handled = 0;
1641 cpuc = &__get_cpu_var(cpu_hw_events);
1643 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1644 if (!test_bit(idx, cpuc->active_mask))
1647 event = cpuc->events[idx];
1650 val = x86_perf_event_update(event, hwc, idx);
1651 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1658 data.period = event->hw.last_period;
1660 if (!x86_perf_event_set_period(event, hwc, idx))
1663 if (perf_event_overflow(event, 1, &data, regs))
1664 p6_pmu_disable_event(hwc, idx);
1668 inc_irq_stat(apic_perf_irqs);
1674 * This handler is triggered by the local APIC, so the APIC IRQ handling
1677 static int intel_pmu_handle_irq(struct pt_regs *regs)
1679 struct perf_sample_data data;
1680 struct cpu_hw_events *cpuc;
1686 cpuc = &__get_cpu_var(cpu_hw_events);
1689 intel_pmu_drain_bts_buffer(cpuc);
1690 status = intel_pmu_get_status();
1698 if (++loops > 100) {
1699 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1700 perf_event_print_debug();
1706 inc_irq_stat(apic_perf_irqs);
1708 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1709 struct perf_event *event = cpuc->events[bit];
1711 clear_bit(bit, (unsigned long *) &status);
1712 if (!test_bit(bit, cpuc->active_mask))
1715 if (!intel_pmu_save_and_restart(event))
1718 data.period = event->hw.last_period;
1720 if (perf_event_overflow(event, 1, &data, regs))
1721 intel_pmu_disable_event(&event->hw, bit);
1724 intel_pmu_ack_status(ack);
1727 * Repeat if there is more work to be done:
1729 status = intel_pmu_get_status();
1738 static int amd_pmu_handle_irq(struct pt_regs *regs)
1740 struct perf_sample_data data;
1741 struct cpu_hw_events *cpuc;
1742 struct perf_event *event;
1743 struct hw_perf_event *hwc;
1744 int idx, handled = 0;
1749 cpuc = &__get_cpu_var(cpu_hw_events);
1751 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1752 if (!test_bit(idx, cpuc->active_mask))
1755 event = cpuc->events[idx];
1758 val = x86_perf_event_update(event, hwc, idx);
1759 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1766 data.period = event->hw.last_period;
1768 if (!x86_perf_event_set_period(event, hwc, idx))
1771 if (perf_event_overflow(event, 1, &data, regs))
1772 amd_pmu_disable_event(hwc, idx);
1776 inc_irq_stat(apic_perf_irqs);
1781 void smp_perf_pending_interrupt(struct pt_regs *regs)
1785 inc_irq_stat(apic_pending_irqs);
1786 perf_event_do_pending();
1790 void set_perf_event_pending(void)
1792 #ifdef CONFIG_X86_LOCAL_APIC
1793 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1797 void perf_events_lapic_init(void)
1799 #ifdef CONFIG_X86_LOCAL_APIC
1800 if (!x86_pmu.apic || !x86_pmu_initialized())
1804 * Always use NMI for PMU
1806 apic_write(APIC_LVTPC, APIC_DM_NMI);
1810 static int __kprobes
1811 perf_event_nmi_handler(struct notifier_block *self,
1812 unsigned long cmd, void *__args)
1814 struct die_args *args = __args;
1815 struct pt_regs *regs;
1817 if (!atomic_read(&active_events))
1831 #ifdef CONFIG_X86_LOCAL_APIC
1832 apic_write(APIC_LVTPC, APIC_DM_NMI);
1835 * Can't rely on the handled return value to say it was our NMI, two
1836 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1838 * If the first NMI handles both, the latter will be empty and daze
1841 x86_pmu.handle_irq(regs);
1846 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1847 .notifier_call = perf_event_nmi_handler,
1852 static struct x86_pmu p6_pmu = {
1854 .handle_irq = p6_pmu_handle_irq,
1855 .disable_all = p6_pmu_disable_all,
1856 .enable_all = p6_pmu_enable_all,
1857 .enable = p6_pmu_enable_event,
1858 .disable = p6_pmu_disable_event,
1859 .eventsel = MSR_P6_EVNTSEL0,
1860 .perfctr = MSR_P6_PERFCTR0,
1861 .event_map = p6_pmu_event_map,
1862 .raw_event = p6_pmu_raw_event,
1863 .max_events = ARRAY_SIZE(p6_perfmon_event_map),
1865 .max_period = (1ULL << 31) - 1,
1869 * Events have 40 bits implemented. However they are designed such
1870 * that bits [32-39] are sign extensions of bit 31. As such the
1871 * effective width of a event for P6-like PMU is 32 bits only.
1873 * See IA-32 Intel Architecture Software developer manual Vol 3B
1876 .event_mask = (1ULL << 32) - 1,
1879 static struct x86_pmu intel_pmu = {
1881 .handle_irq = intel_pmu_handle_irq,
1882 .disable_all = intel_pmu_disable_all,
1883 .enable_all = intel_pmu_enable_all,
1884 .enable = intel_pmu_enable_event,
1885 .disable = intel_pmu_disable_event,
1886 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1887 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1888 .event_map = intel_pmu_event_map,
1889 .raw_event = intel_pmu_raw_event,
1890 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1893 * Intel PMCs cannot be accessed sanely above 32 bit width,
1894 * so we install an artificial 1<<31 period regardless of
1895 * the generic event period:
1897 .max_period = (1ULL << 31) - 1,
1898 .enable_bts = intel_pmu_enable_bts,
1899 .disable_bts = intel_pmu_disable_bts,
1902 static struct x86_pmu amd_pmu = {
1904 .handle_irq = amd_pmu_handle_irq,
1905 .disable_all = amd_pmu_disable_all,
1906 .enable_all = amd_pmu_enable_all,
1907 .enable = amd_pmu_enable_event,
1908 .disable = amd_pmu_disable_event,
1909 .eventsel = MSR_K7_EVNTSEL0,
1910 .perfctr = MSR_K7_PERFCTR0,
1911 .event_map = amd_pmu_event_map,
1912 .raw_event = amd_pmu_raw_event,
1913 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
1916 .event_mask = (1ULL << 48) - 1,
1918 /* use highest bit to detect overflow */
1919 .max_period = (1ULL << 47) - 1,
1922 static int p6_pmu_init(void)
1924 switch (boot_cpu_data.x86_model) {
1926 case 3: /* Pentium Pro */
1928 case 6: /* Pentium II */
1931 case 11: /* Pentium III */
1938 pr_cont("unsupported p6 CPU model %d ",
1939 boot_cpu_data.x86_model);
1945 if (!cpu_has_apic) {
1946 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1947 pr_info("no hardware sampling interrupt available.\n");
1954 static int intel_pmu_init(void)
1956 union cpuid10_edx edx;
1957 union cpuid10_eax eax;
1958 unsigned int unused;
1962 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
1963 /* check for P6 processor family */
1964 if (boot_cpu_data.x86 == 6) {
1965 return p6_pmu_init();
1972 * Check whether the Architectural PerfMon supports
1973 * Branch Misses Retired hw_event or not.
1975 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
1976 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
1979 version = eax.split.version_id;
1983 x86_pmu = intel_pmu;
1984 x86_pmu.version = version;
1985 x86_pmu.num_events = eax.split.num_events;
1986 x86_pmu.event_bits = eax.split.bit_width;
1987 x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1;
1990 * Quirk: v2 perfmon does not report fixed-purpose events, so
1991 * assume at least 3 events:
1993 x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
1996 * Install the hw-cache-events table:
1998 switch (boot_cpu_data.x86_model) {
1999 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2000 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2001 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2002 case 29: /* six-core 45 nm xeon "Dunnington" */
2003 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2004 sizeof(hw_cache_event_ids));
2006 pr_cont("Core2 events, ");
2010 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2011 sizeof(hw_cache_event_ids));
2013 pr_cont("Nehalem/Corei7 events, ");
2016 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2017 sizeof(hw_cache_event_ids));
2019 pr_cont("Atom events, ");
2025 static int amd_pmu_init(void)
2027 /* Performance-monitoring supported from K7 and later: */
2028 if (boot_cpu_data.x86 < 6)
2033 /* Events are common for all AMDs */
2034 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
2035 sizeof(hw_cache_event_ids));
2040 void __init init_hw_perf_events(void)
2044 pr_info("Performance Events: ");
2046 switch (boot_cpu_data.x86_vendor) {
2047 case X86_VENDOR_INTEL:
2048 err = intel_pmu_init();
2050 case X86_VENDOR_AMD:
2051 err = amd_pmu_init();
2057 pr_cont("no PMU driver, software events only.\n");
2061 pr_cont("%s PMU driver.\n", x86_pmu.name);
2063 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
2064 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2065 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
2066 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
2068 perf_event_mask = (1 << x86_pmu.num_events) - 1;
2069 perf_max_events = x86_pmu.num_events;
2071 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
2072 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2073 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
2074 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
2078 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
2079 x86_pmu.intel_ctrl = perf_event_mask;
2081 perf_events_lapic_init();
2082 register_die_notifier(&perf_event_nmi_notifier);
2084 pr_info("... version: %d\n", x86_pmu.version);
2085 pr_info("... bit width: %d\n", x86_pmu.event_bits);
2086 pr_info("... generic registers: %d\n", x86_pmu.num_events);
2087 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
2088 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2089 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
2090 pr_info("... event mask: %016Lx\n", perf_event_mask);
2093 static inline void x86_pmu_read(struct perf_event *event)
2095 x86_perf_event_update(event, &event->hw, event->hw.idx);
2098 static const struct pmu pmu = {
2099 .enable = x86_pmu_enable,
2100 .disable = x86_pmu_disable,
2101 .read = x86_pmu_read,
2102 .unthrottle = x86_pmu_unthrottle,
2105 const struct pmu *hw_perf_event_init(struct perf_event *event)
2109 err = __hw_perf_event_init(event);
2112 event->destroy(event);
2113 return ERR_PTR(err);
2124 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
2126 if (entry->nr < PERF_MAX_STACK_DEPTH)
2127 entry->ip[entry->nr++] = ip;
2130 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
2131 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
2132 static DEFINE_PER_CPU(int, in_nmi_frame);
2136 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
2138 /* Ignore warnings */
2141 static void backtrace_warning(void *data, char *msg)
2143 /* Ignore warnings */
2146 static int backtrace_stack(void *data, char *name)
2148 per_cpu(in_nmi_frame, smp_processor_id()) =
2149 x86_is_stack_id(NMI_STACK, name);
2154 static void backtrace_address(void *data, unsigned long addr, int reliable)
2156 struct perf_callchain_entry *entry = data;
2158 if (per_cpu(in_nmi_frame, smp_processor_id()))
2162 callchain_store(entry, addr);
2165 static const struct stacktrace_ops backtrace_ops = {
2166 .warning = backtrace_warning,
2167 .warning_symbol = backtrace_warning_symbol,
2168 .stack = backtrace_stack,
2169 .address = backtrace_address,
2172 #include "../dumpstack.h"
2175 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
2177 callchain_store(entry, PERF_CONTEXT_KERNEL);
2178 callchain_store(entry, regs->ip);
2180 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2184 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
2186 static unsigned long
2187 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
2189 unsigned long offset, addr = (unsigned long)from;
2190 int type = in_nmi() ? KM_NMI : KM_IRQ0;
2191 unsigned long size, len = 0;
2197 ret = __get_user_pages_fast(addr, 1, 0, &page);
2201 offset = addr & (PAGE_SIZE - 1);
2202 size = min(PAGE_SIZE - offset, n - len);
2204 map = kmap_atomic(page, type);
2205 memcpy(to, map+offset, size);
2206 kunmap_atomic(map, type);
2218 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
2220 unsigned long bytes;
2222 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
2224 return bytes == sizeof(*frame);
2228 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
2230 struct stack_frame frame;
2231 const void __user *fp;
2233 if (!user_mode(regs))
2234 regs = task_pt_regs(current);
2236 fp = (void __user *)regs->bp;
2238 callchain_store(entry, PERF_CONTEXT_USER);
2239 callchain_store(entry, regs->ip);
2241 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2242 frame.next_frame = NULL;
2243 frame.return_address = 0;
2245 if (!copy_stack_frame(fp, &frame))
2248 if ((unsigned long)fp < regs->sp)
2251 callchain_store(entry, frame.return_address);
2252 fp = frame.next_frame;
2257 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
2264 is_user = user_mode(regs);
2266 if (!current || current->pid == 0)
2269 if (is_user && current->state != TASK_RUNNING)
2273 perf_callchain_kernel(regs, entry);
2276 perf_callchain_user(regs, entry);
2279 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
2281 struct perf_callchain_entry *entry;
2284 entry = &__get_cpu_var(pmc_nmi_entry);
2286 entry = &__get_cpu_var(pmc_irq_entry);
2290 perf_do_callchain(regs, entry);
2295 void hw_perf_event_setup_online(int cpu)
2297 init_debug_store_on_cpu(cpu);