2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
19 #define wrmsrl(msr, val) \
21 unsigned int _msr = (msr); \
23 trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \
24 (unsigned long long)(_val)); \
25 native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \
31 * register -------------------------------
32 * | HT | no HT | HT | no HT |
33 *-----------------------------------------
34 * offcore | core | core | cpu | core |
35 * lbr_sel | core | core | cpu | core |
36 * ld_lat | cpu | core | cpu | core |
37 *-----------------------------------------
39 * Given that there is a small number of shared regs,
40 * we can pre-allocate their slot in the per-cpu
41 * per-core reg tables.
44 EXTRA_REG_NONE = -1, /* not used */
46 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
47 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
48 EXTRA_REG_LBR = 2, /* lbr_select */
49 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
51 EXTRA_REG_MAX /* number of entries needed */
54 struct event_constraint {
56 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
66 * struct hw_perf_event.flags flags
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
71 #define PERF_X86_EVENT_COMMITTED 0x0008 /* event passed commit_txn */
72 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0010 /* haswell style datala, load */
73 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0020 /* haswell style datala, unknown */
74 #define PERF_X86_EVENT_EXCL 0x0040 /* HT exclusivity on counter */
75 #define PERF_X86_EVENT_DYNAMIC 0x0080 /* dynamic alloc'd constraint */
76 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */
77 #define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */
78 #define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
79 #define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */
83 int nb_id; /* NorthBridge id */
84 int refcnt; /* reference count */
85 struct perf_event *owners[X86_PMC_IDX_MAX];
86 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
89 /* The maximal number of PEBS events: */
90 #define MAX_PEBS_EVENTS 8
93 * Flags PEBS can handle without an PMI.
95 * TID can only be handled by flushing at context switch.
98 #define PEBS_FREERUNNING_FLAGS \
99 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
100 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
101 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
102 PERF_SAMPLE_TRANSACTION)
105 * A debug store configuration.
107 * We only support architectures that use 64bit fields.
112 u64 bts_absolute_maximum;
113 u64 bts_interrupt_threshold;
114 u64 pebs_buffer_base;
116 u64 pebs_absolute_maximum;
117 u64 pebs_interrupt_threshold;
118 u64 pebs_event_reset[MAX_PEBS_EVENTS];
122 * Per register state.
125 raw_spinlock_t lock; /* per-core: protect structure */
126 u64 config; /* extra MSR config */
127 u64 reg; /* extra MSR number */
128 atomic_t ref; /* reference count */
134 * Used to coordinate shared registers between HT threads or
135 * among events on a single PMU.
137 struct intel_shared_regs {
138 struct er_account regs[EXTRA_REG_MAX];
139 int refcnt; /* per-core: #HT threads */
140 unsigned core_id; /* per-core: core id */
143 enum intel_excl_state_type {
144 INTEL_EXCL_UNUSED = 0, /* counter is unused */
145 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
146 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
149 struct intel_excl_states {
150 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
151 bool sched_started; /* true if scheduling has started */
154 struct intel_excl_cntrs {
157 struct intel_excl_states states[2];
160 u16 has_exclusive[2];
161 u32 exclusive_present;
164 int refcnt; /* per-core: #HT threads */
165 unsigned core_id; /* per-core: core id */
168 #define MAX_LBR_ENTRIES 32
171 X86_PERF_KFREE_SHARED = 0,
172 X86_PERF_KFREE_EXCL = 1,
176 struct cpu_hw_events {
178 * Generic x86 PMC bits
180 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
181 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
182 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
185 int n_events; /* the # of events in the below arrays */
186 int n_added; /* the # last events in the below arrays;
187 they've never been enabled yet */
188 int n_txn; /* the # last events in the below arrays;
189 added in the current transaction */
190 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
191 u64 tags[X86_PMC_IDX_MAX];
193 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
194 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
196 int n_excl; /* the number of exclusive events */
198 unsigned int group_flag;
202 * Intel DebugStore bits
204 struct debug_store *ds;
212 struct perf_branch_stack lbr_stack;
213 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
214 struct er_account *lbr_sel;
218 * Intel host/guest exclude bits
220 u64 intel_ctrl_guest_mask;
221 u64 intel_ctrl_host_mask;
222 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
225 * Intel checkpoint mask
230 * manage shared (per-core, per-cpu) registers
231 * used on Intel NHM/WSM/SNB
233 struct intel_shared_regs *shared_regs;
235 * manage exclusive counter access between hyperthread
237 struct event_constraint *constraint_list; /* in enable order */
238 struct intel_excl_cntrs *excl_cntrs;
239 int excl_thread_id; /* 0 or 1 */
244 struct amd_nb *amd_nb;
245 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
246 u64 perf_ctr_virt_mask;
248 void *kfree_on_online[X86_PERF_KFREE_MAX];
251 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
252 { .idxmsk64 = (n) }, \
260 #define EVENT_CONSTRAINT(c, n, m) \
261 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
263 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
264 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
265 0, PERF_X86_EVENT_EXCL)
268 * The overlap flag marks event constraints with overlapping counter
269 * masks. This is the case if the counter mask of such an event is not
270 * a subset of any other counter mask of a constraint with an equal or
271 * higher weight, e.g.:
273 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
274 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
275 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
277 * The event scheduler may not select the correct counter in the first
278 * cycle because it needs to know which subsequent events will be
279 * scheduled. It may fail to schedule the events then. So we set the
280 * overlap flag for such constraints to give the scheduler a hint which
281 * events to select for counter rescheduling.
283 * Care must be taken as the rescheduling algorithm is O(n!) which
284 * will increase scheduling cycles for an over-commited system
285 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
286 * and its counter masks must be kept at a minimum.
288 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
289 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
292 * Constraint on the Event code.
294 #define INTEL_EVENT_CONSTRAINT(c, n) \
295 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
298 * Constraint on the Event code + UMask + fixed-mask
300 * filter mask to validate fixed counter events.
301 * the following filters disqualify for fixed counters:
306 * - in_tx_checkpointed
307 * The other filters are supported by fixed counters.
308 * The any-thread option is supported starting with v3.
310 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
311 #define FIXED_EVENT_CONSTRAINT(c, n) \
312 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
315 * Constraint on the Event code + UMask
317 #define INTEL_UEVENT_CONSTRAINT(c, n) \
318 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
320 /* Like UEVENT_CONSTRAINT, but match flags too */
321 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
322 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
324 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
325 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
326 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
328 #define INTEL_PLD_CONSTRAINT(c, n) \
329 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
330 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
332 #define INTEL_PST_CONSTRAINT(c, n) \
333 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
334 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
336 /* Event constraint, but match on all event flags too. */
337 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
338 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
340 /* Check only flags, but allow all event/umask */
341 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
342 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
344 /* Check flags and event code, and set the HSW store flag */
345 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
346 __EVENT_CONSTRAINT(code, n, \
347 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
348 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
350 /* Check flags and event code, and set the HSW load flag */
351 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
352 __EVENT_CONSTRAINT(code, n, \
353 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
354 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
356 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
357 __EVENT_CONSTRAINT(code, n, \
358 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
360 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
362 /* Check flags and event code/umask, and set the HSW store flag */
363 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
364 __EVENT_CONSTRAINT(code, n, \
365 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
366 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
368 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
369 __EVENT_CONSTRAINT(code, n, \
370 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
372 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
374 /* Check flags and event code/umask, and set the HSW load flag */
375 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
376 __EVENT_CONSTRAINT(code, n, \
377 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
378 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
380 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
381 __EVENT_CONSTRAINT(code, n, \
382 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
384 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
386 /* Check flags and event code/umask, and set the HSW N/A flag */
387 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
388 __EVENT_CONSTRAINT(code, n, \
389 INTEL_ARCH_EVENT_MASK|INTEL_ARCH_EVENT_MASK, \
390 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
394 * We define the end marker as having a weight of -1
395 * to enable blacklisting of events using a counter bitmask
396 * of zero and thus a weight of zero.
397 * The end marker has a weight that cannot possibly be
398 * obtained from counting the bits in the bitmask.
400 #define EVENT_CONSTRAINT_END { .weight = -1 }
403 * Check for end marker with weight == -1
405 #define for_each_event_constraint(e, c) \
406 for ((e) = (c); (e)->weight != -1; (e)++)
409 * Extra registers for specific events.
411 * Some events need large masks and require external MSRs.
412 * Those extra MSRs end up being shared for all events on
413 * a PMU and sometimes between PMU of sibling HT threads.
414 * In either case, the kernel needs to handle conflicting
415 * accesses to those extra, shared, regs. The data structure
416 * to manage those registers is stored in cpu_hw_event.
423 int idx; /* per_xxx->regs[] reg index */
424 bool extra_msr_access;
427 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
430 .config_mask = (m), \
431 .valid_mask = (vm), \
432 .idx = EXTRA_REG_##i, \
433 .extra_msr_access = true, \
436 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
437 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
439 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
440 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
441 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
443 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
444 INTEL_UEVENT_EXTRA_REG(c, \
445 MSR_PEBS_LD_LAT_THRESHOLD, \
449 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
451 union perf_capabilities {
459 * PMU supports separate counter range for writing
462 u64 full_width_write:1;
467 struct x86_pmu_quirk {
468 struct x86_pmu_quirk *next;
472 union x86_pmu_config {
493 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
496 x86_lbr_exclusive_lbr,
497 x86_lbr_exclusive_bts,
498 x86_lbr_exclusive_pt,
499 x86_lbr_exclusive_max,
503 * struct x86_pmu - generic x86 pmu
507 * Generic x86 PMC bits
511 int (*handle_irq)(struct pt_regs *);
512 void (*disable_all)(void);
513 void (*enable_all)(int added);
514 void (*enable)(struct perf_event *);
515 void (*disable)(struct perf_event *);
516 int (*hw_config)(struct perf_event *event);
517 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
520 int (*addr_offset)(int index, bool eventsel);
521 int (*rdpmc_index)(int index);
522 u64 (*event_map)(int);
525 int num_counters_fixed;
529 unsigned long events_maskl;
530 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
535 struct event_constraint *
536 (*get_event_constraints)(struct cpu_hw_events *cpuc,
538 struct perf_event *event);
540 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
541 struct perf_event *event);
543 void (*start_scheduling)(struct cpu_hw_events *cpuc);
545 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
547 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
549 struct event_constraint *event_constraints;
550 struct x86_pmu_quirk *quirks;
551 int perfctr_second_write;
553 unsigned (*limit_period)(struct perf_event *event, unsigned l);
558 int attr_rdpmc_broken;
560 struct attribute **format_attrs;
561 struct attribute **event_attrs;
563 ssize_t (*events_sysfs_show)(char *page, u64 config);
564 struct attribute **cpu_events;
569 int (*cpu_prepare)(int cpu);
570 void (*cpu_starting)(int cpu);
571 void (*cpu_dying)(int cpu);
572 void (*cpu_dead)(int cpu);
574 void (*check_microcode)(void);
575 void (*sched_task)(struct perf_event_context *ctx,
579 * Intel Arch Perfmon v2+
582 union perf_capabilities intel_cap;
585 * Intel DebugStore bits
592 int pebs_record_size;
593 void (*drain_pebs)(struct pt_regs *regs);
594 struct event_constraint *pebs_constraints;
595 void (*pebs_aliases)(struct perf_event *event);
597 unsigned long free_running_flags;
602 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
603 int lbr_nr; /* hardware stack size */
604 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
605 const int *lbr_sel_map; /* lbr_select mappings */
606 bool lbr_double_abort; /* duplicated lbr aborts */
609 * Intel PT/LBR/BTS are exclusive
611 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
614 * Extra registers for events
616 struct extra_reg *extra_regs;
620 * Intel host/guest support (KVM)
622 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
625 struct x86_perf_task_context {
626 u64 lbr_from[MAX_LBR_ENTRIES];
627 u64 lbr_to[MAX_LBR_ENTRIES];
628 u64 lbr_info[MAX_LBR_ENTRIES];
629 int lbr_callstack_users;
633 #define x86_add_quirk(func_) \
635 static struct x86_pmu_quirk __quirk __initdata = { \
638 __quirk.next = x86_pmu.quirks; \
639 x86_pmu.quirks = &__quirk; \
645 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
646 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
647 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
648 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
650 #define EVENT_VAR(_id) event_attr_##_id
651 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
653 #define EVENT_ATTR(_name, _id) \
654 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
655 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
656 .id = PERF_COUNT_HW_##_id, \
660 #define EVENT_ATTR_STR(_name, v, str) \
661 static struct perf_pmu_events_attr event_attr_##v = { \
662 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
667 extern struct x86_pmu x86_pmu __read_mostly;
669 static inline bool x86_pmu_has_lbr_callstack(void)
671 return x86_pmu.lbr_sel_map &&
672 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
675 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
677 int x86_perf_event_set_period(struct perf_event *event);
680 * Generalized hw caching related hw_event table, filled
681 * in on a per model basis. A value of 0 means
682 * 'not supported', -1 means 'hw_event makes no sense on
683 * this CPU', any other value means the raw hw_event
687 #define C(x) PERF_COUNT_HW_CACHE_##x
689 extern u64 __read_mostly hw_cache_event_ids
690 [PERF_COUNT_HW_CACHE_MAX]
691 [PERF_COUNT_HW_CACHE_OP_MAX]
692 [PERF_COUNT_HW_CACHE_RESULT_MAX];
693 extern u64 __read_mostly hw_cache_extra_regs
694 [PERF_COUNT_HW_CACHE_MAX]
695 [PERF_COUNT_HW_CACHE_OP_MAX]
696 [PERF_COUNT_HW_CACHE_RESULT_MAX];
698 u64 x86_perf_event_update(struct perf_event *event);
700 static inline unsigned int x86_pmu_config_addr(int index)
702 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
703 x86_pmu.addr_offset(index, true) : index);
706 static inline unsigned int x86_pmu_event_addr(int index)
708 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
709 x86_pmu.addr_offset(index, false) : index);
712 static inline int x86_pmu_rdpmc_index(int index)
714 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
717 int x86_add_exclusive(unsigned int what);
719 void x86_del_exclusive(unsigned int what);
721 int x86_reserve_hardware(void);
723 void x86_release_hardware(void);
725 void hw_perf_lbr_event_destroy(struct perf_event *event);
727 int x86_setup_perfctr(struct perf_event *event);
729 int x86_pmu_hw_config(struct perf_event *event);
731 void x86_pmu_disable_all(void);
733 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
736 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
738 if (hwc->extra_reg.reg)
739 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
740 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
743 void x86_pmu_enable_all(int added);
745 int perf_assign_events(struct event_constraint **constraints, int n,
746 int wmin, int wmax, int gpmax, int *assign);
747 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
749 void x86_pmu_stop(struct perf_event *event, int flags);
751 static inline void x86_pmu_disable_event(struct perf_event *event)
753 struct hw_perf_event *hwc = &event->hw;
755 wrmsrl(hwc->config_base, hwc->config);
758 void x86_pmu_enable_event(struct perf_event *event);
760 int x86_pmu_handle_irq(struct pt_regs *regs);
762 extern struct event_constraint emptyconstraint;
764 extern struct event_constraint unconstrained;
766 static inline bool kernel_ip(unsigned long ip)
769 return ip > PAGE_OFFSET;
776 * Not all PMUs provide the right context information to place the reported IP
777 * into full context. Specifically segment registers are typically not
780 * Assuming the address is a linear address (it is for IBS), we fake the CS and
781 * vm86 mode using the known zero-based code segment and 'fix up' the registers
784 * Intel PEBS/LBR appear to typically provide the effective address, nothing
785 * much we can do about that but pray and treat it like a linear address.
787 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
789 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
790 if (regs->flags & X86_VM_MASK)
791 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
795 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
796 ssize_t intel_event_sysfs_show(char *page, u64 config);
798 struct attribute **merge_attr(struct attribute **a, struct attribute **b);
800 #ifdef CONFIG_CPU_SUP_AMD
802 int amd_pmu_init(void);
804 #else /* CONFIG_CPU_SUP_AMD */
806 static inline int amd_pmu_init(void)
811 #endif /* CONFIG_CPU_SUP_AMD */
813 #ifdef CONFIG_CPU_SUP_INTEL
815 static inline bool intel_pmu_has_bts(struct perf_event *event)
817 if (event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
818 !event->attr.freq && event->hw.sample_period == 1)
824 int intel_pmu_save_and_restart(struct perf_event *event);
826 struct event_constraint *
827 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
828 struct perf_event *event);
830 struct intel_shared_regs *allocate_shared_regs(int cpu);
832 int intel_pmu_init(void);
834 void init_debug_store_on_cpu(int cpu);
836 void fini_debug_store_on_cpu(int cpu);
838 void release_ds_buffers(void);
840 void reserve_ds_buffers(void);
842 extern struct event_constraint bts_constraint;
844 void intel_pmu_enable_bts(u64 config);
846 void intel_pmu_disable_bts(void);
848 int intel_pmu_drain_bts_buffer(void);
850 extern struct event_constraint intel_core2_pebs_event_constraints[];
852 extern struct event_constraint intel_atom_pebs_event_constraints[];
854 extern struct event_constraint intel_slm_pebs_event_constraints[];
856 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
858 extern struct event_constraint intel_westmere_pebs_event_constraints[];
860 extern struct event_constraint intel_snb_pebs_event_constraints[];
862 extern struct event_constraint intel_ivb_pebs_event_constraints[];
864 extern struct event_constraint intel_hsw_pebs_event_constraints[];
866 extern struct event_constraint intel_skl_pebs_event_constraints[];
868 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
870 void intel_pmu_pebs_enable(struct perf_event *event);
872 void intel_pmu_pebs_disable(struct perf_event *event);
874 void intel_pmu_pebs_enable_all(void);
876 void intel_pmu_pebs_disable_all(void);
878 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
880 void intel_ds_init(void);
882 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
884 void intel_pmu_lbr_reset(void);
886 void intel_pmu_lbr_enable(struct perf_event *event);
888 void intel_pmu_lbr_disable(struct perf_event *event);
890 void intel_pmu_lbr_enable_all(bool pmi);
892 void intel_pmu_lbr_disable_all(void);
894 void intel_pmu_lbr_read(void);
896 void intel_pmu_lbr_init_core(void);
898 void intel_pmu_lbr_init_nhm(void);
900 void intel_pmu_lbr_init_atom(void);
902 void intel_pmu_lbr_init_snb(void);
904 void intel_pmu_lbr_init_hsw(void);
906 void intel_pmu_lbr_init_skl(void);
908 int intel_pmu_setup_lbr_filter(struct perf_event *event);
910 void intel_pt_interrupt(void);
912 int intel_bts_interrupt(void);
914 void intel_bts_enable_local(void);
916 void intel_bts_disable_local(void);
918 int p4_pmu_init(void);
920 int p6_pmu_init(void);
922 int knc_pmu_init(void);
924 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
927 static inline int is_ht_workaround_enabled(void)
929 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
932 #else /* CONFIG_CPU_SUP_INTEL */
934 static inline void reserve_ds_buffers(void)
938 static inline void release_ds_buffers(void)
942 static inline int intel_pmu_init(void)
947 static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
952 static inline int is_ht_workaround_enabled(void)
956 #endif /* CONFIG_CPU_SUP_INTEL */