arch/x86/kernel/cpu/perf_event_intel.c

   1 /*
   2  * Per core/cpu state
   3  *
   4  * Used to coordinate shared registers between HT threads or
   5  * among events on a single PMU.
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/stddef.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/export.h>
  15 #include <linux/watchdog.h>
  16
  17 #include <asm/cpufeature.h>
  18 #include <asm/hardirq.h>
  19 #include <asm/apic.h>
  20
  21 #include "perf_event.h"
  22
  23 /*
  24  * Intel PerfMon, used on Core and later.
  25  */
  26 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  27 {
  28         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  29         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  30         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  31         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  32         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  33         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  34         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  35         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  36 };
  37
  38 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  39 {
  40         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  41         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  42         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  43         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  44         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  45         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  46         EVENT_CONSTRAINT_END
  47 };
  48
  49 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  50 {
  51         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  52         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  53         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  54         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  55         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  56         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  57         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  58         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  59         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  60         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  61         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  62         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  63         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  64         EVENT_CONSTRAINT_END
  65 };
  66
  67 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  68 {
  69         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  70         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  71         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  72         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  73         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  74         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  75         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  76         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  77         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  78         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  79         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  80         EVENT_CONSTRAINT_END
  81 };
  82
  83 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  84 {
  85         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
  86         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  87         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  88         EVENT_EXTRA_END
  89 };
  90
  91 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  92 {
  93         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  94         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  95         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  96         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  97         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  98         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  99         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
 100         EVENT_CONSTRAINT_END
 101 };
 102
 103 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 104 {
 105         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 106         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 107         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 108         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 109         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 110         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 111         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 112         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 113         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 114         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 115         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 116         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 117
 118         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 119         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 120         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 121         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 122
 123         EVENT_CONSTRAINT_END
 124 };
 125
 126 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 127 {
 128         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 129         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 130         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 131         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 132         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
 133         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 134         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
 135         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 136         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 137         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 138         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 139         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 140         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 141
 142         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 143         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 144         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 145         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 146
 147         EVENT_CONSTRAINT_END
 148 };
 149
 150 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 151 {
 152         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 153         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 154         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 155         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 156         EVENT_EXTRA_END
 157 };
 158
 159 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 160 {
 161         EVENT_CONSTRAINT_END
 162 };
 163
 164 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 165 {
 166         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 167         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 168         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 169         EVENT_CONSTRAINT_END
 170 };
 171
 172 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 173 {
 174         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 175         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 176         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
 177         EVENT_CONSTRAINT_END
 178 };
 179
 180 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 181         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 182         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 183         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 184         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 185         EVENT_EXTRA_END
 186 };
 187
 188 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 189         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 190         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 191         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 192         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 193         EVENT_EXTRA_END
 194 };
 195
 196 EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
 197 EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
 198 EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 199
 200 struct attribute *nhm_events_attrs[] = {
 201         EVENT_PTR(mem_ld_nhm),
 202         NULL,
 203 };
 204
 205 struct attribute *snb_events_attrs[] = {
 206         EVENT_PTR(mem_ld_snb),
 207         EVENT_PTR(mem_st_snb),
 208         NULL,
 209 };
 210
 211 static struct event_constraint intel_hsw_event_constraints[] = {
 212         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 213         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 214         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 215         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
 216         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 217         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 218         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 219         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
 220         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 221         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
 222         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 223         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
 224
 225         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 226         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 227         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 228         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 229
 230         EVENT_CONSTRAINT_END
 231 };
 232
 233 struct event_constraint intel_bdw_event_constraints[] = {
 234         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 235         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 236         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 237         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 238         INTEL_EVENT_CONSTRAINT(0xa3, 0x4),      /* CYCLE_ACTIVITY.* */
 239         EVENT_CONSTRAINT_END
 240 };
 241
 242 static u64 intel_pmu_event_map(int hw_event)
 243 {
 244         return intel_perfmon_event_map[hw_event];
 245 }
 246
 247 #define SNB_DMND_DATA_RD        (1ULL << 0)
 248 #define SNB_DMND_RFO            (1ULL << 1)
 249 #define SNB_DMND_IFETCH         (1ULL << 2)
 250 #define SNB_DMND_WB             (1ULL << 3)
 251 #define SNB_PF_DATA_RD          (1ULL << 4)
 252 #define SNB_PF_RFO              (1ULL << 5)
 253 #define SNB_PF_IFETCH           (1ULL << 6)
 254 #define SNB_LLC_DATA_RD         (1ULL << 7)
 255 #define SNB_LLC_RFO             (1ULL << 8)
 256 #define SNB_LLC_IFETCH          (1ULL << 9)
 257 #define SNB_BUS_LOCKS           (1ULL << 10)
 258 #define SNB_STRM_ST             (1ULL << 11)
 259 #define SNB_OTHER               (1ULL << 15)
 260 #define SNB_RESP_ANY            (1ULL << 16)
 261 #define SNB_NO_SUPP             (1ULL << 17)
 262 #define SNB_LLC_HITM            (1ULL << 18)
 263 #define SNB_LLC_HITE            (1ULL << 19)
 264 #define SNB_LLC_HITS            (1ULL << 20)
 265 #define SNB_LLC_HITF            (1ULL << 21)
 266 #define SNB_LOCAL               (1ULL << 22)
 267 #define SNB_REMOTE              (0xffULL << 23)
 268 #define SNB_SNP_NONE            (1ULL << 31)
 269 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 270 #define SNB_SNP_MISS            (1ULL << 33)
 271 #define SNB_NO_FWD              (1ULL << 34)
 272 #define SNB_SNP_FWD             (1ULL << 35)
 273 #define SNB_HITM                (1ULL << 36)
 274 #define SNB_NON_DRAM            (1ULL << 37)
 275
 276 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 277 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 278 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 279
 280 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 281                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 282                                  SNB_HITM)
 283
 284 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 285 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 286
 287 #define SNB_L3_ACCESS           SNB_RESP_ANY
 288 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 289
 290 static __initconst const u64 snb_hw_cache_extra_regs
 291                                 [PERF_COUNT_HW_CACHE_MAX]
 292                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 293                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 294 {
 295  [ C(LL  ) ] = {
 296         [ C(OP_READ) ] = {
 297                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 298                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 299         },
 300         [ C(OP_WRITE) ] = {
 301                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 302                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 303         },
 304         [ C(OP_PREFETCH) ] = {
 305                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 306                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 307         },
 308  },
 309  [ C(NODE) ] = {
 310         [ C(OP_READ) ] = {
 311                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 312                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 313         },
 314         [ C(OP_WRITE) ] = {
 315                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 316                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 317         },
 318         [ C(OP_PREFETCH) ] = {
 319                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 320                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 321         },
 322  },
 323 };
 324
 325 static __initconst const u64 snb_hw_cache_event_ids
 326                                 [PERF_COUNT_HW_CACHE_MAX]
 327                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 328                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 329 {
 330  [ C(L1D) ] = {
 331         [ C(OP_READ) ] = {
 332                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 333                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 334         },
 335         [ C(OP_WRITE) ] = {
 336                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 337                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 338         },
 339         [ C(OP_PREFETCH) ] = {
 340                 [ C(RESULT_ACCESS) ] = 0x0,
 341                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 342         },
 343  },
 344  [ C(L1I ) ] = {
 345         [ C(OP_READ) ] = {
 346                 [ C(RESULT_ACCESS) ] = 0x0,
 347                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 348         },
 349         [ C(OP_WRITE) ] = {
 350                 [ C(RESULT_ACCESS) ] = -1,
 351                 [ C(RESULT_MISS)   ] = -1,
 352         },
 353         [ C(OP_PREFETCH) ] = {
 354                 [ C(RESULT_ACCESS) ] = 0x0,
 355                 [ C(RESULT_MISS)   ] = 0x0,
 356         },
 357  },
 358  [ C(LL  ) ] = {
 359         [ C(OP_READ) ] = {
 360                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 361                 [ C(RESULT_ACCESS) ] = 0x01b7,
 362                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 363                 [ C(RESULT_MISS)   ] = 0x01b7,
 364         },
 365         [ C(OP_WRITE) ] = {
 366                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 367                 [ C(RESULT_ACCESS) ] = 0x01b7,
 368                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 369                 [ C(RESULT_MISS)   ] = 0x01b7,
 370         },
 371         [ C(OP_PREFETCH) ] = {
 372                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 373                 [ C(RESULT_ACCESS) ] = 0x01b7,
 374                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 375                 [ C(RESULT_MISS)   ] = 0x01b7,
 376         },
 377  },
 378  [ C(DTLB) ] = {
 379         [ C(OP_READ) ] = {
 380                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 381                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 382         },
 383         [ C(OP_WRITE) ] = {
 384                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 385                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 386         },
 387         [ C(OP_PREFETCH) ] = {
 388                 [ C(RESULT_ACCESS) ] = 0x0,
 389                 [ C(RESULT_MISS)   ] = 0x0,
 390         },
 391  },
 392  [ C(ITLB) ] = {
 393         [ C(OP_READ) ] = {
 394                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 395                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 396         },
 397         [ C(OP_WRITE) ] = {
 398                 [ C(RESULT_ACCESS) ] = -1,
 399                 [ C(RESULT_MISS)   ] = -1,
 400         },
 401         [ C(OP_PREFETCH) ] = {
 402                 [ C(RESULT_ACCESS) ] = -1,
 403                 [ C(RESULT_MISS)   ] = -1,
 404         },
 405  },
 406  [ C(BPU ) ] = {
 407         [ C(OP_READ) ] = {
 408                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 409                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 410         },
 411         [ C(OP_WRITE) ] = {
 412                 [ C(RESULT_ACCESS) ] = -1,
 413                 [ C(RESULT_MISS)   ] = -1,
 414         },
 415         [ C(OP_PREFETCH) ] = {
 416                 [ C(RESULT_ACCESS) ] = -1,
 417                 [ C(RESULT_MISS)   ] = -1,
 418         },
 419  },
 420  [ C(NODE) ] = {
 421         [ C(OP_READ) ] = {
 422                 [ C(RESULT_ACCESS) ] = 0x01b7,
 423                 [ C(RESULT_MISS)   ] = 0x01b7,
 424         },
 425         [ C(OP_WRITE) ] = {
 426                 [ C(RESULT_ACCESS) ] = 0x01b7,
 427                 [ C(RESULT_MISS)   ] = 0x01b7,
 428         },
 429         [ C(OP_PREFETCH) ] = {
 430                 [ C(RESULT_ACCESS) ] = 0x01b7,
 431                 [ C(RESULT_MISS)   ] = 0x01b7,
 432         },
 433  },
 434
 435 };
 436
 437 /*
 438  * Notes on the events:
 439  * - data reads do not include code reads (comparable to earlier tables)
 440  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 441  * - remote node access includes remote memory, remote cache, remote mmio.
 442  * - prefetches are not included in the counts because they are not
 443  *   reliably counted.
 444  */
 445
 446 #define HSW_DEMAND_DATA_RD              BIT_ULL(0)
 447 #define HSW_DEMAND_RFO                  BIT_ULL(1)
 448 #define HSW_ANY_RESPONSE                BIT_ULL(16)
 449 #define HSW_SUPPLIER_NONE               BIT_ULL(17)
 450 #define HSW_L3_MISS_LOCAL_DRAM          BIT_ULL(22)
 451 #define HSW_L3_MISS_REMOTE_HOP0         BIT_ULL(27)
 452 #define HSW_L3_MISS_REMOTE_HOP1         BIT_ULL(28)
 453 #define HSW_L3_MISS_REMOTE_HOP2P        BIT_ULL(29)
 454 #define HSW_L3_MISS                     (HSW_L3_MISS_LOCAL_DRAM| \
 455                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 456                                          HSW_L3_MISS_REMOTE_HOP2P)
 457 #define HSW_SNOOP_NONE                  BIT_ULL(31)
 458 #define HSW_SNOOP_NOT_NEEDED            BIT_ULL(32)
 459 #define HSW_SNOOP_MISS                  BIT_ULL(33)
 460 #define HSW_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 461 #define HSW_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 462 #define HSW_SNOOP_HITM                  BIT_ULL(36)
 463 #define HSW_SNOOP_NON_DRAM              BIT_ULL(37)
 464 #define HSW_ANY_SNOOP                   (HSW_SNOOP_NONE| \
 465                                          HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
 466                                          HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
 467                                          HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
 468 #define HSW_SNOOP_DRAM                  (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
 469 #define HSW_DEMAND_READ                 HSW_DEMAND_DATA_RD
 470 #define HSW_DEMAND_WRITE                HSW_DEMAND_RFO
 471 #define HSW_L3_MISS_REMOTE              (HSW_L3_MISS_REMOTE_HOP0|\
 472                                          HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
 473 #define HSW_LLC_ACCESS                  HSW_ANY_RESPONSE
 474
 475 #define BDW_L3_MISS_LOCAL               BIT(26)
 476 #define BDW_L3_MISS                     (BDW_L3_MISS_LOCAL| \
 477                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 478                                          HSW_L3_MISS_REMOTE_HOP2P)
 479
 480
 481 static __initconst const u64 hsw_hw_cache_event_ids
 482                                 [PERF_COUNT_HW_CACHE_MAX]
 483                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 484                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 485 {
 486  [ C(L1D ) ] = {
 487         [ C(OP_READ) ] = {
 488                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 489                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 490         },
 491         [ C(OP_WRITE) ] = {
 492                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 493                 [ C(RESULT_MISS)   ] = 0x0,
 494         },
 495         [ C(OP_PREFETCH) ] = {
 496                 [ C(RESULT_ACCESS) ] = 0x0,
 497                 [ C(RESULT_MISS)   ] = 0x0,
 498         },
 499  },
 500  [ C(L1I ) ] = {
 501         [ C(OP_READ) ] = {
 502                 [ C(RESULT_ACCESS) ] = 0x0,
 503                 [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
 504         },
 505         [ C(OP_WRITE) ] = {
 506                 [ C(RESULT_ACCESS) ] = -1,
 507                 [ C(RESULT_MISS)   ] = -1,
 508         },
 509         [ C(OP_PREFETCH) ] = {
 510                 [ C(RESULT_ACCESS) ] = 0x0,
 511                 [ C(RESULT_MISS)   ] = 0x0,
 512         },
 513  },
 514  [ C(LL  ) ] = {
 515         [ C(OP_READ) ] = {
 516                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 517                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 518         },
 519         [ C(OP_WRITE) ] = {
 520                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 521                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 522         },
 523         [ C(OP_PREFETCH) ] = {
 524                 [ C(RESULT_ACCESS) ] = 0x0,
 525                 [ C(RESULT_MISS)   ] = 0x0,
 526         },
 527  },
 528  [ C(DTLB) ] = {
 529         [ C(OP_READ) ] = {
 530                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 531                 [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
 532         },
 533         [ C(OP_WRITE) ] = {
 534                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 535                 [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 536         },
 537         [ C(OP_PREFETCH) ] = {
 538                 [ C(RESULT_ACCESS) ] = 0x0,
 539                 [ C(RESULT_MISS)   ] = 0x0,
 540         },
 541  },
 542  [ C(ITLB) ] = {
 543         [ C(OP_READ) ] = {
 544                 [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
 545                 [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
 546         },
 547         [ C(OP_WRITE) ] = {
 548                 [ C(RESULT_ACCESS) ] = -1,
 549                 [ C(RESULT_MISS)   ] = -1,
 550         },
 551         [ C(OP_PREFETCH) ] = {
 552                 [ C(RESULT_ACCESS) ] = -1,
 553                 [ C(RESULT_MISS)   ] = -1,
 554         },
 555  },
 556  [ C(BPU ) ] = {
 557         [ C(OP_READ) ] = {
 558                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 559                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 560         },
 561         [ C(OP_WRITE) ] = {
 562                 [ C(RESULT_ACCESS) ] = -1,
 563                 [ C(RESULT_MISS)   ] = -1,
 564         },
 565         [ C(OP_PREFETCH) ] = {
 566                 [ C(RESULT_ACCESS) ] = -1,
 567                 [ C(RESULT_MISS)   ] = -1,
 568         },
 569  },
 570  [ C(NODE) ] = {
 571         [ C(OP_READ) ] = {
 572                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 573                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 574         },
 575         [ C(OP_WRITE) ] = {
 576                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 577                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 578         },
 579         [ C(OP_PREFETCH) ] = {
 580                 [ C(RESULT_ACCESS) ] = 0x0,
 581                 [ C(RESULT_MISS)   ] = 0x0,
 582         },
 583  },
 584 };
 585
 586 static __initconst const u64 hsw_hw_cache_extra_regs
 587                                 [PERF_COUNT_HW_CACHE_MAX]
 588                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 589                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 590 {
 591  [ C(LL  ) ] = {
 592         [ C(OP_READ) ] = {
 593                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
 594                                        HSW_LLC_ACCESS,
 595                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
 596                                        HSW_L3_MISS|HSW_ANY_SNOOP,
 597         },
 598         [ C(OP_WRITE) ] = {
 599                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
 600                                        HSW_LLC_ACCESS,
 601                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
 602                                        HSW_L3_MISS|HSW_ANY_SNOOP,
 603         },
 604         [ C(OP_PREFETCH) ] = {
 605                 [ C(RESULT_ACCESS) ] = 0x0,
 606                 [ C(RESULT_MISS)   ] = 0x0,
 607         },
 608  },
 609  [ C(NODE) ] = {
 610         [ C(OP_READ) ] = {
 611                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
 612                                        HSW_L3_MISS_LOCAL_DRAM|
 613                                        HSW_SNOOP_DRAM,
 614                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
 615                                        HSW_L3_MISS_REMOTE|
 616                                        HSW_SNOOP_DRAM,
 617         },
 618         [ C(OP_WRITE) ] = {
 619                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
 620                                        HSW_L3_MISS_LOCAL_DRAM|
 621                                        HSW_SNOOP_DRAM,
 622                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
 623                                        HSW_L3_MISS_REMOTE|
 624                                        HSW_SNOOP_DRAM,
 625         },
 626         [ C(OP_PREFETCH) ] = {
 627                 [ C(RESULT_ACCESS) ] = 0x0,
 628                 [ C(RESULT_MISS)   ] = 0x0,
 629         },
 630  },
 631 };
 632
 633 static __initconst const u64 westmere_hw_cache_event_ids
 634                                 [PERF_COUNT_HW_CACHE_MAX]
 635                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 636                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 637 {
 638  [ C(L1D) ] = {
 639         [ C(OP_READ) ] = {
 640                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 641                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 642         },
 643         [ C(OP_WRITE) ] = {
 644                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 645                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 646         },
 647         [ C(OP_PREFETCH) ] = {
 648                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 649                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 650         },
 651  },
 652  [ C(L1I ) ] = {
 653         [ C(OP_READ) ] = {
 654                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 655                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 656         },
 657         [ C(OP_WRITE) ] = {
 658                 [ C(RESULT_ACCESS) ] = -1,
 659                 [ C(RESULT_MISS)   ] = -1,
 660         },
 661         [ C(OP_PREFETCH) ] = {
 662                 [ C(RESULT_ACCESS) ] = 0x0,
 663                 [ C(RESULT_MISS)   ] = 0x0,
 664         },
 665  },
 666  [ C(LL  ) ] = {
 667         [ C(OP_READ) ] = {
 668                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 669                 [ C(RESULT_ACCESS) ] = 0x01b7,
 670                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 671                 [ C(RESULT_MISS)   ] = 0x01b7,
 672         },
 673         /*
 674          * Use RFO, not WRITEBACK, because a write miss would typically occur
 675          * on RFO.
 676          */
 677         [ C(OP_WRITE) ] = {
 678                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 679                 [ C(RESULT_ACCESS) ] = 0x01b7,
 680                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 681                 [ C(RESULT_MISS)   ] = 0x01b7,
 682         },
 683         [ C(OP_PREFETCH) ] = {
 684                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 685                 [ C(RESULT_ACCESS) ] = 0x01b7,
 686                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 687                 [ C(RESULT_MISS)   ] = 0x01b7,
 688         },
 689  },
 690  [ C(DTLB) ] = {
 691         [ C(OP_READ) ] = {
 692                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 693                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 694         },
 695         [ C(OP_WRITE) ] = {
 696                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 697                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 698         },
 699         [ C(OP_PREFETCH) ] = {
 700                 [ C(RESULT_ACCESS) ] = 0x0,
 701                 [ C(RESULT_MISS)   ] = 0x0,
 702         },
 703  },
 704  [ C(ITLB) ] = {
 705         [ C(OP_READ) ] = {
 706                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 707                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 708         },
 709         [ C(OP_WRITE) ] = {
 710                 [ C(RESULT_ACCESS) ] = -1,
 711                 [ C(RESULT_MISS)   ] = -1,
 712         },
 713         [ C(OP_PREFETCH) ] = {
 714                 [ C(RESULT_ACCESS) ] = -1,
 715                 [ C(RESULT_MISS)   ] = -1,
 716         },
 717  },
 718  [ C(BPU ) ] = {
 719         [ C(OP_READ) ] = {
 720                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 721                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 722         },
 723         [ C(OP_WRITE) ] = {
 724                 [ C(RESULT_ACCESS) ] = -1,
 725                 [ C(RESULT_MISS)   ] = -1,
 726         },
 727         [ C(OP_PREFETCH) ] = {
 728                 [ C(RESULT_ACCESS) ] = -1,
 729                 [ C(RESULT_MISS)   ] = -1,
 730         },
 731  },
 732  [ C(NODE) ] = {
 733         [ C(OP_READ) ] = {
 734                 [ C(RESULT_ACCESS) ] = 0x01b7,
 735                 [ C(RESULT_MISS)   ] = 0x01b7,
 736         },
 737         [ C(OP_WRITE) ] = {
 738                 [ C(RESULT_ACCESS) ] = 0x01b7,
 739                 [ C(RESULT_MISS)   ] = 0x01b7,
 740         },
 741         [ C(OP_PREFETCH) ] = {
 742                 [ C(RESULT_ACCESS) ] = 0x01b7,
 743                 [ C(RESULT_MISS)   ] = 0x01b7,
 744         },
 745  },
 746 };
 747
 748 /*
 749  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
 750  * See IA32 SDM Vol 3B 30.6.1.3
 751  */
 752
 753 #define NHM_DMND_DATA_RD        (1 << 0)
 754 #define NHM_DMND_RFO            (1 << 1)
 755 #define NHM_DMND_IFETCH         (1 << 2)
 756 #define NHM_DMND_WB             (1 << 3)
 757 #define NHM_PF_DATA_RD          (1 << 4)
 758 #define NHM_PF_DATA_RFO         (1 << 5)
 759 #define NHM_PF_IFETCH           (1 << 6)
 760 #define NHM_OFFCORE_OTHER       (1 << 7)
 761 #define NHM_UNCORE_HIT          (1 << 8)
 762 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
 763 #define NHM_OTHER_CORE_HITM     (1 << 10)
 764                                 /* reserved */
 765 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
 766 #define NHM_REMOTE_DRAM         (1 << 13)
 767 #define NHM_LOCAL_DRAM          (1 << 14)
 768 #define NHM_NON_DRAM            (1 << 15)
 769
 770 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
 771 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
 772
 773 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
 774 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
 775 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
 776
 777 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
 778 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
 779 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
 780
 781 static __initconst const u64 nehalem_hw_cache_extra_regs
 782                                 [PERF_COUNT_HW_CACHE_MAX]
 783                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 784                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 785 {
 786  [ C(LL  ) ] = {
 787         [ C(OP_READ) ] = {
 788                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
 789                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
 790         },
 791         [ C(OP_WRITE) ] = {
 792                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
 793                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
 794         },
 795         [ C(OP_PREFETCH) ] = {
 796                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
 797                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
 798         },
 799  },
 800  [ C(NODE) ] = {
 801         [ C(OP_READ) ] = {
 802                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
 803                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
 804         },
 805         [ C(OP_WRITE) ] = {
 806                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
 807                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
 808         },
 809         [ C(OP_PREFETCH) ] = {
 810                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
 811                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
 812         },
 813  },
 814 };
 815
 816 static __initconst const u64 nehalem_hw_cache_event_ids
 817                                 [PERF_COUNT_HW_CACHE_MAX]
 818                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 819                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 820 {
 821  [ C(L1D) ] = {
 822         [ C(OP_READ) ] = {
 823                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 824                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 825         },
 826         [ C(OP_WRITE) ] = {
 827                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 828                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 829         },
 830         [ C(OP_PREFETCH) ] = {
 831                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 832                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 833         },
 834  },
 835  [ C(L1I ) ] = {
 836         [ C(OP_READ) ] = {
 837                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 838                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 839         },
 840         [ C(OP_WRITE) ] = {
 841                 [ C(RESULT_ACCESS) ] = -1,
 842                 [ C(RESULT_MISS)   ] = -1,
 843         },
 844         [ C(OP_PREFETCH) ] = {
 845                 [ C(RESULT_ACCESS) ] = 0x0,
 846                 [ C(RESULT_MISS)   ] = 0x0,
 847         },
 848  },
 849  [ C(LL  ) ] = {
 850         [ C(OP_READ) ] = {
 851                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 852                 [ C(RESULT_ACCESS) ] = 0x01b7,
 853                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 854                 [ C(RESULT_MISS)   ] = 0x01b7,
 855         },
 856         /*
 857          * Use RFO, not WRITEBACK, because a write miss would typically occur
 858          * on RFO.
 859          */
 860         [ C(OP_WRITE) ] = {
 861                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 862                 [ C(RESULT_ACCESS) ] = 0x01b7,
 863                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 864                 [ C(RESULT_MISS)   ] = 0x01b7,
 865         },
 866         [ C(OP_PREFETCH) ] = {
 867                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 868                 [ C(RESULT_ACCESS) ] = 0x01b7,
 869                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 870                 [ C(RESULT_MISS)   ] = 0x01b7,
 871         },
 872  },
 873  [ C(DTLB) ] = {
 874         [ C(OP_READ) ] = {
 875                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
 876                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 877         },
 878         [ C(OP_WRITE) ] = {
 879                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
 880                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 881         },
 882         [ C(OP_PREFETCH) ] = {
 883                 [ C(RESULT_ACCESS) ] = 0x0,
 884                 [ C(RESULT_MISS)   ] = 0x0,
 885         },
 886  },
 887  [ C(ITLB) ] = {
 888         [ C(OP_READ) ] = {
 889                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 890                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
 891         },
 892         [ C(OP_WRITE) ] = {
 893                 [ C(RESULT_ACCESS) ] = -1,
 894                 [ C(RESULT_MISS)   ] = -1,
 895         },
 896         [ C(OP_PREFETCH) ] = {
 897                 [ C(RESULT_ACCESS) ] = -1,
 898                 [ C(RESULT_MISS)   ] = -1,
 899         },
 900  },
 901  [ C(BPU ) ] = {
 902         [ C(OP_READ) ] = {
 903                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 904                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 905         },
 906         [ C(OP_WRITE) ] = {
 907                 [ C(RESULT_ACCESS) ] = -1,
 908                 [ C(RESULT_MISS)   ] = -1,
 909         },
 910         [ C(OP_PREFETCH) ] = {
 911                 [ C(RESULT_ACCESS) ] = -1,
 912                 [ C(RESULT_MISS)   ] = -1,
 913         },
 914  },
 915  [ C(NODE) ] = {
 916         [ C(OP_READ) ] = {
 917                 [ C(RESULT_ACCESS) ] = 0x01b7,
 918                 [ C(RESULT_MISS)   ] = 0x01b7,
 919         },
 920         [ C(OP_WRITE) ] = {
 921                 [ C(RESULT_ACCESS) ] = 0x01b7,
 922                 [ C(RESULT_MISS)   ] = 0x01b7,
 923         },
 924         [ C(OP_PREFETCH) ] = {
 925                 [ C(RESULT_ACCESS) ] = 0x01b7,
 926                 [ C(RESULT_MISS)   ] = 0x01b7,
 927         },
 928  },
 929 };
 930
 931 static __initconst const u64 core2_hw_cache_event_ids
 932                                 [PERF_COUNT_HW_CACHE_MAX]
 933                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 934                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 935 {
 936  [ C(L1D) ] = {
 937         [ C(OP_READ) ] = {
 938                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
 939                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
 940         },
 941         [ C(OP_WRITE) ] = {
 942                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
 943                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
 944         },
 945         [ C(OP_PREFETCH) ] = {
 946                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
 947                 [ C(RESULT_MISS)   ] = 0,
 948         },
 949  },
 950  [ C(L1I ) ] = {
 951         [ C(OP_READ) ] = {
 952                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
 953                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
 954         },
 955         [ C(OP_WRITE) ] = {
 956                 [ C(RESULT_ACCESS) ] = -1,
 957                 [ C(RESULT_MISS)   ] = -1,
 958         },
 959         [ C(OP_PREFETCH) ] = {
 960                 [ C(RESULT_ACCESS) ] = 0,
 961                 [ C(RESULT_MISS)   ] = 0,
 962         },
 963  },
 964  [ C(LL  ) ] = {
 965         [ C(OP_READ) ] = {
 966                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 967                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 968         },
 969         [ C(OP_WRITE) ] = {
 970                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 971                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 972         },
 973         [ C(OP_PREFETCH) ] = {
 974                 [ C(RESULT_ACCESS) ] = 0,
 975                 [ C(RESULT_MISS)   ] = 0,
 976         },
 977  },
 978  [ C(DTLB) ] = {
 979         [ C(OP_READ) ] = {
 980                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
 981                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
 982         },
 983         [ C(OP_WRITE) ] = {
 984                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
 985                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
 986         },
 987         [ C(OP_PREFETCH) ] = {
 988                 [ C(RESULT_ACCESS) ] = 0,
 989                 [ C(RESULT_MISS)   ] = 0,
 990         },
 991  },
 992  [ C(ITLB) ] = {
 993         [ C(OP_READ) ] = {
 994                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 995                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
 996         },
 997         [ C(OP_WRITE) ] = {
 998                 [ C(RESULT_ACCESS) ] = -1,
 999                 [ C(RESULT_MISS)   ] = -1,
1000         },
1001         [ C(OP_PREFETCH) ] = {
1002                 [ C(RESULT_ACCESS) ] = -1,
1003                 [ C(RESULT_MISS)   ] = -1,
1004         },
1005  },
1006  [ C(BPU ) ] = {
1007         [ C(OP_READ) ] = {
1008                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1009                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1010         },
1011         [ C(OP_WRITE) ] = {
1012                 [ C(RESULT_ACCESS) ] = -1,
1013                 [ C(RESULT_MISS)   ] = -1,
1014         },
1015         [ C(OP_PREFETCH) ] = {
1016                 [ C(RESULT_ACCESS) ] = -1,
1017                 [ C(RESULT_MISS)   ] = -1,
1018         },
1019  },
1020 };
1021
1022 static __initconst const u64 atom_hw_cache_event_ids
1023                                 [PERF_COUNT_HW_CACHE_MAX]
1024                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1025                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1026 {
1027  [ C(L1D) ] = {
1028         [ C(OP_READ) ] = {
1029                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
1030                 [ C(RESULT_MISS)   ] = 0,
1031         },
1032         [ C(OP_WRITE) ] = {
1033                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
1034                 [ C(RESULT_MISS)   ] = 0,
1035         },
1036         [ C(OP_PREFETCH) ] = {
1037                 [ C(RESULT_ACCESS) ] = 0x0,
1038                 [ C(RESULT_MISS)   ] = 0,
1039         },
1040  },
1041  [ C(L1I ) ] = {
1042         [ C(OP_READ) ] = {
1043                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
1044                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
1045         },
1046         [ C(OP_WRITE) ] = {
1047                 [ C(RESULT_ACCESS) ] = -1,
1048                 [ C(RESULT_MISS)   ] = -1,
1049         },
1050         [ C(OP_PREFETCH) ] = {
1051                 [ C(RESULT_ACCESS) ] = 0,
1052                 [ C(RESULT_MISS)   ] = 0,
1053         },
1054  },
1055  [ C(LL  ) ] = {
1056         [ C(OP_READ) ] = {
1057                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1058                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1059         },
1060         [ C(OP_WRITE) ] = {
1061                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1062                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1063         },
1064         [ C(OP_PREFETCH) ] = {
1065                 [ C(RESULT_ACCESS) ] = 0,
1066                 [ C(RESULT_MISS)   ] = 0,
1067         },
1068  },
1069  [ C(DTLB) ] = {
1070         [ C(OP_READ) ] = {
1071                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
1072                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
1073         },
1074         [ C(OP_WRITE) ] = {
1075                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
1076                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
1077         },
1078         [ C(OP_PREFETCH) ] = {
1079                 [ C(RESULT_ACCESS) ] = 0,
1080                 [ C(RESULT_MISS)   ] = 0,
1081         },
1082  },
1083  [ C(ITLB) ] = {
1084         [ C(OP_READ) ] = {
1085                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1086                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
1087         },
1088         [ C(OP_WRITE) ] = {
1089                 [ C(RESULT_ACCESS) ] = -1,
1090                 [ C(RESULT_MISS)   ] = -1,
1091         },
1092         [ C(OP_PREFETCH) ] = {
1093                 [ C(RESULT_ACCESS) ] = -1,
1094                 [ C(RESULT_MISS)   ] = -1,
1095         },
1096  },
1097  [ C(BPU ) ] = {
1098         [ C(OP_READ) ] = {
1099                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1100                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1101         },
1102         [ C(OP_WRITE) ] = {
1103                 [ C(RESULT_ACCESS) ] = -1,
1104                 [ C(RESULT_MISS)   ] = -1,
1105         },
1106         [ C(OP_PREFETCH) ] = {
1107                 [ C(RESULT_ACCESS) ] = -1,
1108                 [ C(RESULT_MISS)   ] = -1,
1109         },
1110  },
1111 };
1112
1113 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1114 {
1115         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1116         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1117         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
1118         EVENT_EXTRA_END
1119 };
1120
1121 #define SLM_DMND_READ           SNB_DMND_DATA_RD
1122 #define SLM_DMND_WRITE          SNB_DMND_RFO
1123 #define SLM_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
1124
1125 #define SLM_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1126 #define SLM_LLC_ACCESS          SNB_RESP_ANY
1127 #define SLM_LLC_MISS            (SLM_SNP_ANY|SNB_NON_DRAM)
1128
1129 static __initconst const u64 slm_hw_cache_extra_regs
1130                                 [PERF_COUNT_HW_CACHE_MAX]
1131                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1132                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1133 {
1134  [ C(LL  ) ] = {
1135         [ C(OP_READ) ] = {
1136                 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1137                 [ C(RESULT_MISS)   ] = SLM_DMND_READ|SLM_LLC_MISS,
1138         },
1139         [ C(OP_WRITE) ] = {
1140                 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1141                 [ C(RESULT_MISS)   ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1142         },
1143         [ C(OP_PREFETCH) ] = {
1144                 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1145                 [ C(RESULT_MISS)   ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1146         },
1147  },
1148 };
1149
1150 static __initconst const u64 slm_hw_cache_event_ids
1151                                 [PERF_COUNT_HW_CACHE_MAX]
1152                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1153                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1154 {
1155  [ C(L1D) ] = {
1156         [ C(OP_READ) ] = {
1157                 [ C(RESULT_ACCESS) ] = 0,
1158                 [ C(RESULT_MISS)   ] = 0x0104, /* LD_DCU_MISS */
1159         },
1160         [ C(OP_WRITE) ] = {
1161                 [ C(RESULT_ACCESS) ] = 0,
1162                 [ C(RESULT_MISS)   ] = 0,
1163         },
1164         [ C(OP_PREFETCH) ] = {
1165                 [ C(RESULT_ACCESS) ] = 0,
1166                 [ C(RESULT_MISS)   ] = 0,
1167         },
1168  },
1169  [ C(L1I ) ] = {
1170         [ C(OP_READ) ] = {
1171                 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1172                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACGE.MISSES */
1173         },
1174         [ C(OP_WRITE) ] = {
1175                 [ C(RESULT_ACCESS) ] = -1,
1176                 [ C(RESULT_MISS)   ] = -1,
1177         },
1178         [ C(OP_PREFETCH) ] = {
1179                 [ C(RESULT_ACCESS) ] = 0,
1180                 [ C(RESULT_MISS)   ] = 0,
1181         },
1182  },
1183  [ C(LL  ) ] = {
1184         [ C(OP_READ) ] = {
1185                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1186                 [ C(RESULT_ACCESS) ] = 0x01b7,
1187                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1188                 [ C(RESULT_MISS)   ] = 0x01b7,
1189         },
1190         [ C(OP_WRITE) ] = {
1191                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1192                 [ C(RESULT_ACCESS) ] = 0x01b7,
1193                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1194                 [ C(RESULT_MISS)   ] = 0x01b7,
1195         },
1196         [ C(OP_PREFETCH) ] = {
1197                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1198                 [ C(RESULT_ACCESS) ] = 0x01b7,
1199                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1200                 [ C(RESULT_MISS)   ] = 0x01b7,
1201         },
1202  },
1203  [ C(DTLB) ] = {
1204         [ C(OP_READ) ] = {
1205                 [ C(RESULT_ACCESS) ] = 0,
1206                 [ C(RESULT_MISS)   ] = 0x0804, /* LD_DTLB_MISS */
1207         },
1208         [ C(OP_WRITE) ] = {
1209                 [ C(RESULT_ACCESS) ] = 0,
1210                 [ C(RESULT_MISS)   ] = 0,
1211         },
1212         [ C(OP_PREFETCH) ] = {
1213                 [ C(RESULT_ACCESS) ] = 0,
1214                 [ C(RESULT_MISS)   ] = 0,
1215         },
1216  },
1217  [ C(ITLB) ] = {
1218         [ C(OP_READ) ] = {
1219                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1220                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES */
1221         },
1222         [ C(OP_WRITE) ] = {
1223                 [ C(RESULT_ACCESS) ] = -1,
1224                 [ C(RESULT_MISS)   ] = -1,
1225         },
1226         [ C(OP_PREFETCH) ] = {
1227                 [ C(RESULT_ACCESS) ] = -1,
1228                 [ C(RESULT_MISS)   ] = -1,
1229         },
1230  },
1231  [ C(BPU ) ] = {
1232         [ C(OP_READ) ] = {
1233                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1234                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1235         },
1236         [ C(OP_WRITE) ] = {
1237                 [ C(RESULT_ACCESS) ] = -1,
1238                 [ C(RESULT_MISS)   ] = -1,
1239         },
1240         [ C(OP_PREFETCH) ] = {
1241                 [ C(RESULT_ACCESS) ] = -1,
1242                 [ C(RESULT_MISS)   ] = -1,
1243         },
1244  },
1245 };
1246
1247 static void intel_pmu_disable_all(void)
1248 {
1249         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1250
1251         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1252
1253         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1254                 intel_pmu_disable_bts();
1255         else
1256                 intel_bts_disable_local();
1257
1258         intel_pmu_pebs_disable_all();
1259         intel_pmu_lbr_disable_all();
1260 }
1261
1262 static void intel_pmu_enable_all(int added)
1263 {
1264         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1265
1266         intel_pmu_pebs_enable_all();
1267         intel_pmu_lbr_enable_all();
1268         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1269                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1270
1271         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1272                 struct perf_event *event =
1273                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1274
1275                 if (WARN_ON_ONCE(!event))
1276                         return;
1277
1278                 intel_pmu_enable_bts(event->hw.config);
1279         } else
1280                 intel_bts_enable_local();
1281 }
1282
1283 /*
1284  * Workaround for:
1285  *   Intel Errata AAK100 (model 26)
1286  *   Intel Errata AAP53  (model 30)
1287  *   Intel Errata BD53   (model 44)
1288  *
1289  * The official story:
1290  *   These chips need to be 'reset' when adding counters by programming the
1291  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1292  *   in sequence on the same PMC or on different PMCs.
1293  *
1294  * In practise it appears some of these events do in fact count, and
1295  * we need to programm all 4 events.
1296  */
1297 static void intel_pmu_nhm_workaround(void)
1298 {
1299         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1300         static const unsigned long nhm_magic[4] = {
1301                 0x4300B5,
1302                 0x4300D2,
1303                 0x4300B1,
1304                 0x4300B1
1305         };
1306         struct perf_event *event;
1307         int i;
1308
1309         /*
1310          * The Errata requires below steps:
1311          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1312          * 2) Configure 4 PERFEVTSELx with the magic events and clear
1313          *    the corresponding PMCx;
1314          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1315          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1316          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1317          */
1318
1319         /*
1320          * The real steps we choose are a little different from above.
1321          * A) To reduce MSR operations, we don't run step 1) as they
1322          *    are already cleared before this function is called;
1323          * B) Call x86_perf_event_update to save PMCx before configuring
1324          *    PERFEVTSELx with magic number;
1325          * C) With step 5), we do clear only when the PERFEVTSELx is
1326          *    not used currently.
1327          * D) Call x86_perf_event_set_period to restore PMCx;
1328          */
1329
1330         /* We always operate 4 pairs of PERF Counters */
1331         for (i = 0; i < 4; i++) {
1332                 event = cpuc->events[i];
1333                 if (event)
1334                         x86_perf_event_update(event);
1335         }
1336
1337         for (i = 0; i < 4; i++) {
1338                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1339                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1340         }
1341
1342         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1343         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1344
1345         for (i = 0; i < 4; i++) {
1346                 event = cpuc->events[i];
1347
1348                 if (event) {
1349                         x86_perf_event_set_period(event);
1350                         __x86_pmu_enable_event(&event->hw,
1351                                         ARCH_PERFMON_EVENTSEL_ENABLE);
1352                 } else
1353                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1354         }
1355 }
1356
1357 static void intel_pmu_nhm_enable_all(int added)
1358 {
1359         if (added)
1360                 intel_pmu_nhm_workaround();
1361         intel_pmu_enable_all(added);
1362 }
1363
1364 static inline u64 intel_pmu_get_status(void)
1365 {
1366         u64 status;
1367
1368         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1369
1370         return status;
1371 }
1372
1373 static inline void intel_pmu_ack_status(u64 ack)
1374 {
1375         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1376 }
1377
1378 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1379 {
1380         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1381         u64 ctrl_val, mask;
1382
1383         mask = 0xfULL << (idx * 4);
1384
1385         rdmsrl(hwc->config_base, ctrl_val);
1386         ctrl_val &= ~mask;
1387         wrmsrl(hwc->config_base, ctrl_val);
1388 }
1389
1390 static inline bool event_is_checkpointed(struct perf_event *event)
1391 {
1392         return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1393 }
1394
1395 static void intel_pmu_disable_event(struct perf_event *event)
1396 {
1397         struct hw_perf_event *hwc = &event->hw;
1398         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1399
1400         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1401                 intel_pmu_disable_bts();
1402                 intel_pmu_drain_bts_buffer();
1403                 return;
1404         }
1405
1406         cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1407         cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1408         cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1409
1410         /*
1411          * must disable before any actual event
1412          * because any event may be combined with LBR
1413          */
1414         if (needs_branch_stack(event))
1415                 intel_pmu_lbr_disable(event);
1416
1417         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1418                 intel_pmu_disable_fixed(hwc);
1419                 return;
1420         }
1421
1422         x86_pmu_disable_event(event);
1423
1424         if (unlikely(event->attr.precise_ip))
1425                 intel_pmu_pebs_disable(event);
1426 }
1427
1428 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1429 {
1430         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1431         u64 ctrl_val, bits, mask;
1432
1433         /*
1434          * Enable IRQ generation (0x8),
1435          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1436          * if requested:
1437          */
1438         bits = 0x8ULL;
1439         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1440                 bits |= 0x2;
1441         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1442                 bits |= 0x1;
1443
1444         /*
1445          * ANY bit is supported in v3 and up
1446          */
1447         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1448                 bits |= 0x4;
1449
1450         bits <<= (idx * 4);
1451         mask = 0xfULL << (idx * 4);
1452
1453         rdmsrl(hwc->config_base, ctrl_val);
1454         ctrl_val &= ~mask;
1455         ctrl_val |= bits;
1456         wrmsrl(hwc->config_base, ctrl_val);
1457 }
1458
1459 static void intel_pmu_enable_event(struct perf_event *event)
1460 {
1461         struct hw_perf_event *hwc = &event->hw;
1462         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1463
1464         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1465                 if (!__this_cpu_read(cpu_hw_events.enabled))
1466                         return;
1467
1468                 intel_pmu_enable_bts(hwc->config);
1469                 return;
1470         }
1471         /*
1472          * must enabled before any actual event
1473          * because any event may be combined with LBR
1474          */
1475         if (needs_branch_stack(event))
1476                 intel_pmu_lbr_enable(event);
1477
1478         if (event->attr.exclude_host)
1479                 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1480         if (event->attr.exclude_guest)
1481                 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1482
1483         if (unlikely(event_is_checkpointed(event)))
1484                 cpuc->intel_cp_status |= (1ull << hwc->idx);
1485
1486         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1487                 intel_pmu_enable_fixed(hwc);
1488                 return;
1489         }
1490
1491         if (unlikely(event->attr.precise_ip))
1492                 intel_pmu_pebs_enable(event);
1493
1494         __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1495 }
1496
1497 /*
1498  * Save and restart an expired event. Called by NMI contexts,
1499  * so it has to be careful about preempting normal event ops:
1500  */
1501 int intel_pmu_save_and_restart(struct perf_event *event)
1502 {
1503         x86_perf_event_update(event);
1504         /*
1505          * For a checkpointed counter always reset back to 0.  This
1506          * avoids a situation where the counter overflows, aborts the
1507          * transaction and is then set back to shortly before the
1508          * overflow, and overflows and aborts again.
1509          */
1510         if (unlikely(event_is_checkpointed(event))) {
1511                 /* No race with NMIs because the counter should not be armed */
1512                 wrmsrl(event->hw.event_base, 0);
1513                 local64_set(&event->hw.prev_count, 0);
1514         }
1515         return x86_perf_event_set_period(event);
1516 }
1517
1518 static void intel_pmu_reset(void)
1519 {
1520         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1521         unsigned long flags;
1522         int idx;
1523
1524         if (!x86_pmu.num_counters)
1525                 return;
1526
1527         local_irq_save(flags);
1528
1529         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1530
1531         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1532                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1533                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
1534         }
1535         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1536                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1537
1538         if (ds)
1539                 ds->bts_index = ds->bts_buffer_base;
1540
1541         local_irq_restore(flags);
1542 }
1543
1544 /*
1545  * This handler is triggered by the local APIC, so the APIC IRQ handling
1546  * rules apply:
1547  */
1548 static int intel_pmu_handle_irq(struct pt_regs *regs)
1549 {
1550         struct perf_sample_data data;
1551         struct cpu_hw_events *cpuc;
1552         int bit, loops;
1553         u64 status;
1554         int handled;
1555
1556         cpuc = this_cpu_ptr(&cpu_hw_events);
1557
1558         /*
1559          * No known reason to not always do late ACK,
1560          * but just in case do it opt-in.
1561          */
1562         if (!x86_pmu.late_ack)
1563                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1564         intel_pmu_disable_all();
1565         handled = intel_pmu_drain_bts_buffer();
1566         handled += intel_bts_interrupt();
1567         status = intel_pmu_get_status();
1568         if (!status)
1569                 goto done;
1570
1571         loops = 0;
1572 again:
1573         intel_pmu_ack_status(status);
1574         if (++loops > 100) {
1575                 static bool warned = false;
1576                 if (!warned) {
1577                         WARN(1, "perfevents: irq loop stuck!\n");
1578                         perf_event_print_debug();
1579                         warned = true;
1580                 }
1581                 intel_pmu_reset();
1582                 goto done;
1583         }
1584
1585         inc_irq_stat(apic_perf_irqs);
1586
1587         intel_pmu_lbr_read();
1588
1589         /*
1590          * CondChgd bit 63 doesn't mean any overflow status. Ignore
1591          * and clear the bit.
1592          */
1593         if (__test_and_clear_bit(63, (unsigned long *)&status)) {
1594                 if (!status)
1595                         goto done;
1596         }
1597
1598         /*
1599          * PEBS overflow sets bit 62 in the global status register
1600          */
1601         if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1602                 handled++;
1603                 x86_pmu.drain_pebs(regs);
1604         }
1605
1606         /*
1607          * Intel PT
1608          */
1609         if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1610                 handled++;
1611                 intel_pt_interrupt();
1612         }
1613
1614         /*
1615          * Checkpointed counters can lead to 'spurious' PMIs because the
1616          * rollback caused by the PMI will have cleared the overflow status
1617          * bit. Therefore always force probe these counters.
1618          */
1619         status |= cpuc->intel_cp_status;
1620
1621         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1622                 struct perf_event *event = cpuc->events[bit];
1623
1624                 handled++;
1625
1626                 if (!test_bit(bit, cpuc->active_mask))
1627                         continue;
1628
1629                 if (!intel_pmu_save_and_restart(event))
1630                         continue;
1631
1632                 perf_sample_data_init(&data, 0, event->hw.last_period);
1633
1634                 if (has_branch_stack(event))
1635                         data.br_stack = &cpuc->lbr_stack;
1636
1637                 if (perf_event_overflow(event, &data, regs))
1638                         x86_pmu_stop(event, 0);
1639         }
1640
1641         /*
1642          * Repeat if there is more work to be done:
1643          */
1644         status = intel_pmu_get_status();
1645         if (status)
1646                 goto again;
1647
1648 done:
1649         intel_pmu_enable_all(0);
1650         /*
1651          * Only unmask the NMI after the overflow counters
1652          * have been reset. This avoids spurious NMIs on
1653          * Haswell CPUs.
1654          */
1655         if (x86_pmu.late_ack)
1656                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1657         return handled;
1658 }
1659
1660 static struct event_constraint *
1661 intel_bts_constraints(struct perf_event *event)
1662 {
1663         struct hw_perf_event *hwc = &event->hw;
1664         unsigned int hw_event, bts_event;
1665
1666         if (event->attr.freq)
1667                 return NULL;
1668
1669         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1670         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1671
1672         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1673                 return &bts_constraint;
1674
1675         return NULL;
1676 }
1677
1678 static int intel_alt_er(int idx)
1679 {
1680         if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
1681                 return idx;
1682
1683         if (idx == EXTRA_REG_RSP_0)
1684                 return EXTRA_REG_RSP_1;
1685
1686         if (idx == EXTRA_REG_RSP_1)
1687                 return EXTRA_REG_RSP_0;
1688
1689         return idx;
1690 }
1691
1692 static void intel_fixup_er(struct perf_event *event, int idx)
1693 {
1694         event->hw.extra_reg.idx = idx;
1695
1696         if (idx == EXTRA_REG_RSP_0) {
1697                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1698                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
1699                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1700         } else if (idx == EXTRA_REG_RSP_1) {
1701                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1702                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
1703                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1704         }
1705 }
1706
1707 /*
1708  * manage allocation of shared extra msr for certain events
1709  *
1710  * sharing can be:
1711  * per-cpu: to be shared between the various events on a single PMU
1712  * per-core: per-cpu + shared by HT threads
1713  */
1714 static struct event_constraint *
1715 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1716                                    struct perf_event *event,
1717                                    struct hw_perf_event_extra *reg)
1718 {
1719         struct event_constraint *c = &emptyconstraint;
1720         struct er_account *era;
1721         unsigned long flags;
1722         int idx = reg->idx;
1723
1724         /*
1725          * reg->alloc can be set due to existing state, so for fake cpuc we
1726          * need to ignore this, otherwise we might fail to allocate proper fake
1727          * state for this extra reg constraint. Also see the comment below.
1728          */
1729         if (reg->alloc && !cpuc->is_fake)
1730                 return NULL; /* call x86_get_event_constraint() */
1731
1732 again:
1733         era = &cpuc->shared_regs->regs[idx];
1734         /*
1735          * we use spin_lock_irqsave() to avoid lockdep issues when
1736          * passing a fake cpuc
1737          */
1738         raw_spin_lock_irqsave(&era->lock, flags);
1739
1740         if (!atomic_read(&era->ref) || era->config == reg->config) {
1741
1742                 /*
1743                  * If its a fake cpuc -- as per validate_{group,event}() we
1744                  * shouldn't touch event state and we can avoid doing so
1745                  * since both will only call get_event_constraints() once
1746                  * on each event, this avoids the need for reg->alloc.
1747                  *
1748                  * Not doing the ER fixup will only result in era->reg being
1749                  * wrong, but since we won't actually try and program hardware
1750                  * this isn't a problem either.
1751                  */
1752                 if (!cpuc->is_fake) {
1753                         if (idx != reg->idx)
1754                                 intel_fixup_er(event, idx);
1755
1756                         /*
1757                          * x86_schedule_events() can call get_event_constraints()
1758                          * multiple times on events in the case of incremental
1759                          * scheduling(). reg->alloc ensures we only do the ER
1760                          * allocation once.
1761                          */
1762                         reg->alloc = 1;
1763                 }
1764
1765                 /* lock in msr value */
1766                 era->config = reg->config;
1767                 era->reg = reg->reg;
1768
1769                 /* one more user */
1770                 atomic_inc(&era->ref);
1771
1772                 /*
1773                  * need to call x86_get_event_constraint()
1774                  * to check if associated event has constraints
1775                  */
1776                 c = NULL;
1777         } else {
1778                 idx = intel_alt_er(idx);
1779                 if (idx != reg->idx) {
1780                         raw_spin_unlock_irqrestore(&era->lock, flags);
1781                         goto again;
1782                 }
1783         }
1784         raw_spin_unlock_irqrestore(&era->lock, flags);
1785
1786         return c;
1787 }
1788
1789 static void
1790 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1791                                    struct hw_perf_event_extra *reg)
1792 {
1793         struct er_account *era;
1794
1795         /*
1796          * Only put constraint if extra reg was actually allocated. Also takes
1797          * care of event which do not use an extra shared reg.
1798          *
1799          * Also, if this is a fake cpuc we shouldn't touch any event state
1800          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1801          * either since it'll be thrown out.
1802          */
1803         if (!reg->alloc || cpuc->is_fake)
1804                 return;
1805
1806         era = &cpuc->shared_regs->regs[reg->idx];
1807
1808         /* one fewer user */
1809         atomic_dec(&era->ref);
1810
1811         /* allocate again next time */
1812         reg->alloc = 0;
1813 }
1814
1815 static struct event_constraint *
1816 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1817                               struct perf_event *event)
1818 {
1819         struct event_constraint *c = NULL, *d;
1820         struct hw_perf_event_extra *xreg, *breg;
1821
1822         xreg = &event->hw.extra_reg;
1823         if (xreg->idx != EXTRA_REG_NONE) {
1824                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1825                 if (c == &emptyconstraint)
1826                         return c;
1827         }
1828         breg = &event->hw.branch_reg;
1829         if (breg->idx != EXTRA_REG_NONE) {
1830                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1831                 if (d == &emptyconstraint) {
1832                         __intel_shared_reg_put_constraints(cpuc, xreg);
1833                         c = d;
1834                 }
1835         }
1836         return c;
1837 }
1838
1839 struct event_constraint *
1840 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1841                           struct perf_event *event)
1842 {
1843         struct event_constraint *c;
1844
1845         if (x86_pmu.event_constraints) {
1846                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1847                         if ((event->hw.config & c->cmask) == c->code) {
1848                                 event->hw.flags |= c->flags;
1849                                 return c;
1850                         }
1851                 }
1852         }
1853
1854         return &unconstrained;
1855 }
1856
1857 static struct event_constraint *
1858 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1859                             struct perf_event *event)
1860 {
1861         struct event_constraint *c;
1862
1863         c = intel_bts_constraints(event);
1864         if (c)
1865                 return c;
1866
1867         c = intel_shared_regs_constraints(cpuc, event);
1868         if (c)
1869                 return c;
1870
1871         c = intel_pebs_constraints(event);
1872         if (c)
1873                 return c;
1874
1875         return x86_get_event_constraints(cpuc, idx, event);
1876 }
1877
1878 static void
1879 intel_start_scheduling(struct cpu_hw_events *cpuc)
1880 {
1881         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1882         struct intel_excl_states *xl, *xlo;
1883         int tid = cpuc->excl_thread_id;
1884         int o_tid = 1 - tid; /* sibling thread */
1885
1886         /*
1887          * nothing needed if in group validation mode
1888          */
1889         if (cpuc->is_fake || !is_ht_workaround_enabled())
1890                 return;
1891
1892         /*
1893          * no exclusion needed
1894          */
1895         if (!excl_cntrs)
1896                 return;
1897
1898         xlo = &excl_cntrs->states[o_tid];
1899         xl = &excl_cntrs->states[tid];
1900
1901         xl->sched_started = true;
1902         xl->num_alloc_cntrs = 0;
1903         /*
1904          * lock shared state until we are done scheduling
1905          * in stop_event_scheduling()
1906          * makes scheduling appear as a transaction
1907          */
1908         WARN_ON_ONCE(!irqs_disabled());
1909         raw_spin_lock(&excl_cntrs->lock);
1910
1911         /*
1912          * save initial state of sibling thread
1913          */
1914         memcpy(xlo->init_state, xlo->state, sizeof(xlo->init_state));
1915 }
1916
1917 static void
1918 intel_stop_scheduling(struct cpu_hw_events *cpuc)
1919 {
1920         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1921         struct intel_excl_states *xl, *xlo;
1922         int tid = cpuc->excl_thread_id;
1923         int o_tid = 1 - tid; /* sibling thread */
1924
1925         /*
1926          * nothing needed if in group validation mode
1927          */
1928         if (cpuc->is_fake || !is_ht_workaround_enabled())
1929                 return;
1930         /*
1931          * no exclusion needed
1932          */
1933         if (!excl_cntrs)
1934                 return;
1935
1936         xlo = &excl_cntrs->states[o_tid];
1937         xl = &excl_cntrs->states[tid];
1938
1939         /*
1940          * make new sibling thread state visible
1941          */
1942         memcpy(xlo->state, xlo->init_state, sizeof(xlo->state));
1943
1944         xl->sched_started = false;
1945         /*
1946          * release shared state lock (acquired in intel_start_scheduling())
1947          */
1948         raw_spin_unlock(&excl_cntrs->lock);
1949 }
1950
1951 static struct event_constraint *
1952 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
1953                            int idx, struct event_constraint *c)
1954 {
1955         struct event_constraint *cx;
1956         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1957         struct intel_excl_states *xl, *xlo;
1958         int is_excl, i;
1959         int tid = cpuc->excl_thread_id;
1960         int o_tid = 1 - tid; /* alternate */
1961
1962         /*
1963          * validating a group does not require
1964          * enforcing cross-thread  exclusion
1965          */
1966         if (cpuc->is_fake || !is_ht_workaround_enabled())
1967                 return c;
1968
1969         /*
1970          * no exclusion needed
1971          */
1972         if (!excl_cntrs)
1973                 return c;
1974         /*
1975          * event requires exclusive counter access
1976          * across HT threads
1977          */
1978         is_excl = c->flags & PERF_X86_EVENT_EXCL;
1979
1980         /*
1981          * xl = state of current HT
1982          * xlo = state of sibling HT
1983          */
1984         xl = &excl_cntrs->states[tid];
1985         xlo = &excl_cntrs->states[o_tid];
1986
1987         /*
1988          * do not allow scheduling of more than max_alloc_cntrs
1989          * which is set to half the available generic counters.
1990          * this helps avoid counter starvation of sibling thread
1991          * by ensuring at most half the counters cannot be in
1992          * exclusive mode. There is not designated counters for the
1993          * limits. Any N/2 counters can be used. This helps with
1994          * events with specifix counter constraints
1995          */
1996         if (xl->num_alloc_cntrs++ == xl->max_alloc_cntrs)
1997                 return &emptyconstraint;
1998
1999         cx = c;
2000
2001         /*
2002          * because we modify the constraint, we need
2003          * to make a copy. Static constraints come
2004          * from static const tables.
2005          *
2006          * only needed when constraint has not yet
2007          * been cloned (marked dynamic)
2008          */
2009         if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2010
2011                 /* sanity check */
2012                 if (idx < 0)
2013                         return &emptyconstraint;
2014
2015                 /*
2016                  * grab pre-allocated constraint entry
2017                  */
2018                 cx = &cpuc->constraint_list[idx];
2019
2020                 /*
2021                  * initialize dynamic constraint
2022                  * with static constraint
2023                  */
2024                 memcpy(cx, c, sizeof(*cx));
2025
2026                 /*
2027                  * mark constraint as dynamic, so we
2028                  * can free it later on
2029                  */
2030                 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2031         }
2032
2033         /*
2034          * From here on, the constraint is dynamic.
2035          * Either it was just allocated above, or it
2036          * was allocated during a earlier invocation
2037          * of this function
2038          */
2039
2040         /*
2041          * Modify static constraint with current dynamic
2042          * state of thread
2043          *
2044          * EXCLUSIVE: sibling counter measuring exclusive event
2045          * SHARED   : sibling counter measuring non-exclusive event
2046          * UNUSED   : sibling counter unused
2047          */
2048         for_each_set_bit(i, cx->idxmsk, X86_PMC_IDX_MAX) {
2049                 /*
2050                  * exclusive event in sibling counter
2051                  * our corresponding counter cannot be used
2052                  * regardless of our event
2053                  */
2054                 if (xl->state[i] == INTEL_EXCL_EXCLUSIVE)
2055                         __clear_bit(i, cx->idxmsk);
2056                 /*
2057                  * if measuring an exclusive event, sibling
2058                  * measuring non-exclusive, then counter cannot
2059                  * be used
2060                  */
2061                 if (is_excl && xl->state[i] == INTEL_EXCL_SHARED)
2062                         __clear_bit(i, cx->idxmsk);
2063         }
2064
2065         /*
2066          * recompute actual bit weight for scheduling algorithm
2067          */
2068         cx->weight = hweight64(cx->idxmsk64);
2069
2070         /*
2071          * if we return an empty mask, then switch
2072          * back to static empty constraint to avoid
2073          * the cost of freeing later on
2074          */
2075         if (cx->weight == 0)
2076                 cx = &emptyconstraint;
2077
2078         return cx;
2079 }
2080
2081 static struct event_constraint *
2082 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2083                             struct perf_event *event)
2084 {
2085         struct event_constraint *c1 = event->hw.constraint;
2086         struct event_constraint *c2;
2087
2088         /*
2089          * first time only
2090          * - static constraint: no change across incremental scheduling calls
2091          * - dynamic constraint: handled by intel_get_excl_constraints()
2092          */
2093         c2 = __intel_get_event_constraints(cpuc, idx, event);
2094         if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2095                 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2096                 c1->weight = c2->weight;
2097                 c2 = c1;
2098         }
2099
2100         if (cpuc->excl_cntrs)
2101                 return intel_get_excl_constraints(cpuc, event, idx, c2);
2102
2103         return c2;
2104 }
2105
2106 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2107                 struct perf_event *event)
2108 {
2109         struct hw_perf_event *hwc = &event->hw;
2110         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2111         struct intel_excl_states *xlo, *xl;
2112         unsigned long flags = 0; /* keep compiler happy */
2113         int tid = cpuc->excl_thread_id;
2114         int o_tid = 1 - tid;
2115
2116         /*
2117          * nothing needed if in group validation mode
2118          */
2119         if (cpuc->is_fake)
2120                 return;
2121
2122         WARN_ON_ONCE(!excl_cntrs);
2123
2124         if (!excl_cntrs)
2125                 return;
2126
2127         xl = &excl_cntrs->states[tid];
2128         xlo = &excl_cntrs->states[o_tid];
2129
2130         /*
2131          * put_constraint may be called from x86_schedule_events()
2132          * which already has the lock held so here make locking
2133          * conditional
2134          */
2135         if (!xl->sched_started)
2136                 raw_spin_lock_irqsave(&excl_cntrs->lock, flags);
2137
2138         /*
2139          * if event was actually assigned, then mark the
2140          * counter state as unused now
2141          */
2142         if (hwc->idx >= 0)
2143                 xlo->state[hwc->idx] = INTEL_EXCL_UNUSED;
2144
2145         if (!xl->sched_started)
2146                 raw_spin_unlock_irqrestore(&excl_cntrs->lock, flags);
2147 }
2148
2149 static void
2150 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2151                                         struct perf_event *event)
2152 {
2153         struct hw_perf_event_extra *reg;
2154
2155         reg = &event->hw.extra_reg;
2156         if (reg->idx != EXTRA_REG_NONE)
2157                 __intel_shared_reg_put_constraints(cpuc, reg);
2158
2159         reg = &event->hw.branch_reg;
2160         if (reg->idx != EXTRA_REG_NONE)
2161                 __intel_shared_reg_put_constraints(cpuc, reg);
2162 }
2163
2164 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2165                                         struct perf_event *event)
2166 {
2167         struct event_constraint *c = event->hw.constraint;
2168
2169         intel_put_shared_regs_event_constraints(cpuc, event);
2170
2171         /*
2172          * is PMU has exclusive counter restrictions, then
2173          * all events are subject to and must call the
2174          * put_excl_constraints() routine
2175          */
2176         if (c && cpuc->excl_cntrs)
2177                 intel_put_excl_constraints(cpuc, event);
2178
2179         /* cleanup dynamic constraint */
2180         if (c && (c->flags & PERF_X86_EVENT_DYNAMIC))
2181                 event->hw.constraint = NULL;
2182 }
2183
2184 static void intel_commit_scheduling(struct cpu_hw_events *cpuc,
2185                                     struct perf_event *event, int cntr)
2186 {
2187         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2188         struct event_constraint *c = event->hw.constraint;
2189         struct intel_excl_states *xlo, *xl;
2190         int tid = cpuc->excl_thread_id;
2191         int o_tid = 1 - tid;
2192         int is_excl;
2193
2194         if (cpuc->is_fake || !c)
2195                 return;
2196
2197         is_excl = c->flags & PERF_X86_EVENT_EXCL;
2198
2199         if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2200                 return;
2201
2202         WARN_ON_ONCE(!excl_cntrs);
2203
2204         if (!excl_cntrs)
2205                 return;
2206
2207         xl = &excl_cntrs->states[tid];
2208         xlo = &excl_cntrs->states[o_tid];
2209
2210         WARN_ON_ONCE(!raw_spin_is_locked(&excl_cntrs->lock));
2211
2212         if (cntr >= 0) {
2213                 if (is_excl)
2214                         xlo->init_state[cntr] = INTEL_EXCL_EXCLUSIVE;
2215                 else
2216                         xlo->init_state[cntr] = INTEL_EXCL_SHARED;
2217         }
2218 }
2219
2220 static void intel_pebs_aliases_core2(struct perf_event *event)
2221 {
2222         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2223                 /*
2224                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2225                  * (0x003c) so that we can use it with PEBS.
2226                  *
2227                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2228                  * PEBS capable. However we can use INST_RETIRED.ANY_P
2229                  * (0x00c0), which is a PEBS capable event, to get the same
2230                  * count.
2231                  *
2232                  * INST_RETIRED.ANY_P counts the number of cycles that retires
2233                  * CNTMASK instructions. By setting CNTMASK to a value (16)
2234                  * larger than the maximum number of instructions that can be
2235                  * retired per cycle (4) and then inverting the condition, we
2236                  * count all cycles that retire 16 or less instructions, which
2237                  * is every cycle.
2238                  *
2239                  * Thereby we gain a PEBS capable cycle counter.
2240                  */
2241                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2242
2243                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2244                 event->hw.config = alt_config;
2245         }
2246 }
2247
2248 static void intel_pebs_aliases_snb(struct perf_event *event)
2249 {
2250         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2251                 /*
2252                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2253                  * (0x003c) so that we can use it with PEBS.
2254                  *
2255                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2256                  * PEBS capable. However we can use UOPS_RETIRED.ALL
2257                  * (0x01c2), which is a PEBS capable event, to get the same
2258                  * count.
2259                  *
2260                  * UOPS_RETIRED.ALL counts the number of cycles that retires
2261                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2262                  * larger than the maximum number of micro-ops that can be
2263                  * retired per cycle (4) and then inverting the condition, we
2264                  * count all cycles that retire 16 or less micro-ops, which
2265                  * is every cycle.
2266                  *
2267                  * Thereby we gain a PEBS capable cycle counter.
2268                  */
2269                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
2270
2271                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2272                 event->hw.config = alt_config;
2273         }
2274 }
2275
2276 static int intel_pmu_hw_config(struct perf_event *event)
2277 {
2278         int ret = x86_pmu_hw_config(event);
2279
2280         if (ret)
2281                 return ret;
2282
2283         if (event->attr.precise_ip && x86_pmu.pebs_aliases)
2284                 x86_pmu.pebs_aliases(event);
2285
2286         if (needs_branch_stack(event)) {
2287                 ret = intel_pmu_setup_lbr_filter(event);
2288                 if (ret)
2289                         return ret;
2290
2291                 /*
2292                  * BTS is set up earlier in this path, so don't account twice
2293                  */
2294                 if (!intel_pmu_has_bts(event)) {
2295                         /* disallow lbr if conflicting events are present */
2296                         if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2297                                 return -EBUSY;
2298
2299                         event->destroy = hw_perf_lbr_event_destroy;
2300                 }
2301         }
2302
2303         if (event->attr.type != PERF_TYPE_RAW)
2304                 return 0;
2305
2306         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2307                 return 0;
2308
2309         if (x86_pmu.version < 3)
2310                 return -EINVAL;
2311
2312         if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2313                 return -EACCES;
2314
2315         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2316
2317         return 0;
2318 }
2319
2320 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2321 {
2322         if (x86_pmu.guest_get_msrs)
2323                 return x86_pmu.guest_get_msrs(nr);
2324         *nr = 0;
2325         return NULL;
2326 }
2327 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2328
2329 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2330 {
2331         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2332         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2333
2334         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2335         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2336         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
2337         /*
2338          * If PMU counter has PEBS enabled it is not enough to disable counter
2339          * on a guest entry since PEBS memory write can overshoot guest entry
2340          * and corrupt guest memory. Disabling PEBS solves the problem.
2341          */
2342         arr[1].msr = MSR_IA32_PEBS_ENABLE;
2343         arr[1].host = cpuc->pebs_enabled;
2344         arr[1].guest = 0;
2345
2346         *nr = 2;
2347         return arr;
2348 }
2349
2350 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2351 {
2352         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2353         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2354         int idx;
2355
2356         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
2357                 struct perf_event *event = cpuc->events[idx];
2358
2359                 arr[idx].msr = x86_pmu_config_addr(idx);
2360                 arr[idx].host = arr[idx].guest = 0;
2361
2362                 if (!test_bit(idx, cpuc->active_mask))
2363                         continue;
2364
2365                 arr[idx].host = arr[idx].guest =
2366                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2367
2368                 if (event->attr.exclude_host)
2369                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2370                 else if (event->attr.exclude_guest)
2371                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2372         }
2373
2374         *nr = x86_pmu.num_counters;
2375         return arr;
2376 }
2377
2378 static void core_pmu_enable_event(struct perf_event *event)
2379 {
2380         if (!event->attr.exclude_host)
2381                 x86_pmu_enable_event(event);
2382 }
2383
2384 static void core_pmu_enable_all(int added)
2385 {
2386         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2387         int idx;
2388
2389         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2390                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2391
2392                 if (!test_bit(idx, cpuc->active_mask) ||
2393                                 cpuc->events[idx]->attr.exclude_host)
2394                         continue;
2395
2396                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2397         }
2398 }
2399
2400 static int hsw_hw_config(struct perf_event *event)
2401 {
2402         int ret = intel_pmu_hw_config(event);
2403
2404         if (ret)
2405                 return ret;
2406         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2407                 return 0;
2408         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2409
2410         /*
2411          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2412          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2413          * this combination.
2414          */
2415         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2416              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2417               event->attr.precise_ip > 0))
2418                 return -EOPNOTSUPP;
2419
2420         if (event_is_checkpointed(event)) {
2421                 /*
2422                  * Sampling of checkpointed events can cause situations where
2423                  * the CPU constantly aborts because of a overflow, which is
2424                  * then checkpointed back and ignored. Forbid checkpointing
2425                  * for sampling.
2426                  *
2427                  * But still allow a long sampling period, so that perf stat
2428                  * from KVM works.
2429                  */
2430                 if (event->attr.sample_period > 0 &&
2431                     event->attr.sample_period < 0x7fffffff)
2432                         return -EOPNOTSUPP;
2433         }
2434         return 0;
2435 }
2436
2437 static struct event_constraint counter2_constraint =
2438                         EVENT_CONSTRAINT(0, 0x4, 0);
2439
2440 static struct event_constraint *
2441 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2442                           struct perf_event *event)
2443 {
2444         struct event_constraint *c;
2445
2446         c = intel_get_event_constraints(cpuc, idx, event);
2447
2448         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2449         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2450                 if (c->idxmsk64 & (1U << 2))
2451                         return &counter2_constraint;
2452                 return &emptyconstraint;
2453         }
2454
2455         return c;
2456 }
2457
2458 /*
2459  * Broadwell:
2460  *
2461  * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2462  * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2463  * the two to enforce a minimum period of 128 (the smallest value that has bits
2464  * 0-5 cleared and >= 100).
2465  *
2466  * Because of how the code in x86_perf_event_set_period() works, the truncation
2467  * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2468  * to make up for the 'lost' events due to carrying the 'error' in period_left.
2469  *
2470  * Therefore the effective (average) period matches the requested period,
2471  * despite coarser hardware granularity.
2472  */
2473 static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2474 {
2475         if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2476                         X86_CONFIG(.event=0xc0, .umask=0x01)) {
2477                 if (left < 128)
2478                         left = 128;
2479                 left &= ~0x3fu;
2480         }
2481         return left;
2482 }
2483
2484 PMU_FORMAT_ATTR(event,  "config:0-7"    );
2485 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
2486 PMU_FORMAT_ATTR(edge,   "config:18"     );
2487 PMU_FORMAT_ATTR(pc,     "config:19"     );
2488 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
2489 PMU_FORMAT_ATTR(inv,    "config:23"     );
2490 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
2491 PMU_FORMAT_ATTR(in_tx,  "config:32");
2492 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
2493
2494 static struct attribute *intel_arch_formats_attr[] = {
2495         &format_attr_event.attr,
2496         &format_attr_umask.attr,
2497         &format_attr_edge.attr,
2498         &format_attr_pc.attr,
2499         &format_attr_inv.attr,
2500         &format_attr_cmask.attr,
2501         NULL,
2502 };
2503
2504 ssize_t intel_event_sysfs_show(char *page, u64 config)
2505 {
2506         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2507
2508         return x86_event_sysfs_show(page, config, event);
2509 }
2510
2511 static __initconst const struct x86_pmu core_pmu = {
2512         .name                   = "core",
2513         .handle_irq             = x86_pmu_handle_irq,
2514         .disable_all            = x86_pmu_disable_all,
2515         .enable_all             = core_pmu_enable_all,
2516         .enable                 = core_pmu_enable_event,
2517         .disable                = x86_pmu_disable_event,
2518         .hw_config              = x86_pmu_hw_config,
2519         .schedule_events        = x86_schedule_events,
2520         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
2521         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
2522         .event_map              = intel_pmu_event_map,
2523         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
2524         .apic                   = 1,
2525         /*
2526          * Intel PMCs cannot be accessed sanely above 32 bit width,
2527          * so we install an artificial 1<<31 period regardless of
2528          * the generic event period:
2529          */
2530         .max_period             = (1ULL << 31) - 1,
2531         .get_event_constraints  = intel_get_event_constraints,
2532         .put_event_constraints  = intel_put_event_constraints,
2533         .event_constraints      = intel_core_event_constraints,
2534         .guest_get_msrs         = core_guest_get_msrs,
2535         .format_attrs           = intel_arch_formats_attr,
2536         .events_sysfs_show      = intel_event_sysfs_show,
2537 };
2538
2539 struct intel_shared_regs *allocate_shared_regs(int cpu)
2540 {
2541         struct intel_shared_regs *regs;
2542         int i;
2543
2544         regs = kzalloc_node(sizeof(struct intel_shared_regs),
2545                             GFP_KERNEL, cpu_to_node(cpu));
2546         if (regs) {
2547                 /*
2548                  * initialize the locks to keep lockdep happy
2549                  */
2550                 for (i = 0; i < EXTRA_REG_MAX; i++)
2551                         raw_spin_lock_init(&regs->regs[i].lock);
2552
2553                 regs->core_id = -1;
2554         }
2555         return regs;
2556 }
2557
2558 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2559 {
2560         struct intel_excl_cntrs *c;
2561         int i;
2562
2563         c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2564                          GFP_KERNEL, cpu_to_node(cpu));
2565         if (c) {
2566                 raw_spin_lock_init(&c->lock);
2567                 for (i = 0; i < X86_PMC_IDX_MAX; i++) {
2568                         c->states[0].state[i] = INTEL_EXCL_UNUSED;
2569                         c->states[0].init_state[i] = INTEL_EXCL_UNUSED;
2570
2571                         c->states[1].state[i] = INTEL_EXCL_UNUSED;
2572                         c->states[1].init_state[i] = INTEL_EXCL_UNUSED;
2573                 }
2574                 c->core_id = -1;
2575         }
2576         return c;
2577 }
2578
2579 static int intel_pmu_cpu_prepare(int cpu)
2580 {
2581         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2582
2583         if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2584                 cpuc->shared_regs = allocate_shared_regs(cpu);
2585                 if (!cpuc->shared_regs)
2586                         return NOTIFY_BAD;
2587         }
2588
2589         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2590                 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2591
2592                 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2593                 if (!cpuc->constraint_list)
2594                         return NOTIFY_BAD;
2595
2596                 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
2597                 if (!cpuc->excl_cntrs) {
2598                         kfree(cpuc->constraint_list);
2599                         kfree(cpuc->shared_regs);
2600                         return NOTIFY_BAD;
2601                 }
2602                 cpuc->excl_thread_id = 0;
2603         }
2604
2605         return NOTIFY_OK;
2606 }
2607
2608 static void intel_pmu_cpu_starting(int cpu)
2609 {
2610         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2611         int core_id = topology_core_id(cpu);
2612         int i;
2613
2614         init_debug_store_on_cpu(cpu);
2615         /*
2616          * Deal with CPUs that don't clear their LBRs on power-up.
2617          */
2618         intel_pmu_lbr_reset();
2619
2620         cpuc->lbr_sel = NULL;
2621
2622         if (!cpuc->shared_regs)
2623                 return;
2624
2625         if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
2626                 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
2627
2628                 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2629                         struct intel_shared_regs *pc;
2630
2631                         pc = per_cpu(cpu_hw_events, i).shared_regs;
2632                         if (pc && pc->core_id == core_id) {
2633                                 *onln = cpuc->shared_regs;
2634                                 cpuc->shared_regs = pc;
2635                                 break;
2636                         }
2637                 }
2638                 cpuc->shared_regs->core_id = core_id;
2639                 cpuc->shared_regs->refcnt++;
2640         }
2641
2642         if (x86_pmu.lbr_sel_map)
2643                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
2644
2645         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2646                 int h = x86_pmu.num_counters >> 1;
2647
2648                 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2649                         struct intel_excl_cntrs *c;
2650
2651                         c = per_cpu(cpu_hw_events, i).excl_cntrs;
2652                         if (c && c->core_id == core_id) {
2653                                 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2654                                 cpuc->excl_cntrs = c;
2655                                 cpuc->excl_thread_id = 1;
2656                                 break;
2657                         }
2658                 }
2659                 cpuc->excl_cntrs->core_id = core_id;
2660                 cpuc->excl_cntrs->refcnt++;
2661                 /*
2662                  * set hard limit to half the number of generic counters
2663                  */
2664                 cpuc->excl_cntrs->states[0].max_alloc_cntrs = h;
2665                 cpuc->excl_cntrs->states[1].max_alloc_cntrs = h;
2666         }
2667 }
2668
2669 static void free_excl_cntrs(int cpu)
2670 {
2671         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2672         struct intel_excl_cntrs *c;
2673
2674         c = cpuc->excl_cntrs;
2675         if (c) {
2676                 if (c->core_id == -1 || --c->refcnt == 0)
2677                         kfree(c);
2678                 cpuc->excl_cntrs = NULL;
2679                 kfree(cpuc->constraint_list);
2680                 cpuc->constraint_list = NULL;
2681         }
2682 }
2683
2684 static void intel_pmu_cpu_dying(int cpu)
2685 {
2686         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2687         struct intel_shared_regs *pc;
2688
2689         pc = cpuc->shared_regs;
2690         if (pc) {
2691                 if (pc->core_id == -1 || --pc->refcnt == 0)
2692                         kfree(pc);
2693                 cpuc->shared_regs = NULL;
2694         }
2695
2696         free_excl_cntrs(cpu);
2697
2698         fini_debug_store_on_cpu(cpu);
2699 }
2700
2701 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2702
2703 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2704
2705 static struct attribute *intel_arch3_formats_attr[] = {
2706         &format_attr_event.attr,
2707         &format_attr_umask.attr,
2708         &format_attr_edge.attr,
2709         &format_attr_pc.attr,
2710         &format_attr_any.attr,
2711         &format_attr_inv.attr,
2712         &format_attr_cmask.attr,
2713         &format_attr_in_tx.attr,
2714         &format_attr_in_tx_cp.attr,
2715
2716         &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
2717         &format_attr_ldlat.attr, /* PEBS load latency */
2718         NULL,
2719 };
2720
2721 static __initconst const struct x86_pmu intel_pmu = {
2722         .name                   = "Intel",
2723         .handle_irq             = intel_pmu_handle_irq,
2724         .disable_all            = intel_pmu_disable_all,
2725         .enable_all             = intel_pmu_enable_all,
2726         .enable                 = intel_pmu_enable_event,
2727         .disable                = intel_pmu_disable_event,
2728         .hw_config              = intel_pmu_hw_config,
2729         .schedule_events        = x86_schedule_events,
2730         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
2731         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
2732         .event_map              = intel_pmu_event_map,
2733         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
2734         .apic                   = 1,
2735         /*
2736          * Intel PMCs cannot be accessed sanely above 32 bit width,
2737          * so we install an artificial 1<<31 period regardless of
2738          * the generic event period:
2739          */
2740         .max_period             = (1ULL << 31) - 1,
2741         .get_event_constraints  = intel_get_event_constraints,
2742         .put_event_constraints  = intel_put_event_constraints,
2743         .pebs_aliases           = intel_pebs_aliases_core2,
2744
2745         .format_attrs           = intel_arch3_formats_attr,
2746         .events_sysfs_show      = intel_event_sysfs_show,
2747
2748         .cpu_prepare            = intel_pmu_cpu_prepare,
2749         .cpu_starting           = intel_pmu_cpu_starting,
2750         .cpu_dying              = intel_pmu_cpu_dying,
2751         .guest_get_msrs         = intel_guest_get_msrs,
2752         .sched_task             = intel_pmu_lbr_sched_task,
2753 };
2754
2755 static __init void intel_clovertown_quirk(void)
2756 {
2757         /*
2758          * PEBS is unreliable due to:
2759          *
2760          *   AJ67  - PEBS may experience CPL leaks
2761          *   AJ68  - PEBS PMI may be delayed by one event
2762          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2763          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2764          *
2765          * AJ67 could be worked around by restricting the OS/USR flags.
2766          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2767          *
2768          * AJ106 could possibly be worked around by not allowing LBR
2769          *       usage from PEBS, including the fixup.
2770          * AJ68  could possibly be worked around by always programming
2771          *       a pebs_event_reset[0] value and coping with the lost events.
2772          *
2773          * But taken together it might just make sense to not enable PEBS on
2774          * these chips.
2775          */
2776         pr_warn("PEBS disabled due to CPU errata\n");
2777         x86_pmu.pebs = 0;
2778         x86_pmu.pebs_constraints = NULL;
2779 }
2780
2781 static int intel_snb_pebs_broken(int cpu)
2782 {
2783         u32 rev = UINT_MAX; /* default to broken for unknown models */
2784
2785         switch (cpu_data(cpu).x86_model) {
2786         case 42: /* SNB */
2787                 rev = 0x28;
2788                 break;
2789
2790         case 45: /* SNB-EP */
2791                 switch (cpu_data(cpu).x86_mask) {
2792                 case 6: rev = 0x618; break;
2793                 case 7: rev = 0x70c; break;
2794                 }
2795         }
2796
2797         return (cpu_data(cpu).microcode < rev);
2798 }
2799
2800 static void intel_snb_check_microcode(void)
2801 {
2802         int pebs_broken = 0;
2803         int cpu;
2804
2805         get_online_cpus();
2806         for_each_online_cpu(cpu) {
2807                 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2808                         break;
2809         }
2810         put_online_cpus();
2811
2812         if (pebs_broken == x86_pmu.pebs_broken)
2813                 return;
2814
2815         /*
2816          * Serialized by the microcode lock..
2817          */
2818         if (x86_pmu.pebs_broken) {
2819                 pr_info("PEBS enabled due to microcode update\n");
2820                 x86_pmu.pebs_broken = 0;
2821         } else {
2822                 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2823                 x86_pmu.pebs_broken = 1;
2824         }
2825 }
2826
2827 /*
2828  * Under certain circumstances, access certain MSR may cause #GP.
2829  * The function tests if the input MSR can be safely accessed.
2830  */
2831 static bool check_msr(unsigned long msr, u64 mask)
2832 {
2833         u64 val_old, val_new, val_tmp;
2834
2835         /*
2836          * Read the current value, change it and read it back to see if it
2837          * matches, this is needed to detect certain hardware emulators
2838          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
2839          */
2840         if (rdmsrl_safe(msr, &val_old))
2841                 return false;
2842
2843         /*
2844          * Only change the bits which can be updated by wrmsrl.
2845          */
2846         val_tmp = val_old ^ mask;
2847         if (wrmsrl_safe(msr, val_tmp) ||
2848             rdmsrl_safe(msr, &val_new))
2849                 return false;
2850
2851         if (val_new != val_tmp)
2852                 return false;
2853
2854         /* Here it's sure that the MSR can be safely accessed.
2855          * Restore the old value and return.
2856          */
2857         wrmsrl(msr, val_old);
2858
2859         return true;
2860 }
2861
2862 static __init void intel_sandybridge_quirk(void)
2863 {
2864         x86_pmu.check_microcode = intel_snb_check_microcode;
2865         intel_snb_check_microcode();
2866 }
2867
2868 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2869         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2870         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2871         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2872         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2873         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2874         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2875         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
2876 };
2877
2878 static __init void intel_arch_events_quirk(void)
2879 {
2880         int bit;
2881
2882         /* disable event that reported as not presend by cpuid */
2883         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2884                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
2885                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2886                         intel_arch_events_map[bit].name);
2887         }
2888 }
2889
2890 static __init void intel_nehalem_quirk(void)
2891 {
2892         union cpuid10_ebx ebx;
2893
2894         ebx.full = x86_pmu.events_maskl;
2895         if (ebx.split.no_branch_misses_retired) {
2896                 /*
2897                  * Erratum AAJ80 detected, we work it around by using
2898                  * the BR_MISP_EXEC.ANY event. This will over-count
2899                  * branch-misses, but it's still much better than the
2900                  * architectural event which is often completely bogus:
2901                  */
2902                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2903                 ebx.split.no_branch_misses_retired = 0;
2904                 x86_pmu.events_maskl = ebx.full;
2905                 pr_info("CPU erratum AAJ80 worked around\n");
2906         }
2907 }
2908
2909 /*
2910  * enable software workaround for errata:
2911  * SNB: BJ122
2912  * IVB: BV98
2913  * HSW: HSD29
2914  *
2915  * Only needed when HT is enabled. However detecting
2916  * if HT is enabled is difficult (model specific). So instead,
2917  * we enable the workaround in the early boot, and verify if
2918  * it is needed in a later initcall phase once we have valid
2919  * topology information to check if HT is actually enabled
2920  */
2921 static __init void intel_ht_bug(void)
2922 {
2923         x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
2924
2925         x86_pmu.commit_scheduling = intel_commit_scheduling;
2926         x86_pmu.start_scheduling = intel_start_scheduling;
2927         x86_pmu.stop_scheduling = intel_stop_scheduling;
2928 }
2929
2930 EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
2931 EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
2932
2933 /* Haswell special events */
2934 EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
2935 EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
2936 EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
2937 EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
2938 EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
2939 EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
2940 EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
2941 EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
2942 EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
2943 EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
2944 EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
2945 EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
2946
2947 static struct attribute *hsw_events_attrs[] = {
2948         EVENT_PTR(tx_start),
2949         EVENT_PTR(tx_commit),
2950         EVENT_PTR(tx_abort),
2951         EVENT_PTR(tx_capacity),
2952         EVENT_PTR(tx_conflict),
2953         EVENT_PTR(el_start),
2954         EVENT_PTR(el_commit),
2955         EVENT_PTR(el_abort),
2956         EVENT_PTR(el_capacity),
2957         EVENT_PTR(el_conflict),
2958         EVENT_PTR(cycles_t),
2959         EVENT_PTR(cycles_ct),
2960         EVENT_PTR(mem_ld_hsw),
2961         EVENT_PTR(mem_st_hsw),
2962         NULL
2963 };
2964
2965 __init int intel_pmu_init(void)
2966 {
2967         union cpuid10_edx edx;
2968         union cpuid10_eax eax;
2969         union cpuid10_ebx ebx;
2970         struct event_constraint *c;
2971         unsigned int unused;
2972         struct extra_reg *er;
2973         int version, i;
2974
2975         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2976                 switch (boot_cpu_data.x86) {
2977                 case 0x6:
2978                         return p6_pmu_init();
2979                 case 0xb:
2980                         return knc_pmu_init();
2981                 case 0xf:
2982                         return p4_pmu_init();
2983                 }
2984                 return -ENODEV;
2985         }
2986
2987         /*
2988          * Check whether the Architectural PerfMon supports
2989          * Branch Misses Retired hw_event or not.
2990          */
2991         cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2992         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
2993                 return -ENODEV;
2994
2995         version = eax.split.version_id;
2996         if (version < 2)
2997                 x86_pmu = core_pmu;
2998         else
2999                 x86_pmu = intel_pmu;
3000
3001         x86_pmu.version                 = version;
3002         x86_pmu.num_counters            = eax.split.num_counters;
3003         x86_pmu.cntval_bits             = eax.split.bit_width;
3004         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
3005
3006         x86_pmu.events_maskl            = ebx.full;
3007         x86_pmu.events_mask_len         = eax.split.mask_length;
3008
3009         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3010
3011         /*
3012          * Quirk: v2 perfmon does not report fixed-purpose events, so
3013          * assume at least 3 events:
3014          */
3015         if (version > 1)
3016                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
3017
3018         if (boot_cpu_has(X86_FEATURE_PDCM)) {
3019                 u64 capabilities;
3020
3021                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3022                 x86_pmu.intel_cap.capabilities = capabilities;
3023         }
3024
3025         intel_ds_init();
3026
3027         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3028
3029         /*
3030          * Install the hw-cache-events table:
3031          */
3032         switch (boot_cpu_data.x86_model) {
3033         case 14: /* 65nm Core "Yonah" */
3034                 pr_cont("Core events, ");
3035                 break;
3036
3037         case 15: /* 65nm Core2 "Merom"          */
3038                 x86_add_quirk(intel_clovertown_quirk);
3039         case 22: /* 65nm Core2 "Merom-L"        */
3040         case 23: /* 45nm Core2 "Penryn"         */
3041         case 29: /* 45nm Core2 "Dunnington (MP) */
3042                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3043                        sizeof(hw_cache_event_ids));
3044
3045                 intel_pmu_lbr_init_core();
3046
3047                 x86_pmu.event_constraints = intel_core2_event_constraints;
3048                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
3049                 pr_cont("Core2 events, ");
3050                 break;
3051
3052         case 30: /* 45nm Nehalem    */
3053         case 26: /* 45nm Nehalem-EP */
3054         case 46: /* 45nm Nehalem-EX */
3055                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3056                        sizeof(hw_cache_event_ids));
3057                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3058                        sizeof(hw_cache_extra_regs));
3059
3060                 intel_pmu_lbr_init_nhm();
3061
3062                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
3063                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
3064                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3065                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
3066
3067                 x86_pmu.cpu_events = nhm_events_attrs;
3068
3069                 /* UOPS_ISSUED.STALLED_CYCLES */
3070                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3071                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3072                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3073                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3074                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3075
3076                 x86_add_quirk(intel_nehalem_quirk);
3077
3078                 pr_cont("Nehalem events, ");
3079                 break;
3080
3081         case 28: /* 45nm Atom "Pineview"   */
3082         case 38: /* 45nm Atom "Lincroft"   */
3083         case 39: /* 32nm Atom "Penwell"    */
3084         case 53: /* 32nm Atom "Cloverview" */
3085         case 54: /* 32nm Atom "Cedarview"  */
3086                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3087                        sizeof(hw_cache_event_ids));
3088
3089                 intel_pmu_lbr_init_atom();
3090
3091                 x86_pmu.event_constraints = intel_gen_event_constraints;
3092                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
3093                 pr_cont("Atom events, ");
3094                 break;
3095
3096         case 55: /* 22nm Atom "Silvermont"                */
3097         case 76: /* 14nm Atom "Airmont"                   */
3098         case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
3099                 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3100                         sizeof(hw_cache_event_ids));
3101                 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3102                        sizeof(hw_cache_extra_regs));
3103
3104                 intel_pmu_lbr_init_atom();
3105
3106                 x86_pmu.event_constraints = intel_slm_event_constraints;
3107                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3108                 x86_pmu.extra_regs = intel_slm_extra_regs;
3109                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3110                 pr_cont("Silvermont events, ");
3111                 break;
3112
3113         case 37: /* 32nm Westmere    */
3114         case 44: /* 32nm Westmere-EP */
3115         case 47: /* 32nm Westmere-EX */
3116                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3117                        sizeof(hw_cache_event_ids));
3118                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3119                        sizeof(hw_cache_extra_regs));
3120
3121                 intel_pmu_lbr_init_nhm();
3122
3123                 x86_pmu.event_constraints = intel_westmere_event_constraints;
3124                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3125                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
3126                 x86_pmu.extra_regs = intel_westmere_extra_regs;
3127                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3128
3129                 x86_pmu.cpu_events = nhm_events_attrs;
3130
3131                 /* UOPS_ISSUED.STALLED_CYCLES */
3132                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3133                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3134                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3135                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3136                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3137
3138                 pr_cont("Westmere events, ");
3139                 break;
3140
3141         case 42: /* 32nm SandyBridge         */
3142         case 45: /* 32nm SandyBridge-E/EN/EP */
3143                 x86_add_quirk(intel_sandybridge_quirk);
3144                 x86_add_quirk(intel_ht_bug);
3145                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3146                        sizeof(hw_cache_event_ids));
3147                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3148                        sizeof(hw_cache_extra_regs));
3149
3150                 intel_pmu_lbr_init_snb();
3151
3152                 x86_pmu.event_constraints = intel_snb_event_constraints;
3153                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
3154                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3155                 if (boot_cpu_data.x86_model == 45)
3156                         x86_pmu.extra_regs = intel_snbep_extra_regs;
3157                 else
3158                         x86_pmu.extra_regs = intel_snb_extra_regs;
3159
3160
3161                 /* all extra regs are per-cpu when HT is on */
3162                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3163                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3164
3165                 x86_pmu.cpu_events = snb_events_attrs;
3166
3167                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3168                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3169                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3170                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
3171                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3172                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
3173
3174                 pr_cont("SandyBridge events, ");
3175                 break;
3176
3177         case 58: /* 22nm IvyBridge       */
3178         case 62: /* 22nm IvyBridge-EP/EX */
3179                 x86_add_quirk(intel_ht_bug);
3180                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3181                        sizeof(hw_cache_event_ids));
3182                 /* dTLB-load-misses on IVB is different than SNB */
3183                 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3184
3185                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3186                        sizeof(hw_cache_extra_regs));
3187
3188                 intel_pmu_lbr_init_snb();
3189
3190                 x86_pmu.event_constraints = intel_ivb_event_constraints;
3191                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3192                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3193                 if (boot_cpu_data.x86_model == 62)
3194                         x86_pmu.extra_regs = intel_snbep_extra_regs;
3195                 else
3196                         x86_pmu.extra_regs = intel_snb_extra_regs;
3197                 /* all extra regs are per-cpu when HT is on */
3198                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3199                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3200
3201                 x86_pmu.cpu_events = snb_events_attrs;
3202
3203                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3204                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3205                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3206
3207                 pr_cont("IvyBridge events, ");
3208                 break;
3209
3210
3211         case 60: /* 22nm Haswell Core */
3212         case 63: /* 22nm Haswell Server */
3213         case 69: /* 22nm Haswell ULT */
3214         case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
3215                 x86_add_quirk(intel_ht_bug);
3216                 x86_pmu.late_ack = true;
3217                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3218                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3219
3220                 intel_pmu_lbr_init_hsw();
3221
3222                 x86_pmu.event_constraints = intel_hsw_event_constraints;
3223                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3224                 x86_pmu.extra_regs = intel_snbep_extra_regs;
3225                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3226                 /* all extra regs are per-cpu when HT is on */
3227                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3228                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3229
3230                 x86_pmu.hw_config = hsw_hw_config;
3231                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3232                 x86_pmu.cpu_events = hsw_events_attrs;
3233                 x86_pmu.lbr_double_abort = true;
3234                 pr_cont("Haswell events, ");
3235                 break;
3236
3237         case 61: /* 14nm Broadwell Core-M */
3238         case 86: /* 14nm Broadwell Xeon D */
3239                 x86_pmu.late_ack = true;
3240                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3241                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3242
3243                 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3244                 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3245                                                                          BDW_L3_MISS|HSW_SNOOP_DRAM;
3246                 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3247                                                                           HSW_SNOOP_DRAM;
3248                 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3249                                                                              BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3250                 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3251                                                                               BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3252
3253                 intel_pmu_lbr_init_snb();
3254
3255                 x86_pmu.event_constraints = intel_bdw_event_constraints;
3256                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3257                 x86_pmu.extra_regs = intel_snbep_extra_regs;
3258                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3259                 /* all extra regs are per-cpu when HT is on */
3260                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3261                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3262
3263                 x86_pmu.hw_config = hsw_hw_config;
3264                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3265                 x86_pmu.cpu_events = hsw_events_attrs;
3266                 x86_pmu.limit_period = bdw_limit_period;
3267                 pr_cont("Broadwell events, ");
3268                 break;
3269
3270         default:
3271                 switch (x86_pmu.version) {
3272                 case 1:
3273                         x86_pmu.event_constraints = intel_v1_event_constraints;
3274                         pr_cont("generic architected perfmon v1, ");
3275                         break;
3276                 default:
3277                         /*
3278                          * default constraints for v2 and up
3279                          */
3280                         x86_pmu.event_constraints = intel_gen_event_constraints;
3281                         pr_cont("generic architected perfmon, ");
3282                         break;
3283                 }
3284         }
3285
3286         if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3287                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3288                      x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3289                 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3290         }
3291         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3292
3293         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3294                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3295                      x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3296                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3297         }
3298
3299         x86_pmu.intel_ctrl |=
3300                 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3301
3302         if (x86_pmu.event_constraints) {
3303                 /*
3304                  * event on fixed counter2 (REF_CYCLES) only works on this
3305                  * counter, so do not extend mask to generic counters
3306                  */
3307                 for_each_event_constraint(c, x86_pmu.event_constraints) {
3308                         if (c->cmask != FIXED_EVENT_FLAGS
3309                             || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3310                                 continue;
3311                         }
3312
3313                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
3314                         c->weight += x86_pmu.num_counters;
3315                 }
3316         }
3317
3318         /*
3319          * Access LBR MSR may cause #GP under certain circumstances.
3320          * E.g. KVM doesn't support LBR MSR
3321          * Check all LBT MSR here.
3322          * Disable LBR access if any LBR MSRs can not be accessed.
3323          */
3324         if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3325                 x86_pmu.lbr_nr = 0;
3326         for (i = 0; i < x86_pmu.lbr_nr; i++) {
3327                 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3328                       check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3329                         x86_pmu.lbr_nr = 0;
3330         }
3331
3332         /*
3333          * Access extra MSR may cause #GP under certain circumstances.
3334          * E.g. KVM doesn't support offcore event
3335          * Check all extra_regs here.
3336          */
3337         if (x86_pmu.extra_regs) {
3338                 for (er = x86_pmu.extra_regs; er->msr; er++) {
3339                         er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
3340                         /* Disable LBR select mapping */
3341                         if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3342                                 x86_pmu.lbr_sel_map = NULL;
3343                 }
3344         }
3345
3346         /* Support full width counters using alternative MSR range */
3347         if (x86_pmu.intel_cap.full_width_write) {
3348                 x86_pmu.max_period = x86_pmu.cntval_mask;
3349                 x86_pmu.perfctr = MSR_IA32_PMC0;
3350                 pr_cont("full-width counters, ");
3351         }
3352
3353         return 0;
3354 }
3355
3356 /*
3357  * HT bug: phase 2 init
3358  * Called once we have valid topology information to check
3359  * whether or not HT is enabled
3360  * If HT is off, then we disable the workaround
3361  */
3362 static __init int fixup_ht_bug(void)
3363 {
3364         int cpu = smp_processor_id();
3365         int w, c;
3366         /*
3367          * problem not present on this CPU model, nothing to do
3368          */
3369         if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3370                 return 0;
3371
3372         w = cpumask_weight(topology_thread_cpumask(cpu));
3373         if (w > 1) {
3374                 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3375                 return 0;
3376         }
3377
3378         watchdog_nmi_disable_all();
3379
3380         x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3381
3382         x86_pmu.commit_scheduling = NULL;
3383         x86_pmu.start_scheduling = NULL;
3384         x86_pmu.stop_scheduling = NULL;
3385
3386         watchdog_nmi_enable_all();
3387
3388         get_online_cpus();
3389
3390         for_each_online_cpu(c) {
3391                 free_excl_cntrs(c);
3392         }
3393
3394         put_online_cpus();
3395         pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3396         return 0;
3397 }
3398 subsys_initcall(fixup_ht_bug)