1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
5 #include <asm/perf_event.h>
8 #include "perf_event.h"
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE PAGE_SIZE
17 * pebs_record_32 for p4 and core not supported
19 struct pebs_record_32 {
27 union intel_x86_pebs_dse {
30 unsigned int ld_dse:4;
31 unsigned int ld_stlb_miss:1;
32 unsigned int ld_locked:1;
33 unsigned int ld_reserved:26;
36 unsigned int st_l1d_hit:1;
37 unsigned int st_reserved1:3;
38 unsigned int st_stlb_miss:1;
39 unsigned int st_locked:1;
40 unsigned int st_reserved2:26;
46 * Map PEBS Load Latency Data Source encodings to generic
47 * memory data source information
49 #define P(a, b) PERF_MEM_S(a, b)
50 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
51 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53 static const u64 pebs_data_source[] = {
54 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
55 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
56 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
57 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
58 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
59 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
60 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
62 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
63 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
64 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
65 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
66 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
67 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
68 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
69 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
72 static u64 precise_store_data(u64 status)
74 union intel_x86_pebs_dse dse;
75 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
81 * 1 = stored missed 2nd level TLB
83 * so it either hit the walker or the OS
84 * otherwise hit 2nd level TLB
92 * bit 0: hit L1 data cache
93 * if not set, then all we know is that
102 * bit 5: Locked prefix
105 val |= P(LOCK, LOCKED);
110 static u64 precise_store_data_hsw(u64 status)
112 union perf_mem_data_src dse;
115 dse.mem_op = PERF_MEM_OP_STORE;
116 dse.mem_lvl = PERF_MEM_LVL_NA;
118 dse.mem_lvl = PERF_MEM_LVL_L1;
119 /* Nothing else supported. Sorry. */
123 static u64 load_latency_data(u64 status)
125 union intel_x86_pebs_dse dse;
127 int model = boot_cpu_data.x86_model;
128 int fam = boot_cpu_data.x86;
133 * use the mapping table for bit 0-3
135 val = pebs_data_source[dse.ld_dse];
138 * Nehalem models do not support TLB, Lock infos
140 if (fam == 0x6 && (model == 26 || model == 30
141 || model == 31 || model == 46)) {
142 val |= P(TLB, NA) | P(LOCK, NA);
147 * 0 = did not miss 2nd level TLB
148 * 1 = missed 2nd level TLB
150 if (dse.ld_stlb_miss)
151 val |= P(TLB, MISS) | P(TLB, L2);
153 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
156 * bit 5: locked prefix
159 val |= P(LOCK, LOCKED);
164 struct pebs_record_core {
168 u64 r8, r9, r10, r11;
169 u64 r12, r13, r14, r15;
172 struct pebs_record_nhm {
176 u64 r8, r9, r10, r11;
177 u64 r12, r13, r14, r15;
178 u64 status, dla, dse, lat;
182 * Same as pebs_record_nhm, with two additional fields.
184 struct pebs_record_hsw {
188 u64 r8, r9, r10, r11;
189 u64 r12, r13, r14, r15;
190 u64 status, dla, dse, lat;
191 u64 real_ip, tsx_tuning;
194 union hsw_tsx_tuning {
196 u32 cycles_last_block : 32,
199 instruction_abort : 1,
200 non_instruction_abort : 1,
209 void init_debug_store_on_cpu(int cpu)
211 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
216 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
217 (u32)((u64)(unsigned long)ds),
218 (u32)((u64)(unsigned long)ds >> 32));
221 void fini_debug_store_on_cpu(int cpu)
223 if (!per_cpu(cpu_hw_events, cpu).ds)
226 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
229 static int alloc_pebs_buffer(int cpu)
231 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
232 int node = cpu_to_node(cpu);
233 int max, thresh = 1; /* always use a single PEBS record */
239 buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
240 if (unlikely(!buffer))
243 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
245 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
246 ds->pebs_index = ds->pebs_buffer_base;
247 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
248 max * x86_pmu.pebs_record_size;
250 ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
251 thresh * x86_pmu.pebs_record_size;
256 static void release_pebs_buffer(int cpu)
258 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
260 if (!ds || !x86_pmu.pebs)
263 kfree((void *)(unsigned long)ds->pebs_buffer_base);
264 ds->pebs_buffer_base = 0;
267 static int alloc_bts_buffer(int cpu)
269 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
270 int node = cpu_to_node(cpu);
277 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL, node);
278 if (unlikely(!buffer))
281 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
284 ds->bts_buffer_base = (u64)(unsigned long)buffer;
285 ds->bts_index = ds->bts_buffer_base;
286 ds->bts_absolute_maximum = ds->bts_buffer_base +
287 max * BTS_RECORD_SIZE;
288 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
289 thresh * BTS_RECORD_SIZE;
294 static void release_bts_buffer(int cpu)
296 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
298 if (!ds || !x86_pmu.bts)
301 kfree((void *)(unsigned long)ds->bts_buffer_base);
302 ds->bts_buffer_base = 0;
305 static int alloc_ds_buffer(int cpu)
307 int node = cpu_to_node(cpu);
308 struct debug_store *ds;
310 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
314 per_cpu(cpu_hw_events, cpu).ds = ds;
319 static void release_ds_buffer(int cpu)
321 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
326 per_cpu(cpu_hw_events, cpu).ds = NULL;
330 void release_ds_buffers(void)
334 if (!x86_pmu.bts && !x86_pmu.pebs)
338 for_each_online_cpu(cpu)
339 fini_debug_store_on_cpu(cpu);
341 for_each_possible_cpu(cpu) {
342 release_pebs_buffer(cpu);
343 release_bts_buffer(cpu);
344 release_ds_buffer(cpu);
349 void reserve_ds_buffers(void)
351 int bts_err = 0, pebs_err = 0;
354 x86_pmu.bts_active = 0;
355 x86_pmu.pebs_active = 0;
357 if (!x86_pmu.bts && !x86_pmu.pebs)
368 for_each_possible_cpu(cpu) {
369 if (alloc_ds_buffer(cpu)) {
374 if (!bts_err && alloc_bts_buffer(cpu))
377 if (!pebs_err && alloc_pebs_buffer(cpu))
380 if (bts_err && pebs_err)
385 for_each_possible_cpu(cpu)
386 release_bts_buffer(cpu);
390 for_each_possible_cpu(cpu)
391 release_pebs_buffer(cpu);
394 if (bts_err && pebs_err) {
395 for_each_possible_cpu(cpu)
396 release_ds_buffer(cpu);
398 if (x86_pmu.bts && !bts_err)
399 x86_pmu.bts_active = 1;
401 if (x86_pmu.pebs && !pebs_err)
402 x86_pmu.pebs_active = 1;
404 for_each_online_cpu(cpu)
405 init_debug_store_on_cpu(cpu);
415 struct event_constraint bts_constraint =
416 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
418 void intel_pmu_enable_bts(u64 config)
420 unsigned long debugctlmsr;
422 debugctlmsr = get_debugctlmsr();
424 debugctlmsr |= DEBUGCTLMSR_TR;
425 debugctlmsr |= DEBUGCTLMSR_BTS;
426 debugctlmsr |= DEBUGCTLMSR_BTINT;
428 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
429 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
431 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
432 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
434 update_debugctlmsr(debugctlmsr);
437 void intel_pmu_disable_bts(void)
439 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
440 unsigned long debugctlmsr;
445 debugctlmsr = get_debugctlmsr();
448 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
449 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
451 update_debugctlmsr(debugctlmsr);
454 int intel_pmu_drain_bts_buffer(void)
456 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
457 struct debug_store *ds = cpuc->ds;
463 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
464 struct bts_record *at, *top;
465 struct perf_output_handle handle;
466 struct perf_event_header header;
467 struct perf_sample_data data;
473 if (!x86_pmu.bts_active)
476 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
477 top = (struct bts_record *)(unsigned long)ds->bts_index;
482 memset(®s, 0, sizeof(regs));
484 ds->bts_index = ds->bts_buffer_base;
486 perf_sample_data_init(&data, 0, event->hw.last_period);
489 * Prepare a generic sample, i.e. fill in the invariant fields.
490 * We will overwrite the from and to address before we output
493 perf_prepare_sample(&header, &data, event, ®s);
495 if (perf_output_begin(&handle, event, header.size * (top - at)))
498 for (; at < top; at++) {
502 perf_output_sample(&handle, &header, &data, event);
505 perf_output_end(&handle);
507 /* There's new data available. */
508 event->hw.interrupts++;
509 event->pending_kill = POLL_IN;
516 struct event_constraint intel_core2_pebs_event_constraints[] = {
517 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
518 INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
519 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
520 INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
521 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
525 struct event_constraint intel_atom_pebs_event_constraints[] = {
526 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
527 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
528 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
532 struct event_constraint intel_slm_pebs_event_constraints[] = {
533 INTEL_UEVENT_CONSTRAINT(0x0103, 0x1), /* REHABQ.LD_BLOCK_ST_FORWARD_PS */
534 INTEL_UEVENT_CONSTRAINT(0x0803, 0x1), /* REHABQ.LD_SPLITS_PS */
535 INTEL_UEVENT_CONSTRAINT(0x0204, 0x1), /* MEM_UOPS_RETIRED.L2_HIT_LOADS_PS */
536 INTEL_UEVENT_CONSTRAINT(0x0404, 0x1), /* MEM_UOPS_RETIRED.L2_MISS_LOADS_PS */
537 INTEL_UEVENT_CONSTRAINT(0x0804, 0x1), /* MEM_UOPS_RETIRED.DTLB_MISS_LOADS_PS */
538 INTEL_UEVENT_CONSTRAINT(0x2004, 0x1), /* MEM_UOPS_RETIRED.HITM_PS */
539 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY_PS */
540 INTEL_UEVENT_CONSTRAINT(0x00c4, 0x1), /* BR_INST_RETIRED.ALL_BRANCHES_PS */
541 INTEL_UEVENT_CONSTRAINT(0x7ec4, 0x1), /* BR_INST_RETIRED.JCC_PS */
542 INTEL_UEVENT_CONSTRAINT(0xbfc4, 0x1), /* BR_INST_RETIRED.FAR_BRANCH_PS */
543 INTEL_UEVENT_CONSTRAINT(0xebc4, 0x1), /* BR_INST_RETIRED.NON_RETURN_IND_PS */
544 INTEL_UEVENT_CONSTRAINT(0xf7c4, 0x1), /* BR_INST_RETIRED.RETURN_PS */
545 INTEL_UEVENT_CONSTRAINT(0xf9c4, 0x1), /* BR_INST_RETIRED.CALL_PS */
546 INTEL_UEVENT_CONSTRAINT(0xfbc4, 0x1), /* BR_INST_RETIRED.IND_CALL_PS */
547 INTEL_UEVENT_CONSTRAINT(0xfdc4, 0x1), /* BR_INST_RETIRED.REL_CALL_PS */
548 INTEL_UEVENT_CONSTRAINT(0xfec4, 0x1), /* BR_INST_RETIRED.TAKEN_JCC_PS */
549 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_MISP_RETIRED.ALL_BRANCHES_PS */
550 INTEL_UEVENT_CONSTRAINT(0x7ec5, 0x1), /* BR_INST_MISP_RETIRED.JCC_PS */
551 INTEL_UEVENT_CONSTRAINT(0xebc5, 0x1), /* BR_INST_MISP_RETIRED.NON_RETURN_IND_PS */
552 INTEL_UEVENT_CONSTRAINT(0xf7c5, 0x1), /* BR_INST_MISP_RETIRED.RETURN_PS */
553 INTEL_UEVENT_CONSTRAINT(0xfbc5, 0x1), /* BR_INST_MISP_RETIRED.IND_CALL_PS */
554 INTEL_UEVENT_CONSTRAINT(0xfec5, 0x1), /* BR_INST_MISP_RETIRED.TAKEN_JCC_PS */
558 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
559 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
560 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
561 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
562 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
563 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
564 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
565 INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
566 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
567 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
568 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
569 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
573 struct event_constraint intel_westmere_pebs_event_constraints[] = {
574 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
575 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
576 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
577 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
578 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
579 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
580 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
581 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
582 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
583 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
584 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
588 struct event_constraint intel_snb_pebs_event_constraints[] = {
589 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
590 INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
591 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
592 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
593 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
594 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
595 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
596 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
597 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
598 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
599 INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
603 struct event_constraint intel_ivb_pebs_event_constraints[] = {
604 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
605 INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
606 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
607 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
608 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
609 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
610 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
611 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
612 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
613 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
614 INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
618 struct event_constraint intel_hsw_pebs_event_constraints[] = {
619 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
620 INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
621 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
622 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
623 INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
624 INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
625 INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
626 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.* */
627 /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
628 INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
629 /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
630 INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
631 INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
632 INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
633 /* MEM_UOPS_RETIRED.SPLIT_STORES */
634 INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
635 INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
636 INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
637 INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
638 INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
639 INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
640 /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
641 INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
642 /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
643 INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
644 /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
645 INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
646 /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
647 INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
648 INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
649 INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
654 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
656 struct event_constraint *c;
658 if (!event->attr.precise_ip)
661 if (x86_pmu.pebs_constraints) {
662 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
663 if ((event->hw.config & c->cmask) == c->code) {
664 event->hw.flags |= c->flags;
670 return &emptyconstraint;
673 void intel_pmu_pebs_enable(struct perf_event *event)
675 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
676 struct hw_perf_event *hwc = &event->hw;
678 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
680 cpuc->pebs_enabled |= 1ULL << hwc->idx;
682 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
683 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
684 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
685 cpuc->pebs_enabled |= 1ULL << 63;
688 void intel_pmu_pebs_disable(struct perf_event *event)
690 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
691 struct hw_perf_event *hwc = &event->hw;
693 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
695 if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
696 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
697 else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
698 cpuc->pebs_enabled &= ~(1ULL << 63);
701 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
703 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
706 void intel_pmu_pebs_enable_all(void)
708 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
710 if (cpuc->pebs_enabled)
711 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
714 void intel_pmu_pebs_disable_all(void)
716 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
718 if (cpuc->pebs_enabled)
719 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
722 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
724 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
725 unsigned long from = cpuc->lbr_entries[0].from;
726 unsigned long old_to, to = cpuc->lbr_entries[0].to;
727 unsigned long ip = regs->ip;
731 * We don't need to fixup if the PEBS assist is fault like
733 if (!x86_pmu.intel_cap.pebs_trap)
737 * No LBR entry, no basic block, no rewinding
739 if (!cpuc->lbr_stack.nr || !from || !to)
743 * Basic blocks should never cross user/kernel boundaries
745 if (kernel_ip(ip) != kernel_ip(to))
749 * unsigned math, either ip is before the start (impossible) or
750 * the basic block is larger than 1 page (sanity)
752 if ((ip - to) > PAGE_SIZE)
756 * We sampled a branch insn, rewind using the LBR stack
759 set_linear_ip(regs, from);
765 u8 buf[MAX_INSN_SIZE];
769 if (!kernel_ip(ip)) {
770 int bytes, size = MAX_INSN_SIZE;
772 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
781 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
783 insn_init(&insn, kaddr, is_64bit);
784 insn_get_length(&insn);
789 set_linear_ip(regs, old_to);
794 * Even though we decoded the basic block, the instruction stream
795 * never matched the given IP, either the TO or the IP got corrupted.
800 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
802 if (pebs->tsx_tuning) {
803 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
804 return tsx.cycles_last_block;
809 static void __intel_pmu_pebs_event(struct perf_event *event,
810 struct pt_regs *iregs, void *__pebs)
813 * We cast to the biggest pebs_record but are careful not to
814 * unconditionally access the 'extra' entries.
816 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
817 struct pebs_record_hsw *pebs = __pebs;
818 struct perf_sample_data data;
823 if (!intel_pmu_save_and_restart(event))
826 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
827 fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
828 PERF_X86_EVENT_PEBS_ST_HSW);
830 perf_sample_data_init(&data, 0, event->hw.last_period);
832 data.period = event->hw.last_period;
833 sample_type = event->attr.sample_type;
836 * if PEBS-LL or PreciseStore
840 * Use latency for weight (only avail with PEBS-LL)
842 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
843 data.weight = pebs->lat;
846 * data.data_src encodes the data source
848 if (sample_type & PERF_SAMPLE_DATA_SRC) {
850 data.data_src.val = load_latency_data(pebs->dse);
851 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
853 precise_store_data_hsw(pebs->dse);
855 data.data_src.val = precise_store_data(pebs->dse);
860 * We use the interrupt regs as a base because the PEBS record
861 * does not contain a full regs set, specifically it seems to
862 * lack segment descriptors, which get used by things like
865 * In the simple case fix up only the IP and BP,SP regs, for
866 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
867 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
870 regs.flags = pebs->flags;
871 set_linear_ip(®s, pebs->ip);
875 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
876 regs.ip = pebs->real_ip;
877 regs.flags |= PERF_EFLAGS_EXACT;
878 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
879 regs.flags |= PERF_EFLAGS_EXACT;
881 regs.flags &= ~PERF_EFLAGS_EXACT;
883 if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
884 x86_pmu.intel_cap.pebs_format >= 1)
885 data.addr = pebs->dla;
887 /* Only set the TSX weight when no memory weight was requested. */
888 if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll &&
889 (x86_pmu.intel_cap.pebs_format >= 2))
890 data.weight = intel_hsw_weight(pebs);
892 if (has_branch_stack(event))
893 data.br_stack = &cpuc->lbr_stack;
895 if (perf_event_overflow(event, &data, ®s))
896 x86_pmu_stop(event, 0);
899 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
901 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
902 struct debug_store *ds = cpuc->ds;
903 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
904 struct pebs_record_core *at, *top;
907 if (!x86_pmu.pebs_active)
910 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
911 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
914 * Whatever else happens, drain the thing
916 ds->pebs_index = ds->pebs_buffer_base;
918 if (!test_bit(0, cpuc->active_mask))
921 WARN_ON_ONCE(!event);
923 if (!event->attr.precise_ip)
931 * Should not happen, we program the threshold at 1 and do not
934 WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
937 __intel_pmu_pebs_event(event, iregs, at);
940 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
942 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
943 struct debug_store *ds = cpuc->ds;
944 struct perf_event *event = NULL;
949 if (!x86_pmu.pebs_active)
952 at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
953 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
955 ds->pebs_index = ds->pebs_buffer_base;
957 n = (top - at) / x86_pmu.pebs_record_size;
962 * Should not happen, we program the threshold at 1 and do not
965 WARN_ONCE(n > x86_pmu.max_pebs_events,
966 "Unexpected number of pebs records %d\n", n);
968 for (; at < top; at += x86_pmu.pebs_record_size) {
969 struct pebs_record_nhm *p = at;
971 for_each_set_bit(bit, (unsigned long *)&p->status,
972 x86_pmu.max_pebs_events) {
973 event = cpuc->events[bit];
974 if (!test_bit(bit, cpuc->active_mask))
977 WARN_ON_ONCE(!event);
979 if (!event->attr.precise_ip)
982 if (__test_and_set_bit(bit, (unsigned long *)&status))
988 if (!event || bit >= x86_pmu.max_pebs_events)
991 __intel_pmu_pebs_event(event, iregs, at);
996 * BTS, PEBS probe and setup
999 void intel_ds_init(void)
1002 * No support for 32bit formats
1004 if (!boot_cpu_has(X86_FEATURE_DTES64))
1007 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1008 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1010 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1011 int format = x86_pmu.intel_cap.pebs_format;
1015 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1016 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1017 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1021 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1022 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1023 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1027 pr_cont("PEBS fmt2%c, ", pebs_type);
1028 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1029 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1033 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1039 void perf_restore_debug_store(void)
1041 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1043 if (!x86_pmu.bts && !x86_pmu.pebs)
1046 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);