arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #ifdef CONFIG_CPU_SUP_INTEL
   2
   3 /* The maximal number of PEBS events: */
   4 #define MAX_PEBS_EVENTS         4
   5
   6 /* The size of a BTS record in bytes: */
   7 #define BTS_RECORD_SIZE         24
   8
   9 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  10 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  11
  12 /*
  13  * pebs_record_32 for p4 and core not supported
  14
  15 struct pebs_record_32 {
  16         u32 flags, ip;
  17         u32 ax, bc, cx, dx;
  18         u32 si, di, bp, sp;
  19 };
  20
  21  */
  22
  23 struct pebs_record_core {
  24         u64 flags, ip;
  25         u64 ax, bx, cx, dx;
  26         u64 si, di, bp, sp;
  27         u64 r8,  r9,  r10, r11;
  28         u64 r12, r13, r14, r15;
  29 };
  30
  31 struct pebs_record_nhm {
  32         u64 flags, ip;
  33         u64 ax, bx, cx, dx;
  34         u64 si, di, bp, sp;
  35         u64 r8,  r9,  r10, r11;
  36         u64 r12, r13, r14, r15;
  37         u64 status, dla, dse, lat;
  38 };
  39
  40 /*
  41  * Bits in the debugctlmsr controlling branch tracing.
  42  */
  43 #define X86_DEBUGCTL_TR                 (1 << 6)
  44 #define X86_DEBUGCTL_BTS                (1 << 7)
  45 #define X86_DEBUGCTL_BTINT              (1 << 8)
  46 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
  47 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
  48
  49 /*
  50  * A debug store configuration.
  51  *
  52  * We only support architectures that use 64bit fields.
  53  */
  54 struct debug_store {
  55         u64     bts_buffer_base;
  56         u64     bts_index;
  57         u64     bts_absolute_maximum;
  58         u64     bts_interrupt_threshold;
  59         u64     pebs_buffer_base;
  60         u64     pebs_index;
  61         u64     pebs_absolute_maximum;
  62         u64     pebs_interrupt_threshold;
  63         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  64 };
  65
  66 static void init_debug_store_on_cpu(int cpu)
  67 {
  68         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
  69
  70         if (!ds)
  71                 return;
  72
  73         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
  74                      (u32)((u64)(unsigned long)ds),
  75                      (u32)((u64)(unsigned long)ds >> 32));
  76 }
  77
  78 static void fini_debug_store_on_cpu(int cpu)
  79 {
  80         if (!per_cpu(cpu_hw_events, cpu).ds)
  81                 return;
  82
  83         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
  84 }
  85
  86 static void release_ds_buffers(void)
  87 {
  88         int cpu;
  89
  90         if (!x86_pmu.bts && !x86_pmu.pebs)
  91                 return;
  92
  93         get_online_cpus();
  94
  95         for_each_online_cpu(cpu)
  96                 fini_debug_store_on_cpu(cpu);
  97
  98         for_each_possible_cpu(cpu) {
  99                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 100
 101                 if (!ds)
 102                         continue;
 103
 104                 per_cpu(cpu_hw_events, cpu).ds = NULL;
 105
 106                 kfree((void *)(unsigned long)ds->pebs_buffer_base);
 107                 kfree((void *)(unsigned long)ds->bts_buffer_base);
 108                 kfree(ds);
 109         }
 110
 111         put_online_cpus();
 112 }
 113
 114 static int reserve_ds_buffers(void)
 115 {
 116         int cpu, err = 0;
 117
 118         if (!x86_pmu.bts && !x86_pmu.pebs)
 119                 return 0;
 120
 121         get_online_cpus();
 122
 123         for_each_possible_cpu(cpu) {
 124                 struct debug_store *ds;
 125                 void *buffer;
 126                 int max, thresh;
 127
 128                 err = -ENOMEM;
 129                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
 130                 if (unlikely(!ds)) {
 131                         kfree(buffer);
 132                         break;
 133                 }
 134                 per_cpu(cpu_hw_events, cpu).ds = ds;
 135
 136                 if (x86_pmu.bts) {
 137                         buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
 138                         if (unlikely(!buffer))
 139                                 break;
 140
 141                         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 142                         thresh = max / 16;
 143
 144                         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 145                         ds->bts_index = ds->bts_buffer_base;
 146                         ds->bts_absolute_maximum = ds->bts_buffer_base +
 147                                 max * BTS_RECORD_SIZE;
 148                         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 149                                 thresh * BTS_RECORD_SIZE;
 150                 }
 151
 152                 if (x86_pmu.pebs) {
 153                         buffer = kzalloc(PEBS_BUFFER_SIZE, GFP_KERNEL);
 154                         if (unlikely(!buffer))
 155                                 break;
 156
 157                         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 158
 159                         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 160                         ds->pebs_index = ds->pebs_buffer_base;
 161                         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 162                                 max * x86_pmu.pebs_record_size;
 163                         /*
 164                          * Always use single record PEBS
 165                          */
 166                         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
 167                                 x86_pmu.pebs_record_size;
 168                 }
 169
 170                 err = 0;
 171         }
 172
 173         if (err)
 174                 release_ds_buffers();
 175         else {
 176                 for_each_online_cpu(cpu)
 177                         init_debug_store_on_cpu(cpu);
 178         }
 179
 180         put_online_cpus();
 181
 182         return err;
 183 }
 184
 185 /*
 186  * BTS
 187  */
 188
 189 static struct event_constraint bts_constraint =
 190         EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
 191
 192 static void intel_pmu_enable_bts(u64 config)
 193 {
 194         unsigned long debugctlmsr;
 195
 196         debugctlmsr = get_debugctlmsr();
 197
 198         debugctlmsr |= X86_DEBUGCTL_TR;
 199         debugctlmsr |= X86_DEBUGCTL_BTS;
 200         debugctlmsr |= X86_DEBUGCTL_BTINT;
 201
 202         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 203                 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
 204
 205         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 206                 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
 207
 208         update_debugctlmsr(debugctlmsr);
 209 }
 210
 211 static void intel_pmu_disable_bts(void)
 212 {
 213         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 214         unsigned long debugctlmsr;
 215
 216         if (!cpuc->ds)
 217                 return;
 218
 219         debugctlmsr = get_debugctlmsr();
 220
 221         debugctlmsr &=
 222                 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
 223                   X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
 224
 225         update_debugctlmsr(debugctlmsr);
 226 }
 227
 228 static void intel_pmu_drain_bts_buffer(void)
 229 {
 230         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 231         struct debug_store *ds = cpuc->ds;
 232         struct bts_record {
 233                 u64     from;
 234                 u64     to;
 235                 u64     flags;
 236         };
 237         struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
 238         struct bts_record *at, *top;
 239         struct perf_output_handle handle;
 240         struct perf_event_header header;
 241         struct perf_sample_data data;
 242         struct pt_regs regs;
 243
 244         if (!event)
 245                 return;
 246
 247         if (!ds)
 248                 return;
 249
 250         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 251         top = (struct bts_record *)(unsigned long)ds->bts_index;
 252
 253         if (top <= at)
 254                 return;
 255
 256         ds->bts_index = ds->bts_buffer_base;
 257
 258         perf_sample_data_init(&data, 0);
 259         data.period = event->hw.last_period;
 260         regs.ip     = 0;
 261
 262         /*
 263          * Prepare a generic sample, i.e. fill in the invariant fields.
 264          * We will overwrite the from and to address before we output
 265          * the sample.
 266          */
 267         perf_prepare_sample(&header, &data, event, &regs);
 268
 269         if (perf_output_begin(&handle, event, header.size * (top - at), 1, 1))
 270                 return;
 271
 272         for (; at < top; at++) {
 273                 data.ip         = at->from;
 274                 data.addr       = at->to;
 275
 276                 perf_output_sample(&handle, &header, &data, event);
 277         }
 278
 279         perf_output_end(&handle);
 280
 281         /* There's new data available. */
 282         event->hw.interrupts++;
 283         event->pending_kill = POLL_IN;
 284 }
 285
 286 /*
 287  * PEBS
 288  */
 289
 290 static struct event_constraint intel_core_pebs_events[] = {
 291         PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
 292         PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 293         PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 294         PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 295         PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
 296         PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
 297         PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
 298         PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
 299         PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
 300         EVENT_CONSTRAINT_END
 301 };
 302
 303 static struct event_constraint intel_nehalem_pebs_events[] = {
 304         PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
 305         PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
 306         PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
 307         PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
 308         PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
 309         PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
 310         PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
 311         PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
 312         PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
 313         EVENT_CONSTRAINT_END
 314 };
 315
 316 static struct event_constraint *
 317 intel_pebs_constraints(struct perf_event *event)
 318 {
 319         struct event_constraint *c;
 320
 321         if (!event->attr.precise)
 322                 return NULL;
 323
 324         if (x86_pmu.pebs_constraints) {
 325                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 326                         if ((event->hw.config & c->cmask) == c->code)
 327                                 return c;
 328                 }
 329         }
 330
 331         return &emptyconstraint;
 332 }
 333
 334 static void intel_pmu_pebs_enable(struct perf_event *event)
 335 {
 336         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 337         struct hw_perf_event *hwc = &event->hw;
 338         u64 val = cpuc->pebs_enabled;
 339
 340         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 341
 342         val |= 1ULL << hwc->idx;
 343         wrmsrl(MSR_IA32_PEBS_ENABLE, val);
 344
 345         if (x86_pmu.intel_cap.pebs_trap)
 346                 intel_pmu_lbr_enable(event);
 347 }
 348
 349 static void intel_pmu_pebs_disable(struct perf_event *event)
 350 {
 351         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 352         struct hw_perf_event *hwc = &event->hw;
 353         u64 val = cpuc->pebs_enabled;
 354
 355         val &= ~(1ULL << hwc->idx);
 356         wrmsrl(MSR_IA32_PEBS_ENABLE, val);
 357
 358         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 359
 360         if (x86_pmu.intel_cap.pebs_trap)
 361                 intel_pmu_lbr_disable(event);
 362 }
 363
 364 static void intel_pmu_pebs_enable_all(void)
 365 {
 366         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 367
 368         if (cpuc->pebs_enabled)
 369                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 370 }
 371
 372 static void intel_pmu_pebs_disable_all(void)
 373 {
 374         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 375
 376         if (cpuc->pebs_enabled)
 377                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 378 }
 379
 380 #include <asm/insn.h>
 381
 382 static inline bool kernel_ip(unsigned long ip)
 383 {
 384 #ifdef CONFIG_X86_32
 385         return ip > PAGE_OFFSET;
 386 #else
 387         return (long)ip < 0;
 388 #endif
 389 }
 390
 391 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 392 {
 393         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 394         unsigned long from = cpuc->lbr_entries[0].from;
 395         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 396         unsigned long ip = regs->ip;
 397
 398         /*
 399          * We don't need to fixup if the PEBS assist is fault like
 400          */
 401         if (!x86_pmu.intel_cap.pebs_trap)
 402                 return 1;
 403
 404         if (!cpuc->lbr_stack.nr || !from || !to)
 405                 return 0;
 406
 407         if (ip < to)
 408                 return 0;
 409
 410         /*
 411          * We sampled a branch insn, rewind using the LBR stack
 412          */
 413         if (ip == to) {
 414                 regs->ip = from;
 415                 return 1;
 416         }
 417
 418         do {
 419                 struct insn insn;
 420                 u8 buf[MAX_INSN_SIZE];
 421                 void *kaddr;
 422
 423                 old_to = to;
 424                 if (!kernel_ip(ip)) {
 425                         int bytes, size = min_t(int, MAX_INSN_SIZE, ip - to);
 426
 427                         bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 428                         if (bytes != size)
 429                                 return 0;
 430
 431                         kaddr = buf;
 432                 } else
 433                         kaddr = (void *)to;
 434
 435                 kernel_insn_init(&insn, kaddr);
 436                 insn_get_length(&insn);
 437                 to += insn.length;
 438         } while (to < ip);
 439
 440         if (to == ip) {
 441                 regs->ip = old_to;
 442                 return 1;
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int intel_pmu_save_and_restart(struct perf_event *event);
 449 static void intel_pmu_disable_event(struct perf_event *event);
 450
 451 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 452 {
 453         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 454         struct debug_store *ds = cpuc->ds;
 455         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 456         struct pebs_record_core *at, *top;
 457         struct perf_sample_data data;
 458         struct perf_raw_record raw;
 459         struct pt_regs regs;
 460         int n;
 461
 462         if (!event || !ds || !x86_pmu.pebs)
 463                 return;
 464
 465         intel_pmu_pebs_disable_all();
 466
 467         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 468         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 469
 470         if (top <= at)
 471                 goto out;
 472
 473         ds->pebs_index = ds->pebs_buffer_base;
 474
 475         if (!intel_pmu_save_and_restart(event))
 476                 goto out;
 477
 478         perf_sample_data_init(&data, 0);
 479         data.period = event->hw.last_period;
 480
 481         if (event->attr.sample_type & PERF_SAMPLE_RAW) {
 482                 raw.size = x86_pmu.pebs_record_size;
 483                 raw.data = at;
 484                 data.raw = &raw;
 485         }
 486
 487         n = top - at;
 488
 489         /*
 490          * Should not happen, we program the threshold at 1 and do not
 491          * set a reset value.
 492          */
 493         WARN_ON_ONCE(n > 1);
 494
 495         /*
 496          * We use the interrupt regs as a base because the PEBS record
 497          * does not contain a full regs set, specifically it seems to
 498          * lack segment descriptors, which get used by things like
 499          * user_mode().
 500          *
 501          * In the simple case fix up only the IP and BP,SP regs, for
 502          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 503          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 504          */
 505         regs = *iregs;
 506         regs.ip = at->ip;
 507         regs.bp = at->bp;
 508         regs.sp = at->sp;
 509
 510         if (intel_pmu_pebs_fixup_ip(&regs))
 511                 regs.flags |= PERF_EFLAGS_EXACT;
 512         else
 513                 regs.flags &= ~PERF_EFLAGS_EXACT;
 514
 515         if (perf_event_overflow(event, 1, &data, &regs))
 516                 intel_pmu_disable_event(event);
 517
 518 out:
 519         intel_pmu_pebs_enable_all();
 520 }
 521
 522 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 523 {
 524         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 525         struct debug_store *ds = cpuc->ds;
 526         struct pebs_record_nhm *at, *top;
 527         struct perf_sample_data data;
 528         struct perf_event *event = NULL;
 529         struct perf_raw_record raw;
 530         struct pt_regs regs;
 531         int bit, n;
 532
 533         if (!ds || !x86_pmu.pebs)
 534                 return;
 535
 536         intel_pmu_pebs_disable_all();
 537
 538         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
 539         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
 540
 541         if (top <= at)
 542                 goto out;
 543
 544         ds->pebs_index = ds->pebs_buffer_base;
 545
 546         n = top - at;
 547
 548         /*
 549          * Should not happen, we program the threshold at 1 and do not
 550          * set a reset value.
 551          */
 552         WARN_ON_ONCE(n > MAX_PEBS_EVENTS);
 553
 554         for ( ; at < top; at++) {
 555                 for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
 556                         if (!cpuc->events[bit]->attr.precise)
 557                                 continue;
 558
 559                         event = cpuc->events[bit];
 560                 }
 561
 562                 if (!event)
 563                         continue;
 564
 565                 if (!intel_pmu_save_and_restart(event))
 566                         continue;
 567
 568                 perf_sample_data_init(&data, 0);
 569                 data.period = event->hw.last_period;
 570
 571                 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
 572                         raw.size = x86_pmu.pebs_record_size;
 573                         raw.data = at;
 574                         data.raw = &raw;
 575                 }
 576
 577                 /*
 578                  * See the comment in intel_pmu_drain_pebs_core()
 579                  */
 580                 regs = *iregs;
 581                 regs.ip = at->ip;
 582                 regs.bp = at->bp;
 583                 regs.sp = at->sp;
 584
 585                 if (intel_pmu_pebs_fixup_ip(&regs))
 586                         regs.flags |= PERF_EFLAGS_EXACT;
 587                 else
 588                         regs.flags &= ~PERF_EFLAGS_EXACT;
 589
 590                 if (perf_event_overflow(event, 1, &data, &regs))
 591                         intel_pmu_disable_event(event);
 592         }
 593 out:
 594         intel_pmu_pebs_enable_all();
 595 }
 596
 597 /*
 598  * BTS, PEBS probe and setup
 599  */
 600
 601 static void intel_ds_init(void)
 602 {
 603         /*
 604          * No support for 32bit formats
 605          */
 606         if (!boot_cpu_has(X86_FEATURE_DTES64))
 607                 return;
 608
 609         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
 610         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
 611         if (x86_pmu.pebs) {
 612                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
 613                 int format = x86_pmu.intel_cap.pebs_format;
 614
 615                 switch (format) {
 616                 case 0:
 617                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
 618                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
 619                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
 620                         x86_pmu.pebs_constraints = intel_core_pebs_events;
 621                         break;
 622
 623                 case 1:
 624                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
 625                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
 626                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
 627                         x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
 628                         break;
 629
 630                 default:
 631                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
 632                         x86_pmu.pebs = 0;
 633                         break;
 634                 }
 635         }
 636 }
 637
 638 #else /* CONFIG_CPU_SUP_INTEL */
 639
 640 static int reseve_ds_buffers(void)
 641 {
 642         return 0;
 643 }
 644
 645 static void release_ds_buffers(void)
 646 {
 647 }
 648
 649 #endif /* CONFIG_CPU_SUP_INTEL */