1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
5 #include <asm/perf_event.h>
8 #include "perf_event.h"
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE PAGE_SIZE
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
18 * pebs_record_32 for p4 and core not supported
20 struct pebs_record_32 {
28 union intel_x86_pebs_dse {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
54 static const u64 pebs_data_source[] = {
55 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
56 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
57 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
58 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
59 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
61 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
62 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
63 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
65 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
66 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
67 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
68 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
69 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
70 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
73 static u64 precise_store_data(u64 status)
75 union intel_x86_pebs_dse dse;
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
82 * 1 = stored missed 2nd level TLB
84 * so it either hit the walker or the OS
85 * otherwise hit 2nd level TLB
93 * bit 0: hit L1 data cache
94 * if not set, then all we know is that
103 * bit 5: Locked prefix
106 val |= P(LOCK, LOCKED);
111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
113 union perf_mem_data_src dse;
115 dse.val = PERF_MEM_NA;
117 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
118 dse.mem_op = PERF_MEM_OP_STORE;
119 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
120 dse.mem_op = PERF_MEM_OP_LOAD;
123 * L1 info only valid for following events:
125 * MEM_UOPS_RETIRED.STLB_MISS_STORES
126 * MEM_UOPS_RETIRED.LOCK_STORES
127 * MEM_UOPS_RETIRED.SPLIT_STORES
128 * MEM_UOPS_RETIRED.ALL_STORES
130 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
132 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
134 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
139 static u64 load_latency_data(u64 status)
141 union intel_x86_pebs_dse dse;
143 int model = boot_cpu_data.x86_model;
144 int fam = boot_cpu_data.x86;
149 * use the mapping table for bit 0-3
151 val = pebs_data_source[dse.ld_dse];
154 * Nehalem models do not support TLB, Lock infos
156 if (fam == 0x6 && (model == 26 || model == 30
157 || model == 31 || model == 46)) {
158 val |= P(TLB, NA) | P(LOCK, NA);
163 * 0 = did not miss 2nd level TLB
164 * 1 = missed 2nd level TLB
166 if (dse.ld_stlb_miss)
167 val |= P(TLB, MISS) | P(TLB, L2);
169 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
172 * bit 5: locked prefix
175 val |= P(LOCK, LOCKED);
180 struct pebs_record_core {
184 u64 r8, r9, r10, r11;
185 u64 r12, r13, r14, r15;
188 struct pebs_record_nhm {
192 u64 r8, r9, r10, r11;
193 u64 r12, r13, r14, r15;
194 u64 status, dla, dse, lat;
198 * Same as pebs_record_nhm, with two additional fields.
200 struct pebs_record_hsw {
204 u64 r8, r9, r10, r11;
205 u64 r12, r13, r14, r15;
206 u64 status, dla, dse, lat;
207 u64 real_ip, tsx_tuning;
210 union hsw_tsx_tuning {
212 u32 cycles_last_block : 32,
215 instruction_abort : 1,
216 non_instruction_abort : 1,
225 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
227 void init_debug_store_on_cpu(int cpu)
229 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
234 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
235 (u32)((u64)(unsigned long)ds),
236 (u32)((u64)(unsigned long)ds >> 32));
239 void fini_debug_store_on_cpu(int cpu)
241 if (!per_cpu(cpu_hw_events, cpu).ds)
244 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
247 static DEFINE_PER_CPU(void *, insn_buffer);
249 static int alloc_pebs_buffer(int cpu)
251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
252 int node = cpu_to_node(cpu);
253 int max, thresh = 1; /* always use a single PEBS record */
254 void *buffer, *ibuffer;
259 buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
260 if (unlikely(!buffer))
264 * HSW+ already provides us the eventing ip; no need to allocate this
267 if (x86_pmu.intel_cap.pebs_format < 2) {
268 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
273 per_cpu(insn_buffer, cpu) = ibuffer;
276 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
278 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
279 ds->pebs_index = ds->pebs_buffer_base;
280 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
281 max * x86_pmu.pebs_record_size;
283 ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
284 thresh * x86_pmu.pebs_record_size;
289 static void release_pebs_buffer(int cpu)
291 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
293 if (!ds || !x86_pmu.pebs)
296 kfree(per_cpu(insn_buffer, cpu));
297 per_cpu(insn_buffer, cpu) = NULL;
299 kfree((void *)(unsigned long)ds->pebs_buffer_base);
300 ds->pebs_buffer_base = 0;
303 static int alloc_bts_buffer(int cpu)
305 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
306 int node = cpu_to_node(cpu);
313 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
314 if (unlikely(!buffer)) {
315 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
319 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
322 ds->bts_buffer_base = (u64)(unsigned long)buffer;
323 ds->bts_index = ds->bts_buffer_base;
324 ds->bts_absolute_maximum = ds->bts_buffer_base +
325 max * BTS_RECORD_SIZE;
326 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
327 thresh * BTS_RECORD_SIZE;
332 static void release_bts_buffer(int cpu)
334 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
336 if (!ds || !x86_pmu.bts)
339 kfree((void *)(unsigned long)ds->bts_buffer_base);
340 ds->bts_buffer_base = 0;
343 static int alloc_ds_buffer(int cpu)
345 int node = cpu_to_node(cpu);
346 struct debug_store *ds;
348 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
352 per_cpu(cpu_hw_events, cpu).ds = ds;
357 static void release_ds_buffer(int cpu)
359 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
364 per_cpu(cpu_hw_events, cpu).ds = NULL;
368 void release_ds_buffers(void)
372 if (!x86_pmu.bts && !x86_pmu.pebs)
376 for_each_online_cpu(cpu)
377 fini_debug_store_on_cpu(cpu);
379 for_each_possible_cpu(cpu) {
380 release_pebs_buffer(cpu);
381 release_bts_buffer(cpu);
382 release_ds_buffer(cpu);
387 void reserve_ds_buffers(void)
389 int bts_err = 0, pebs_err = 0;
392 x86_pmu.bts_active = 0;
393 x86_pmu.pebs_active = 0;
395 if (!x86_pmu.bts && !x86_pmu.pebs)
406 for_each_possible_cpu(cpu) {
407 if (alloc_ds_buffer(cpu)) {
412 if (!bts_err && alloc_bts_buffer(cpu))
415 if (!pebs_err && alloc_pebs_buffer(cpu))
418 if (bts_err && pebs_err)
423 for_each_possible_cpu(cpu)
424 release_bts_buffer(cpu);
428 for_each_possible_cpu(cpu)
429 release_pebs_buffer(cpu);
432 if (bts_err && pebs_err) {
433 for_each_possible_cpu(cpu)
434 release_ds_buffer(cpu);
436 if (x86_pmu.bts && !bts_err)
437 x86_pmu.bts_active = 1;
439 if (x86_pmu.pebs && !pebs_err)
440 x86_pmu.pebs_active = 1;
442 for_each_online_cpu(cpu)
443 init_debug_store_on_cpu(cpu);
453 struct event_constraint bts_constraint =
454 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
456 void intel_pmu_enable_bts(u64 config)
458 unsigned long debugctlmsr;
460 debugctlmsr = get_debugctlmsr();
462 debugctlmsr |= DEBUGCTLMSR_TR;
463 debugctlmsr |= DEBUGCTLMSR_BTS;
464 debugctlmsr |= DEBUGCTLMSR_BTINT;
466 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
467 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
469 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
470 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
472 update_debugctlmsr(debugctlmsr);
475 void intel_pmu_disable_bts(void)
477 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
478 unsigned long debugctlmsr;
483 debugctlmsr = get_debugctlmsr();
486 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
487 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
489 update_debugctlmsr(debugctlmsr);
492 int intel_pmu_drain_bts_buffer(void)
494 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
495 struct debug_store *ds = cpuc->ds;
501 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
502 struct bts_record *at, *top;
503 struct perf_output_handle handle;
504 struct perf_event_header header;
505 struct perf_sample_data data;
511 if (!x86_pmu.bts_active)
514 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
515 top = (struct bts_record *)(unsigned long)ds->bts_index;
520 memset(®s, 0, sizeof(regs));
522 ds->bts_index = ds->bts_buffer_base;
524 perf_sample_data_init(&data, 0, event->hw.last_period);
527 * Prepare a generic sample, i.e. fill in the invariant fields.
528 * We will overwrite the from and to address before we output
531 perf_prepare_sample(&header, &data, event, ®s);
533 if (perf_output_begin(&handle, event, header.size * (top - at)))
536 for (; at < top; at++) {
540 perf_output_sample(&handle, &header, &data, event);
543 perf_output_end(&handle);
545 /* There's new data available. */
546 event->hw.interrupts++;
547 event->pending_kill = POLL_IN;
554 struct event_constraint intel_core2_pebs_event_constraints[] = {
555 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
556 INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
557 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
558 INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
559 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
563 struct event_constraint intel_atom_pebs_event_constraints[] = {
564 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
565 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
566 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
570 struct event_constraint intel_slm_pebs_event_constraints[] = {
571 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
572 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
573 /* Allow all events as PEBS with no flags */
574 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
578 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
579 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
580 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
581 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
582 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
583 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
584 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
585 INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
586 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
587 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
588 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
589 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
593 struct event_constraint intel_westmere_pebs_event_constraints[] = {
594 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
595 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
596 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
597 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
598 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
599 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
600 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
601 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
602 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
603 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
604 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
608 struct event_constraint intel_snb_pebs_event_constraints[] = {
609 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
610 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
611 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
612 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
613 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
614 /* Allow all events as PEBS with no flags */
615 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
619 struct event_constraint intel_ivb_pebs_event_constraints[] = {
620 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
621 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
622 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
623 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
624 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
625 /* Allow all events as PEBS with no flags */
626 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
630 struct event_constraint intel_hsw_pebs_event_constraints[] = {
631 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
632 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
633 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
634 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
635 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
636 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
637 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
638 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
639 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
640 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
641 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
642 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
643 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
644 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
645 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
646 /* Allow all events as PEBS with no flags */
647 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
651 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
653 struct event_constraint *c;
655 if (!event->attr.precise_ip)
658 if (x86_pmu.pebs_constraints) {
659 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
660 if ((event->hw.config & c->cmask) == c->code) {
661 event->hw.flags |= c->flags;
667 return &emptyconstraint;
670 void intel_pmu_pebs_enable(struct perf_event *event)
672 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
673 struct hw_perf_event *hwc = &event->hw;
675 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
677 cpuc->pebs_enabled |= 1ULL << hwc->idx;
679 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
680 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
681 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
682 cpuc->pebs_enabled |= 1ULL << 63;
685 void intel_pmu_pebs_disable(struct perf_event *event)
687 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
688 struct hw_perf_event *hwc = &event->hw;
690 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
692 if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
693 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
694 else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
695 cpuc->pebs_enabled &= ~(1ULL << 63);
698 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
700 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
703 void intel_pmu_pebs_enable_all(void)
705 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
707 if (cpuc->pebs_enabled)
708 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
711 void intel_pmu_pebs_disable_all(void)
713 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
715 if (cpuc->pebs_enabled)
716 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
719 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
721 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
722 unsigned long from = cpuc->lbr_entries[0].from;
723 unsigned long old_to, to = cpuc->lbr_entries[0].to;
724 unsigned long ip = regs->ip;
729 * We don't need to fixup if the PEBS assist is fault like
731 if (!x86_pmu.intel_cap.pebs_trap)
735 * No LBR entry, no basic block, no rewinding
737 if (!cpuc->lbr_stack.nr || !from || !to)
741 * Basic blocks should never cross user/kernel boundaries
743 if (kernel_ip(ip) != kernel_ip(to))
747 * unsigned math, either ip is before the start (impossible) or
748 * the basic block is larger than 1 page (sanity)
750 if ((ip - to) > PEBS_FIXUP_SIZE)
754 * We sampled a branch insn, rewind using the LBR stack
757 set_linear_ip(regs, from);
761 if (!kernel_ip(ip)) {
763 u8 *buf = this_cpu_read(insn_buffer);
765 size = ip - to; /* Must fit our buffer, see above */
766 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
781 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
783 insn_init(&insn, kaddr, is_64bit);
784 insn_get_length(&insn);
787 kaddr += insn.length;
791 set_linear_ip(regs, old_to);
796 * Even though we decoded the basic block, the instruction stream
797 * never matched the given IP, either the TO or the IP got corrupted.
802 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
804 if (pebs->tsx_tuning) {
805 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
806 return tsx.cycles_last_block;
811 static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
813 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
815 /* For RTM XABORTs also log the abort code from AX */
816 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
817 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
821 static void __intel_pmu_pebs_event(struct perf_event *event,
822 struct pt_regs *iregs, void *__pebs)
824 #define PERF_X86_EVENT_PEBS_HSW_PREC \
825 (PERF_X86_EVENT_PEBS_ST_HSW | \
826 PERF_X86_EVENT_PEBS_LD_HSW | \
827 PERF_X86_EVENT_PEBS_NA_HSW)
829 * We cast to the biggest pebs_record but are careful not to
830 * unconditionally access the 'extra' entries.
832 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
833 struct pebs_record_hsw *pebs = __pebs;
834 struct perf_sample_data data;
838 int fl = event->hw.flags;
840 if (!intel_pmu_save_and_restart(event))
843 sample_type = event->attr.sample_type;
844 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
846 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
847 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
849 perf_sample_data_init(&data, 0, event->hw.last_period);
851 data.period = event->hw.last_period;
854 * Use latency for weight (only avail with PEBS-LL)
856 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
857 data.weight = pebs->lat;
860 * data.data_src encodes the data source
863 u64 val = PERF_MEM_NA;
865 val = load_latency_data(pebs->dse);
866 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
867 val = precise_datala_hsw(event, pebs->dse);
869 val = precise_store_data(pebs->dse);
870 data.data_src.val = val;
874 * We use the interrupt regs as a base because the PEBS record
875 * does not contain a full regs set, specifically it seems to
876 * lack segment descriptors, which get used by things like
879 * In the simple case fix up only the IP and BP,SP regs, for
880 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
881 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
884 regs.flags = pebs->flags;
885 set_linear_ip(®s, pebs->ip);
889 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
890 regs.ip = pebs->real_ip;
891 regs.flags |= PERF_EFLAGS_EXACT;
892 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
893 regs.flags |= PERF_EFLAGS_EXACT;
895 regs.flags &= ~PERF_EFLAGS_EXACT;
897 if ((sample_type & PERF_SAMPLE_ADDR) &&
898 x86_pmu.intel_cap.pebs_format >= 1)
899 data.addr = pebs->dla;
901 if (x86_pmu.intel_cap.pebs_format >= 2) {
902 /* Only set the TSX weight when no memory weight. */
903 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
904 data.weight = intel_hsw_weight(pebs);
906 if (sample_type & PERF_SAMPLE_TRANSACTION)
907 data.txn = intel_hsw_transaction(pebs);
910 if (has_branch_stack(event))
911 data.br_stack = &cpuc->lbr_stack;
913 if (perf_event_overflow(event, &data, ®s))
914 x86_pmu_stop(event, 0);
917 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
919 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
920 struct debug_store *ds = cpuc->ds;
921 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
922 struct pebs_record_core *at, *top;
925 if (!x86_pmu.pebs_active)
928 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
929 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
932 * Whatever else happens, drain the thing
934 ds->pebs_index = ds->pebs_buffer_base;
936 if (!test_bit(0, cpuc->active_mask))
939 WARN_ON_ONCE(!event);
941 if (!event->attr.precise_ip)
949 * Should not happen, we program the threshold at 1 and do not
952 WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
955 __intel_pmu_pebs_event(event, iregs, at);
958 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
960 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
961 struct debug_store *ds = cpuc->ds;
962 struct perf_event *event = NULL;
967 if (!x86_pmu.pebs_active)
970 at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
971 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
973 ds->pebs_index = ds->pebs_buffer_base;
975 if (unlikely(at > top))
979 * Should not happen, we program the threshold at 1 and do not
982 WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
983 "Unexpected number of pebs records %ld\n",
984 (long)(top - at) / x86_pmu.pebs_record_size);
986 for (; at < top; at += x86_pmu.pebs_record_size) {
987 struct pebs_record_nhm *p = at;
989 for_each_set_bit(bit, (unsigned long *)&p->status,
990 x86_pmu.max_pebs_events) {
991 event = cpuc->events[bit];
992 if (!test_bit(bit, cpuc->active_mask))
995 WARN_ON_ONCE(!event);
997 if (!event->attr.precise_ip)
1000 if (__test_and_set_bit(bit, (unsigned long *)&status))
1006 if (!event || bit >= x86_pmu.max_pebs_events)
1009 __intel_pmu_pebs_event(event, iregs, at);
1014 * BTS, PEBS probe and setup
1017 void __init intel_ds_init(void)
1020 * No support for 32bit formats
1022 if (!boot_cpu_has(X86_FEATURE_DTES64))
1025 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1026 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1028 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1029 int format = x86_pmu.intel_cap.pebs_format;
1033 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1034 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1035 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1039 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1040 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1041 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1045 pr_cont("PEBS fmt2%c, ", pebs_type);
1046 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1047 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1051 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1057 void perf_restore_debug_store(void)
1059 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1061 if (!x86_pmu.bts && !x86_pmu.pebs)
1064 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);