1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
5 #include <asm/perf_event.h>
8 #include "perf_event.h"
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE PAGE_SIZE
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
18 * pebs_record_32 for p4 and core not supported
20 struct pebs_record_32 {
28 union intel_x86_pebs_dse {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
54 static const u64 pebs_data_source[] = {
55 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
56 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
57 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
58 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
59 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
61 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
62 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
63 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
65 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
66 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
67 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
68 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
69 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
70 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
73 static u64 precise_store_data(u64 status)
75 union intel_x86_pebs_dse dse;
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
82 * 1 = stored missed 2nd level TLB
84 * so it either hit the walker or the OS
85 * otherwise hit 2nd level TLB
93 * bit 0: hit L1 data cache
94 * if not set, then all we know is that
103 * bit 5: Locked prefix
106 val |= P(LOCK, LOCKED);
111 static u64 precise_store_data_hsw(struct perf_event *event, u64 status)
113 union perf_mem_data_src dse;
114 u64 cfg = event->hw.config & INTEL_ARCH_EVENT_MASK;
117 dse.mem_op = PERF_MEM_OP_STORE;
118 dse.mem_lvl = PERF_MEM_LVL_NA;
121 * L1 info only valid for following events:
123 * MEM_UOPS_RETIRED.STLB_MISS_STORES
124 * MEM_UOPS_RETIRED.LOCK_STORES
125 * MEM_UOPS_RETIRED.SPLIT_STORES
126 * MEM_UOPS_RETIRED.ALL_STORES
128 if (cfg != 0x12d0 && cfg != 0x22d0 && cfg != 0x42d0 && cfg != 0x82d0)
132 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
134 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
136 /* Nothing else supported. Sorry. */
140 static u64 load_latency_data(u64 status)
142 union intel_x86_pebs_dse dse;
144 int model = boot_cpu_data.x86_model;
145 int fam = boot_cpu_data.x86;
150 * use the mapping table for bit 0-3
152 val = pebs_data_source[dse.ld_dse];
155 * Nehalem models do not support TLB, Lock infos
157 if (fam == 0x6 && (model == 26 || model == 30
158 || model == 31 || model == 46)) {
159 val |= P(TLB, NA) | P(LOCK, NA);
164 * 0 = did not miss 2nd level TLB
165 * 1 = missed 2nd level TLB
167 if (dse.ld_stlb_miss)
168 val |= P(TLB, MISS) | P(TLB, L2);
170 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
173 * bit 5: locked prefix
176 val |= P(LOCK, LOCKED);
181 struct pebs_record_core {
185 u64 r8, r9, r10, r11;
186 u64 r12, r13, r14, r15;
189 struct pebs_record_nhm {
193 u64 r8, r9, r10, r11;
194 u64 r12, r13, r14, r15;
195 u64 status, dla, dse, lat;
199 * Same as pebs_record_nhm, with two additional fields.
201 struct pebs_record_hsw {
205 u64 r8, r9, r10, r11;
206 u64 r12, r13, r14, r15;
207 u64 status, dla, dse, lat;
208 u64 real_ip, tsx_tuning;
211 union hsw_tsx_tuning {
213 u32 cycles_last_block : 32,
216 instruction_abort : 1,
217 non_instruction_abort : 1,
226 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
228 void init_debug_store_on_cpu(int cpu)
230 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
235 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
236 (u32)((u64)(unsigned long)ds),
237 (u32)((u64)(unsigned long)ds >> 32));
240 void fini_debug_store_on_cpu(int cpu)
242 if (!per_cpu(cpu_hw_events, cpu).ds)
245 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
248 static DEFINE_PER_CPU(void *, insn_buffer);
250 static int alloc_pebs_buffer(int cpu)
252 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
253 int node = cpu_to_node(cpu);
254 int max, thresh = 1; /* always use a single PEBS record */
255 void *buffer, *ibuffer;
260 buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
261 if (unlikely(!buffer))
265 * HSW+ already provides us the eventing ip; no need to allocate this
268 if (x86_pmu.intel_cap.pebs_format < 2) {
269 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
274 per_cpu(insn_buffer, cpu) = ibuffer;
277 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
279 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
280 ds->pebs_index = ds->pebs_buffer_base;
281 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
282 max * x86_pmu.pebs_record_size;
284 ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
285 thresh * x86_pmu.pebs_record_size;
290 static void release_pebs_buffer(int cpu)
292 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
294 if (!ds || !x86_pmu.pebs)
297 kfree(per_cpu(insn_buffer, cpu));
298 per_cpu(insn_buffer, cpu) = NULL;
300 kfree((void *)(unsigned long)ds->pebs_buffer_base);
301 ds->pebs_buffer_base = 0;
304 static int alloc_bts_buffer(int cpu)
306 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
307 int node = cpu_to_node(cpu);
314 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
315 if (unlikely(!buffer)) {
316 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
320 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
323 ds->bts_buffer_base = (u64)(unsigned long)buffer;
324 ds->bts_index = ds->bts_buffer_base;
325 ds->bts_absolute_maximum = ds->bts_buffer_base +
326 max * BTS_RECORD_SIZE;
327 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
328 thresh * BTS_RECORD_SIZE;
333 static void release_bts_buffer(int cpu)
335 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
337 if (!ds || !x86_pmu.bts)
340 kfree((void *)(unsigned long)ds->bts_buffer_base);
341 ds->bts_buffer_base = 0;
344 static int alloc_ds_buffer(int cpu)
346 int node = cpu_to_node(cpu);
347 struct debug_store *ds;
349 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
353 per_cpu(cpu_hw_events, cpu).ds = ds;
358 static void release_ds_buffer(int cpu)
360 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
365 per_cpu(cpu_hw_events, cpu).ds = NULL;
369 void release_ds_buffers(void)
373 if (!x86_pmu.bts && !x86_pmu.pebs)
377 for_each_online_cpu(cpu)
378 fini_debug_store_on_cpu(cpu);
380 for_each_possible_cpu(cpu) {
381 release_pebs_buffer(cpu);
382 release_bts_buffer(cpu);
383 release_ds_buffer(cpu);
388 void reserve_ds_buffers(void)
390 int bts_err = 0, pebs_err = 0;
393 x86_pmu.bts_active = 0;
394 x86_pmu.pebs_active = 0;
396 if (!x86_pmu.bts && !x86_pmu.pebs)
407 for_each_possible_cpu(cpu) {
408 if (alloc_ds_buffer(cpu)) {
413 if (!bts_err && alloc_bts_buffer(cpu))
416 if (!pebs_err && alloc_pebs_buffer(cpu))
419 if (bts_err && pebs_err)
424 for_each_possible_cpu(cpu)
425 release_bts_buffer(cpu);
429 for_each_possible_cpu(cpu)
430 release_pebs_buffer(cpu);
433 if (bts_err && pebs_err) {
434 for_each_possible_cpu(cpu)
435 release_ds_buffer(cpu);
437 if (x86_pmu.bts && !bts_err)
438 x86_pmu.bts_active = 1;
440 if (x86_pmu.pebs && !pebs_err)
441 x86_pmu.pebs_active = 1;
443 for_each_online_cpu(cpu)
444 init_debug_store_on_cpu(cpu);
454 struct event_constraint bts_constraint =
455 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
457 void intel_pmu_enable_bts(u64 config)
459 unsigned long debugctlmsr;
461 debugctlmsr = get_debugctlmsr();
463 debugctlmsr |= DEBUGCTLMSR_TR;
464 debugctlmsr |= DEBUGCTLMSR_BTS;
465 debugctlmsr |= DEBUGCTLMSR_BTINT;
467 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
468 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
470 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
471 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
473 update_debugctlmsr(debugctlmsr);
476 void intel_pmu_disable_bts(void)
478 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
479 unsigned long debugctlmsr;
484 debugctlmsr = get_debugctlmsr();
487 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
488 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
490 update_debugctlmsr(debugctlmsr);
493 int intel_pmu_drain_bts_buffer(void)
495 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
496 struct debug_store *ds = cpuc->ds;
502 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
503 struct bts_record *at, *top;
504 struct perf_output_handle handle;
505 struct perf_event_header header;
506 struct perf_sample_data data;
512 if (!x86_pmu.bts_active)
515 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
516 top = (struct bts_record *)(unsigned long)ds->bts_index;
521 memset(®s, 0, sizeof(regs));
523 ds->bts_index = ds->bts_buffer_base;
525 perf_sample_data_init(&data, 0, event->hw.last_period);
528 * Prepare a generic sample, i.e. fill in the invariant fields.
529 * We will overwrite the from and to address before we output
532 perf_prepare_sample(&header, &data, event, ®s);
534 if (perf_output_begin(&handle, event, header.size * (top - at)))
537 for (; at < top; at++) {
541 perf_output_sample(&handle, &header, &data, event);
544 perf_output_end(&handle);
546 /* There's new data available. */
547 event->hw.interrupts++;
548 event->pending_kill = POLL_IN;
555 struct event_constraint intel_core2_pebs_event_constraints[] = {
556 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
557 INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
558 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
559 INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
560 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
564 struct event_constraint intel_atom_pebs_event_constraints[] = {
565 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
566 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
567 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
571 struct event_constraint intel_slm_pebs_event_constraints[] = {
572 INTEL_UEVENT_CONSTRAINT(0x0103, 0x1), /* REHABQ.LD_BLOCK_ST_FORWARD_PS */
573 INTEL_UEVENT_CONSTRAINT(0x0803, 0x1), /* REHABQ.LD_SPLITS_PS */
574 INTEL_UEVENT_CONSTRAINT(0x0204, 0x1), /* MEM_UOPS_RETIRED.L2_HIT_LOADS_PS */
575 INTEL_UEVENT_CONSTRAINT(0x0404, 0x1), /* MEM_UOPS_RETIRED.L2_MISS_LOADS_PS */
576 INTEL_UEVENT_CONSTRAINT(0x0804, 0x1), /* MEM_UOPS_RETIRED.DTLB_MISS_LOADS_PS */
577 INTEL_UEVENT_CONSTRAINT(0x2004, 0x1), /* MEM_UOPS_RETIRED.HITM_PS */
578 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY_PS */
579 INTEL_UEVENT_CONSTRAINT(0x00c4, 0x1), /* BR_INST_RETIRED.ALL_BRANCHES_PS */
580 INTEL_UEVENT_CONSTRAINT(0x7ec4, 0x1), /* BR_INST_RETIRED.JCC_PS */
581 INTEL_UEVENT_CONSTRAINT(0xbfc4, 0x1), /* BR_INST_RETIRED.FAR_BRANCH_PS */
582 INTEL_UEVENT_CONSTRAINT(0xebc4, 0x1), /* BR_INST_RETIRED.NON_RETURN_IND_PS */
583 INTEL_UEVENT_CONSTRAINT(0xf7c4, 0x1), /* BR_INST_RETIRED.RETURN_PS */
584 INTEL_UEVENT_CONSTRAINT(0xf9c4, 0x1), /* BR_INST_RETIRED.CALL_PS */
585 INTEL_UEVENT_CONSTRAINT(0xfbc4, 0x1), /* BR_INST_RETIRED.IND_CALL_PS */
586 INTEL_UEVENT_CONSTRAINT(0xfdc4, 0x1), /* BR_INST_RETIRED.REL_CALL_PS */
587 INTEL_UEVENT_CONSTRAINT(0xfec4, 0x1), /* BR_INST_RETIRED.TAKEN_JCC_PS */
588 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_MISP_RETIRED.ALL_BRANCHES_PS */
589 INTEL_UEVENT_CONSTRAINT(0x7ec5, 0x1), /* BR_INST_MISP_RETIRED.JCC_PS */
590 INTEL_UEVENT_CONSTRAINT(0xebc5, 0x1), /* BR_INST_MISP_RETIRED.NON_RETURN_IND_PS */
591 INTEL_UEVENT_CONSTRAINT(0xf7c5, 0x1), /* BR_INST_MISP_RETIRED.RETURN_PS */
592 INTEL_UEVENT_CONSTRAINT(0xfbc5, 0x1), /* BR_INST_MISP_RETIRED.IND_CALL_PS */
593 INTEL_UEVENT_CONSTRAINT(0xfec5, 0x1), /* BR_INST_MISP_RETIRED.TAKEN_JCC_PS */
597 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
598 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
599 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
600 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
601 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
602 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
603 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
604 INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
605 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
606 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
607 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
608 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
612 struct event_constraint intel_westmere_pebs_event_constraints[] = {
613 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
614 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
615 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
616 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
617 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
618 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
619 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
620 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
621 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
622 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
623 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
627 struct event_constraint intel_snb_pebs_event_constraints[] = {
628 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
629 INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
630 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
631 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
632 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
633 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
634 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
635 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
636 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
637 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
638 INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
639 INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
643 struct event_constraint intel_ivb_pebs_event_constraints[] = {
644 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
645 INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
646 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
647 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
648 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
649 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
650 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
651 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
652 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
653 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
654 INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
658 struct event_constraint intel_hsw_pebs_event_constraints[] = {
659 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
660 INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
661 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
662 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
663 INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
664 INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
665 INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
666 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.* */
667 /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
668 INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
669 /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
670 INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
671 INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
672 INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
673 /* MEM_UOPS_RETIRED.SPLIT_STORES */
674 INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
675 INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
676 INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
677 INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
678 INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
679 INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
680 /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
681 INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
682 /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
683 INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
684 /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
685 INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
686 /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
687 INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
688 INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
689 INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
694 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
696 struct event_constraint *c;
698 if (!event->attr.precise_ip)
701 if (x86_pmu.pebs_constraints) {
702 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
703 if ((event->hw.config & c->cmask) == c->code) {
704 event->hw.flags |= c->flags;
710 return &emptyconstraint;
713 void intel_pmu_pebs_enable(struct perf_event *event)
715 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
716 struct hw_perf_event *hwc = &event->hw;
718 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
720 cpuc->pebs_enabled |= 1ULL << hwc->idx;
722 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
723 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
724 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
725 cpuc->pebs_enabled |= 1ULL << 63;
728 void intel_pmu_pebs_disable(struct perf_event *event)
730 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
731 struct hw_perf_event *hwc = &event->hw;
733 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
735 if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
736 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
737 else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
738 cpuc->pebs_enabled &= ~(1ULL << 63);
741 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
743 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
746 void intel_pmu_pebs_enable_all(void)
748 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
750 if (cpuc->pebs_enabled)
751 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
754 void intel_pmu_pebs_disable_all(void)
756 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
758 if (cpuc->pebs_enabled)
759 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
762 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
764 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
765 unsigned long from = cpuc->lbr_entries[0].from;
766 unsigned long old_to, to = cpuc->lbr_entries[0].to;
767 unsigned long ip = regs->ip;
772 * We don't need to fixup if the PEBS assist is fault like
774 if (!x86_pmu.intel_cap.pebs_trap)
778 * No LBR entry, no basic block, no rewinding
780 if (!cpuc->lbr_stack.nr || !from || !to)
784 * Basic blocks should never cross user/kernel boundaries
786 if (kernel_ip(ip) != kernel_ip(to))
790 * unsigned math, either ip is before the start (impossible) or
791 * the basic block is larger than 1 page (sanity)
793 if ((ip - to) > PEBS_FIXUP_SIZE)
797 * We sampled a branch insn, rewind using the LBR stack
800 set_linear_ip(regs, from);
804 if (!kernel_ip(ip)) {
806 u8 *buf = this_cpu_read(insn_buffer);
808 size = ip - to; /* Must fit our buffer, see above */
809 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
824 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
826 insn_init(&insn, kaddr, is_64bit);
827 insn_get_length(&insn);
830 kaddr += insn.length;
834 set_linear_ip(regs, old_to);
839 * Even though we decoded the basic block, the instruction stream
840 * never matched the given IP, either the TO or the IP got corrupted.
845 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
847 if (pebs->tsx_tuning) {
848 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
849 return tsx.cycles_last_block;
854 static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
856 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
858 /* For RTM XABORTs also log the abort code from AX */
859 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
860 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
864 static void __intel_pmu_pebs_event(struct perf_event *event,
865 struct pt_regs *iregs, void *__pebs)
868 * We cast to the biggest pebs_record but are careful not to
869 * unconditionally access the 'extra' entries.
871 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
872 struct pebs_record_hsw *pebs = __pebs;
873 struct perf_sample_data data;
878 if (!intel_pmu_save_and_restart(event))
881 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
882 fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
883 PERF_X86_EVENT_PEBS_ST_HSW);
885 perf_sample_data_init(&data, 0, event->hw.last_period);
887 data.period = event->hw.last_period;
888 sample_type = event->attr.sample_type;
891 * if PEBS-LL or PreciseStore
895 * Use latency for weight (only avail with PEBS-LL)
897 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
898 data.weight = pebs->lat;
901 * data.data_src encodes the data source
903 if (sample_type & PERF_SAMPLE_DATA_SRC) {
905 data.data_src.val = load_latency_data(pebs->dse);
906 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
908 precise_store_data_hsw(event, pebs->dse);
910 data.data_src.val = precise_store_data(pebs->dse);
915 * We use the interrupt regs as a base because the PEBS record
916 * does not contain a full regs set, specifically it seems to
917 * lack segment descriptors, which get used by things like
920 * In the simple case fix up only the IP and BP,SP regs, for
921 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
922 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
925 regs.flags = pebs->flags;
926 set_linear_ip(®s, pebs->ip);
930 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
931 regs.ip = pebs->real_ip;
932 regs.flags |= PERF_EFLAGS_EXACT;
933 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
934 regs.flags |= PERF_EFLAGS_EXACT;
936 regs.flags &= ~PERF_EFLAGS_EXACT;
938 if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
939 x86_pmu.intel_cap.pebs_format >= 1)
940 data.addr = pebs->dla;
942 if (x86_pmu.intel_cap.pebs_format >= 2) {
943 /* Only set the TSX weight when no memory weight. */
944 if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll)
945 data.weight = intel_hsw_weight(pebs);
947 if (event->attr.sample_type & PERF_SAMPLE_TRANSACTION)
948 data.txn = intel_hsw_transaction(pebs);
951 if (has_branch_stack(event))
952 data.br_stack = &cpuc->lbr_stack;
954 if (perf_event_overflow(event, &data, ®s))
955 x86_pmu_stop(event, 0);
958 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
960 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
961 struct debug_store *ds = cpuc->ds;
962 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
963 struct pebs_record_core *at, *top;
966 if (!x86_pmu.pebs_active)
969 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
970 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
973 * Whatever else happens, drain the thing
975 ds->pebs_index = ds->pebs_buffer_base;
977 if (!test_bit(0, cpuc->active_mask))
980 WARN_ON_ONCE(!event);
982 if (!event->attr.precise_ip)
990 * Should not happen, we program the threshold at 1 and do not
993 WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
996 __intel_pmu_pebs_event(event, iregs, at);
999 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1001 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1002 struct debug_store *ds = cpuc->ds;
1003 struct perf_event *event = NULL;
1008 if (!x86_pmu.pebs_active)
1011 at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1012 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1014 ds->pebs_index = ds->pebs_buffer_base;
1016 if (unlikely(at > top))
1020 * Should not happen, we program the threshold at 1 and do not
1021 * set a reset value.
1023 WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
1024 "Unexpected number of pebs records %ld\n",
1025 (long)(top - at) / x86_pmu.pebs_record_size);
1027 for (; at < top; at += x86_pmu.pebs_record_size) {
1028 struct pebs_record_nhm *p = at;
1030 for_each_set_bit(bit, (unsigned long *)&p->status,
1031 x86_pmu.max_pebs_events) {
1032 event = cpuc->events[bit];
1033 if (!test_bit(bit, cpuc->active_mask))
1036 WARN_ON_ONCE(!event);
1038 if (!event->attr.precise_ip)
1041 if (__test_and_set_bit(bit, (unsigned long *)&status))
1047 if (!event || bit >= x86_pmu.max_pebs_events)
1050 __intel_pmu_pebs_event(event, iregs, at);
1055 * BTS, PEBS probe and setup
1058 void intel_ds_init(void)
1061 * No support for 32bit formats
1063 if (!boot_cpu_has(X86_FEATURE_DTES64))
1066 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1067 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1069 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1070 int format = x86_pmu.intel_cap.pebs_format;
1074 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1075 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1076 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1080 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1081 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1082 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1086 pr_cont("PEBS fmt2%c, ", pebs_type);
1087 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1088 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1092 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1098 void perf_restore_debug_store(void)
1100 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1102 if (!x86_pmu.bts && !x86_pmu.pebs)
1105 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);